[WebAssembly] Support single-floating-point immediate value

[kateinoigakukun]

Summary

As mentioned in TODO comment, casting double to float causes NaNs to change bits.
To avoid the change, this patch adds support for single-floating-point immediate value on MachineCode.

[kateinoigakukun]

Fix for failing test cases

[sunfish]

On some 32-bit x86 hosts, particularly those that use x87 arithmetic, loading and storing with floating-point types can change the NaN bit pattern. To preserve the bit pattern reliably, MCOperand should represent floating-point immediates by representing the bits in int32_t for 32-bit and int64_t for 64-bit. Codegen and MC don't usually look at the value, but where they do need to interpret it as a floating-point value, they can reinterpret the bits on demand.

[kateinoigakukun]

I couldn't reproduce the failure of opt-bisect-legacy-pass-manager.ll on my x86_64 host. I can't figure out why the test suite failed.

[sunfish]

Is looks possible that the test failure was due to an unrelated commit 210f40fe9a30212396311d265904b2d73859c53d. If so, it's possible it's fixed as of 74ab5d98d07f0b0226f45ccca8df6a450d52fb7b.

llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp

291

MCOperand::createFPImm, and the other functions which also hold the value in floating-point types can also implicitly convert NaN bits. To preserve it in all cases, there should be a way to construct an MCOperand from an integer holding the bits, so this code can do something like Imm->getValueAPF()->bitcastToAPInt().getZExtValue() and pass the value in.

Similar for getFPImm on the consuming side.

[kateinoigakukun]

@sunfish Could you take a look again?

[MaxDesiatov]

Hi @sunfish, would you be able to have another look at this or recommend someone else for review otherwise? Thank you!

[sunfish]

Looks good to me.

llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

132

Ideally, FltOp should also store uint32_t/uint64_t instead of just a double, for the same reasons as the rest of this patch. But I think it's fine to address this later.

[jrtc27]

Having createFPImm and createSFPImm (similarly for the add methods) seems confusing. Can we not have a uniform SFP/DFP split in the names everywhere, since you're already touching the uses of the former due to changing the types?

[kateinoigakukun]

Having createFPImm and createSFPImm (similarly for the add methods) seems confusing. Can we not have a uniform SFP/DFP split in the names everywhere, since you're already touching the uses of the former due to changing the types?

I updated to have a uniform SFP/DFP in floating-point APIs.

[kateinoigakukun]

@jrtc27 @sunfish Sorry for the lack of updates for so long, I fixed the CI issue and it's ready for review 🙏

[sunfish]

Looks good!

[kateinoigakukun]

@sunfish Thanks for your review! I don't have a commit access, so could you commit this patch? 🙏

[kateinoigakukun]

Sorry for pinging. Could you land this patch? 🙏

llvm/include/llvm/MC/MCInst.h

 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCINST_H
 #define LLVM_MC_MCINST_H
 
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/bit.h"
 #include "llvm/Support/SMLoc.h"
 #include <cassert>
 #include <cstddef>
 #include <cstdint>
 
 namespace llvm {
 
 class MCExpr;
 class MCInst;
 class MCInstPrinter;
 class raw_ostream;
 
 /// Instances of this class represent operands of the MCInst class.
 /// This is a simple discriminated union.
 class MCOperand {
   enum MachineOperandType : unsigned char {
-    kInvalid,     ///< Uninitialized.
-    kRegister,    ///< Register operand.
-    kImmediate,   ///< Immediate operand.
-    kFPImmediate, ///< Floating-point immediate operand.
-    kExpr,        ///< Relocatable immediate operand.
-    kInst         ///< Sub-instruction operand.
+    kInvalid,      ///< Uninitialized.
+    kRegister,     ///< Register operand.
+    kImmediate,    ///< Immediate operand.
+    kSFPImmediate, ///< Single-floating-point immediate operand.
+    kDFPImmediate, ///< Double-Floating-point immediate operand.
+    kExpr,         ///< Relocatable immediate operand.
+    kInst          ///< Sub-instruction operand.
   };
   MachineOperandType Kind = kInvalid;
 
   union {
     unsigned RegVal;
     int64_t ImmVal;
-    double FPImmVal;
+    uint32_t SFPImmVal;
+    uint64_t FPImmVal;
     const MCExpr *ExprVal;
     const MCInst *InstVal;
   };
 
 public:
-  MCOperand() : FPImmVal(0.0) {}
+  MCOperand() : FPImmVal(0) {}
 
   bool isValid() const { return Kind != kInvalid; }
   bool isReg() const { return Kind == kRegister; }
   bool isImm() const { return Kind == kImmediate; }
-  bool isFPImm() const { return Kind == kFPImmediate; }
+  bool isSFPImm() const { return Kind == kSFPImmediate; }
+  bool isDFPImm() const { return Kind == kDFPImmediate; }
   bool isExpr() const { return Kind == kExpr; }
   bool isInst() const { return Kind == kInst; }
 
   /// Returns the register number.
   unsigned getReg() const {
     assert(isReg() && "This is not a register operand!");
     return RegVal;
   }
int64_t getImm() const {
     return ImmVal;
   }
 
   void setImm(int64_t Val) {
     assert(isImm() && "This is not an immediate");
     ImmVal = Val;
   }
 
-  double getFPImm() const {
-    assert(isFPImm() && "This is not an FP immediate");
+  uint32_t getSFPImm() const {
+    assert(isSFPImm() && "This is not an SFP immediate");
+    return SFPImmVal;
+  }
+
+  void setSFPImm(uint32_t Val) {
+    assert(isSFPImm() && "This is not an SFP immediate");
+    SFPImmVal = Val;
+  }
+
+  uint64_t getDFPImm() const {
+    assert(isDFPImm() && "This is not an FP immediate");
     return FPImmVal;
   }
 
-  void setFPImm(double Val) {
-    assert(isFPImm() && "This is not an FP immediate");
+  void setDFPImm(uint64_t Val) {
+    assert(isDFPImm() && "This is not an FP immediate");
     FPImmVal = Val;
   }
 
   const MCExpr *getExpr() const {
     assert(isExpr() && "This is not an expression");
     return ExprVal;
   }
 
public:
 
   static MCOperand createImm(int64_t Val) {
     MCOperand Op;
     Op.Kind = kImmediate;
     Op.ImmVal = Val;
     return Op;
   }
 
-  static MCOperand createFPImm(double Val) {
+  static MCOperand createSFPImm(uint32_t Val) {
+    MCOperand Op;
+    Op.Kind = kSFPImmediate;
+    Op.SFPImmVal = Val;
+    return Op;
+  }
+
+  static MCOperand createDFPImm(uint64_t Val) {
     MCOperand Op;
-    Op.Kind = kFPImmediate;
+    Op.Kind = kDFPImmediate;
     Op.FPImmVal = Val;
     return Op;
   }
 
   static MCOperand createExpr(const MCExpr *Val) {
     MCOperand Op;
     Op.Kind = kExpr;
     Op.ExprVal = Val;

llvm/include/llvm/MC/MCInstBuilder.h

public:
   }
 
   /// Add a new integer immediate operand.
   MCInstBuilder &addImm(int64_t Val) {
     Inst.addOperand(MCOperand::createImm(Val));
     return *this;
   }
 
+  /// Add a new single floating point immediate operand.
+  MCInstBuilder &addSFPImm(uint32_t Val) {
+    Inst.addOperand(MCOperand::createSFPImm(Val));
+    return *this;
+  }
+
   /// Add a new floating point immediate operand.
-  MCInstBuilder &addFPImm(double Val) {
-    Inst.addOperand(MCOperand::createFPImm(Val));
+  MCInstBuilder &addDFPImm(uint64_t Val) {
+    Inst.addOperand(MCOperand::createDFPImm(Val));
     return *this;
   }
 
   /// Add a new MCExpr operand.
   MCInstBuilder &addExpr(const MCExpr *Val) {
     Inst.addOperand(MCOperand::createExpr(Val));
     return *this;
   }

llvm/lib/MC/MCInst.cpp

 void MCOperand::print(raw_ostream &OS) const {
   OS << "<MCOperand ";
   if (!isValid())
     OS << "INVALID";
   else if (isReg())
     OS << "Reg:" << getReg();
   else if (isImm())
     OS << "Imm:" << getImm();
-  else if (isFPImm())
-    OS << "FPImm:" << getFPImm();
+  else if (isSFPImm())
+    OS << "SFPImm:" << bit_cast<float>(getSFPImm());
+  else if (isDFPImm())
+    OS << "DFPImm:" << bit_cast<double>(getDFPImm());
   else if (isExpr()) {
     OS << "Expr:(" << *getExpr() << ")";
   } else if (isInst()) {
     OS << "Inst:(" << *getInst() << ")";
   } else
     OS << "UNDEFINED";
   OS << ">";
 }

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

void AArch64InstPrinter::printBTIHintOp(const MCInst *MI, unsigned OpNum,
   else
     O << '#' << formatImm(btihintop);
 }
 
 void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
                                            const MCSubtargetInfo &STI,
                                            raw_ostream &O) {
   const MCOperand &MO = MI->getOperand(OpNum);
   float FPImm =
-      MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm());
+      MO.isDFPImm() ? bit_cast<double>(MO.getDFPImm()) : AArch64_AM::getFPImmFloat(MO.getImm());
 
   // 8 decimal places are enough to perfectly represent permitted floats.
   O << format("#%.8f", FPImm);
 }
 
 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
   while (Stride--) {
     switch (Reg) {

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

case MCOI::OPERAND_REGISTER:
       // from a disassembler bug.
       O << "/*invalid immediate*/";
       break;
     default:
       // We hit this for the immediate instruction bits that don't yet have a
       // custom printer.
       llvm_unreachable("unexpected immediate operand type");
     }
-  } else if (Op.isFPImm()) {
+  } else if (Op.isDFPImm()) {
+    double Value = bit_cast<double>(Op.getDFPImm());
     // We special case 0.0 because otherwise it will be printed as an integer.
-    if (Op.getFPImm() == 0.0)
+    if (Value == 0.0)
       O << "0.0";
     else {
       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
       int RCID = Desc.OpInfo[OpNo].RegClass;
       unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
       if (RCBits == 32)
-        printImmediate32(FloatToBits(Op.getFPImm()), STI, O);
+        printImmediate32(FloatToBits(Value), STI, O);
       else if (RCBits == 64)
-        printImmediate64(DoubleToBits(Op.getFPImm()), STI, O);
+        printImmediate64(DoubleToBits(Value), STI, O);
       else
         llvm_unreachable("Invalid register class size");
     }
   } else if (Op.isExpr()) {
     const MCExpr *Exp = Op.getExpr();
     Exp->print(O, &MAI);
   } else {
     O << "/*INV_OP*/";
void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
   // This is important for integer literals because
   // -1 is not the same value as neg(1).
   bool NegMnemo = false;
 
   if (InputModifiers & SISrcMods::NEG) {
     if (OpNo + 1 < MI->getNumOperands() &&
         (InputModifiers & SISrcMods::ABS) == 0) {
       const MCOperand &Op = MI->getOperand(OpNo + 1);
-      NegMnemo = Op.isImm() || Op.isFPImm();
+      NegMnemo = Op.isImm() || Op.isDFPImm();
     }
     if (NegMnemo) {
       O << "neg(";
     } else {
       O << '-';
     }
   }
 
case R600::PRED_SEL_OFF:
       break;
 
     default:
       O << getRegisterName(Op.getReg());
       break;
     }
   } else if (Op.isImm()) {
       O << Op.getImm();
-  } else if (Op.isFPImm()) {
+  } else if (Op.isDFPImm()) {
     // We special case 0.0 because otherwise it will be printed as an integer.
-    if (Op.getFPImm() == 0.0)
+    if (Op.getDFPImm() == 0.0)
       O << "0.0";
     else {
-      O << Op.getFPImm();
+      O << bit_cast<double>(Op.getDFPImm());
     }
   } else if (Op.isExpr()) {
     const MCExpr *Exp = Op.getExpr();
     Exp->print(O, &MAI);
   } else {
     O << "/*INV_OP*/";
   }
 }

llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
   if (MO.isExpr()) {
     const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
     if (!C)
       return 255;
 
     Imm = C->getValue();
   } else {
 
-    assert(!MO.isFPImm());
+    assert(!MO.isDFPImm());
 
     if (!MO.isImm())
       return ~0;
 
     Imm = MO.getImm();
   }
 
   switch (OpInfo.OperandType) {

llvm/lib/Target/ARM/ARMMCInstLower.cpp

case MachineOperand::MO_ConstantPoolIndex:
     break;
   case MachineOperand::MO_BlockAddress:
     MCOp = GetSymbolRef(MO, GetBlockAddressSymbol(MO.getBlockAddress()));
     break;
   case MachineOperand::MO_FPImmediate: {
     APFloat Val = MO.getFPImm()->getValueAPF();
     bool ignored;
     Val.convert(APFloat::IEEEdouble(), APFloat::rmTowardZero, &ignored);
-    MCOp = MCOperand::createFPImm(Val.convertToDouble());
+    MCOp = MCOperand::createDFPImm(Val.convertToDouble());
     break;
   }
   case MachineOperand::MO_RegisterMask:
     // Ignore call clobbers.
     return false;
   }
   return true;
 }

llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

if (MO.isReg()) {
     case ARM::Q0:  case ARM::Q1:  case ARM::Q2:  case ARM::Q3:
     case ARM::Q4:  case ARM::Q5:  case ARM::Q6:  case ARM::Q7:
     case ARM::Q8:  case ARM::Q9:  case ARM::Q10: case ARM::Q11:
     case ARM::Q12: case ARM::Q13: case ARM::Q14: case ARM::Q15:
       return 2 * RegNo;
     }
   } else if (MO.isImm()) {
     return static_cast<unsigned>(MO.getImm());
-  } else if (MO.isFPImm()) {
-    return static_cast<unsigned>(APFloat(MO.getFPImm())
-                     .bitcastToAPInt().getHiBits(32).getLimitedValue());
+  } else if (MO.isDFPImm()) {
+    return static_cast<unsigned>(bit_cast<double>(MO.getDFPImm()));
   }
 
   llvm_unreachable("Unable to encode MCOperand!");
 }
 
 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
 bool ARMMCCodeEmitter::
 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg,

llvm/lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp

 
 unsigned AVRMCCodeEmitter::getMachineOpValue(const MCInst &MI,
                                              const MCOperand &MO,
                                              SmallVectorImpl<MCFixup> &Fixups,
                                              const MCSubtargetInfo &STI) const {
   if (MO.isReg()) return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
   if (MO.isImm()) return static_cast<unsigned>(MO.getImm());
 
-  if (MO.isFPImm())
-    return static_cast<unsigned>(APFloat(MO.getFPImm())
-                                     .bitcastToAPInt()
-                                     .getHiBits(32)
-                                     .getLimitedValue());
+  if (MO.isDFPImm())
+    return static_cast<unsigned>(bit_cast<double>(MO.getDFPImm()));
 
   // MO must be an Expr.
   assert(MO.isExpr());
 
   return getExprOpValue(MO.getExpr(), Fixups, STI);
 }
 
 void AVRMCCodeEmitter::emitInstruction(uint64_t Val, unsigned Size,

llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                   SmallVectorImpl<MCFixup> &Fixups,
                   const MCSubtargetInfo &STI) const {
   if (MO.isReg()) {
     unsigned Reg = MO.getReg();
     unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg);
     return RegNo;
   } else if (MO.isImm()) {
     return static_cast<unsigned>(MO.getImm());
-  } else if (MO.isFPImm()) {
-    return static_cast<unsigned>(APFloat(MO.getFPImm())
-        .bitcastToAPInt().getHiBits(32).getLimitedValue());
+  } else if (MO.isDFPImm()) {
+    return static_cast<unsigned>(bit_cast<double>(MO.getDFPImm()));
   }
   // MO must be an Expr.
   assert(MO.isExpr());
   return getExprOpValue(MO.getExpr(),Fixups, STI);
 }
 
 /// Return binary encoding of memory related operand.
 /// If the offset operand requires relocation, record the relocation.

llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp

void addImmOperands(MCInst &Inst, unsigned N) const {
     if (Kind == Integer)
       Inst.addOperand(MCOperand::createImm(Int.Val));
     else if (Kind == Symbol)
       Inst.addOperand(MCOperand::createExpr(Sym.Exp));
     else
       llvm_unreachable("Should be integer immediate or symbol!");
   }
 
-  void addFPImmOperands(MCInst &Inst, unsigned N) const {
+  void addFPImmf32Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     if (Kind == Float)
-      Inst.addOperand(MCOperand::createFPImm(Flt.Val));
+      Inst.addOperand(
+          MCOperand::createSFPImm(bit_cast<uint32_t>(float(Flt.Val))));
+    else
+      llvm_unreachable("Should be float immediate!");
+  }
+
+  void addFPImmf64Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    if (Kind == Float)
+      Inst.addOperand(MCOperand::createDFPImm(bit_cast<uint64_t>(Flt.Val)));
     else
       llvm_unreachable("Should be float immediate!");
   }
 
   void addBrListOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && isBrList() && "Invalid BrList!");
     for (auto Br : BrL.List)
       Inst.addOperand(MCOperand::createImm(Br));

llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp

 template <typename T>
 bool parseImmediate(MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes) {
   if (Size + sizeof(T) > Bytes.size())
     return false;
   T Val = support::endian::read<T, support::endianness::little, 1>(
       Bytes.data() + Size);
   Size += sizeof(T);
   if (std::is_floating_point<T>::value) {
-    MI.addOperand(MCOperand::createFPImm(static_cast<double>(Val)));
+    MI.addOperand(MCOperand::createDFPImm(static_cast<double>(Val)));
   } else {
     MI.addOperand(MCOperand::createImm(static_cast<int64_t>(Val)));
   }
   return true;
 }
 
 Optional<MCDisassembler::DecodeStatus> WebAssemblyDisassembler::onSymbolStart(
     SymbolInfoTy &Symbol, uint64_t &Size, ArrayRef<uint8_t> Bytes,

llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp

else if (WAReg != WebAssemblyFunctionInfo::UnusedReg)
       O << "$push" << WebAssemblyFunctionInfo::getWARegStackId(WAReg);
     else
       O << "$drop";
     // Add a '=' suffix if this is a def.
     if (OpNo < MII.get(MI->getOpcode()).getNumDefs() || IsVariadicDef)
       O << '=';
   } else if (Op.isImm()) {
     O << Op.getImm();
-  } else if (Op.isFPImm()) {
-    const MCInstrDesc &Desc = MII.get(MI->getOpcode());
-    const MCOperandInfo &Info = Desc.OpInfo[OpNo];
-    if (Info.OperandType == WebAssembly::OPERAND_F32IMM) {
-      // TODO: MC converts all floating point immediate operands to double.
-      // This is fine for numeric values, but may cause NaNs to change bits.
-      O << ::toString(APFloat(float(Op.getFPImm())));
-    } else {
-      assert(Info.OperandType == WebAssembly::OPERAND_F64IMM);
-      O << ::toString(APFloat(Op.getFPImm()));
-    }
+  } else if (Op.isSFPImm()) {
+    O << ::toString(APFloat(bit_cast<float>(Op.getSFPImm())));
+  } else if (Op.isDFPImm()) {
+    O << ::toString(APFloat(bit_cast<double>(Op.getDFPImm())));
   } else {
     assert(Op.isExpr() && "unknown operand kind in printOperand");
     // call_indirect instructions have a TYPEINDEX operand that we print
     // as a signature here, such that the assembler can recover this
     // information.
     auto SRE = static_cast<const MCSymbolRefExpr *>(Op.getExpr());
     if (SRE->getKind() == MCSymbolRefExpr::VK_WASM_TYPEINDEX) {
       auto &Sym = static_cast<const MCSymbolWasm &>(SRE->getSymbol());

llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp

if (MO.isReg()) {
           llvm_unreachable("wasm globals should only be accessed symbolicly");
         default:
           encodeULEB128(uint64_t(MO.getImm()), OS);
         }
       } else {
         encodeULEB128(uint64_t(MO.getImm()), OS);
       }
 
-    } else if (MO.isFPImm()) {
-      const MCOperandInfo &Info = Desc.OpInfo[I];
-      if (Info.OperandType == WebAssembly::OPERAND_F32IMM) {
-        // TODO: MC converts all floating point immediate operands to double.
-        // This is fine for numeric values, but may cause NaNs to change bits.
-        auto F = float(MO.getFPImm());
-        support::endian::write<float>(OS, F, support::little);
-      } else {
-        assert(Info.OperandType == WebAssembly::OPERAND_F64IMM);
-        double D = MO.getFPImm();
-        support::endian::write<double>(OS, D, support::little);
-      }
-
+    } else if (MO.isSFPImm()) {
+      uint32_t F = MO.getSFPImm();
+      support::endian::write<uint32_t>(OS, F, support::little);
+    } else if (MO.isDFPImm()) {
+      uint64_t D = MO.getDFPImm();
+      support::endian::write<uint64_t>(OS, D, support::little);
     } else if (MO.isExpr()) {
       const MCOperandInfo &Info = Desc.OpInfo[I];
       llvm::MCFixupKind FixupKind;
       size_t PaddedSize = 5;
       switch (Info.OperandType) {
       case WebAssembly::OPERAND_I32IMM:
         FixupKind = MCFixupKind(WebAssembly::fixup_sleb128_i32);
         break;

llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td

def WebAssemblythrow : SDNode<"WebAssemblyISD::THROW", SDT_WebAssemblyThrow,
                               [SDNPHasChain, SDNPVariadic]>;
 
 //===----------------------------------------------------------------------===//
 // WebAssembly-specific Operands.
 //===----------------------------------------------------------------------===//
 
 // Default Operand has AsmOperandClass "Imm" which is for integers (and
 // symbols), so specialize one for floats:
-def FPImmAsmOperand : AsmOperandClass {
-  let Name = "FPImm";
+class FPImmAsmOperand<ValueType ty> : AsmOperandClass {
+  let Name = "FPImm" # ty;
   let PredicateMethod = "isFPImm";
 }
 
 class FPOperand<ValueType ty> : Operand<ty> {
-  AsmOperandClass ParserMatchClass = FPImmAsmOperand;
+  AsmOperandClass ParserMatchClass = FPImmAsmOperand<ty>;
 }
 
 let OperandNamespace = "WebAssembly" in {
 
 let OperandType = "OPERAND_BASIC_BLOCK" in
 def bb_op : Operand<OtherVT>;
 
 let OperandType = "OPERAND_LOCAL" in

llvm/lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp

case MachineOperand::MO_Immediate: {
           // With typed function references, this will need a case for type
           // index operands.  Otherwise, fall through.
         }
       }
       MCOp = MCOperand::createImm(MO.getImm());
       break;
     }
     case MachineOperand::MO_FPImmediate: {
-      // TODO: MC converts all floating point immediate operands to double.
-      // This is fine for numeric values, but may cause NaNs to change bits.
       const ConstantFP *Imm = MO.getFPImm();
+      const uint64_t BitPattern =
+          Imm->getValueAPF().bitcastToAPInt().getZExtValue();
       if (Imm->getType()->isFloatTy())
-        MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToFloat());
+        MCOp = MCOperand::createSFPImm(static_cast<uint32_t>(BitPattern));
       else if (Imm->getType()->isDoubleTy())
-        MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToDouble());
+        MCOp = MCOperand::createDFPImm(BitPattern);
       else
         llvm_unreachable("unknown floating point immediate type");
       break;
     }
     case MachineOperand::MO_GlobalAddress:
       MCOp = lowerSymbolOperand(MO, GetGlobalAddressSymbol(MO));
       break;
     case MachineOperand::MO_ExternalSymbol:

llvm/test/CodeGen/WebAssembly/immediates.ll

 ; CHECK-LABEL: custom_nan_f32:
 ; CHECK-NEXT: .functype custom_nan_f32 () -> (f32){{$}}
 ; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, -nan:0x6bcdef{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @custom_nan_f32() {
   ret float 0xFFFD79BDE0000000
 }
 
-; TODO: LLVM's MC layer stores f32 operands as host doubles, requiring a
-; conversion, so the bits of the NaN are not fully preserved.
-
 ; CHECK-LABEL: custom_nans_f32:
 ; CHECK-NEXT: .functype custom_nans_f32 () -> (f32){{$}}
-; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, -nan:0x6bcdef{{$}}
+; CHECK-NEXT: f32.const $push[[NUM:[0-9]+]]=, -nan:0x2bcdef{{$}}
 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
 define float @custom_nans_f32() {
   ret float 0xFFF579BDE0000000
 }
 
 ; CHECK-LABEL: negzero_f64:
 ; CHECK-NEXT: .functype negzero_f64 () -> (f64){{$}}
 ; CHECK-NEXT: f64.const $push[[NUM:[0-9]+]]=, -0x0p0{{$}}

llvm/test/CodeGen/WebAssembly/snan_literal.ll

+; RUN: llc < %s --filetype=obj | llvm-objdump -d - | FileCheck %s
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown"
+
+define float @float_sNaN() #0 {
+entry:
+; CHECK: 00 00 a0 7f
+  ret float 0x7ff4000000000000
+}
+
+define float @float_qNaN() #0 {
+entry:
+; CHECK: 00 00 e0 7f
+  ret float 0x7ffc000000000000
+}
+
+
+define double @double_sNaN() #0 {
+entry:
+; CHECK: 00 00 00 00 00 00 f4 7f
+  ret double 0x7ff4000000000000
+}
+
+define double @double_qNaN() #0 {
+entry:
+; CHECK: 00 00 00 00 00 00 fc 7f
+  ret double 0x7ffc000000000000
+}
+

llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp

bool tryDeserializeFPOperand(StringRef String, double &Value) {
     return EndPointer == String.end();
   }
 
   void serializeMCOperand(const MCOperand &MCOperand, raw_ostream &OS) {
     if (MCOperand.isReg()) {
       OS << getRegName(MCOperand.getReg());
     } else if (MCOperand.isImm()) {
       serializeIntegerOperand(OS, MCOperand.getImm());
-    } else if (MCOperand.isFPImm()) {
-      serializeFPOperand(OS, MCOperand.getFPImm());
+    } else if (MCOperand.isDFPImm()) {
+      serializeFPOperand(OS, bit_cast<double>(MCOperand.getDFPImm()));
     } else {
       OS << kInvalidOperand;
     }
   }
 
   MCOperand deserializeMCOperand(StringRef String) {
     assert(!String.empty());
     int64_t IntValue = 0;
     double DoubleValue = 0;
     if (tryDeserializeIntegerOperand(String, IntValue))
       return MCOperand::createImm(IntValue);
     if (tryDeserializeFPOperand(String, DoubleValue))
-      return MCOperand::createFPImm(DoubleValue);
+      return MCOperand::createDFPImm(bit_cast<uint64_t>(DoubleValue));
     if (auto RegNo = getRegNo(String))
       return MCOperand::createReg(*RegNo);
     if (String != kInvalidOperand)
       ErrorStream << "Unknown Operand: '" << String << "'\n";
     return {};
   }
 
   StringRef getInstrName(unsigned InstrNo) {

llvm/tools/llvm-exegesis/lib/MCInstrDescView.cpp

 void DumpMCOperand(const MCRegisterInfo &MCRegisterInfo, const MCOperand &Op,
                    raw_ostream &OS) {
   if (!Op.isValid())
     OS << "Invalid";
   else if (Op.isReg())
     OS << MCRegisterInfo.getName(Op.getReg());
   else if (Op.isImm())
     OS << Op.getImm();
-  else if (Op.isFPImm())
-    OS << Op.getFPImm();
+  else if (Op.isDFPImm())
+    OS << bit_cast<double>(Op.getDFPImm());
+  else if (Op.isSFPImm())
+    OS << bit_cast<float>(Op.getSFPImm());
   else if (Op.isExpr())
     OS << "Expr";
   else if (Op.isInst())
     OS << "SubInst";
 }
 
 void DumpMCInst(const MCRegisterInfo &MCRegisterInfo,
                 const MCInstrInfo &MCInstrInfo, const MCInst &MCInst,

llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp

TEST(BenchmarkResultTest, WriteToAndReadFromDisk) {
   ExitOnError ExitOnErr;
 
   InstructionBenchmark ToDisk;
 
   ToDisk.Key.Instructions.push_back(MCInstBuilder(X86::XOR32rr)
                                         .addReg(X86::AL)
                                         .addReg(X86::AH)
                                         .addImm(123)
-                                        .addFPImm(0.5));
+                                        .addDFPImm(bit_cast<uint64_t>(0.5)));
   ToDisk.Key.Config = "config";
   ToDisk.Key.RegisterInitialValues = {
       RegisterValue{X86::AL, APInt(8, "-1", 10)},
       RegisterValue{X86::AH, APInt(8, "123", 10)}};
   ToDisk.Mode = InstructionBenchmark::Latency;
   ToDisk.CpuName = "cpu_name";
   ToDisk.LLVMTriple = "llvm_triple";
   ToDisk.NumRepetitions = 1;