Consider increasing the default ARM32 max page size to 64k.

[thieta]

Summary

After some discussion on the mailing list: http://lists.llvm.org/pipermail/llvm-dev/2020-April/140549.html I was recommended to open up a Pull Request for changing the default page size on ARM32 in LLD.

The current 4k page size doesn't work if the arm system has a higher page size configured. There are some systems out there that do this and it leads to the binary getting Killed! by the kernel, this is scenario that is hard to debug and a more compatible value might be good as we see adoption of lld go up.

Another thing to consider is that arm32 binaries can be executed on arm64 and there the 64k page size is pretty common. This is what GNU LD considered: https://github.com/bminor/binutils-gdb/commit/7572ca8989ead4c3425a1500bc241eaaeffa2c89

The question to the community is - would the increased compatibility be worth the hassle for the people that would have to tweak it with a option?

Note that the current diff doesn't update the tests to account for the new page size. There are 58 tests failing after this change, but I didn't want to update them all until I know if there is any interest in tweaking this value or not.

[nickdesaulniers]

From the mailing list:

The default page size in GNU ld for arm is 64k so binaries linked with ld
just worked on this device.

Can you help me verify that?

This is what GNU LD considered

But that link is referring to max page size, not the default page size?

[thieta]

Hello Nick,

Maybe I am using the wrong terminology here and in that case I am sorry. What I mean is the default max page size for the arm32 target in lld. Here is the tests I can boil it down to:

Consider hello.c

#include <stdio.h>

int main(int argc, char** argv)
{
  printf("Hello World!\n");
  return 0;
}

I build this three different ways:

With lld no arguments about max page size:

clang --target=arm-linux-gnueabi -march=armv7-a -mthumb -mfloat-abi=soft -mfpu=vfpv3-d16 --sysroot=$TOOLCHAIN_DIR/arm-linux-gnueabi/libc --gcc-toolchain=$TOOLCHAIN_DIR hello.c -o hello-lld -fuse-ld=lld

With ld.bfd:

clang --target=arm-linux-gnueabi -march=armv7-a -mthumb -mfloat-abi=soft -mfpu=vfpv3-d16 --sysroot=$TOOLCHAIN_DIR/arm-linux-gnueabi/libc --gcc-toolchain=$TOOLCHAIN_DIR hello.c -o hello-bfd -fuse-ld=bfd

And finally with lld and max-page-size argument:

clang --target=arm-linux-gnueabi -march=armv7-a -mthumb -mfloat-abi=soft -mfpu=vfpv3-d16 --sysroot=$TOOLCHAIN_DIR/arm-linux-gnueabi/libc --gcc-toolchain=$TOOLCHAIN_DIR hello.c -o hello -fuse-ld=lld -Wl,-max-page-size=0x10000

I copied them over to the device and ran them:

root@WD-EX2100 root # ./hello-bfd
Hello World!
root@WD-EX2100 root # ./hello-lld
Killed
root@WD-EX2100 root # ./hello-lld-max-page
Hello World!
root@WD-EX2100 root #

As you see it works when we set the max-page-size, we can also verify this quickly with readelf:

➜ readelf -a hello-bfd | grep LOAD
  LOAD           0x000000 0x00010000 0x00010000 0x0043c 0x0043c R E 0x10000
  LOAD           0x00043c 0x0002043c 0x0002043c 0x0011c 0x00120 RW  0x10000

➜ readelf -a hello-lld | grep LOAD
  LOAD           0x000000 0x00010000 0x00010000 0x003e4 0x003e4 R   0x1000
  LOAD           0x0003e4 0x000113e4 0x000113e4 0x001cc 0x001cc R E 0x1000
  LOAD           0x0005b0 0x000125b0 0x000125b0 0x000d8 0x000d8 RW  0x1000
  LOAD           0x000688 0x00013688 0x00013688 0x00024 0x00025 RW  0x1000

➜ readelf -a hello-lld-max-page | grep LOAD
  LOAD           0x000000 0x00010000 0x00010000 0x003e4 0x003e4 R   0x10000
  LOAD           0x0003e4 0x000203e4 0x000203e4 0x001cc 0x001cc R E 0x10000
  LOAD           0x0005b0 0x000305b0 0x000305b0 0x000d8 0x000d8 RW  0x10000
  LOAD           0x000688 0x00040688 0x00040688 0x00024 0x00025 RW  0x10000

And just to confirm the device have the following page size configuration:

root@WD-EX2100 root # getconf PAGESIZE
32768

And we can try it on another device with another page size configuration:

root@Netgear-RN102:~# getconf PAGESIZE
4096
root@Netgear-RN102:~# ./hello-lld
Hello World!
root@Netgear-RN102:~# ./hello-bfd
Hello World!
root@Netgear-RN102:~# ./hello-lld-max-page
Hello World!

Hope this was the information you where looking for.

I also uploaded the binaries here: https://artifacts.plex.tv/testing/page_size_tests.tar.gz

[psmith]

Some references:
The GNU ld change to 64k max page size was made in 2014 https://patches.linaro.org/patch/32565/ [RFC] ld/ARM: Increase maximum page size to 64kB
My understanding from conversations at Arm and Linaro was that this was made primarily for the benefit of people running AArch32 executables on a AArch64 kernel built for 64k page sizes. In practice I don't think there ended up being a widely used distribution that simultaneously used 64K page size and offered a 32-bit user space. Ubuntu's decision to use 4k citing compatibility with old Arm v7 binaries https://wiki.ubuntu.com/ARM64/performance

The change to 64k page size for AArch64 in LLD D25079
Android driver forcing 4k page size in AArch64 D55029
Small number of Arm systems using non 4k page size in context of Gold https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=844467

As mentioned on llvm-dev the tests will need updating, I'm sorry this will be a rather tedious job.

My understanding is that Android and ChromeOs are the largest users of LLD on Arm that are most likely to be hurt by any image size changes. It is true that the change to adding a max-page-size in virtual memory rather than aligning to the next max-page-size will have helped mitigate this a bit, but I think we may still see an increase either side of RELRO. I'd very much like to hear from these folks to see if this hurts them, or if they are willing to force 4k alignment in the clang driver and if so how much time do they need to prepare for it?

[srhines]

We (Android Google folks) have an internal thread going on about what implications this might have, but I can say that I am concerned about making this kind of change for ARM Android targets. Even though we manually set a 4KB max page size in our platform builds for 32-bit, we also have to consider the needs of NDK developers (i.e. those folks making native applications/games/etc.). Some of their build configurations might behave very differently with this change, so my current thinking is that 64KB should not be the default for ARM Android targets.

[thieta]

@srhines Thanks for your reply! Would it be enough for you guys to expand this block in clang https://github.com/llvm/llvm-project/blob/master/clang/lib/Driver/ToolChains/Linux.cpp#L256 for Android's usage? Or would a change in lld make more sense?

[jyknight]

In D77330#1959071, @srhines wrote:

We (Android Google folks) have an internal thread going on about what implications this might have, but I can say that I am concerned about making this kind of change for ARM Android targets. Even though we manually set a 4KB max page size in our platform builds for 32-bit, we also have to consider the needs of NDK developers (i.e. those folks making native applications/games/etc.). Some of their build configurations might behave very differently with this change, so my current thinking is that 64KB should not be the default for ARM Android targets.

Can you say more about your concern? I was actually thinking the exact opposite -- that the special-case in the Driver to use 4K pages on Android AArch64 could very likely be removed, now that using the default 64k max-page-size will no longer cause the binary size to increase.

[MaskRay]

In D77330#1960004, @jyknight wrote:

In D77330#1959071, @srhines wrote:

We (Android Google folks) have an internal thread going on about what implications this might have, but I can say that I am concerned about making this kind of change for ARM Android targets. Even though we manually set a 4KB max page size in our platform builds for 32-bit, we also have to consider the needs of NDK developers (i.e. those folks making native applications/games/etc.). Some of their build configurations might behave very differently with this change, so my current thinking is that 64KB should not be the default for ARM Android targets.

Can you say more about your concern? I was actually thinking the exact opposite -- that the special-case in the Driver to use 4K pages on Android AArch64 could very likely be removed, now that using the default 64k max-page-size will no longer cause the binary size to increase.

I am slightly in favor of D77330 because the change will improve consistency with GNU ld, considering that the binary size is not affected by max-page-size at all (since D66749), and I think the patch does not weaken ASLR.
By default there are 4 PT_LOAD segments: R, RX, RW(RELRO) and RW(non-RELRO).
This patch mostly changes p_vaddr/p_paddr of RX, RW(RELRO) and RW(non-RELRO) and thus the distances between two adjacent segments.

My question is now more about whether Android uses -z separate-code and whether Android expects NDK developers (from the context above they seem to be able to enable arbitrary linker scripts and options) to use -z separate-code with -z max-page-size=65536. -z separate-code + -z max-page-size=65536 can waste a lot of bytes (up to 2 * 65536) due to padding. There can be padding before the RX and the RW(RELRO).

Deleting -z max-page-size from the clang driver should have no downside if they don't use -z separate-code.

The only thing that may motivate -z separate-code is probably eXecute-Only Memory (see --execute-only (D49456)) and probably SHF_ARM_PURECODE (rL326207) plus the intention to not share file bytes between R and RX.

[srhines]

So it turns out that the ld shipped in the NDK actually did have the 64KB max-page-size patch, so not taking this patch would change current user behavior. Thanks to @MaskRay for sharing the exact binutils patch we were looking for to verify that it has it. For that reason, this patch should be fine for our 32-bit ARM NDK users. For the platform, we'll see if we should just set the max-page-size back to 4KB explicitly in the build rules, but that shouldn't affect this CL.

In D77330#1960004, @jyknight wrote:

In D77330#1959071, @srhines wrote:

We (Android Google folks) have an internal thread going on about what implications this might have, but I can say that I am concerned about making this kind of change for ARM Android targets. Even though we manually set a 4KB max page size in our platform builds for 32-bit, we also have to consider the needs of NDK developers (i.e. those folks making native applications/games/etc.). Some of their build configurations might behave very differently with this change, so my current thinking is that 64KB should not be the default for ARM Android targets.

Can you say more about your concern? I was actually thinking the exact opposite -- that the special-case in the Driver to use 4K pages on Android AArch64 could very likely be removed, now that using the default 64k max-page-size will no longer cause the binary size to increase.

Android is currently using -z separate-code for AArch64. Upping the default max page size will bloat the binaries even more (it costs us ~17MB alone on our platform image for -z separate-code with the 4KB max-page-size - Google-folk can look at http://b/150506341 for more details on the tradeoffs here). Thanks to @rprichard for pointing out recent changes here so that I hopefully can avoid regressing other size/performance behaviors unintentionally. For removing the special case in Clang, I'll go ahead and hard-code the 4KB max-page-size in aosp, so our behavior won't change with a future toolchain update. That will allow me to remove the driver hack safely. Thanks everyone for the good suggestions here, and for helping simplify things while not causing any unintended side effects.

[srhines]

I should have looked more closely at the AOSP sources, because we already hard-code the expected 4KB max-page-size. We do have some crufty flags that can be cleaned up, so I'll do that instead (https://android-review.googlesource.com/c/platform/build/soong/+/1278815). :) I'll also go ahead and create/test a CL to revert the Clang driver change forcing 4KB max-page-size next week.

[thieta]

So it sounds like I could go ahead and start changing the tests to match this? I can get to it during the weekend I hope. I anyone have a huge objection to this getting merged - let me know asap.

[rprichard]

In D77330#1961215, @srhines wrote:

So it turns out that the ld shipped in the NDK actually did have the 64KB max-page-size patch, so not taking this patch would change current user behavior. Thanks to @MaskRay for sharing the exact binutils patch we were looking for to verify that it has it. For that reason, this patch should be fine for our 32-bit ARM NDK users. For the platform, we'll see if we should just set the max-page-size back to 4KB explicitly in the build rules, but that shouldn't affect this CL.

It's a bit hairier than this. The NDK ships ld.bfd, ld.gold, and ld.lld. The plain "ld" for arm32 is ld.gold, and "ld" for arm64 is ld.bfd. (AFAIK, that inconsistency has existed at least since NDK r10e. We're hoping to switch "ld" to ld.lld soon-ish for all architectures.)

Before the platform switched to lld, I think it was using ld.gold on all architectures.

• For arm32, the NDK ld.gold(default), defaults to a max-page-size of 0x1000, but ld.bfd defaults to 0x10000 instead. (Even upstream arm32 gold looks like it uses 0x1000 still.)
• For arm64, it looks like the NDK ld.bfd(default) has used a max-page-size of 0x10000 since at least r10e, but ld.gold switched from 0x1000 to 0x10000 between r15 and r16.

For arm32, I think a 64KiB max-page-size (on an OS where the pages are actually 4KiB) would create vaddr gaps between each object's segments. It looks like the Bionic loader maps a gap as inaccessible memory, but the kernel loader leaves the gap unmapped, so something else could be mapped into an executable's gap. If another DSO were mapped into that area, perhaps it could break something? (e.g. arm32 C++ exception unwinding can break. That was fixed for Q+, but old platform versions are still unfixed.) Newer devices seem to keep non-fixed mmap VMAs away from the executable's VMAs, though, which avoids the issue.

I think each DSO gap adds another VMA, and I think this change could add up to 3 of them per DSO. (IIRC, VMA usage is a problem because the bookkeeping uses expensive non-pageable kernel memory.) This issue is easy to fix, though, by building the arm32 platform with -z,max-page-size=0x1000. (I checked a 32-bit device's system_server. I saw 318 DSOs, and it looked like a 64KiB max-page-size could add up to 192KiB of vaddr padding per DSO, for a total increase of up to 60MiB of vaddr usage.)

[thieta]

A small ping here.

If I understand it correctly Android build scripts would have to be adjusted if we change this to make sure the 4k max page size is still happening when building the core system libraries. Is that a bigger task so that we can't merge this or would it better with a clang driver change similar to what we do with android aarch64 here:https://github.com/llvm/llvm-project/blob/master/clang/lib/Driver/ToolChains/Linux.cpp#L256 - I am happy to include that in my work if that's something that would make life easier in android land.

I am still trying to find out if this is a change we want to land so that I can start working on the unit tests in that case.

[MaskRay]

I am still in favor of this change:

• Better interoperability with AArch64
• No size difference (for most cases)
• Better compatibility GNU ld>=2014
• We have plenty of approaches to specify -z max-page-size=4096 for Android NDK users
• Importantly, we have a contributor who is willing to fix the 58 tests

git shortlog --after 2014-01-01 -- gold/arm.cc says there has been very little activity. I don't want us to be locked down by decisions in gold due to lack of maintenance.

[rprichard]

Yeah, the change seems OK to me. I think we want Android to continue using a 4K max-page-size, though.

clang driver change similar to what we do with android aarch64 here:https://github.com/llvm/llvm-project/blob/master/clang/lib/Driver/ToolChains/Linux.cpp#L256

That seems fine to me.

[srhines]

I agree with Ryan. Please update the Clang driver for this to pass this same flag for 32-bit ARM as we already pass for AArch64.

[MaskRay]

In D77330#1968854, @srhines wrote:

I agree with Ryan. Please update the Clang driver for this to pass this same flag for 32-bit ARM as we already pass for AArch64.

I'll do it :/ D77746. The original description was outdated and I want to make some amendment to the test as well.

[thieta]

I have started working on the tests - I have 17 left to do - but since the diff is going to be big I thought I wanted to upload this for now and start collecting feedback to make sure I am doing the right things here.

To be honest - I am not that well versed with the inner workings and the assembler that I am modifying here - I understand the alignments and addresses needs to change but not always why. But I am slowly working through it - please let me know if I am messing anything up here.

[thieta]

lld/test/ELF/arm-thumb-interwork-abs.s

31

This looked a bit strange to me as I was working through this test. I am not sure if the -57352 is correct here it seems like a very large negative number which is not something I usually see in the other files. If anyone can double check it it would be great.

[psmith]

I can check this over, but I'll have to do it in my spare time after work so it may take some time to go through it all. I should be able to answer any specific questions without too much delay though so feel free to ask if there is anything that isn't clear? I'll be/am on Easter break right now, will probably be Tuesday before I can check again.

lld/test/ELF/arm-adr.s

85

Apologies in advance for being a pain. Please could you fix up the comments? PC-relative Arm and Thumb instructions can be a bit strange if you aren't used to them, as the PC-bias of 8 on Arm and 4 on Thumb needs to be accounted for. I wrote a comment hand evaluating the instructions in a lot of these cases to show that the disassembled immediate was correct.

I would hope in the majority of cases, like this one, the fix up is relatively straightforward.

There will be more than just this test affected, at this stage I won't highlight each one. In most of the tests the comments are identified as / although this is a relatively new convention that may not exist older tests. When updating the comment please could you start with / rather than //? The reason behind the convention is so that it is easier to pick up comments from FileCheck lines.

lld/test/ELF/arm-thumb-interwork-abs.s

31

The offset looks good to me. The symbol "sym" is defined via defsym to be 0x13001 which is higher than the call site with 4k pages, but lower when using 64k pages. Given that 0x21000 = 135168 in decimal a hand evaluation of the B instruction gives me 135168 + 8 - 57352 = 0x13000 which is what we'd expect the destination address to be for a Thumb defsym of 0x13001.

[thieta]

lld/test/ELF/arm-adr.s

85

No problem - I can update the tests.

I am a bit confused about the comment about / - did you mean that comments should have three slashes first? or just one? Some tests seems to have comments with /// but I don't see anything with / and this also seems to annoy lit. So I am going to guess you mean /// - let me know if that's the wrong assumption.

lld/test/ELF/arm-thumb-interwork-abs.s

31

Thanks for the clarification.

[thieta]

lld/test/ELF/arm-branch-rangethunk.s

12

@psmith - I just remembered that I didn't get this test to work. @MaskRay told me that the Inputs/far-long-arm-abs.s had to be updated as well - but can't say I am sure how exactly.

So if anyone could show me the exact values or how to calculate them in the input file that would be very helpful.

[psmith]

lld/test/ELF/arm-adr.s

85

Yes you've got it right; I meant 3 /// to start a non FileCheck comment.

/// 0x11808 + 0x8 + 0x400 = 0x11c10 = dat3

There are likely to be older tests that don't follow the new-ish convention, if you have to modify any of them it would be great to update them to follow the new convention.

lld/test/ELF/arm-branch-rangethunk.s

12

Looking at the numbers in far-arm-abs.s and far-long-arm-abs.s the values of the symbols are:
far-arm-abs.s

too_far1 0x2020008
too_far2 0x202000c
too_far3 0x2020010

far-long-arm-abs.s

too_far1 0x2020014
too_far2 0x2020018
too_far3 0x202001c

The address of the first branch in the old disassembly is 0x20000, for far-arm-abs.s the offset is therefore 0x2020008 - 0x20000 = 0x2000008 which including the 8 byte pc-bias is just out of range of the maximum branch displacement. The short thunks can just about reach these addresses if placed after .text. In far-long-arm-abs.s the addresses are 0x2020014 - 0x20000 = 0x2000014 which is just out of range of the short thunk, but is in range of the long-thunk.

I think that if you alter the addresses of too_far* symbols such that the offset from the first branch instruction matches 0x2000008 for far-arm-abs.s and 0x2000014 for far-long-arm-abs.s then this should work.

While not strictly necessary, there is an opportunity for a small cleanup. The far symbol in far-arm-abs.s is not used by this test, only arm-branch.s. The far symbol in far-long-arm-abs.s is not used at all by any test. It may be worth splitting out far-arm-abs.s into two files?
far-arm-abs.s just contains the symbol far and is used by arm-branch.s
far-arm-short-abs.s contains the too_far* symbols from far-arm-abs.s
far-arm-long-abs.s // contains the too_far* symbols from far-long-arm-abs.s with far removed.

[thieta]

This adjusts the comments as suggested by @psmith and addresses all the tests except the following three:

lld :: ELF/arm-branch-rangethunk.s
lld :: ELF/arm-thunk-largesection.s
lld :: ELF/arm-thunk-multipass-plt.s

I am not able to get them to pass and would like some help to get them to work. Otherwise I hope this is more or less done. It's been kind of a slog getting through the tests but hopefully I did it correctly :)

[thieta]

Oh I see that there are some files I forgot to update the comments to have /// - I'll revisit them later this week.

[psmith]

In D77330#1983784, @thieta wrote:

This adjusts the comments as suggested by @psmith and addresses all the tests except the following three:

lld :: ELF/arm-branch-rangethunk.s
lld :: ELF/arm-thunk-largesection.s
lld :: ELF/arm-thunk-multipass-plt.s

I am not able to get them to pass and would like some help to get them to work. Otherwise I hope this is more or less done. It's been kind of a slog getting through the tests but hopefully I did it correctly :)

I'll take a look although it may take some time to go through these. May report back after I've looked at each one.

[psmith]

I've uploaded a fixed arm-branch-rangethunks.s

D77330.diff4 KBDownload

I took out the modification to raise the .balign to 0x20000 as I don't think it is necessary. I updated the comment and used --no-show-raw-insn in objdump -d as this makes it easier to read. Apart from that the only difference is that the .text section starts at 0x30000 instead of 0x20000 so I needed to add 0x10000 to the far-arm-abs.s and far-long-arm.s values. Can you check the attachment works and add it to the patch?

I'll try and get to the other 2 failing tests later this week or the weekend.

[thieta]

I have applied @psmith changes to arm-branch-rangethunk.s and reworked arm-branch.s to work with the changes above.

[thieta]

we are now only down to two failing tests:

Failing Tests (2):
  lld :: ELF/arm-thunk-largesection.s
  lld :: ELF/arm-thunk-multipass-plt.s

lld/test/ELF/arm-branch-rangethunk.s

12

This test passes now 🎉

[psmith]

D77330-fixup2.diff10 KBDownload

Attaching a diff that will fix the other 2 tests. The arm-thunk-multipass-plt.s has a .got.plt that is more heavily aligned so the PLT entries needed adjusting. The arm-thunk-largesection.s needed the section start and stop addresses adjusting for a higher start address. Can you check that these work and re-upload. I'll then do a run through all the tests to see if I can spot anything else.

[thieta]

This applies the latest patch from @psmith which means that all the tests now passes! 🎉

[thieta]

@psmith This worked! All patches is now passing with the latest diff. I did a quick rebase as well - no conflicts.

[MaskRay]

Thanks!

[psmith]

LGTM too, I'd be lying if I said I checked every one of the numbers, but I think the overall test changes are consistent with changing the page size. There are a couple of files arm-plt-reloc.s and arm-thumb-plt-reloc.s where there are some comments that could be made /, if you've got the time to fix prior to committing then great. I don't think that is important enough to hold up the patch though, I appreciate the amount of work that you've put in.

[thieta]

Thanks guys - I don't have commit access. So could anyone of you commit this? Please use my email address [e-mail] if you commit as another author.

[nickdesaulniers]

Hmm...seems to have regressed ARMv5 Linux kernel boots according to a bisection from @nathanchance (https://groups.google.com/g/clang-built-linux/c/aKDK-N6JN4g)

[psmith]

In D77330#1994680, @nickdesaulniers wrote:

Hmm...seems to have regressed ARMv5 Linux kernel boots according to a bisection from @nathanchance (https://groups.google.com/g/clang-built-linux/c/aKDK-N6JN4g)

I don't think that URL is publicly visible.

In theory increasing the max page size shouldn't have changed anything significant, especially given that ld.bfd defaults to the same page size, it may have flushed out another bug though. Would it be possible to raise a PR with a reproducer?

[MaskRay]

In D77330#1994680, @nickdesaulniers wrote:

Hmm...seems to have regressed ARMv5 Linux kernel boots according to a bisection from @nathanchance (https://groups.google.com/g/clang-built-linux/c/aKDK-N6JN4g)

@nathnchance Add -z max-page-size=4096 TO LDFLAGS (-z is also a recognized gcc/clang driver option) to restore the previous behavior. But as Peter said, this change likely flushed out another bug.

(I made a typo in the commit subject 6536->65536, sorry :) )

[nathanchance]

In D77330#1994737, @psmith wrote:

In D77330#1994680, @nickdesaulniers wrote:

Hmm...seems to have regressed ARMv5 Linux kernel boots according to a bisection from @nathanchance (https://groups.google.com/g/clang-built-linux/c/aKDK-N6JN4g)

I don't think that URL is publicly visible.

I don't know why that started happening :/

In theory increasing the max page size shouldn't have changed anything significant, especially given that ld.bfd defaults to the same page size, it may have flushed out another bug though. Would it be possible to raise a PR with a reproducer?

Done: https://bugs.llvm.org/show_bug.cgi?id=45632

Feel free to ping me for more information/debugging as needed.

[grimar]

In D77330#1995415, @nathanchance wrote:

In D77330#1994737, @psmith wrote:

In D77330#1994680, @nickdesaulniers wrote:

Hmm...seems to have regressed ARMv5 Linux kernel boots according to a bisection from @nathanchance (https://groups.google.com/g/clang-built-linux/c/aKDK-N6JN4g)

I don't think that URL is publicly visible.

I don't know why that started happening :/

I think we saw such issue before. That time I think the URL of a page from incognito mode worked (i.e. a different URL to the same page).

[srhines]

In D77330#1996255, @grimar wrote:

In D77330#1995415, @nathanchance wrote:

In D77330#1994737, @psmith wrote:

In D77330#1994680, @nickdesaulniers wrote:

Hmm...seems to have regressed ARMv5 Linux kernel boots according to a bisection from @nathanchance (https://groups.google.com/g/clang-built-linux/c/aKDK-N6JN4g)

I don't think that URL is publicly visible.

I don't know why that started happening :/

I think we saw such issue before. That time I think the URL of a page from incognito mode worked (i.e. a different URL to the same page).

https://groups.google.com/forum/#!topic/clang-built-linux/aKDK-N6JN4g is the publicly visible version of that page. I'm not quite sure why it works this way, but it wasn't too hard for me to find it. Thanks for pointing out that it should be visible even in incognito.

[psmith]

In D77330#1995415, @nathanchance wrote:

In D77330#1994737, @psmith wrote:

In D77330#1994680, @nickdesaulniers wrote:

Hmm...seems to have regressed ARMv5 Linux kernel boots according to a bisection from @nathanchance (https://groups.google.com/g/clang-built-linux/c/aKDK-N6JN4g)

I don't think that URL is publicly visible.

I don't know why that started happening :/

In theory increasing the max page size shouldn't have changed anything significant, especially given that ld.bfd defaults to the same page size, it may have flushed out another bug though. Would it be possible to raise a PR with a reproducer?

Done: https://bugs.llvm.org/show_bug.cgi?id=45632

Feel free to ping me for more information/debugging as needed.

Thanks for the PR. The change to the pagesize to 64k, along with the lowest starting address of 0xc0008000 has meant that LLD now thinks it can add allocate the headers, ELF header and PT_PHDR in the first loadable segment. Other than that the only changes are the alignments of the program segments. At this point I don't know what is causing the problem. It is possible that the PT_PHDR and the extra program segment are confusing the boot-loader /compressor/decompressor.

ld.bfd with its 64k page size has a very different strategy for generating program headers. It generates 3 large program headers whereas LLD generates many smaller ones. I've put more details in the PR.

Anyhow I'm pretty sure that we've just flushed out another problem/difference between how LLD and BFD handle linker scripts that has turned out to cause a problem.

lld/ELF/Arch/ARM.cpp

ARM::ARM() {
   tlsModuleIndexRel = R_ARM_TLS_DTPMOD32;
   tlsOffsetRel = R_ARM_TLS_DTPOFF32;
   gotBaseSymInGotPlt = false;
   pltHeaderSize = 32;
   pltEntrySize = 16;
   ipltEntrySize = 16;
   trapInstr = {0xd4, 0xd4, 0xd4, 0xd4};
   needsThunks = true;
+  defaultMaxPageSize = 65536;
 }
 
 uint32_t ARM::calcEFlags() const {
   // The ABIFloatType is used by loaders to detect the floating point calling
   // convention.
   uint32_t abiFloatType = 0;
   if (config->armVFPArgs == ARMVFPArgKind::Base ||
       config->armVFPArgs == ARMVFPArgKind::Default)

lld/test/ELF/arm-abs32-dyn.s

 // a writable section.
  .word bar(target1)
 
 // RUN: ld.lld -shared -o %t.so %t.o
 // RUN: llvm-readobj --symbols --dyn-relocations %t.so | FileCheck %s
 // RUN: llvm-readelf -x .data %t.so | FileCheck --check-prefix=HEX %s
 
 // CHECK:      Dynamic Relocations {
-// CHECK-NEXT:   0x3204 R_ARM_RELATIVE
-// CHECK-NEXT:   0x3208 R_ARM_RELATIVE
-// CHECK-NEXT:   0x3200 R_ARM_ABS32 foo 0x0
+// CHECK-NEXT:   0x30204 R_ARM_RELATIVE
+// CHECK-NEXT:   0x30208 R_ARM_RELATIVE
+// CHECK-NEXT:   0x30200 R_ARM_ABS32 foo 0x0
 // CHECK-NEXT: }
 
 // CHECK:      Symbols [
 // CHECK:        Symbol {
 // CHECK:          Name: bar
-// CHECK-NEXT:     Value: 0x11A8
+// CHECK-NEXT:     Value: 0x101A8
 
 // CHECK:        Symbol {
 // CHECK:          Name: foo
-// CHECK-NEXT:     Value: 0x11A8
+// CHECK-NEXT:     Value: 0x101A8
 
-// HEX: 0x00003200 00000000 a8110000 a8110000
+// HEX: 0x00030200 00000000 a8010100 a8010100

lld/test/ELF/arm-adr.s

  bx lr
 
  .section .os6, "ax", %progbits
  .type afunc, %function
  .balign 4
 afunc:
  bx lr
 
-// CHECK:      00011410 <dat1>:
-// CHECK-NEXT: 11410: andeq   r0, r0, r0
+// CHECK:      00020410 <dat1>:
+// CHECK-NEXT: 20410: andeq   r0, r0, r0
 
-// CHECK:      00011414 <dat2>:
-// CHECK-NEXT: 11414: andeq   r0, r0, r0
+// CHECK:      00020414 <dat2>:
+// CHECK-NEXT: 20414: andeq   r0, r0, r0
 
-// CHECK:     00011800 <_start>:
+// CHECK:     00020800 <_start>:
 /// 0x11800 + 0x8 - 0x3f8 = 0x11410 = dat1
-// CHECK-NEXT: 11800: sub     r0, pc, #1016
+// CHECK-NEXT: 20800: sub     r0, pc, #1016
 /// 0x11804 + 0x8 - 0x3f8 = 0x11414 = dat2
-// CHECK-NEXT: 11804: sub     r0, pc, #1016
+// CHECK-NEXT: 20804: sub     r0, pc, #1016
 /// 0x11808 + 0x8 + 0x400 = 0x11c10 = dat3
-// CHECK-NEXT: 11808: add     r0, pc, #1024
+// CHECK-NEXT: 20808: add     r0, pc, #1024
 /// 0x1180c + 0x8 + 0x400 = 0x11c14 = dat4
-// CHECK-NEXT: 1180c: add     r0, pc, #1024
+// CHECK-NEXT: 2080c: add     r0, pc, #1024
 
-// CHECK:      00011c10 <dat3>:
-// CHECK-NEXT: 11c10: andeq   r0, r0, r0
+// CHECK:      00020c10 <dat3>:
+// CHECK-NEXT: 20c10: andeq   r0, r0, r0
 
-// CHECK:      00011c14 <dat4>:
-// CHECK-NEXT: 11c14: andeq   r0, r0, r0
+// CHECK:      00020c14 <dat4>:
+// CHECK-NEXT: 20c14: andeq   r0, r0, r0
 
-// CHECK:      00011c18 <tfunc>:
-// CHECK-NEXT: 11c18: bx      lr
+// CHECK:      00020c18 <tfunc>:
+// CHECK-NEXT: 20c18: bx      lr
 
-// CHECK:      00011c1c <arm_func>:
+// CHECK:      00020c1c <arm_func>:
 /// 0x11c1c + 0x8 - 0xb = 11c19 = tfunc
-// CHECK-NEXT: 11c1c: sub     r0, pc, #11
+// CHECK-NEXT: 20c1c: sub     r0, pc, #11
 /// 0x11c20 + 0x8 = 0x11c28 = afunc
-// CHECK-NEXT: 11c20: add     r0, pc, #0
-// CHECK-NEXT: 11c24: bx      lr
+// CHECK-NEXT: 20c20: add     r0, pc, #0
+// CHECK-NEXT: 20c24: bx      lr
 
-// CHECK:      00011c28 <afunc>:
-// CHECK-NEXT: 11c28: bx      lr
+// CHECK:      00020c28 <afunc>:
+// CHECK-NEXT: 20c28: bx      lr

lld/test/ELF/arm-bl-v6.s

 // REQUIRES: arm
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv6-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t -o %t2
-// RUN: llvm-objdump -d --triple=armv6-none-linux-gnueabi --start-address=0x12000 --stop-address=0x12008 %t2 | FileCheck --check-prefix=CHECK-ARM1 %s
-// RUN: llvm-objdump -d --triple=thumbv6-none-linux-gnueabi %t2 --start-address=0x12008 --stop-address=0x1200c | FileCheck --check-prefix=CHECK-THUMB1 %s
-// RUN: llvm-objdump -d --triple=armv6-none-linux-gnueabi --start-address=0x21200c --stop-address=0x212014 %t2 | FileCheck --check-prefix=CHECK-ARM2 %s
-// RUN: llvm-objdump -d --triple=thumbv6-none-linux-gnueabi %t2 --start-address=0x613000 --stop-address=0x613002 | FileCheck --check-prefix=CHECK-THUMB2 %s
+// RUN: llvm-objdump -d --triple=armv6-none-linux-gnueabi --start-address=0x21000 --stop-address=0x21008 %t2 | FileCheck --check-prefix=CHECK-ARM1 %s
+// RUN: llvm-objdump -d --triple=thumbv6-none-linux-gnueabi %t2 --start-address=0x21008 --stop-address=0x2100c | FileCheck --check-prefix=CHECK-THUMB1 %s
+// RUN: llvm-objdump -d --triple=armv6-none-linux-gnueabi --start-address=0x22100c --stop-address=0x221014 %t2 | FileCheck --check-prefix=CHECK-ARM2 %s
+// RUN: llvm-objdump -d --triple=thumbv6-none-linux-gnueabi %t2 --start-address=0x622000 --stop-address=0x622002 | FileCheck --check-prefix=CHECK-THUMB2 %s
 
 // On Arm v6 the range of a Thumb BL instruction is only 4 megabytes as the
 // extended range encoding is not supported. The following example has a Thumb
 // BL that is out of range on ARM v6 and requires a range extension thunk.
 // As v6 does not support MOVT or MOVW instructions the Thunk must not
 // use these instructions either.
 
 
 // ARM v6 supports blx so we shouldn't see the blx not supported warning.
 // CHECK-NOT: warning: lld uses blx instruction, no object with architecture supporting feature detected.
  .text
  .syntax unified
  .cpu    arm1176jzf-s
  .globl _start
  .type   _start,%function
  .balign 0x1000
 _start:
   bl thumbfunc
   bx lr
 
 // CHECK-ARM1: Disassembly of section .text:
 // CHECK-ARM1-EMPTY:
 // CHECK-ARM1-NEXT: <_start>:
-// CHECK-ARM1-NEXT:    12000:   00 00 00 fa     blx     #0 <thumbfunc>
-// CHECK-ARM1-NEXT:    12004:   1e ff 2f e1     bx      lr
+// CHECK-ARM1-NEXT:    21000:   00 00 00 fa     blx     #0 <thumbfunc>
+// CHECK-ARM1-NEXT:    21004:   1e ff 2f e1     bx      lr
  .thumb
  .section .text.2, "ax", %progbits
  .globl thumbfunc
  .type thumbfunc,%function
 thumbfunc:
  bl farthumbfunc
 
 // CHECK-THUMB1: <thumbfunc>:
-// CHECK-THUMB1-NEXT:    12008: 00 f2 00 e8   blx #2097152
+// CHECK-THUMB1-NEXT:    21008: 00 f2 00 e8   blx #2097152
 // 6 Megabytes, enough to make farthumbfunc out of range of caller
 // on a v6 Arm, but not on a v7 Arm.
 
  .section .text.3, "ax", %progbits
  .space 0x200000
 // CHECK-ARM2: <__ARMv5ABSLongThunk_farthumbfunc>:
-// CHECK-ARM2-NEXT:   21200c:   04 f0 1f e5     ldr     pc, [pc, #-4]
+// CHECK-ARM2-NEXT:   22100c:   04 f0 1f e5     ldr     pc, [pc, #-4]
 // CHECK-ARM2: <$d>:
-// CHECK-ARM2-NEXT:   212010:   01 30 61 00     .word   0x00613001
+// CHECK-ARM2-NEXT:   221010:   01 20 62 00     .word   0x00622001
  .section .text.4, "ax", %progbits
  .space 0x200000
 
  .section .text.5, "ax", %progbits
  .space 0x200000
 
  .thumb
  .section .text.6, "ax", %progbits
  .balign 0x1000
  .globl farthumbfunc
  .type farthumbfunc,%function
 farthumbfunc:
  bx lr
 // CHECK-THUMB2: <farthumbfunc>:
-// CHECK-THUMB2-NEXT:   613000:        70 47   bx      lr
+// CHECK-THUMB2-NEXT:   622000:        70 47   bx      lr

lld/test/ELF/arm-branch-rangethunk.s

 // REQUIRES: arm
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/far-arm-abs.s -o %tfar
 // RUN: ld.lld  %t %tfar -o %t2
 // RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t2 | FileCheck --check-prefix=SHORT %s
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/far-long-arm-abs.s -o %tfarlong
 // RUN: ld.lld  %t %tfarlong -o %t3
 // RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi %t3 | FileCheck --check-prefix=LONG %s
  .syntax unified
  .section .text, "ax",%progbits
  .globl _start
- .balign 0x10000
+ .balign 0x20000
  .type _start,%function
 _start:
  // address of too_far symbols are just out of range of ARM branch with
  // 26-bit immediate field and an addend of -8
  bl  too_far1
  b   too_far2
  beq too_far3
 

lld/test/ELF/arm-branch-undef-weak-plt-thunk.s

 // REQUIRES: arm
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %S/Inputs/arm-shared.s -o %t1.o
 // RUN: ld.lld %t1.o --shared -soname=t1.so -o %t1.so
 // RUN: llvm-mc -arm-add-build-attributes -filetype=obj -triple=armv7a-none-linux-gnueabi %s -o %t.o
 // RUN: ld.lld %t.o %t1.so -o %t
-// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi --start-address=0x111e4 --stop-address=0x11204 %t | FileCheck %s
+// RUN: llvm-objdump -d --triple=armv7a-none-linux-gnueabi --start-address=0x201e4 --stop-address=0x20204 %t | FileCheck %s
 
 // When we are dynamic linking, undefined weak references have a PLT entry so
 // we must create a thunk for the branch to the PLT entry.
 
  .text
  .globl bar2
  .weak undefined_weak_we_expect_a_plt_entry_for
 _start:
  .globl _start
  .type _start, %function
  b undefined_weak_we_expect_a_plt_entry_for
  bl bar2
 // Create 32 Mb gap between the call to the weak reference and the PLT so that
 // the b and bl need a range-extension thunk.
  .section .text.1, "ax", %progbits
  .space 32 * 1024 * 1024
 
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <_start>:
-// CHECK-NEXT:    111e4:       00 00 00 ea     b       #0 <__ARMv7ABSLongThunk_undefined_weak_we_expect_a_plt_entry_for>
-// CHECK-NEXT:    111e8:       02 00 00 eb     bl      #8 <__ARMv7ABSLongThunk_bar2>
+// CHECK-NEXT:    201e4:       00 00 00 ea     b       #0 <__ARMv7ABSLongThunk_undefined_weak_we_expect_a_plt_entry_for>
+// CHECK-NEXT:    201e8:       02 00 00 eb     bl      #8 <__ARMv7ABSLongThunk_bar2>
 // CHECK: <__ARMv7ABSLongThunk_undefined_weak_we_expect_a_plt_entry_for>:
-// CHECK-NEXT:    111ec:        30 c2 01 e3     movw    r12, #4656
-// CHECK-NEXT:    111f0:        01 c2 40 e3     movt    r12, #513
-// CHECK-NEXT:    111f4:        1c ff 2f e1     bx      r12
+// CHECK-NEXT:    201ec:        30 c2 00 e3     movw    r12, #560
+// CHECK-NEXT:    201f0:        02 c2 40 e3     movt    r12, #514
+// CHECK-NEXT:    201f4:        1c ff 2f e1     bx      r12
 // CHECK: <__ARMv7ABSLongThunk_bar2>:
-// CHECK-NEXT:    111f8:        40 c2 01 e3     movw    r12, #4672
-// CHECK-NEXT:    111fc:        01 c2 40 e3     movt    r12, #513
-// CHECK-NEXT:    11200:        1c ff 2f e1     bx      r12
+// CHECK-NEXT:    201f8:        40 c2 00 e3     movw    r12, #576
+// CHECK-NEXT:    201fc:        02 c2 40 e3     movt    r12, #514
+// CHECK-NEXT:    20200:        1c ff 2f e1     bx      r12

lld/test/ELF/arm-copy.s

  .word z
 
 // CHECK:     Name: .bss
 // CHECK-NEXT:     Type: SHT_NOBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
 // CHECK-NEXT:       SHF_WRITE
 // CHECK-NEXT:     ]
-// CHECK-NEXT:     Address: 0x13220
+// CHECK-NEXT:     Address: 0x40220
 // CHECK-NEXT:     Offset:
 // CHECK-NEXT:     Size: 8
 // CHECK-NEXT:     Link:
 // CHECK-NEXT:     Info:
 // CHECK-NEXT:     AddressAlignment: 16
 
 // CHECK: Relocations [
 // CHECK-NEXT:  Section {{.*}} .rel.dyn {
 // CHECK-NEXT:    Relocation {
-// CHECK-NEXT:      Offset: 0x13220
+// CHECK-NEXT:      Offset: 0x40220
 // CHECK-NEXT:      Type: R_ARM_COPY
 // CHECK-NEXT:      Symbol: y
 // CHECK-NEXT:      Addend: 0x0
 // CHECK-NEXT:    }
 // CHECK-NEXT:    Relocation {
-// CHECK-NEXT:      Offset: 0x13224
+// CHECK-NEXT:      Offset: 0x40224
 // CHECK-NEXT:      Type: R_ARM_COPY
 // CHECK-NEXT:      Symbol: z
 // CHECK-NEXT:      Addend: 0x0
 // CHECK-NEXT:    }
 // CHECK-NEXT:  }
 
 // CHECK: Symbols [
 // CHECK:     Name: y
-// CHECK-NEXT:    Value: 0x13220
+// CHECK-NEXT:    Value: 0x40220
 // CHECK-NEXT:    Size: 4
 // CHECK-NEXT:    Binding: Global
 // CHECK-NEXT:    Type: Object
 // CHECK-NEXT:    Other:
 // CHECK-NEXT:    Section: .bss
 // CHECK:    Name: z
-// CHECK-NEXT:    Value: 0x13224
+// CHECK-NEXT:    Value: 0x40224
 // CHECK-NEXT:    Size: 4
 // CHECK-NEXT:    Binding: Global
 // CHECK-NEXT:    Type: Object
 // CHECK-NEXT:    Other: 0
 // CHECK-NEXT:    Section: .bss
 
 // CODE: Disassembly of section .text:
 // CODE-EMPTY:
 // CODE-NEXT: <_start>:
 // S + A = 0x13220 + 0 = 65536 * 1 + 12832
-// CODE-NEXT:   111b4:       movw    r2, #12832
-// CODE-NEXT:   111b8:       movt    r2, #1
-// CODE-NEXT:   111bc:       ldr     r3, [pc, #4]
-// CODE-NEXT:   111c0:       ldr     r3, [r3]
+// CODE-NEXT:   201b4:       movw    r2, #544
+// CODE-NEXT:   201b8:       movt    r2, #4
+// CODE-NEXT:   201bc:       ldr     r3, [pc, #4]
+// CODE-NEXT:   201c0:       ldr     r3, [r3]
 
 
 // RODATA: Contents of section .rodata:
 // S(z) = 0x13004
-// RODATA-NEXT: 101b0 24320100
+// RODATA-NEXT: 101b0 24020400

lld/test/ELF/arm-execute-only.s

 // REQUIRES: arm
 
 // RUN: llvm-mc -filetype=obj -triple=armv7-pc-linux %s -o %t.o
 // RUN: ld.lld %t.o -o %t.so -shared
 // RUN: llvm-readelf -l %t.so | FileCheck --implicit-check-not=LOAD %s
 
 // RUN: echo ".section .foo,\"ax\"; \
 // RUN:       bx lr" > %t.s
 // RUN: llvm-mc -filetype=obj -triple=armv7-pc-linux %t.s -o %t2.o
 // RUN: ld.lld %t.o %t2.o -o %t.so -shared
 // RUN: llvm-readelf -l %t.so | FileCheck --check-prefix=DIFF --implicit-check-not=LOAD %s
 
-// CHECK:      LOAD           0x000000 0x00000000 0x00000000 0x0016d 0x0016d  R 0x1000
-// CHECK:      LOAD           0x000170 0x00001170 0x00001170 0x{{.*}} 0x{{.*}} R E 0x1000
-// CHECK:      LOAD           0x000174 0x00002174 0x00002174 0x{{.*}} 0x{{.*}}   E 0x1000
-// CHECK:      LOAD           0x000178 0x00003178 0x00003178 0x00038  0x00038  RW  0x1000
+// CHECK:      LOAD           0x000000 0x00000000 0x00000000 0x0016d 0x0016d  R 0x10000
+// CHECK:      LOAD           0x000170 0x00010170 0x00010170 0x{{.*}} 0x{{.*}} R E 0x10000
+// CHECK:      LOAD           0x000174 0x00020174 0x00020174 0x{{.*}} 0x{{.*}}   E 0x10000
+// CHECK:      LOAD           0x000178 0x00030178 0x00030178 0x00038  0x00038  RW  0x10000
 
 // CHECK: 01     .dynsym .gnu.hash .hash .dynstr
 // CHECK: 02     .text
 // CHECK: 03     .foo
 // CHECK: 04     .dynamic
 
-// DIFF:      LOAD           0x000000 0x00000000 0x00000000 0x0014d 0x0014d R   0x1000
-// DIFF:      LOAD           0x000150 0x00001150 0x00001150 0x0000c 0x0000c R E 0x1000
-// DIFF:      LOAD           0x00015c 0x0000215c 0x0000215c 0x00038 0x00038 RW  0x1000
+// DIFF:      LOAD           0x000000 0x00000000 0x00000000 0x0014d 0x0014d R   0x10000
+// DIFF:      LOAD           0x000150 0x00010150 0x00010150 0x0000c 0x0000c R E 0x10000
+// DIFF:      LOAD           0x00015c 0x0002015c 0x0002015c 0x00038 0x00038 RW  0x10000
 
 // DIFF: 01     .dynsym .gnu.hash .hash .dynstr
 // DIFF: 02     .text .foo
 // DIFF: 03     .dynamic
 
         bx lr
         .section .foo,"axy"
         bx lr

lld/test/ELF/arm-exidx-add-missing.s

f3:
         // Dummy implementation of personality routines to satisfy reference
         // from exception tables, linker will generate EXIDX_CANTUNWIND.
         .section .text.__aeabi_unwind_cpp_pr0, "ax", %progbits
         .global __aeabi_unwind_cpp_pr0
 __aeabi_unwind_cpp_pr0:
         bx lr
 
 // f1, f2
-// CHECK:      100d4 28100000 08849780 24100000 01000000
+// CHECK:      100d4 28000100 08849780 24000100 01000000
 // f3, __aeabi_unwind_cpp_pr0
-// CHECK-NEXT: 100e4 20100000 01000000 1c100000 01000000
+// CHECK-NEXT: 100e4 20000100 01000000 1c000100 01000000
 // sentinel
-// CHECK-NEXT: 100f4 18100000 01000000
+// CHECK-NEXT: 100f4 18000100 01000000
 
 // f1, (f2, f3, __aeabi_unwind_cpp_pr0)
-// CHECK-MERGE:      100d4 18100000 08849780 14100000 01000000
+// CHECK-MERGE:      100d4 18000100 08849780 14000100 01000000
 // sentinel
-// CHECK-MERGE-NEXT: 100e4 18100000 01000000
+// CHECK-MERGE-NEXT: 100e4 18000100 01000000
 

lld/test/ELF/arm-exidx-canunwind.s

 _start:
  bl func1
  bl func2
  bx lr
 
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <_start>:
-// CHECK-NEXT:    11108:       bl      #4 <func1>
+// CHECK-NEXT:    20108:       bl      #4 <func1>
 // CHECK-NEXT:                 bl      #4 <func2>
 // CHECK-NEXT:                 bx      lr
 // CHECK:      <func1>:
-// CHECK-NEXT:    11114:       bx      lr
+// CHECK-NEXT:    20114:       bx      lr
 // CHECK:      <func2>:
-// CHECK-NEXT:    11118:       bx      lr
+// CHECK-NEXT:    20118:       bx      lr
 // CHECK:      <__gxx_personality_v0>:
-// CHECK-NEXT:    1111c:       bx      lr
+// CHECK-NEXT:    2011c:       bx      lr
 // CHECK:      <__aeabi_unwind_cpp_pr0>:
-// CHECK-NEXT:    11120:       bx      lr
+// CHECK-NEXT:    20120:       bx      lr
 
 // 100d4 + 0x1034 = 0x11108 = main (linker generated cantunwind)
 // 100dc + 0x1038 = 0x11114 = func1 (inline unwinding data)
-// CHECK-EXIDX:      100d4 34100000 01000000 38100000 08849780
+// CHECK-EXIDX:      100d4 34000100 01000000 38000100 08849780
 // 100e4 + 0x1034 = 0x11118 = func2 (100e8 + 14 = 100fc = .ARM.extab entry)
 // 100ec + 0x1030 = 0x1111c = __gxx_personality_v0 (linker generated cantunwind)
-// CHECK-EXIDX-NEXT: 100e4 34100000 14000000 30100000 01000000
+// CHECK-EXIDX-NEXT: 100e4 34000100 14000000 30000100 01000000
 // 100f4 + 0x1030 = 1101c = sentinel
-// CHECK-EXIDX-NEXT: 100f4 30100000 01000000
+// CHECK-EXIDX-NEXT: 100f4 30000100 01000000
 
 // CHECK-PT:          Name: .ARM.exidx
 // CHECK-PT-NEXT:     Type: SHT_ARM_EXIDX (0x70000001)
 // CHECK-PT-NEXT:     Flags [
 // CHECK-PT-NEXT:       SHF_ALLOC
 // CHECK-PT-NEXT:       SHF_LINK_ORDER
 // CHECK-PT-NEXT:     ]
 // CHECK-PT-NEXT:     Address: 0x100D4

lld/test/ELF/arm-exidx-dedup.s

 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj --arm-add-build-attributes -triple=armv7a-none-linux-gnueabi %s -o %t
 // RUN: ld.lld %t --no-merge-exidx-entries -o %t2
 // RUN: llvm-objdump -s %t2 | FileCheck --check-prefix CHECK-DUPS %s
 // RUN: ld.lld %t -o %t3
 // RUN: llvm-objdump -s %t3 | FileCheck %s
 
 // Test that lld can at least remove duplicate .ARM.exidx sections. A more
 // fine grained implementation will be able to remove duplicate entries within
 // a .ARM.exidx section.
 
 // With duplicate entries
 // CHECK-DUPS: Contents of section .ARM.exidx:
-// CHECK-DUPS-NEXT: 100d4 78100000 01000000 74100000 01000000
-// CHECK-DUPS-NEXT: 100e4 70100000 01000000 6c100000 01000000
-// CHECK-DUPS-NEXT: 100f4 68100000 08849780 64100000 08849780
-// CHECK-DUPS-NEXT: 10104 60100000 08849780 5c100000 24000000
-// CHECK-DUPS-NEXT: 10114 58100000 28000000 54100000 01000000
-// CHECK-DUPS-NEXT: 10124 50100000 01000000 4c100000 01000000
+// CHECK-DUPS-NEXT: 100d4 78000100 01000000 74000100 01000000
+// CHECK-DUPS-NEXT: 100e4 70000100 01000000 6c000100 01000000
+// CHECK-DUPS-NEXT: 100f4 68000100 08849780 64000100 08849780
+// CHECK-DUPS-NEXT: 10104 60000100 08849780 5c000100 24000000
+// CHECK-DUPS-NEXT: 10114 58000100 28000000 54000100 01000000
+// CHECK-DUPS-NEXT: 10124 50000100 01000000 4c000100 01000000
 // CHECK-DUPS-NEXT: Contents of section .ARM.extab:
 
 // After duplicate entry removal
 // CHECK: Contents of section .ARM.exidx:
-// CHECK-NEXT: 100d4 48100000 01000000 50100000 08849780
-// CHECK-NEXT: 100e4 54100000 1c000000 50100000 20000000
-// CHECK-NEXT: 100f4 4c100000 01000000 4c100000 01000000
+// CHECK-NEXT: 100d4 48000100 01000000 50000100 08849780
+// CHECK-NEXT: 100e4 54000100 1c000000 50000100 20000000
+// CHECK-NEXT: 100f4 4c000100 01000000 4c000100 01000000
 // CHECK-NEXT: Contents of section .ARM.extab:
         .syntax unified
 
         // Expect 1 EXIDX_CANTUNWIND entry.
         .section .text.00, "ax", %progbits
         .globl _start
 _start:
         .fnstart

lld/test/ELF/arm-exidx-emit-relocs.s

  .fnend
 
  .section .text.__aeabi_unwind_cpp_pr0, "ax", %progbits
  .global __aeabi_unwind_cpp_pr0
 __aeabi_unwind_cpp_pr0:
  bx lr
 
 // CHECK: Contents of section .ARM.exidx:
-// CHECK-NEXT:  100d4 28100000 08849780 28100000 01000000
-// CHECK-NEXT:  100e4 28100000 08849780 24100000 01000000
-// CHECK-NEXT:  100f4 20100000 01000000
+// CHECK-NEXT:  100d4 28000100 08849780 28000100 01000000
+// CHECK-NEXT:  100e4 28000100 08849780 24000100 01000000
+// CHECK-NEXT:  100f4 20000100 01000000
 
 // CHECK-RELOCS-NOT: Relocation section '.rel.ARM.exidx'

lld/test/ELF/arm-exidx-gc.s

  bx lr
 
 // GC should have only removed unusedfunc1 and unusedfunc2 the personality
 // routines are kept alive by references from live .ARM.exidx and .ARM.extab
 // sections
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <_start>:
-// CHECK-NEXT:   1110c:       bl      #4 <func1>
-// CHECK-NEXT:   11110:       bl      #4 <func2>
-// CHECK-NEXT:   11114:       bx      lr
+// CHECK-NEXT:   2010c:       bl      #4 <func1>
+// CHECK-NEXT:   20110:       bl      #4 <func2>
+// CHECK-NEXT:   20114:       bx      lr
 // CHECK: <func1>:
-// CHECK-NEXT:   11118:       bx      lr
+// CHECK-NEXT:   20118:       bx      lr
 // CHECK: <func2>:
-// CHECK-NEXT:   1111c:       bx      lr
+// CHECK-NEXT:   2011c:       bx      lr
 // CHECK: <__gxx_personality_v0>:
-// CHECK-NEXT:   11120:       bx      lr
+// CHECK-NEXT:   20120:       bx      lr
 // CHECK: <__aeabi_unwind_cpp_pr0>:
-// CHECK-NEXT:   11124:       bx      lr
+// CHECK-NEXT:   20124:       bx      lr
 
 // GC should have removed table entries for unusedfunc1, unusedfunc2
 // and __gxx_personality_v1
 // CHECK-NOT: unusedfunc1
 // CHECK-NOT: unusedfunc2
 // CHECK-NOT: __gxx_personality_v1
 
 // CHECK-EXIDX: Contents of section .ARM.exidx:
 // 100d4 + 1038 = 1110c = _start
 // 100dc + 103c = 11118 = func1
-// CHECK-EXIDX-NEXT: 100d4 38100000 01000000 3c100000 08849780
+// CHECK-EXIDX-NEXT: 100d4 38000100 01000000 3c000100 08849780
 // 100e4 + 1038 = 1111c = func2 (100e8 + 1c = 10104 = .ARM.extab)
 // 100ec + 1034 = 11120 = __gxx_personality_v0
-// CHECK-EXIDX-NEXT: 100e4 38100000 1c000000 34100000 01000000
+// CHECK-EXIDX-NEXT: 100e4 38000100 1c000000 34000100 01000000
 // 100f4 + 1030 = 11018 = __aeabi_unwind_cpp_pr0
 // 100fc + 102c = 1101c = __aeabi_unwind_cpp_pr0 + sizeof(__aeabi_unwind_cpp_pr0)
-// CHECK-EXIDX-NEXT: 100f4 30100000 01000000 2c100000 01000000
+// CHECK-EXIDX-NEXT: 100f4 30000100 01000000 2c000100 01000000
 // CHECK-EXIDX-NEXT: Contents of section .ARM.extab:
 // 10104 + 101c = 11120 = __gxx_personality_v0
-// CHECK-EXIDX-NEXT: 10104 1c100000 b0b0b000
+// CHECK-EXIDX-NEXT: 10104 1c000100 b0b0b000

lld/test/ELF/arm-exidx-order.s

  .cantunwind
  .fnend
 
 // Check default no linker script order.
 
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK: <_start>:
-// CHECK-NEXT:    11124:       bx      lr
+// CHECK-NEXT:    20124:       bx      lr
 // CHECK: <f1>:
-// CHECK-NEXT:    11128:       bx      lr
+// CHECK-NEXT:    20128:       bx      lr
 // CHECK: <f2>:
-// CHECK-NEXT:    1112c:       bx      lr
+// CHECK-NEXT:    2012c:       bx      lr
 // CHECK: <f3>:
-// CHECK-NEXT:    11130:       bx      lr
+// CHECK-NEXT:    20130:       bx      lr
 // CHECK: <func4>:
-// CHECK-NEXT:    11134:       bx      lr
+// CHECK-NEXT:    20134:       bx      lr
 // CHECK: <func5>:
-// CHECK-NEXT:    11138:       bx      lr
+// CHECK-NEXT:    20138:       bx      lr
 // CHECK: Disassembly of section .func1:
 // CHECK-EMPTY:
 // CHECK-NEXT: <func1>:
-// CHECK-NEXT:    1113c:       bx      lr
+// CHECK-NEXT:    2013c:       bx      lr
 // CHECK: Disassembly of section .func2:
 // CHECK-EMPTY:
 // CHECK-NEXT: <func2>:
-// CHECK-NEXT:    11140:       bx      lr
+// CHECK-NEXT:    20140:       bx      lr
 // CHECK: Disassembly of section .func3:
 // CHECK-EMPTY:
 // CHECK-NEXT: <func3>:
-// CHECK-NEXT:    11144:       bx      lr
+// CHECK-NEXT:    20144:       bx      lr
 
 // Each .ARM.exidx section has two 4 byte fields
 // Field 1 is the 31-bit offset to the function. The top bit is used to
 // indicate whether Field 2 is a pointer or an inline table entry.
 // Field 2 is either a pointer to a .ARM.extab section or an inline table
 // In this example all Field 2 entries are inline can't unwind (0x1)
 // We expect to see the entries in the same order as the functions
 
 // CHECK-EXIDX: Contents of section .ARM.exidx:
 // 100d4 + 1050 = 11124 = _start
 // 100dc + 104c = 11128 = f1
-// CHECK-EXIDX-NEXT:       100d4 50100000 01000000 4c100000 01000000
+// CHECK-EXIDX-NEXT:       100d4 50000100 01000000 4c000100 01000000
 // 100e4 + 1048 = 1112c = f2
 // 100ec + 1044 = 11130 = f3
-// CHECK-EXIDX-NEXT:  100e4 48100000 01000000 44100000 01000000
+// CHECK-EXIDX-NEXT:  100e4 48000100 01000000 44000100 01000000
 // 100f4 + 1040 = 11134 = func4
 // 100fc + 103c = 11138 = func5
-// CHECK-EXIDX-NEXT:  100f4 40100000 01000000 3c100000 01000000
+// CHECK-EXIDX-NEXT:  100f4 40000100 01000000 3c000100 01000000
 // 10104 + 1038 = 1113c = func1
 // 1010c + 1034 = 11140 = func2
-// CHECK-EXIDX-NEXT:  10104 38100000 01000000 34100000 01000000
+// CHECK-EXIDX-NEXT:  10104 38000100 01000000 34000100 01000000
 // 10114 + 1030 = 11144 = func3
-// CHECK-EXIDX-NEXT:  10114 30100000 01000000
+// CHECK-EXIDX-NEXT:  10114 30000100 01000000
 
 // Check that PT_ARM_EXIDX program header has been generated that describes
 // the .ARM.exidx output section
 // CHECK-PT:          Name: .ARM.exidx
 // CHECK-PT-NEXT:     Type: SHT_ARM_EXIDX (0x70000001)
 // CHECK-PT-NEXT:     Flags [
 // CHECK-PT-NEXT:       SHF_ALLOC
 // CHECK-PT-NEXT:       SHF_LINK_ORDER

lld/test/ELF/arm-exidx-shared.s

 
  .section .text.__aeabi_unwind_cpp_pr0, "ax", %progbits
  .global __aeabi_unwind_cpp_pr0
 __aeabi_unwind_cpp_pr0:
  bx lr
 
 // CHECK: Relocations [
 // CHECK-NEXT:   Section {{.*}} .rel.plt {
-// CHECK-NEXT:     0x32DC R_ARM_JUMP_SLOT __gxx_personality_v0
+// CHECK-NEXT:     0x302DC R_ARM_JUMP_SLOT __gxx_personality_v0
 
 // CHECK-EXTAB: Contents of section .ARM.extab:
-// 0x0238 + 0x1038 = 0x1270 = __gxx_personality_v0(PLT)      
-// CHECK-EXTAB-NEXT: 0238 38100000 b0b0b000 00000000 
+// 0x0238 + 0x1038 = 0x1270 = __gxx_personality_v0(PLT)
+// CHECK-EXTAB-NEXT: 0238 38000100 b0b0b000 00000000

lld/test/ELF/arm-fix-cortex-a8-blx.s

 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=armv7a-linux-gnueabihf --arm-add-build-attributes %s -o %t.o
 // RUN: ld.lld --fix-cortex-a8 -verbose %t.o -o %t2 2>&1 | FileCheck %s
-// RUN: llvm-objdump -d --no-show-raw-insn --start-address=0x12ffa --stop-address=0x13008 %t2 | FileCheck --check-prefix=CHECK-PATCH %s
+// RUN: llvm-objdump -d --no-show-raw-insn --start-address=0x21ffa --stop-address=0x22008 %t2 | FileCheck --check-prefix=CHECK-PATCH %s
 
 /// Test that the patch can work on an unrelocated BLX. Neither clang or GCC
 /// will emit these without a relocation, but they could be produced by ELF
 /// processing tools.
 
-// CHECK: ld.lld: detected cortex-a8-657419 erratum sequence starting at 12FFE in unpatched output.
+// CHECK: ld.lld: detected cortex-a8-657419 erratum sequence starting at 21FFE in unpatched output.
 
  .syntax unified
  .text
 
  .type _start, %function
  .balign 4096
  .global _start
  .arm
 _start:
  bx lr
  .space 4086
  .thumb
 /// 32-bit Branch link and exchange spans 2 4KiB regions, preceded by a
 /// 32-bit non branch instruction. Expect a patch.
  nop.w
 /// Encoding for blx _start. Use .inst.n directives to avoid a relocation.
  .inst.n 0xf7ff
  .inst.n 0xe800
 
-// CHECK-PATCH:         12ffa:          nop.w
-// CHECK-PATCH-NEXT:    12ffe:          blx     #4
-// CHECK-PATCH:      00013004 <__CortexA8657417_12FFE>:
-// CHECK-PATCH-NEXT:    13004:          b       #-4104
+// CHECK-PATCH:         21ffa:          nop.w
+// CHECK-PATCH-NEXT:    21ffe:          blx     #4
+// CHECK-PATCH:      00022004 <__CortexA8657417_21FFE>:
+// CHECK-PATCH-NEXT:    22004:          b       #-4104

lld/test/ELF/arm-fix-cortex-a8-nopatch.s

 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=armv7a-linux-gnueabihf --arm-add-build-attributes %s -o %t.o
 // RUN: ld.lld --fix-cortex-a8 -verbose %t.o -o %t2
-// RUN: llvm-objdump -d %t2 --start-address=0x12ffa --stop-address=0x13002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE1 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x13ffa --stop-address=0x14002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE2 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x14ffa --stop-address=0x15002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE3 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x15ffa --stop-address=0x16006 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE4 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x16ffe --stop-address=0x17002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE5 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x18000 --stop-address=0x18004 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE6 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x19002 --stop-address=0x19006 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE7 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x21ffa --stop-address=0x22002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE1 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x22ffa --stop-address=0x23002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE2 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x23ffa --stop-address=0x24002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE3 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x24ffa --stop-address=0x25006 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE4 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x25ffe --stop-address=0x26002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE5 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x27000 --stop-address=0x28004 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE6 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x28002 --stop-address=0x29006 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE7 %s
 
 /// Test boundary conditions of the cortex-a8 erratum. The following cases
 /// should not trigger the Erratum
  .syntax unified
  .thumb
  .text
  .global _start
  .balign 4096
  .thumb_func
 _start:
  nop.w
  .space 4086
  .thumb_func
 target:
 /// 32-bit branch spans 2 4KiB regions, preceded by a 32-bit branch so no patch
 /// expected.
  b.w target
  b.w target
 
-// CALLSITE1:      00012ffa <target>:
-// CALLSITE1-NEXT:    12ffa:            b.w     #-4
-// CALLSITE1-NEXT:    12ffe:            b.w     #-8
+// CALLSITE1:      00021ffa <target>:
+// CALLSITE1-NEXT:    21ffa:            b.w     #-4
+// CALLSITE1-NEXT:    21ffe:            b.w     #-8
 
  .space 4088
  .type target2, %function
 target2:
 /// 32-bit Branch and link spans 2 4KiB regions, preceded by a 16-bit
 /// instruction so no patch expected.
  nop
  nop
  bl target2
 
-// CALLSITE2:      00013ffa <target2>:
-// CALLSITE2-NEXT:    13ffa:            nop
-// CALLSITE2-NEXT:    13ffc:            nop
-// CALLSITE2-NEXT:    13ffe:            bl      #-8
+// CALLSITE2:      00022ffa <target2>:
+// CALLSITE2-NEXT:    22ffa:            nop
+// CALLSITE2-NEXT:    22ffc:            nop
+// CALLSITE2-NEXT:    22ffe:            bl      #-8
 
  .space 4088
  .type target3, %function
 target3:
 /// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
 /// non branch instruction, branch is backwards but outside 4KiB region. So
 /// expect no patch.
  nop.w
  beq.w target2
 
-// CALLSITE3:      00014ffa <target3>:
-// CALLSITE3-NEXT:    14ffa:            nop.w
-// CALLSITE3-NEXT:    14ffe:            beq.w   #-4104
+// CALLSITE3:      00023ffa <target3>:
+// CALLSITE3-NEXT:    23ffa:            nop.w
+// CALLSITE3-NEXT:    23ffe:            beq.w   #-4104
 
  .space 4088
  .type source4, %function
 source4:
 /// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
 /// non branch instruction, branch is forwards to 2nd region so expect no patch.
  nop.w
  beq.w target4
  .thumb_func
 target4:
  nop.w
 
-// CALLSITE4:      00015ffa <source4>:
-// CALLSITE4-NEXT:    15ffa:            nop.w
-// CALLSITE4-NEXT:    15ffe:            beq.w   #0
-// CALLSITE4:      00016002 <target4>:
-// CALLSITE4-NEXT:    16002:            nop.w
+// CALLSITE4:      00024ffa <source4>:
+// CALLSITE4-NEXT:    24ffa:            nop.w
+// CALLSITE4-NEXT:    24ffe:            beq.w   #0
+// CALLSITE4:      00025002 <target4>:
+// CALLSITE4-NEXT:    25002:            nop.w
 
  .space 4084
  .type target5, %function
 
 target5:
 /// 32-bit conditional branch spans 2 4KiB regions, preceded by the encoding of
 /// a 32-bit thumb instruction, but in ARM state (illegal instruction), we
 /// should not decode and match it as Thumb, expect no patch.
  .arm
  .inst 0x800f3af /// nop.w encoding in Thumb
  .thumb
  .thumb_func
 source5:
  beq.w target5
 
-// CALLSITE5:      00016ffe <source5>:
-// CALLSITE5-NEXT:    16ffe:            beq.w   #-8
+// CALLSITE5:      00025ffe <source5>:
+// CALLSITE5-NEXT:    25ffe:            beq.w   #-8
 
 /// Edge case where two word sequence starts at offset 0xffc, check that
 /// we don't match. In this case the branch will be completely in the 2nd
 /// region and the branch will target the second region. This will pass a
 /// branch destination in the same region test, but not the branch must have
 /// and address of the form xxxxxffe.
  .space 4090
  .type target6, %function
  nop.w
 /// Make sure target of branch is in the same 4KiB region as the branch.
 target6:
  bl target6
 
-// CALLSITE6:      00018000 <target6>:
-// CALLSITE6-NEXT:    18000:            bl      #-4
+// CALLSITE6:      00027000 <target6>:
+// CALLSITE6-NEXT:    27000:            bl      #-4
 
 /// Edge case where two word sequence starts at offset 0xffe, check that
 /// we don't match. In this case the branch will be completely in the 2nd
 /// region and the branch will target the second region. This will pass a
 /// branch destination in the same region test, but not the branch must have
 /// and address of the form xxxxxffe.
  .space 4090
  .type target7, %function
  nop.w
 /// Make sure target of branch is in the same 4KiB region as the branch.
 target7:
  bl target7
 
-// CALLSITE7:      00019002 <target7>:
-// CALLSITE7:         19002:            bl      #-4
+// CALLSITE7:      00028002 <target7>:
+// CALLSITE7:         28002:            bl      #-4

lld/test/ELF/arm-fix-cortex-a8-recognize.s

 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=armv7a-linux-gnueabihf --arm-add-build-attributes %s -o %t.o
 // RUN: ld.lld --fix-cortex-a8 -verbose %t.o -o %t2 2>&1 | FileCheck %s
-// RUN: llvm-objdump -d %t2 --start-address=0x1a004 --stop-address=0x1a024 --no-show-raw-insn | FileCheck --check-prefix=CHECK-PATCHES %s
-// RUN: llvm-objdump -d %t2 --start-address=0x12ffa --stop-address=0x13002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE1 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x13ffa --stop-address=0x14002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE2 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x14ffa --stop-address=0x15002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE3 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x15ff4 --stop-address=0x16002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE4 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x16ffa --stop-address=0x17002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE5 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x17ffa --stop-address=0x18002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE6 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x18ffa --stop-address=0x19002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE7 %s
-// RUN: llvm-objdump -d %t2 --start-address=0x19ff4 --stop-address=0x1a002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE8 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x29004 --stop-address=0x29024 --no-show-raw-insn | FileCheck --check-prefix=CHECK-PATCHES %s
+// RUN: llvm-objdump -d %t2 --start-address=0x21ffa --stop-address=0x22002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE1 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x22ffa --stop-address=0x23002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE2 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x23ffa --stop-address=0x24002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE3 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x24ff4 --stop-address=0x25002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE4 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x25ffa --stop-address=0x26002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE5 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x26ffa --stop-address=0x27002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE6 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x27ffa --stop-address=0x28002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE7 %s
+// RUN: llvm-objdump -d %t2 --start-address=0x28ff4 --stop-address=0x29002 --no-show-raw-insn | FileCheck --check-prefix=CALLSITE8 %s
 // RUN: ld.lld --fix-cortex-a8 -verbose -r %t.o -o %t3 2>&1 | FileCheck --check-prefix=CHECK-RELOCATABLE-LLD %s
 // RUN: llvm-objdump --no-show-raw-insn -d %t3 --start-address=0xffa --stop-address=0x1002 | FileCheck --check-prefix=CHECK-RELOCATABLE %s
 
-// CHECK:      ld.lld: detected cortex-a8-657419 erratum sequence starting at 12FFE in unpatched output.
-// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 13FFE in unpatched output.
-// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 14FFE in unpatched output.
-// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 15FFE in unpatched output.
-// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 16FFE in unpatched output.
-// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 17FFE in unpatched output.
-// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 18FFE in unpatched output.
+// CHECK:      ld.lld: detected cortex-a8-657419 erratum sequence starting at 22FFE in unpatched output.
+// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 23FFE in unpatched output.
+// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 24FFE in unpatched output.
+// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 25FFE in unpatched output.
+// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 26FFE in unpatched output.
+// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 27FFE in unpatched output.
+// CHECK-NEXT: ld.lld: detected cortex-a8-657419 erratum sequence starting at 28FFE in unpatched output.
 
 /// We do not detect errors when doing a relocatable link as we don't know what
 /// the final addresses are.
 // CHECK-RELOCATABLE-LLD-NOT: ld.lld: detected cortex-a8-657419 erratum sequence
 
 /// Basic tests for the -fix-cortex-a8 erratum fix. The full details of the
 /// erratum and the patch are in ARMA8ErrataFix.cpp . The test creates an
 /// instance of the erratum every 4KiB (32-bit non-branch, followed by 32-bit

  .global target
  .type target, %function
 target:
 /// 32-bit Branch spans 2 4KiB regions, preceded by a 32-bit non branch
 /// instruction, expect a patch.
  nop.w
  b.w target
 
-// CALLSITE1:      00012ffa <target>:
-// CALLSITE1-NEXT:    12ffa:            nop.w
-// CALLSITE1-NEXT:    12ffe:            b.w     #28674
+// CALLSITE1:      00021ffa <target>:
+// CALLSITE1-NEXT:    21ffa:            nop.w
+// CALLSITE1-NEXT:    21ffe:            b.w     #28674
 /// Expect no patch when doing a relocatable link ld -r.
 // CHECK-RELOCATABLE: 00000ffa <target>:
 // CHECK-RELOCATABLE-NEXT:      ffa:            nop.w
 // CHECK-RELOCATABLE-NEXT:      ffe:            b.w     #-4
 
  .space 4088
  .type target2, %function
  .local target2
 target2:
 /// 32-bit Branch and link spans 2 4KiB regions, preceded by a 32-bit
 /// non branch instruction, expect a patch.
  nop.w
  bl target2
 
-// CALLSITE2:      00013ffa <target2>:
-// CALLSITE2-NEXT:    13ffa:            nop.w
-// CALLSITE2-NEXT:    13ffe:            bl      #24582
+// CALLSITE2:      00022ffa <target2>:
+// CALLSITE2-NEXT:    22ffa:            nop.w
+// CALLSITE2-NEXT:    22ffe:            bl      #24582
 
  .space 4088
  .type target3, %function
  .local target3
 target3:
 /// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
 /// non branch instruction, expect a patch.
  nop.w
  beq.w target3
 
-// CALLSITE3:      00014ffa <target3>:
-// CALLSITE3-NEXT:    14ffa:            nop.w
-// CALLSITE3-NEXT:    14ffe:            beq.w   #20490
+// CALLSITE3:      00023ffa <target3>:
+// CALLSITE3-NEXT:    23ffa:            nop.w
+// CALLSITE3-NEXT:    23ffe:            beq.w   #20490
 
  .space 4082
  .type target4, %function
  .local target4
  .arm
 target4:
  bx lr
  .space 2
  .thumb
 /// 32-bit Branch link and exchange spans 2 4KiB regions, preceded by a
 /// 32-bit non branch instruction, blx always goes via relocation. Expect
 /// a patch.
  nop.w
  blx target4
 
 /// Target = 0x19010 __CortexA8657417_15FFE
-// CALLSITE4:      00015ff4 <target4>:
-// CALLSITE4-NEXT:    15ff4:            bx      lr
-// CALLSITE4:         15ff8:    00 00           .short  0x0000
-// CALLSITE4:         15ffa:            nop.w
-// CALLSITE4-NEXT:    15ffe:            blx     #16400
+// CALLSITE4:      00024ff4 <target4>:
+// CALLSITE4-NEXT:    24ff4:            bx      lr
+// CALLSITE4:         24ff8:    00 00           .short  0x0000
+// CALLSITE4:         24ffa:            nop.w
+// CALLSITE4-NEXT:    24ffe:            blx     #16400
 
 /// Separate sections for source and destination of branches to force
 /// a relocation.
  .section .text.0, "ax", %progbits
  .balign 2
  .global target5
  .type target5, %function
 target5:
  nop.w
  .section .text.1, "ax", %progbits
  .space 4084
 /// 32-bit branch spans 2 4KiB regions, preceded by a 32-bit non branch
 /// instruction, expect a patch. Branch to global symbol so goes via a
 /// relocation.
  nop.w
  b.w target5
 
 /// Target = 0x19014 __CortexA8657417_16FFE
-// CALLSITE5:         16ffa:            nop.w
-// CALLSITE5-NEXT:    16ffe:            b.w     #12306
+// CALLSITE5:         25ffa:            nop.w
+// CALLSITE5-NEXT:    25ffe:            b.w     #12306
 
  .section .text.2, "ax", %progbits
  .balign 2
  .global target6
  .type target6, %function
 target6:
  nop.w
  .section .text.3, "ax", %progbits
  .space 4084
 /// 32-bit branch and link spans 2 4KiB regions, preceded by a 32-bit
 /// non branch instruction, expect a patch. Branch to global symbol so
 /// goes via a relocation.
  nop.w
  bl target6
 
 /// Target = 0x19018 __CortexA8657417_17FFE
-// CALLSITE6:         17ffa:            nop.w
-// CALLSITE6-NEXT:    17ffe:            bl      #8214
+// CALLSITE6:         26ffa:            nop.w
+// CALLSITE6-NEXT:    26ffe:            bl      #8214
 
  .section .text.4, "ax", %progbits
  .global target7
  .type target7, %function
 target7:
  nop.w
  .section .text.5, "ax", %progbits
  .space 4084
 /// 32-bit conditional branch spans 2 4KiB regions, preceded by a 32-bit
 /// non branch instruction, expect a patch. Branch to global symbol so
 /// goes via a relocation.
  nop.w
  bne.w target7
 
-// CALLSITE7:         18ffa:            nop.w
-// CALLSITE7-NEXT:    18ffe:            bne.w   #4122
+// CALLSITE7:         27ffa:            nop.w
+// CALLSITE7-NEXT:    27ffe:            bne.w   #4122
 
  .section .text.6, "ax", %progbits
  .space 4082
  .arm
  .global target8
  .type target8, %function
 target8:
  bx lr
 
  .section .text.7, "ax", %progbits
  .space 2
  .thumb
 /// 32-bit Branch link spans 2 4KiB regions, preceded by a 32-bit non branch
 /// instruction, expect a patch. The target of the BL is in ARM state so we
 /// expect it to be turned into a BLX. The patch must be in ARM state to
 /// avoid a state change thunk.
  nop.w
  bl target8
 
-// CALLSITE8:      00019ff4 <target8>:
-// CALLSITE8-NEXT:    19ff4:            bx      lr
-// CALLSITE8:         19ff8:    00 00           .short  0x0000
-// CALLSITE8:         19ffa:            nop.w
-// CALLSITE8-NEXT:    19ffe:            blx     #32
+// CALLSITE8:      00028ff4 <target8>:
+// CALLSITE8-NEXT:    28ff4:            bx      lr
+// CALLSITE8:         28ff8:    00 00           .short  0x0000
+// CALLSITE8:         28ffa:            nop.w
+// CALLSITE8-NEXT:    28ffe:            blx     #32
 
-// CHECK-PATCHES: 0001a004 <__CortexA8657417_12FFE>:
-// CHECK-PATCHES-NEXT:    1a004:        b.w     #-28686
+// CHECK-PATCHES: 00029004 <__CortexA8657417_21FFE>:
+// CHECK-PATCHES-NEXT:    29004:        b.w     #-28686
 
-// CHECK-PATCHES:      0001a008 <__CortexA8657417_13FFE>:
-// CHECK-PATCHES-NEXT:    1a008:        b.w     #-24594
+// CHECK-PATCHES:      00029008 <__CortexA8657417_22FFE>:
+// CHECK-PATCHES-NEXT:    29008:        b.w     #-24594
 
-// CHECK-PATCHES:      0001a00c <__CortexA8657417_14FFE>:
-// CHECK-PATCHES-NEXT:    1a00c:        b.w     #-20502
+// CHECK-PATCHES:      0002900c <__CortexA8657417_23FFE>:
+// CHECK-PATCHES-NEXT:    2900c:        b.w     #-20502
 
-// CHECK-PATCHES:      0001a010 <__CortexA8657417_15FFE>:
-// CHECK-PATCHES-NEXT:    1a010:        b       #-16420
+// CHECK-PATCHES:      00029010 <__CortexA8657417_24FFE>:
+// CHECK-PATCHES-NEXT:    29010:        b       #-16420
 
-// CHECK-PATCHES:      0001a014 <__CortexA8657417_16FFE>:
-// CHECK-PATCHES-NEXT:    1a014:        b.w     #-16406
+// CHECK-PATCHES:      00029014 <__CortexA8657417_25FFE>:
+// CHECK-PATCHES-NEXT:    29014:        b.w     #-16406
 
-// CHECK-PATCHES:      0001a018 <__CortexA8657417_17FFE>:
-// CHECK-PATCHES-NEXT:    1a018:        b.w     #-12314
+// CHECK-PATCHES:      00029018 <__CortexA8657417_26FFE>:
+// CHECK-PATCHES-NEXT:    29018:        b.w     #-12314
 
-// CHECK-PATCHES:      0001a01c <__CortexA8657417_18FFE>:
-// CHECK-PATCHES-NEXT:    1a01c:        b.w     #-8222
+// CHECK-PATCHES:      0002901c <__CortexA8657417_27FFE>:
+// CHECK-PATCHES-NEXT:    2901c:        b.w     #-8222
 
-// CHECK-PATCHES:      0001a020 <__CortexA8657417_19FFE>:
-// CHECK-PATCHES-NEXT:    1a020:        b       #-52
+// CHECK-PATCHES:      00029020 <__CortexA8657417_28FFE>:
+// CHECK-PATCHES-NEXT:    29020:        b       #-52

lld/test/ELF/arm-fix-cortex-a8-thunk-align.s

_start:
   b.w arm_func
 thumb_target:
   .space 4096 - 10
   /// erratum patch needed
   nop.w
   b.w thumb_target
 
 /// Expect thunk and patch to be inserted here
-// CHECK:  00003004 <__ThumbV7PILongThunk_arm_func>:
-// CHECK-NEXT: 3004: movw    r12, #4088
-// CHECK-NEXT:       movt    r12, #256
-// CHECK-NEXT:       add     r12, pc
-// CHECK-NEXT:       bx      r12
-// CHECK:  00004004 <__CortexA8657417_2FFE>:
-// CHECK-NEXT: 4004: b.w     #-8196
+// CHECK:  00012004 <__ThumbV7PILongThunk_arm_func>:
+// CHECK-NEXT: 12004: movw    r12, #4088
+// CHECK-NEXT:        movt    r12, #256
+// CHECK-NEXT:        add     r12, pc
+// CHECK-NEXT:        bx      r12
+// CHECK:  00013004 <__CortexA8657417_11FFE>:
+// CHECK-NEXT: 13004: b.w     #-8196
  .section .text.02
  /// Take us over thunk section spacing
  .space 16 * 1024 * 1024
 
  .section .text.03, "ax", %progbits
  .arm
  .balign 4
  .type arm_func, %function
 arm_func:
   bx lr

lld/test/ELF/arm-fpic-got.s

 
 // CHECK: Section {
 // CHECK:    Name: .got
 // CHECK-NEXT:    Type: SHT_PROGBITS
 // CHECK-NEXT:      Flags [
 // CHECK-NEXT:      SHF_ALLOC
 // CHECK-NEXT:      SHF_WRITE
 // CHECK-NEXT:    ]
-// CHECK-NEXT:    Address: 0x12128
+// CHECK-NEXT:    Address: 0x30128
 // CHECK-NEXT:    Offset:
 // CHECK-NEXT:    Size: 4
 // CHECK-NEXT:    Link:
 // CHECK-NEXT:    Info:
 // CHECK-NEXT:    AddressAlignment: 4
 // CHECK-NEXT:    EntrySize:
 
 // SYMBOLS:    Name: val
-// SYMBOLS-NEXT:    Value: 0x1312C
+// SYMBOLS-NEXT:    Value: 0x4012C
 // SYMBOLS-NEXT:    Size: 4
 // SYMBOLS-NEXT:    Binding: Global
 // SYMBOLS-NEXT:    Type: Object
 // SYMBOLS-NEXT:    Other:
 // SYMBOLS-NEXT:    Section: .data
 
 // CODE: Disassembly of section .text:
 // CODE-EMPTY:
 // CODE-NEXT: <_start>:
-// CODE-NEXT:   11114:       ldr     r0, [pc, #8]
-// CODE-NEXT:   11118:       ldr     r0, [pc, r0]
-// CODE-NEXT:   1111c:       ldr     r0, [r0]
-// CODE-NEXT:   11120:       bx      lr
+// CODE-NEXT:   20114:       ldr     r0, [pc, #8]
+// CODE-NEXT:   20118:       ldr     r0, [pc, r0]
+// CODE-NEXT:   2011c:       ldr     r0, [r0]
+// CODE-NEXT:   20120:       bx      lr
 // CODE: <$d.1>:
 // 0x11124 + 0x1008 + 8 = 0x12128 = .got
-// CODE-NEXT:   11124:       08 10 00 00
+// CODE-NEXT:   20124:       08 00 01 00

lld/test/ELF/arm-gnu-ifunc-plt.s

 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=armv7a-linux-gnueabihf %S/Inputs/arm-shared.s -o %t1.o
 // RUN: ld.lld %t1.o --shared -soname=t.so -o %t.so
 // RUN: llvm-mc -filetype=obj -triple=armv7a-linux-gnueabihf %s -o %t.o
 // RUN: ld.lld %t.so %t.o -o %tout
 // RUN: llvm-objdump --triple=armv7a-linux-gnueabihf -d --no-show-raw-insn %tout | FileCheck %s --check-prefix=DISASM
 // RUN: llvm-objdump -s %tout | FileCheck %s --check-prefix=GOTPLT
 // RUN: llvm-readobj -r --dynamic-table %tout | FileCheck %s
 
 // Check that the IRELATIVE relocations are last in the .got
 // CHECK: Relocations [
 // CHECK-NEXT:   Section (5) .rel.dyn {
-// CHECK-NEXT:     0x122E0 R_ARM_GLOB_DAT bar2 0x0
-// CHECK-NEXT:     0x122E4 R_ARM_GLOB_DAT zed2 0x0
-// CHECK-NEXT:     0x122E8 R_ARM_IRELATIVE - 0x0
-// CHECK-NEXT:     0x122EC R_ARM_IRELATIVE - 0x0
+// CHECK-NEXT:     0x302E0 R_ARM_GLOB_DAT bar2 0x0
+// CHECK-NEXT:     0x302E4 R_ARM_GLOB_DAT zed2 0x0
+// CHECK-NEXT:     0x302E8 R_ARM_IRELATIVE - 0x0
+// CHECK-NEXT:     0x302EC R_ARM_IRELATIVE - 0x0
 // CHECK-NEXT:   }
 // CHECK-NEXT:   Section (6) .rel.plt {
-// CHECK-NEXT:     0x132FC R_ARM_JUMP_SLOT bar2 0x0
-// CHECK-NEXT:     0x13300 R_ARM_JUMP_SLOT zed2 0x0
+// CHECK-NEXT:     0x402FC R_ARM_JUMP_SLOT bar2 0x0
+// CHECK-NEXT:     0x40300 R_ARM_JUMP_SLOT zed2 0x0
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
 
 // Check that the GOT entries refer back to the ifunc resolver
 // GOTPLT: Contents of section .got:
-// GOTPLT-NEXT:  122e0 00000000 00000000 dc110100 e0110100
+// GOTPLT-NEXT:  302e0 00000000 00000000 dc010200 e0010200
 // GOTPLT: Contents of section .got.plt:
-// GOTPLT-NEXT:  132f0 00000000 00000000 00000000 00120100
-// GOTPLT-NEXT:  13300 00120100
+// GOTPLT-NEXT:  402f0 00000000 00000000 00000000 00020200
+// GOTPLT-NEXT:  40300 00020200
 
 // DISASM: Disassembly of section .text:
 // DISASM-EMPTY:
 // DISASM-NEXT: <foo>:
-// DISASM-NEXT:    111dc:       bx      lr
+// DISASM-NEXT:    201dc:       bx      lr
 // DISASM: <bar>:
-// DISASM-NEXT:    111e0:       bx      lr
+// DISASM-NEXT:    201e0:       bx      lr
 // DISASM: <_start>:
-// DISASM-NEXT:    111e4:       bl      #84
-// DISASM-NEXT:    111e8:       bl      #96
+// DISASM-NEXT:    201e4:       bl      #84
+// DISASM-NEXT:    201e8:       bl      #96
 // DISASM: <$d.1>:
-// DISASM-NEXT:    111ec:       00 00 00 00     .word   0x00000000
-// DISASM-NEXT:    111f0:       04 00 00 00     .word   0x00000004
-// DISASM:         111f4:       bl      #36
-// DISASM-NEXT:    111f8:       bl      #48
+// DISASM-NEXT:    201ec:       00 00 00 00     .word   0x00000000
+// DISASM-NEXT:    201f0:       04 00 00 00     .word   0x00000004
+// DISASM:         201f4:       bl      #36
+// DISASM-NEXT:    201f8:       bl      #48
 // DISASM-EMPTY:
 // DISASM-NEXT: Disassembly of section .plt:
 // DISASM-EMPTY:
 // DISASM-NEXT: <$a>:
-// DISASM-NEXT:    11200:       str     lr, [sp, #-4]!
-// DISASM-NEXT:    11204:       add     lr, pc, #0, #12
-// DISASM-NEXT:    11208:       add     lr, lr, #8192
-// DISASM-NEXT:    1120c:       ldr     pc, [lr, #236]!
+// DISASM-NEXT:    20200:       str     lr, [sp, #-4]!
+// DISASM-NEXT:    20204:       add     lr, pc, #0, #12
+// DISASM-NEXT:    20208:       add     lr, lr, #32
+// DISASM-NEXT:    2020c:       ldr     pc, [lr, #236]!
 // DISASM: <$d>:
-// DISASM-NEXT:    11210:       d4 d4 d4 d4     .word   0xd4d4d4d4
-// DISASM-NEXT:    11214:       d4 d4 d4 d4     .word   0xd4d4d4d4
-// DISASM-NEXT:    11218:       d4 d4 d4 d4     .word   0xd4d4d4d4
-// DISASM-NEXT:    1121c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DISASM-NEXT:    20210:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DISASM-NEXT:    20214:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DISASM-NEXT:    20218:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DISASM-NEXT:    2021c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 // DISASM: <$a>:
-// DISASM-NEXT:    11220:       add     r12, pc, #0, #12
-// DISASM-NEXT:    11224:       add     r12, r12, #8192
-// DISASM-NEXT:    11228:       ldr     pc, [r12, #212]!
+// DISASM-NEXT:    20220:       add     r12, pc, #0, #12
+// DISASM-NEXT:    20224:       add     r12, r12, #32
+// DISASM-NEXT:    20228:       ldr     pc, [r12, #212]!
 // DISASM: <$d>:
-// DISASM-NEXT:    1122c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DISASM-NEXT:    2022c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 // DISASM: <$a>:
-// DISASM-NEXT:    11230:       add     r12, pc, #0, #12
-// DISASM-NEXT:    11234:       add     r12, r12, #8192
-// DISASM-NEXT:    11238:       ldr     pc, [r12, #200]!
+// DISASM-NEXT:    20230:       add     r12, pc, #0, #12
+// DISASM-NEXT:    20234:       add     r12, r12, #32
+// DISASM-NEXT:    20238:       ldr     pc, [r12, #200]!
 // DISASM: <$d>:
-// DISASM-NEXT:    1123c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DISASM-NEXT:    2023c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 // DISASM: <$a>:
-// DISASM-NEXT:    11240:       add     r12, pc, #0, #12
-// DISASM-NEXT:    11244:       add     r12, r12, #4096
-// DISASM-NEXT:    11248:       ldr     pc, [r12, #160]!
+// DISASM-NEXT:    20240:       add     r12, pc, #0, #12
+// DISASM-NEXT:    20244:       add     r12, r12, #16
+// DISASM-NEXT:    20248:       ldr     pc, [r12, #160]!
 // DISASM: <$d>:
-// DISASM-NEXT:    1124c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DISASM-NEXT:    2024c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 // DISASM: <$a>:
-// DISASM-NEXT:    11250:       add     r12, pc, #0, #12
-// DISASM-NEXT:    11254:       add     r12, r12, #4096
-// DISASM-NEXT:    11258:       ldr     pc, [r12, #148]!
+// DISASM-NEXT:    20250:       add     r12, pc, #0, #12
+// DISASM-NEXT:    20254:       add     r12, r12, #16
+// DISASM-NEXT:    20258:       ldr     pc, [r12, #148]!
 // DISASM: <$d>:
-// DISASM-NEXT:    1125c: d4 d4 d4 d4   .word 0xd4d4d4d4
+// DISASM-NEXT:    2025c: d4 d4 d4 d4   .word 0xd4d4d4d4
 
 .syntax unified
 .text
 .type foo STT_GNU_IFUNC
 .globl foo
 foo:
  bx lr
 

lld/test/ELF/arm-gnu-ifunc.s

 // CHECK-NEXT:     Link:
 // CHECK-NEXT:     Info: 4
 // CHECK:          Name: .iplt
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
 // CHECK-NEXT:       SHF_EXECINSTR
 // CHECK-NEXT:     ]
-// CHECK-NEXT:     Address: 0x11130
+// CHECK-NEXT:     Address: 0x20130
 // CHECK-NEXT:     Offset: 0x130
 // CHECK-NEXT:     Size: 32
 // CHECK:          Index: 4
 // CHECK-NEXT:     Name: .got
 // CHECK-NEXT:     Type: SHT_PROGBITS
 // CHECK-NEXT:     Flags [
 // CHECK-NEXT:       SHF_ALLOC
 // CHECK-NEXT:       SHF_WRITE
 // CHECK-NEXT:     ]
-// CHECK-NEXT:     Address: 0x12150
+// CHECK-NEXT:     Address: 0x30150
 // CHECK-NEXT:     Offset: 0x150
 // CHECK-NEXT:     Size: 8
 // CHECK:      Relocations [
 // CHECK-NEXT:   Section (1) .rel.dyn {
-// CHECK-NEXT:     0x12150 R_ARM_IRELATIVE
-// CHECK-NEXT:     0x12154 R_ARM_IRELATIVE
+// CHECK-NEXT:     0x30150 R_ARM_IRELATIVE
+// CHECK-NEXT:     0x30154 R_ARM_IRELATIVE
 // CHECK-NEXT:   }
 // CHECK-NEXT: ]
 // CHECK:        Symbol {
 // CHECK:          Name: __rel_iplt_end
 // CHECK-NEXT:     Value: 0x10104
 // CHECK-NEXT:     Size: 0
 // CHECK-NEXT:     Binding: Local
 // CHECK-NEXT:     Type: None

 // CHECK-NEXT:     Type: None
 // CHECK-NEXT:     Other [
 // CHECK-NEXT:       STV_HIDDEN
 // CHECK-NEXT:     ]
 // CHECK-NEXT:     Section: .rel.dyn
 // CHECK-NEXT:   }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: _start
-// CHECK-NEXT:    Value: 0x1110C
+// CHECK-NEXT:    Value: 0x2010C
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global
 // CHECK-NEXT:    Type: None
 // CHECK-NEXT:    Other:
 // CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: bar
-// CHECK-NEXT:    Value: 0x11108
+// CHECK-NEXT:    Value: 0x20108
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global
 // CHECK-NEXT:    Type: GNU_IFunc
 // CHECK-NEXT:    Other: 0
 // CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: foo
-// CHECK-NEXT:    Value: 0x11104
+// CHECK-NEXT:    Value: 0x20104
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Binding: Global
 // CHECK-NEXT:    Type: GNU_IFunc
 // CHECK-NEXT:    Other: 0
 // CHECK-NEXT:    Section: .text
 // CHECK-NEXT:  }
 
 // DISASM: Disassembly of section .text:
 // DISASM-EMPTY:
 // DISASM-NEXT: <foo>:
-// DISASM-NEXT:    11104:      bx      lr
+// DISASM-NEXT:    20104:      bx      lr
 // DISASM: <bar>:
-// DISASM-NEXT:    11108:      bx      lr
+// DISASM-NEXT:    20108:      bx      lr
 // DISASM: <_start>:
-// DISASM-NEXT:    1110c:      bl      #28
-// DISASM-NEXT:    11110:      bl      #40
+// DISASM-NEXT:    2010c:      bl      #28
+// DISASM-NEXT:    20110:      bl      #40
 // 1 * 65536 + 244 = 0x100f4 __rel_iplt_start
-// DISASM-NEXT:    11114:      movw    r0, #244
-// DISASM-NEXT:    11118:      movt    r0, #1
+// DISASM-NEXT:    20114:      movw    r0, #244
+// DISASM-NEXT:    20118:      movt    r0, #1
 // 1 * 65536 + 260 = 0x10104 __rel_iplt_end
-// DISASM-NEXT:    1111c:      movw    r0, #260
-// DISASM-NEXT:    11120:      movt    r0, #1
+// DISASM-NEXT:    2011c:      movw    r0, #260
+// DISASM-NEXT:    20120:      movt    r0, #1
 // DISASM-EMPTY:
 // DISASM-NEXT: Disassembly of section .iplt:
 // DISASM-EMPTY:
 // DISASM-NEXT: <$a>:
-// DISASM-NEXT:    11130:       add     r12, pc, #0, #12
-// DISASM-NEXT:    11134:       add     r12, r12, #4096
-// DISASM-NEXT:    11138:       ldr     pc, [r12, #24]!
+// DISASM-NEXT:    20130:       add     r12, pc, #0, #12
+// DISASM-NEXT:    20134:       add     r12, r12, #16
+// DISASM-NEXT:    20138:       ldr     pc, [r12, #24]!
 // DISASM: <$d>:
-// DISASM-NEXT:    1113c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DISASM-NEXT:    2013c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 // DISASM: <$a>:
-// DISASM-NEXT:    11140:       add     r12, pc, #0, #12
-// DISASM-NEXT:    11144:       add     r12, r12, #4096
-// DISASM-NEXT:    11148:       ldr     pc, [r12, #12]!
+// DISASM-NEXT:    20140:       add     r12, pc, #0, #12
+// DISASM-NEXT:    20144:       add     r12, r12, #16
+// DISASM-NEXT:    20148:       ldr     pc, [r12, #12]!
 // DISASM: <$d>:
-// DISASM-NEXT:    1114c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DISASM-NEXT:    2014c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 

lld/test/ELF/arm-got-relative.s

 
  .globl function
  .align 2
 function:
  .type function, %function
  bx lr
 
 // CHECK: Dynamic Relocations {
-// CHECK-NEXT:  0x220C R_ARM_GLOB_DAT function 0x0
+// CHECK-NEXT:  0x2020C R_ARM_GLOB_DAT function 0x0
 
 // CHECK: Name: _GLOBAL_OFFSET_TABLE_
-// CHECK-NEXT:    Value: 0x220C
+// CHECK-NEXT:    Value: 0x2020C
 // CHECK-NEXT:    Size:
 // CHECK-NEXT:    Binding: Local
 // CHECK-NEXT:    Type: None
 // CHECK-NEXT:    Other [
 // CHECK-NEXT:      STV_HIDDEN
 // CHECK-NEXT:    ]
 // CHECK-NEXT:    Section: .got
 
 // CODE: Disassembly of section .text:
 // CODE-EMPTY:
 // CODE-NEXT: <_start>:
-// CODE-NEXT:    11a0:        08 30 9f e5    ldr     r3, [pc, #8]
-// CODE-NEXT:    11a4:        08 20 9f e5    ldr     r2, [pc, #8]
-// CODE-NEXT:    11a8:        03 00 8f e0    add     r0, pc, r3
-// CODE-NEXT:    11ac:        1e ff 2f e1    bx      lr
+// CODE-NEXT:    101a0:        08 30 9f e5    ldr     r3, [pc, #8]
+// CODE-NEXT:    101a4:        08 20 9f e5    ldr     r2, [pc, #8]
+// CODE-NEXT:    101a8:        03 00 8f e0    add     r0, pc, r3
+// CODE-NEXT:    101ac:        1e ff 2f e1    bx      lr
 // CODE: <$d.1>:
 // (_GLOBAL_OFFSET_TABLE_ = 0x220c) - (0x11a8 + 8) = 0x105c
-// CODE-NEXT:    11b0:        5c 10 00 00
+// CODE-NEXT:    101b0:        5c 00 01 00
 // (Got(function) - GotBase = 0x0
-// CODE-NEXT:    11b4:        00 00 00 00
+// CODE-NEXT:    101b4:        00 00 00 00

lld/test/ELF/arm-gotoff.s

 // REQUIRES: arm
 // RUN: llvm-mc -filetype=obj -triple=armv7a-linux-gnueabi %s -o %t.o
 // RUN: ld.lld %t.o -o %t
 // RUN: llvm-readobj -S -r --symbols %t | FileCheck %s
 // RUN: llvm-objdump --triple=armv7a-linux-gnueabi -d %t | FileCheck --check-prefix=DISASM %s
 
 // Test the R_ARM_GOTOFF32 relocation
 
 // CHECK:      Name: .got
 // CHECK-NEXT:    Type: SHT_PROGBITS (0x1)
 // CHECK-NEXT:    Flags [
 // CHECK-NEXT:      SHF_ALLOC
 // CHECK-NEXT:      SHF_WRITE
 // CHECK-NEXT:    ]
-// CHECK-NEXT:    Address: 0x12124
+// CHECK-NEXT:    Address: 0x30124
 // CHECK-NEXT:    Offset: 0x124
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Link:
 // CHECK-NEXT:    Info:
 // CHECK-NEXT:    AddressAlignment:
 
 // CHECK:    Name: .bss
 // CHECK-NEXT:    Type: SHT_NOBITS
 // CHECK-NEXT:    Flags [
 // CHECK-NEXT:      SHF_ALLOC
 // CHECK-NEXT:      SHF_WRITE
 // CHECK-NEXT:    ]
-// CHECK-NEXT:    Address: 0x13124
+// CHECK-NEXT:    Address: 0x40124
 // CHECK-NEXT:    Offset:
 // CHECK-NEXT:    Size: 20
 // CHECK-NEXT:    Link:
 // CHECK-NEXT:    Info:
 // CHECK-NEXT:    AddressAlignment: 1
 
 // CHECK-NEXT:    EntrySize: 0
 
 // CHECK:       Symbol {
 // CHECK:       Name: bar
-// CHECK-NEXT:    Value: 0x13124
+// CHECK-NEXT:    Value: 0x40124
 // CHECK-NEXT:    Size: 10
 // CHECK-NEXT:    Binding: Global
 // CHECK-NEXT:    Type: Object
 // CHECK-NEXT:    Other: 0
 // CHECK-NEXT:    Section: .bss
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Symbol {
 // CHECK-NEXT:    Name: obj
-// CHECK-NEXT:    Value: 0x1312E
+// CHECK-NEXT:    Value: 0x4012E
 // CHECK-NEXT:    Size: 10
 // CHECK-NEXT:    Binding: Global
 // CHECK-NEXT:    Type: Object
 // CHECK-NEXT:    Other: 0
 // CHECK-NEXT:    Section: .bss
 
 // DISASM:      Disassembly of section .text:
 // DISASM-EMPTY:

lld/test/ELF/arm-icf-exidx.s

 
  .section .text.h
  .global __aeabi_unwind_cpp_pr0
 __aeabi_unwind_cpp_pr0:
  nop
  bx lr
 
 // CHECK: Contents of section .ARM.exidx:
-// CHECK-NEXT:  100d4 18100000 b0b0b080 14100000 01000000
+// CHECK-NEXT:  100d4 18000100 b0b0b080 14000100 01000000
 
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <g>:
-// CHECK-NEXT:    110ec:        1e ff 2f e1     bx      lr
+// CHECK-NEXT:    200ec:        1e ff 2f e1     bx      lr
 // CHECK: <__aeabi_unwind_cpp_pr0>:
-// CHECK-NEXT:    110f0:        00 f0 20 e3     nop
-// CHECK-NEXT:    110f4:        1e ff 2f e1     bx      lr
+// CHECK-NEXT:    200f0:        00 f0 20 e3     nop
+// CHECK-NEXT:    200f4:        1e ff 2f e1     bx      lr

lld/test/ELF/arm-mov-relocs.s

  .align 8
  movw r0, :lower16:label
  movw r1, :lower16:label1
  movw r2, :lower16:label2 + 4
  movw r3, :lower16:label3
  movw r4, :lower16:label3 + 4
 // CHECK-LABEL: Disassembly of section .R_ARM_MOVW_ABS_NC
 // CHECK-EMPTY:
-// CHECK: 12000: movw    r0, #0
+// CHECK: 21000: movw    r0, #0
 // CHECK:        movw    r1, #4
 // CHECK:        movw    r2, #12
 // CHECK:        movw    r3, #65532
 /// :lower16:label3 + 4 = :lower16:0x30000 = 0
 // CHECK:        movw    r4, #0
 
  .section .R_ARM_MOVT_ABS, "ax",%progbits
  .align 8
  movt r0, :upper16:label
  movt r1, :upper16:label1
  movt r2, :upper16:label2 + 4
  movt r3, :upper16:label3
  movt r4, :upper16:label3 + 4
 // CHECK-LABEL: Disassembly of section .R_ARM_MOVT_ABS
 // CHECK-EMPTY:
-// CHECK: 12100: movt    r0, #2
-// CHECK:        movt    r1, #2
-// CHECK:        movt    r2, #2
-// CHECK:        movt    r3, #2
+// CHECK: 21100: movt    r0, #4
+// CHECK:        movt    r1, #4
+// CHECK:        movt    r2, #4
+// CHECK:        movt    r3, #4
 /// :upper16:label3 + 4 = :upper16:0x30000 = 3
-// CHECK:        movt    r4, #3
+// CHECK:        movt    r4, #5
 
 .section .R_ARM_MOVW_PREL_NC, "ax",%progbits
 .align 8
  movw r0, :lower16:label - .
  movw r1, :lower16:label1 - .
  movw r2, :lower16:label2 + 4 - .
  movw r3, :lower16:label3 - .
  movw r4, :lower16:label3 + 0x2214 - .
 // CHECK-LABEL: Disassembly of section .R_ARM_MOVW_PREL_NC
 // CHECK-EMPTY:
 /// :lower16:label - . = 56832
-// CHECK: 12200: movw    r0, #56832
+// CHECK: 21200: movw    r0, #60928
 /// :lower16:label1 - . = 56832
-// CHECK:        movw    r1, #56832
-/// :lower16:label2 - . + 4 = 56836
-// CHECK:        movw    r2, #56836
-/// :lower16:label3 - . = 56816
-// CHECK:        movw    r3, #56816
-/// :lower16:label3 - . + 0x2214 = :lower16:0x20000 = 0
-// CHECK:        movw    r4, #0
+// CHECK:        movw    r1, #60928
+/// :lower16:label2 - . + 4 = 60932
+// CHECK:        movw    r2, #60932
+/// :lower16:label3 - . = 60912
+// CHECK:        movw    r3, #60912
+/// :lower16:label3 - . + 0x2214 = :lower16:0x20000 = 4096
+// CHECK:        movw    r4, #4096
 
 .section .R_ARM_MOVT_PREL, "ax",%progbits
 .align 8
  movt r0, :upper16:label - .
  movt r1, :upper16:label1 - .
  movt r2, :upper16:label2 + 0x4 - .
  movt r3, :upper16:label3 - .
  movt r4, :upper16:label3 + 0x2314 - .
 // CHECK-LABEL: Disassembly of section .R_ARM_MOVT_PREL
 // CHECK-EMPTY:
-/// :upper16:label - . = :upper16:0xdd00  = 0
-// CHECK: 12300: movt    r0, #0
-/// :upper16:label1 - . = :upper16:0xdd00 = 0
-// CHECK:        movt    r1, #0
-/// :upper16:label2 - . + 4 = :upper16:0xdd04 = 0
-// CHECK:        movt    r2, #0
-/// :upper16:label3 - . = :upper16:0x1dcf0 = 1
-// CHECK:        movt    r3, #1
-/// :upper16:label3 - . + 0x2314 = :upper16:0x20000 = 2
-// CHECK:        movt    r4, #2
+/// :upper16:label - . = :upper16:0xdd00  = 1
+// CHECK: 21300: movt    r0, #1
+/// :upper16:label1 - . = :upper16:0xdd00 = 1
+// CHECK:        movt    r1, #1
+/// :upper16:label2 - . + 4 = :upper16:0xdd04 = 1
+// CHECK:        movt    r2, #1
+/// :upper16:label3 - . = :upper16:0x1dcf0 = 2
+// CHECK:        movt    r3, #2
+/// :upper16:label3 - . + 0x2314 = :upper16:0x20000 = 3
+// CHECK:        movt    r4, #3
 
 .section .R_ARM_MOVW_BREL_NC, "ax",%progbits
 .align 8
  movw r0, :lower16:label(sbrel)
  movw r1, :lower16:label1(sbrel)
  movw r2, :lower16:label2(sbrel)
  movw r3, :lower16:label3(sbrel)
  movw r4, :lower16:label3.4(sbrel)
 // CHECK-LABEL: Disassembly of section .R_ARM_MOVW_BREL_NC
 // CHECK-EMPTY:
 // SB = .destination
 /// :lower16:label - SB = 0
-// CHECK: 12400: movw    r0, #0
+// CHECK: 21400: movw    r0, #0
 /// :lower16:label1 - SB = 4
 // CHECK:        movw    r1, #4
 /// :lower16:label2 - SB = 8
 // CHECK:        movw    r2, #8
 /// :lower16:label3 - SB = 0xfffc
 // CHECK:        movw    r3, #65532
 /// :lower16:label3.4 - SB = :lower16:0x10000 = 0
 // CHECK:        movw    r4, #0
 
 .section .R_ARM_MOVT_BREL, "ax",%progbits
 .align 8
  movt r0, :upper16:label(sbrel)
  movt r1, :upper16:label1(sbrel)
  movt r2, :upper16:label2(sbrel)
  movt r3, :upper16:label3(sbrel)
  movt r4, :upper16:label3.4(sbrel)
 // CHECK-LABEL: Disassembly of section .R_ARM_MOVT_BREL
 // CHECK-EMPTY:
 // SB = .destination
 /// :upper16:label - SB = 0
-// CHECK: 12500: movt    r0, #0
+// CHECK: 21500: movt    r0, #0
 /// :upper16:label1 - SB = 0
 // CHECK:        movt    r1, #0
 /// :upper16:label2 - SB = 0
 // CHECK:        movt    r2, #0
 /// :upper16:label3 - SB = 0
 // CHECK:        movt    r3, #0
 /// :upper16:label3.4 - SB = :upper16:0x10000 = 1
 // CHECK:        movt    r4, #1
 
 .section .R_ARM_THM_MOVW_ABS_NC, "ax",%progbits
 .align 8
  movw r0, :lower16:label
  movw r1, :lower16:label1
  movw r2, :lower16:label2 + 4
  movw r3, :lower16:label3
  movw r4, :lower16:label3 + 4
 // CHECK-LABEL: Disassembly of section .R_ARM_THM_MOVW_ABS_NC
 // CHECK-EMPTY:
-// CHECK: 12600: movw    r0, #0
+// CHECK: 21600: movw    r0, #0
 // CHECK:        movw    r1, #4
 // CHECK:        movw    r2, #12
 // CHECK:        movw    r3, #65532
 // CHECK:        movw    r4, #0
 
 .section .R_ARM_THM_MOVT_ABS, "ax",%progbits
 .align 8
  movt r0, :upper16:label
  movt r1, :upper16:label1
  movt r2, :upper16:label2 + 4
  movt r3, :upper16:label3
  movt r4, :upper16:label3 + 4
 // CHECK-LABEL: Disassembly of section .R_ARM_THM_MOVT_ABS
 // CHECK-EMPTY:
-// CHECK: 12700: movt    r0, #2
-// CHECK:        movt    r1, #2
-// CHECK:        movt    r2, #2
-// CHECK:        movt    r3, #2
-// CHECK:        movt    r4, #3
+// CHECK: 21700: movt    r0, #4
+// CHECK:        movt    r1, #4
+// CHECK:        movt    r2, #4
+// CHECK:        movt    r3, #4
+// CHECK:        movt    r4, #5
 
 .section .R_ARM_THM_MOVW_PREL_NC, "ax",%progbits
 .align 8
  movw r0, :lower16:label - .
  movw r1, :lower16:label1 - .
  movw r2, :lower16:label2 + 4 - .
  movw r3, :lower16:label3 - .
  movw r4, :lower16:label3 + 0x2814 - .
 // CHECK-LABEL: Disassembly of section .R_ARM_THM_MOVW_PREL_NC
 // CHECK-EMPTY:
-/// :lower16:label - . = 55296
-// CHECK: 12800: movw    r0, #55296
-/// :lower16:label1 - . = 55296
-// CHECK:        movw    r1, #55296
-/// :lower16:label2 - . + 4 = 55300
-// CHECK:        movw    r2, #55300
-/// :lower16:label3 - . = 55280
-// CHECK:        movw    r3, #55280
+/// :lower16:label - . = 59392
+// CHECK: 21800: movw    r0, #59392
+/// :lower16:label1 - . = 59392
+// CHECK:        movw    r1, #59392
+/// :lower16:label2 - . + 4 = 59396
+// CHECK:        movw    r2, #59396
+/// :lower16:label3 - . = 59376
+// CHECK:        movw    r3, #59376
 /// :lower16:label3 - . + 0x2814 = 0x20000
-// CHECK:        movw    r4, #0
+// CHECK:        movw    r4, #4096
 
 .section .R_ARM_THM_MOVT_PREL, "ax",%progbits
 .align 8
  movt r0, :upper16:label - .
  movt r1, :upper16:label1 - .
  movt r2, :upper16:label2 + 0x4 - .
  movt r3, :upper16:label3 - .
  movt r4, :upper16:label3 + 0x2914 - .
 // CHECK-LABEL: Disassembly of section .R_ARM_THM_MOVT_PREL
 // CHECK-EMPTY:
-/// :upper16:label - . = :upper16:0xd700  = 0
-// CHECK: 12900: movt    r0, #0
-/// :upper16:label1 - . = :upper16:0xd700 = 0
-// CHECK:        movt    r1, #0
-/// :upper16:label2 - . + 4 = :upper16:0xd704 = 0
-// CHECK:        movt    r2, #0
-/// :upper16:label3 - . = :upper16:0x1d6f0 = 1
-// CHECK:        movt    r3, #1
-/// :upper16:label3 - . + 0x2914 = :upper16:0x20000 = 2
-// CHECK:        movt    r4, #2
+/// :upper16:label - . = :upper16:0xd700  = 1
+// CHECK: 21900: movt    r0, #1
+/// :upper16:label1 - . = :upper16:0xd700 = 1
+// CHECK:        movt    r1, #1
+/// :upper16:label2 - . + 4 = :upper16:0xd704 = 1
+// CHECK:        movt    r2, #1
+/// :upper16:label3 - . = :upper16:0x1d6f0 = 2
+// CHECK:        movt    r3, #2
+/// :upper16:label3 - . + 0x2914 = :upper16:0x20000 = 3
+// CHECK:        movt    r4, #3
 
 .section .R_ARM_THM_MOVW_BREL_NC, "ax",%progbits
 .align 8
  movw r0, :lower16:label(sbrel)
  movw r1, :lower16:label1(sbrel)
  movw r2, :lower16:label2(sbrel)
  movw r3, :lower16:label3(sbrel)
  movw r4, :lower16:label3.4(sbrel)
 // CHECK-LABEL: Disassembly of section .R_ARM_THM_MOVW_BREL_NC
 // CHECK-EMPTY:
 // SB = .destination
 /// :lower16:label - SB = 0
-// CHECK: 12a00: movw    r0, #0
+// CHECK: 21a00: movw    r0, #0
 /// :lower16:label1 - SB = 4
 // CHECK:        movw    r1, #4
 /// :lower16:label2 - SB = 8
 // CHECK:        movw    r2, #8
 /// :lower16:label3 - SB = 0xfffc
 // CHECK:        movw    r3, #65532
 /// :lower16:label3.4 - SB = :lower16:0x10000 = 0
 // CHECK:        movw    r4, #0
 
 .section .R_ARM_THM_MOVT_BREL, "ax",%progbits
 .align 8
  movt r0, :upper16:label(sbrel)
  movt r1, :upper16:label1(sbrel)
  movt r2, :upper16:label2(sbrel)
  movt r3, :upper16:label3(sbrel)
  movt r4, :upper16:label3.4(sbrel)
 // CHECK-LABEL: Disassembly of section .R_ARM_THM_MOVT_BREL
 // CHECK-EMPTY:
 /// SB = .destination
 /// :upper16:label - SB = 0
-// CHECK: 12b00: movt    r0, #0
+// CHECK: 21b00: movt    r0, #0
 /// :upper16:label1 - SB = 0
 // CHECK:        movt    r1, #0
 /// :upper16:label2 - SB = 0
 // CHECK:        movt    r2, #0
 /// :upper16:label3 - SB = 0
 // CHECK:        movt    r3, #0
 /// :upper16:label3.4 - SB = :upper16:0x10000 = 1
 // CHECK:        movt    r4, #1

lld/test/ELF/arm-pie-relative.s

 
  .data
  .global sym
 sym:
  .word 0
 
 // CHECK:      Relocations [
 // CHECK-NEXT:   Section (5) .rel.dyn {
-// CHECK-NEXT:     0x21DC R_ARM_RELATIVE
+// CHECK-NEXT:     0x201DC R_ARM_RELATIVE
 
 // GOT:      section '.got':
-// GOT-NEXT: 0x000021dc e0310000
+// GOT-NEXT: 0x000201dc e0010300

lld/test/ELF/arm-plt-reloc.s

  b func1
  bl func2
  beq func3
 
 // Executable, expect no PLT
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <func1>:
-// CHECK-NEXT:   110b4:       bx      lr
+// CHECK-NEXT:   200b4:       bx      lr
 // CHECK: <func2>:
-// CHECK-NEXT:   110b8:       bx      lr
+// CHECK-NEXT:   200b8:       bx      lr
 // CHECK: <func3>:
-// CHECK-NEXT:   110bc:       bx      lr
+// CHECK-NEXT:   200bc:       bx      lr
 // CHECK: <_start>:
-// CHECK-NEXT:   110c0:       b       #-20 <func1>
-// CHECK-NEXT:   110c4:       bl      #-20 <func2>
-// CHECK-NEXT:   110c8:       beq     #-20 <func3>
+// CHECK-NEXT:   200c0:       b       #-20 <func1>
+// CHECK-NEXT:   200c4:       bl      #-20 <func2>
+// CHECK-NEXT:   200c8:       beq     #-20 <func3>
 
 // Expect PLT entries as symbols can be preempted
 // The .got.plt and .plt displacement is small so we can use small PLT entries.
 // DSO: Disassembly of section .text:
 // DSO-EMPTY:
 // DSO-NEXT: <func1>:
-// DSO-NEXT:     1214:       bx      lr
+// DSO-NEXT:     10214:       bx      lr
 // DSO: <func2>:
-// DSO-NEXT:     1218:       bx      lr
+// DSO-NEXT:     10218:       bx      lr
 // DSO: <func3>:
-// DSO-NEXT:     121c:       bx      lr
+// DSO-NEXT:     1021c:       bx      lr
 // DSO: <_start>:
-// S(0x1214) - P(0x1220) + A(-8) = 0x2c = 32
-// DSO-NEXT:     1220:       b       #40
-// S(0x1218) - P(0x1224) + A(-8) = 0x38 = 56
-// DSO-NEXT:     1224:       bl      #52
-// S(0x121c) - P(0x1228) + A(-8) = 0x44 = 68
-// DSO-NEXT:     1228:       beq     #64
+// S(0x10214) - P(0x10220) + A(-8) = 0x2c = 32
+// DSO-NEXT:     10220:       b       #40
+// S(0x10218) - P(0x10224) + A(-8) = 0x38 = 56
+// DSO-NEXT:     10224:       bl      #52
+// S(0x1021c) - P(0x10228) + A(-8) = 0x44 = 68
+// DSO-NEXT:     10228:       beq     #64
 // DSO-EMPTY:
 // DSO-NEXT: Disassembly of section .plt:
 // DSO-EMPTY:
 // DSO-NEXT: <$a>:
-// DSO-NEXT:     1230:       str     lr, [sp, #-4]!
-// (0x1234 + 8) + (0 RoR 12) + 8192 + 164 = 0x32e0 = .got.plt[2]
-// DSO-NEXT:     1234:       add     lr, pc, #0, #12
-// DSO-NEXT:     1238:       add     lr, lr, #8192
-// DSO-NEXT:     123c:       ldr     pc, [lr, #164]!
+// DSO-NEXT:     10230:       str     lr, [sp, #-4]!
+// (0x10234 + 8) + (0 RoR 12) + 8192 + 164 = 0x32e0 = .got.plt[2]
+// DSO-NEXT:     10234:       add     lr, pc, #0, #12
+// DSO-NEXT:     10238:       add     lr, lr, #32
+// DSO-NEXT:     1023c:       ldr     pc, [lr, #164]!
 // DSO: <$d>:
-// DSO-NEXT:     1240:       d4 d4 d4 d4     .word   0xd4d4d4d4
-// DSO-NEXT:     1244:       d4 d4 d4 d4     .word   0xd4d4d4d4
-// DSO-NEXT:     1248:       d4 d4 d4 d4     .word   0xd4d4d4d4
-// DSO-NEXT:     124c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     10240:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     10244:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     10248:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     1024c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 // DSO: <$a>:
-// (0x1250 + 8) + (0 RoR 12) + 8192 + 140 = 0x32e4
-// DSO-NEXT:     1250:       add     r12, pc, #0, #12
-// DSO-NEXT:     1254:       add     r12, r12, #8192
-// DSO-NEXT:     1258:       ldr     pc, [r12, #140]!
+// (0x10250 + 8) + (0 RoR 12) + 8192 + 140 = 0x32e4
+// DSO-NEXT:     10250:       add     r12, pc, #0, #12
+// DSO-NEXT:     10254:       add     r12, r12, #32
+// DSO-NEXT:     10258:       ldr     pc, [r12, #140]!
 // DSO: <$d>:
-// DSO-NEXT:     125c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     1025c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 // DSO: <$a>:
-// (0x1260 + 8) + (0 RoR 12) + 8192 + 128 = 0x32e8
-// DSO-NEXT:     1260:       add     r12, pc, #0, #12
-// DSO-NEXT:     1264:       add     r12, r12, #8192
-// DSO-NEXT:     1268:       ldr     pc, [r12, #128]!
+// (0x10260 + 8) + (0 RoR 12) + 8192 + 128 = 0x32e8
+// DSO-NEXT:     10260:       add     r12, pc, #0, #12
+// DSO-NEXT:     10264:       add     r12, r12, #32
+// DSO-NEXT:     10268:       ldr     pc, [r12, #128]!
 // DSO: <$d>:
-// DSO-NEXT:     126c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     1026c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 // DSO: <$a>:
-// (0x1270 + 8) + (0 RoR 12) + 8192 + 116 = 0x32ec
-// DSO-NEXT:     1270:       add     r12, pc, #0, #12
-// DSO-NEXT:     1274:       add     r12, r12, #8192
-// DSO-NEXT:     1278:       ldr     pc, [r12, #116]!
+// (0x10270 + 8) + (0 RoR 12) + 8192 + 116 = 0x32ec
+// DSO-NEXT:     10270:       add     r12, pc, #0, #12
+// DSO-NEXT:     10274:       add     r12, r12, #32
+// DSO-NEXT:     10278:       ldr     pc, [r12, #116]!
 // DSO: <$d>:
-// DSO-NEXT:     127c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     1027c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 
 
 // DSOREL:    Name: .got.plt
 // DSOREL-NEXT:    Type: SHT_PROGBITS
 // DSOREL-NEXT:    Flags [
 // DSOREL-NEXT:      SHF_ALLOC
 // DSOREL-NEXT:      SHF_WRITE
 // DSOREL-NEXT:    ]
-// DSOREL-NEXT:    Address: 0x32D8
+// DSOREL-NEXT:    Address: 0x302D8
 // DSOREL-NEXT:    Offset:
 // DSOREL-NEXT:    Size: 24
 // DSOREL-NEXT:    Link:
 // DSOREL-NEXT:    Info:
 // DSOREL-NEXT:    AddressAlignment: 4
 // DSOREL-NEXT:    EntrySize:
 // DSOREL:  Relocations [
 // DSOREL-NEXT:  Section {{.*}} .rel.plt {
-// DSOREL-NEXT:    0x32E4 R_ARM_JUMP_SLOT func1 0x0
-// DSOREL-NEXT:    0x32E8 R_ARM_JUMP_SLOT func2 0x0
-// DSOREL-NEXT:    0x32EC R_ARM_JUMP_SLOT func3 0x0
+// DSOREL-NEXT:    0x302E4 R_ARM_JUMP_SLOT func1 0x0
+// DSOREL-NEXT:    0x302E8 R_ARM_JUMP_SLOT func2 0x0
+// DSOREL-NEXT:    0x302EC R_ARM_JUMP_SLOT func3 0x0
 
 // Test a large separation between the .plt and .got.plt
 // The .got.plt and .plt displacement is large but still within the range
 // of the short plt sequence.
 // RUN: echo "SECTIONS { \
 // RUN:       .text 0x1000 : { *(.text) } \
 // RUN:       .plt  0x2000 : { *(.plt) *(.plt.*) } \
 // RUN:       .got.plt 0x1100000 : { *(.got.plt) } \

lld/test/ELF/arm-sbrel32.s

foo2:   .word 20
 
         .bss
 foo3:   .space 4
 foo4:   .space 4
 
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <_start>:
-// CHECK-NEXT:    110d4:        1e ff 2f e1     bx      lr
-// CHECK:         110d8:        00 00 00 00     .word   0x00000000
-// CHECK-NEXT:    110dc:        04 00 00 00     .word   0x00000004
-// CHECK-NEXT:    110e0:        08 00 00 00     .word   0x00000008
-// CHECK-NEXT:    110e4:        0c 00 00 00     .word   0x0000000c
+// CHECK-NEXT:    200d4:        1e ff 2f e1     bx      lr
+// CHECK:         200d8:        00 00 00 00     .word   0x00000000
+// CHECK-NEXT:    200dc:        04 00 00 00     .word   0x00000004
+// CHECK-NEXT:    200e0:        08 00 00 00     .word   0x00000008
+// CHECK-NEXT:    200e4:        0c 00 00 00     .word   0x0000000c

lld/test/ELF/arm-target1.s

 
 .text
   .word patatino(target1)
   patatino:
         .word 32
 // Force generation of $d.0 as section is not all data
   nop
 // RELATIVE: SYMBOL TABLE:
-// RELATIVE: 00001154 l       .text           00000000 patatino
+// RELATIVE: 00010154 l       .text           00000000 patatino
 // RELATIVE: Disassembly of section .text:
 // RELATIVE-EMPTY:
 // RELATIVE: <$d.0>:
-// RELATIVE:     1150:       04 00 00 00     .word   0x00000004
+// RELATIVE:     10150:       04 00 00 00     .word   0x00000004
 
 // ABS: can't create dynamic relocation R_ARM_TARGET1 against symbol: patatino in readonly segment; recompile object files with -fPIC or pass '-Wl,-z,notext' to allow text relocations in the output
 // ABS: >>> defined in {{.*}}.o
 // ABS: >>> referenced by {{.*}}.o:(.text+0x0)

lld/test/ELF/arm-target2.s

 __gxx_personality_v0:
  bx lr
 
  .rodata
 _ZTIi:  .word 0
 
 // CHECK: Contents of section .ARM.extab:
 // 0x1012c + 0x2010 = 0x1213c = .got
-// CHECK-NEXT:  10124 14100000 b0b0b000 10200000
+// CHECK-NEXT:  10124 14000100 b0b0b000 10000200
 
 // CHECK-ABS: Contents of section .ARM.extab:
 // 0x100f0 = .rodata
-// CHECK-ABS-NEXT: 100e4 14100000 b0b0b000 f0000100
+// CHECK-ABS-NEXT: 100e4 14000100 b0b0b000 f0000100
 
 // CHECK-REL: Contents of section .ARM.extab:
 // 0x100ec + 4 = 0x100f0 = .rodata
-// CHECK-REL-NEXT: 100e4 14100000 b0b0b000 04000000
+// CHECK-REL-NEXT: 100e4 14000100 b0b0b000 04000000
 
 // CHECK: Contents of section .rodata:
 // CHECK-NEXT: 10130 00000000
 
 // CHECK-ABS: Contents of section .rodata:
 // CHECK-ABS-NEXT: 100f0 00000000
 
 // CHECK-REL: Contents of section .rodata:
 // CHECK-REL-NEXT: 100f0 00000000
 
 // CHECK: Contents of section .got:
 // 10130 = _ZTIi
-// CHECK-NEXT: 1213c 30010100
+// CHECK-NEXT: 3013c 30010100

lld/test/ELF/arm-thumb-adr.s

  .section .text.03, "ax", %progbits
  .balign 4
  .space 1016
  .type target2, %function
 target2:
  nop
  bx lr
 
-// CHECK: 000110b4 <_start>:
-// CHECK-NEXT: 110b4: adr     r0, #0
-// CHECK-NEXT: 110b6: adr     r1, #1020
+// CHECK: 000200b4 <_start>:
+// CHECK-NEXT: 200b4: adr     r0, #0
+// CHECK-NEXT: 200b6: adr     r1, #1020
 
-// CHECK: 000110b8 <target1>:
-// CHECK-NEXT: 110b8: nop
-// CHECK-NEXT: 110ba: bx      lr
+// CHECK: 000200b8 <target1>:
+// CHECK-NEXT: 200b8: nop
+// CHECK-NEXT: 200ba: bx      lr
 
-// CHECK: 000114b4 <target2>:
-// CHECK-NEXT: 114b4: nop
-// CHECK-NEXT: 114b6: bx      lr
+// CHECK: 000204b4 <target2>:
+// CHECK-NEXT: 204b4: nop
+// CHECK-NEXT: 204b6: bx      lr

lld/test/ELF/arm-thumb-interwork-abs.s

// WARN: branch and link relocation: R_ARM_CALL to non STT_FUNC symbol: sym interworking not performed; consider using directive '.type sym, %function' to give symbol type STT_FUNC if interworking between ARM and Thumb is required
   blx sym
 .thumb
 thumb_caller:
   b sym
   bl sym
   blx sym
 // WARN: branch and link relocation: R_ARM_THM_CALL to non STT_FUNC symbol: sym interworking not performed; consider using directive '.type sym, %function' to give symbol type STT_FUNC if interworking between ARM and Thumb is required
 
-// CHECK: 00012000 <arm_caller>:
-// CHECK-NEXT:    12000: b   #4088
-// CHECK-NEXT:    12004: bl  #4084
-// CHECK-NEXT:    12008: blx #4080
+// CHECK: 00021000 <arm_caller>:
+// CHECK-NEXT:    21000: b   #-57352
+// CHECK-NEXT:    21004: bl  #-57356
+// CHECK-NEXT:    21008: blx #-57360
 
-// CHECK: 0001200c <thumb_caller>:
-// CHECK-NEXT:    1200c: b.w     #4080
-// CHECK-NEXT:    12010: bl      #4076
-// CHECK-NEXT:    12014: blx     #4076
+// CHECK: 0002100c <thumb_caller>:
+// CHECK-NEXT:    2100c: b.w     #-57360
+// CHECK-NEXT:    21010: bl      #-57364
+// CHECK-NEXT:    21014: blx     #-57364

lld/test/ELF/arm-thumb-interwork-notfunc.s

  bl thumb_func_with_explicit_notype
  blx .arm_target
  blx arm_func_with_notype
  blx arm_func_with_explicit_notype
  blx .thumb_target
  blx thumb_func_with_notype
  blx thumb_func_with_explicit_notype
 
-// CHECK: 00012008 <_start>:
-// CHECK-NEXT: 12008: b       #-16
-// CHECK-NEXT: 1200c: b       #-20
-// CHECK-NEXT: 12010: b       #-24
-// CHECK-NEXT: 12014: b       #-24
-// CHECK-NEXT: 12018: b       #-28
-// CHECK-NEXT: 1201c: b       #-32
-// CHECK-NEXT: 12020: bl      #-40
-// CHECK-NEXT: 12024: bl      #-44
-// CHECK-NEXT: 12028: bl      #-48
-// CHECK-NEXT: 1202c: bl      #-48
-// CHECK-NEXT: 12030: bl      #-52
-// CHECK-NEXT: 12034: bl      #-56
-// CHECK-NEXT: 12038: blx     #-64
-// CHECK-NEXT: 1203c: blx     #-68
-// CHECK-NEXT: 12040: blx     #-72
-// CHECK-NEXT: 12044: blx     #-72
-// CHECK-NEXT: 12048: blx     #-76
-// CHECK-NEXT: 1204c: blx     #-80
-
-// CHECK: 00012050 <thumb_caller>:
-// CHECK-NEXT: 12050: b.w     #-84
-// CHECK-NEXT: 12054: b.w     #-88
-// CHECK-NEXT: 12058: b.w     #-92
-// CHECK-NEXT: 1205c: b.w     #-92
-// CHECK-NEXT: 12060: b.w     #-96
-// CHECK-NEXT: 12064: b.w     #-100
-// CHECK-NEXT: 12068: beq.w   #-108
-// CHECK-NEXT: 1206c: beq.w   #-112
-// CHECK-NEXT: 12070: beq.w   #-116
-// CHECK-NEXT: 12074: beq.w   #-116
-// CHECK-NEXT: 12078: beq.w   #-120
-// CHECK-NEXT: 1207c: beq.w   #-124
-// CHECK-NEXT: 12080: bl      #-132
-// CHECK-NEXT: 12084: bl      #-136
-// CHECK-NEXT: 12088: bl      #-140
-// CHECK-NEXT: 1208c: bl      #-140
-// CHECK-NEXT: 12090: bl      #-144
-// CHECK-NEXT: 12094: bl      #-148
-// CHECK-NEXT: 12098: blx     #-156
-// CHECK-NEXT: 1209c: blx     #-160
-// CHECK-NEXT: 120a0: blx     #-164
-// CHECK-NEXT: 120a4: blx     #-164
-// CHECK-NEXT: 120a8: blx     #-168
-// CHECK-NEXT: 120ac: blx     #-172
+// CHECK: 00021008 <_start>:
+// CHECK-NEXT: 21008: b       #-16
+// CHECK-NEXT: 2100c: b       #-20
+// CHECK-NEXT: 21010: b       #-24
+// CHECK-NEXT: 21014: b       #-24
+// CHECK-NEXT: 21018: b       #-28
+// CHECK-NEXT: 2101c: b       #-32
+// CHECK-NEXT: 21020: bl      #-40
+// CHECK-NEXT: 21024: bl      #-44
+// CHECK-NEXT: 21028: bl      #-48
+// CHECK-NEXT: 2102c: bl      #-48
+// CHECK-NEXT: 21030: bl      #-52
+// CHECK-NEXT: 21034: bl      #-56
+// CHECK-NEXT: 21038: blx     #-64
+// CHECK-NEXT: 2103c: blx     #-68
+// CHECK-NEXT: 21040: blx     #-72
+// CHECK-NEXT: 21044: blx     #-72
+// CHECK-NEXT: 21048: blx     #-76
+// CHECK-NEXT: 2104c: blx     #-80
+
+// CHECK: 00021050 <thumb_caller>:
+// CHECK-NEXT: 21050: b.w     #-84
+// CHECK-NEXT: 21054: b.w     #-88
+// CHECK-NEXT: 21058: b.w     #-92
+// CHECK-NEXT: 2105c: b.w     #-92
+// CHECK-NEXT: 21060: b.w     #-96
+// CHECK-NEXT: 21064: b.w     #-100
+// CHECK-NEXT: 21068: beq.w   #-108
+// CHECK-NEXT: 2106c: beq.w   #-112
+// CHECK-NEXT: 21070: beq.w   #-116
+// CHECK-NEXT: 21074: beq.w   #-116
+// CHECK-NEXT: 21078: beq.w   #-120
+// CHECK-NEXT: 2107c: beq.w   #-124
+// CHECK-NEXT: 21080: bl      #-132
+// CHECK-NEXT: 21084: bl      #-136
+// CHECK-NEXT: 21088: bl      #-140
+// CHECK-NEXT: 2108c: bl      #-140
+// CHECK-NEXT: 21090: bl      #-144
+// CHECK-NEXT: 21094: bl      #-148
+// CHECK-NEXT: 21098: blx     #-156
+// CHECK-NEXT: 2109c: blx     #-160
+// CHECK-NEXT: 210a0: blx     #-164
+// CHECK-NEXT: 210a4: blx     #-164
+// CHECK-NEXT: 210a8: blx     #-168
+// CHECK-NEXT: 210ac: blx     #-172

lld/test/ELF/arm-thumb-interwork-shared.s

  bl weakref
 
 // Check that we generate a thunk for an undefined symbol called via a plt
 // entry.
 
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <sym1>:
-// CHECK-NEXT:     11e0: b.w #12 <__ThumbV7PILongThunk_elsewhere>
+// CHECK-NEXT:     101e0: b.w #12 <__ThumbV7PILongThunk_elsewhere>
 // CHECK-NEXT:           b.w #20 <__ThumbV7PILongThunk_weakref>
 // CHECK-NEXT:           blx #68
 // CHECK-NEXT:           blx #80
 // CHECK: <__ThumbV7PILongThunk_elsewhere>:
-// CHECK-NEXT:     11f0: movw    r12, #52
+// CHECK-NEXT:     101f0: movw    r12, #52
 // CHECK-NEXT:           movt    r12, #0
 // CHECK-NEXT:           add     r12, pc
 // CHECK-NEXT:           bx      r12
 // CHECK: <__ThumbV7PILongThunk_weakref>:
-// CHECK-NEXT:     11fc: movw    r12, #56
+// CHECK-NEXT:     101fc: movw    r12, #56
 // CHECK-NEXT:           movt    r12, #0
 // CHECK-NEXT:           add     r12, pc
 // CHECK-NEXT:           bx      r12
 
 // CHECK: Disassembly of section .plt:
 // CHECK-EMPTY:
 // CHECK-NEXT: <$a>:
-// CHECK-NEXT:     1210: str     lr, [sp, #-4]!
+// CHECK-NEXT:     10210: str     lr, [sp, #-4]!
 // CHECK-NEXT:           add     lr, pc, #0, #12
-// CHECK-NEXT:           add     lr, lr, #8192
+// CHECK-NEXT:           add     lr, lr, #32
 // CHECK-NEXT:           ldr     pc, [lr, #148]!
 // CHECK: <$d>:
-// CHECK-NEXT:     1220: d4 d4 d4 d4 .word   0xd4d4d4d4
+// CHECK-NEXT:     10220: d4 d4 d4 d4 .word   0xd4d4d4d4
 // CHECK-NEXT:           .word   0xd4d4d4d4
 // CHECK-NEXT:           .word   0xd4d4d4d4
 // CHECK-NEXT:           .word   0xd4d4d4d4
 // CHECK: <$a>:
-// CHECK-NEXT:     1230: add     r12, pc, #0, #12
-// CHECK-NEXT:           add     r12, r12, #8192
+// CHECK-NEXT:     10230: add     r12, pc, #0, #12
+// CHECK-NEXT:           add     r12, r12, #32
 // CHECK-NEXT:           ldr     pc, [r12, #124]!
 // CHECK: <$d>:
-// CHECK-NEXT:     123c: d4 d4 d4 d4 .word   0xd4d4d4d4
+// CHECK-NEXT:     1023c: d4 d4 d4 d4 .word   0xd4d4d4d4
 // CHECK: <$a>:
-// CHECK-NEXT:     1240: add     r12, pc, #0, #12
-// CHECK-NEXT:           add     r12, r12, #8192
+// CHECK-NEXT:     10240: add     r12, pc, #0, #12
+// CHECK-NEXT:           add     r12, r12, #32
 // CHECK-NEXT:           ldr     pc, [r12, #112]!
 // CHECK: <$d>:
-// CHECK-NEXT:     124c: d4 d4 d4 d4 .word   0xd4d4d4d4
+// CHECK-NEXT:     1024c: d4 d4 d4 d4 .word   0xd4d4d4d4

lld/test/ELF/arm-thumb-interwork-thunk-v5.s

// support for the blx instruction for Thumb BL and BLX to an Arm symbol.
         .balign 0x1000
 _start:
         b thumb_func
         bl thumb_func
         blx thumb_func
         bx lr
 
 // CHECK: <_start>:
-// CHECK-NEXT: 12000: 03 00 00 ea     b       #12 <__ARMv5ABSLongThunk_thumb_func>
-// CHECK-NEXT: 12004: 01 00 00 fa     blx     #4 <thumb_func>
-// CHECK-NEXT: 12008: 00 00 00 fa     blx     #0 <thumb_func>
-// CHECK-NEXT: 1200c: 1e ff 2f e1     bx      lr
+// CHECK-NEXT: 21000: 03 00 00 ea     b       #12 <__ARMv5ABSLongThunk_thumb_func>
+// CHECK-NEXT: 21004: 01 00 00 fa     blx     #4 <thumb_func>
+// CHECK-NEXT: 21008: 00 00 00 fa     blx     #0 <thumb_func>
+// CHECK-NEXT: 2100c: 1e ff 2f e1     bx      lr
 
 // CHECK: <thumb_func>:
-// CHECK-NEXT: 12010: 70 47   bx      lr
+// CHECK-NEXT: 21010: 70 47   bx      lr
 
 // CHECK: <__ARMv5ABSLongThunk_thumb_func>:
-// CHECK-NEXT: 12014: 04 f0 1f e5     ldr     pc, [pc, #-4]
+// CHECK-NEXT: 21014: 04 f0 1f e5     ldr     pc, [pc, #-4]
 // CHECK: <$d>:
-// CHECK-NEXT: 12018: 11 20 01 00     .word   0x00012011
+// CHECK-NEXT: 21018: 11 10 02 00     .word   0x00021011
 
 // CHECK-PI: <_start>:
-// CHECK-PI-NEXT: 2000: 03 00 00 ea     b       #12 <__ARMV5PILongThunk_thumb_func>
-// CHECK-PI-NEXT: 2004: 01 00 00 fa     blx     #4 <thumb_func>
-// CHECK-PI-NEXT: 2008: 00 00 00 fa     blx     #0 <thumb_func>
-// CHECK-PI-NEXT: 200c: 1e ff 2f e1     bx      lr
+// CHECK-PI-NEXT: 11000: 03 00 00 ea     b       #12 <__ARMV5PILongThunk_thumb_func>
+// CHECK-PI-NEXT: 11004: 01 00 00 fa     blx     #4 <thumb_func>
+// CHECK-PI-NEXT: 11008: 00 00 00 fa     blx     #0 <thumb_func>
+// CHECK-PI-NEXT: 1100c: 1e ff 2f e1     bx      lr
 
 // CHECK-PI: <thumb_func>:
-// CHECK-PI-NEXT: 2010: 70 47   bx      lr
+// CHECK-PI-NEXT: 11010: 70 47   bx      lr
 
 // CHECK-PI: <__ARMV5PILongThunk_thumb_func>:
-// CHECK-PI-NEXT: 2014: 04 c0 9f e5     ldr     r12, [pc, #4]
-// CHECK-PI-NEXT: 2018: 0c c0 8f e0     add     r12, pc, r12
-// CHECK-PI-NEXT: 201c: 1c ff 2f e1     bx      r12
+// CHECK-PI-NEXT: 11014: 04 c0 9f e5     ldr     r12, [pc, #4]
+// CHECK-PI-NEXT: 11018: 0c c0 8f e0     add     r12, pc, r12
+// CHECK-PI-NEXT: 1101c: 1c ff 2f e1     bx      r12
 // CHECK-PI: <$d>:
-// CHECK-PI-NEXT: 2020: f1 ff ff ff     .word   0xfffffff1
+// CHECK-PI-NEXT: 11020: f1 ff ff ff     .word   0xfffffff1
 
         .section .text.1, "ax", %progbits
         .thumb
         .hidden thumb_func
         .type thumb_func, %function
 thumb_func:
         bx lr

lld/test/ELF/arm-thumb-ldrlit.s

  .section .text.03, "ax", %progbits
  .balign 4
  .space 1016
  .type target2, %function
 target2:
  nop
  bx lr
 
-// CHECK: 000110b4 <_start>:
-// CHECK-NEXT: 110b4: ldr     r0, [pc, #0]
-// CHECK-NEXT: 110b6: ldr     r1, [pc, #1020]
+// CHECK: 000200b4 <_start>:
+// CHECK-NEXT: 200b4: ldr     r0, [pc, #0]
+// CHECK-NEXT: 200b6: ldr     r1, [pc, #1020]
 
-// CHECK: 000110b8 <target1>:
-// CHECK-NEXT: 110b8: nop
-// CHECK-NEXT: 110ba: bx      lr
+// CHECK: 000200b8 <target1>:
+// CHECK-NEXT: 200b8: nop
+// CHECK-NEXT: 200ba: bx      lr
 
-// CHECK: 000114b4 <target2>:
-// CHECK-NEXT: 114b4: nop
-// CHECK-NEXT: 114b6: bx      lr
+// CHECK: 000204b4 <target2>:
+// CHECK-NEXT: 204b4: nop
+// CHECK-NEXT: 204b6: bx      lr

lld/test/ELF/arm-thumb-no-undefined-thunk.s

  bl target
  b target
  b.w target
 
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <_start>:
 // 0x110b8 = next instruction
-// CHECK:         110b4: {{.*}} bl      #0
-// CHECK-NEXT:    110b8: {{.*}} b.w     #0 <_start+0x8>
-// CHECK-NEXT:    110bc: {{.*}} b.w     #0 <_start+0xc>
+// CHECK:         200b4: {{.*}} bl      #0
+// CHECK-NEXT:    200b8: {{.*}} b.w     #0 <_start+0x8>
+// CHECK-NEXT:    200bc: {{.*}} b.w     #0 <_start+0xc>

lld/test/ELF/arm-thumb-plt-range-thunk-os.s

 // CHECK3: <far_preemptible>:
 // CHECK3:  4000000:       00 f0 16 e8     blx     #44
 
 // CHECK4: Disassembly of section .plt:
 // CHECK4-EMPTY:
 // CHECK4-NEXT: <$a>:
 // CHECK4-NEXT:  4000010: 04 e0 2d e5   str lr, [sp, #-4]!
 // CHECK4-NEXT:  4000014: 00 e6 8f e2   add lr, pc, #0, #12
-// CHECK4-NEXT:  4000018: 02 ea 8e e2   add lr, lr, #8192
+// CHECK4-NEXT:  4000018: 20 ea 8e e2   add lr, lr, #32
 // CHECK4-NEXT:  400001c: a4 f0 be e5   ldr pc, [lr, #164]!
 // CHECK4: <$d>:
 // CHECK4-NEXT:  4000020: d4 d4 d4 d4   .word 0xd4d4d4d4
 // CHECK4-NEXT:  4000024: d4 d4 d4 d4   .word 0xd4d4d4d4
 // CHECK4-NEXT:  4000028: d4 d4 d4 d4   .word 0xd4d4d4d4
 // CHECK4-NEXT:  400002c: d4 d4 d4 d4   .word 0xd4d4d4d4
 // CHECK4: <$a>:
 // CHECK4-NEXT:  4000030: 00 c6 8f e2   add r12, pc, #0, #12
-// CHECK4-NEXT:  4000034: 02 ca 8c e2   add r12, r12, #8192
+// CHECK4-NEXT:  4000034: 20 ca 8c e2   add r12, r12, #32
 // CHECK4-NEXT:  4000038: 8c f0 bc e5   ldr pc, [r12, #140]!
 // CHECK4: <$d>:
 // CHECK4-NEXT:  400003c: d4 d4 d4 d4   .word 0xd4d4d4d4
 // CHECK4: <$a>:
 // CHECK4-NEXT:  4000040: 00 c6 8f e2   add r12, pc, #0, #12
-// CHECK4-NEXT:  4000044: 02 ca 8c e2   add r12, r12, #8192
+// CHECK4-NEXT:  4000044: 20 ca 8c e2   add r12, r12, #32
 // CHECK4-NEXT:  4000048: 80 f0 bc e5   ldr pc, [r12, #128]!
 // CHECK4: <$d>:
 // CHECK4-NEXT:  400004c: d4 d4 d4 d4   .word 0xd4d4d4d4
 // CHECK4: <$a>:
 // CHECK4-NEXT:  4000050: 00 c6 8f e2   add r12, pc, #0, #12
-// CHECK4-NEXT:  4000054: 02 ca 8c e2   add r12, r12, #8192
+// CHECK4-NEXT:  4000054: 20 ca 8c e2   add r12, r12, #32
 // CHECK4-NEXT:  4000058: 74 f0 bc e5   ldr pc, [r12, #116]!
 // CHECK4: <$d>:
 // CHECK4-NEXT:  400005c: d4 d4 d4 d4   .word 0xd4d4d4d4

lld/test/ELF/arm-thumb-plt-reloc.s

  bl func1
  bl func2
  bl func3
 
 // Executable, expect no PLT
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <func1>:
-// CHECK-NEXT:   110b4: 70 47   bx      lr
+// CHECK-NEXT:   200b4: 70 47   bx      lr
 // CHECK: <func2>:
-// CHECK-NEXT:   110b6: 70 47   bx      lr
+// CHECK-NEXT:   200b6: 70 47   bx      lr
 // CHECK: <func3>:
-// CHECK-NEXT:   110b8: 70 47   bx      lr
-// CHECK-NEXT:   110ba: d4 d4
+// CHECK-NEXT:   200b8: 70 47   bx      lr
+// CHECK-NEXT:   200ba: d4 d4
 // CHECK: <_start>:
-// . + 4 -12 = 0x110b4 = func1
-// CHECK-NEXT:   110bc: ff f7 fa ff     bl      #-12
-// . + 4 -14 = 0x110b6 = func2
-// CHECK-NEXT:   110c0: ff f7 f9 ff     bl      #-14
-// . + 4 -16 = 0x110b8 = func3
-// CHECK-NEXT:   110c4: ff f7 f8 ff     bl      #-16
+// . + 4 -12 = 0x200b4 = func1
+// CHECK-NEXT:   200bc: ff f7 fa ff     bl      #-12
+// . + 4 -14 = 0x200b6 = func2
+// CHECK-NEXT:   200c0: ff f7 f9 ff     bl      #-14
+// . + 4 -16 = 0x200b8 = func3
+// CHECK-NEXT:   200c4: ff f7 f8 ff     bl      #-16
 
 // Expect PLT entries as symbols can be preempted
 // .text is Thumb and .plt is ARM, llvm-objdump can currently only disassemble
 // as ARM or Thumb. Work around by disassembling twice.
 // DSO: Disassembly of section .text:
 // DSO-EMPTY:
 // DSO-NEXT: <func1>:
-// DSO-NEXT:     1214:     70 47   bx      lr
+// DSO-NEXT:     10214:     70 47   bx      lr
 // DSO: <func2>:
-// DSO-NEXT:     1216:     70 47   bx      lr
+// DSO-NEXT:     10216:     70 47   bx      lr
 // DSO: <func3>:
-// DSO-NEXT:     1218:     70 47   bx      lr
-// DSO-NEXT:     121a:     d4 d4   bmi     #-88
+// DSO-NEXT:     10218:     70 47   bx      lr
+// DSO-NEXT:     1021a:     d4 d4   bmi     #-88
 // DSO: <_start>:
-// . + 48 + 4 = 0x1250 = PLT func1
-// DSO-NEXT:     121c:     00 f0 18 e8     blx     #48
-// . + 60 + 4 = 0x1260 = PLT func2
-// DSO-NEXT:     1220:     00 f0 1e e8     blx     #60
-// . + 72 + 4 = 0x1270 = PLT func3
-// DSO-NEXT:     1224:     00 f0 24 e8     blx     #72
+// . + 48 + 4 = 0x10250 = PLT func1
+// DSO-NEXT:     1021c:     00 f0 18 e8     blx     #48
+// . + 60 + 4 = 0x10260 = PLT func2
+// DSO-NEXT:     10220:     00 f0 1e e8     blx     #60
+// . + 72 + 4 = 0x10270 = PLT func3
+// DSO-NEXT:     10224:     00 f0 24 e8     blx     #72
 // DSO: Disassembly of section .plt:
 // DSO-EMPTY:
 // DSO-NEXT: <$a>:
-// DSO-NEXT:     1230:       04 e0 2d e5     str     lr, [sp, #-4]!
-// (0x1234 + 8) + (0 RoR 12) + 8192 + 164 = 0x32e0 = .got.plt[3]
-// DSO-NEXT:     1234:       00 e6 8f e2     add     lr, pc, #0, #12
-// DSO-NEXT:     1238:       02 ea 8e e2     add     lr, lr, #8192
-// DSO-NEXT:     123c:       a4 f0 be e5     ldr     pc, [lr, #164]!
+// DSO-NEXT:     10230:       04 e0 2d e5     str     lr, [sp, #-4]!
+// (0x10234 + 8) + (0 RoR 12) + 8192 + 164 = 0x32e0 = .got.plt[3]
+// DSO-NEXT:     10234:       00 e6 8f e2     add     lr, pc, #0, #12
+// DSO-NEXT:     10238:       20 ea 8e e2     add     lr, lr, #32
+// DSO-NEXT:     1023c:       a4 f0 be e5     ldr     pc, [lr, #164]!
 // DSO: <$d>:
 
-// DSO-NEXT:     1240:       d4 d4 d4 d4     .word   0xd4d4d4d4
-// DSO-NEXT:     1244:       d4 d4 d4 d4     .word   0xd4d4d4d4
-// DSO-NEXT:     1248:       d4 d4 d4 d4     .word   0xd4d4d4d4
-// DSO-NEXT:     124c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     10240:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     10244:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     10248:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     1024c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 // DSO: <$a>:
-// (0x1250 + 8) + (0 RoR 12) + 8192 + 140 = 0x32e4
-// DSO-NEXT:     1250:       00 c6 8f e2     add     r12, pc, #0, #12
-// DSO-NEXT:     1254:       02 ca 8c e2     add     r12, r12, #8192
-// DSO-NEXT:     1258:       8c f0 bc e5     ldr     pc, [r12, #140]!
+// (0x10250 + 8) + (0 RoR 12) + 8192 + 140 = 0x32e4
+// DSO-NEXT:     10250:       00 c6 8f e2     add     r12, pc, #0, #12
+// DSO-NEXT:     10254:       20 ca 8c e2     add     r12, r12, #32
+// DSO-NEXT:     10258:       8c f0 bc e5     ldr     pc, [r12, #140]!
 // DSO: <$d>:
-// DSO-NEXT:     125c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     1025c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 // DSO: <$a>:
-// (0x1260 + 8) + (0 RoR 12) + 8192 + 128 = 0x32e8
-// DSO-NEXT:     1260:       00 c6 8f e2     add     r12, pc, #0, #12
-// DSO-NEXT:     1264:       02 ca 8c e2     add     r12, r12, #8192
-// DSO-NEXT:     1268:       80 f0 bc e5     ldr     pc, [r12, #128]!
+// (0x10260 + 8) + (0 RoR 12) + 8192 + 128 = 0x32e8
+// DSO-NEXT:     10260:       00 c6 8f e2     add     r12, pc, #0, #12
+// DSO-NEXT:     10264:       20 ca 8c e2     add     r12, r12, #32
+// DSO-NEXT:     10268:       80 f0 bc e5     ldr     pc, [r12, #128]!
 // DSO: <$d>:
-// DSO-NEXT:     126c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     1026c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 // DSO: <$a>:
-// (0x1270 + 8) + (0 RoR 12) + 8192 + 116 = 0x32ec
-// DSO-NEXT:     1270:       00 c6 8f e2     add     r12, pc, #0, #12
-// DSO-NEXT:     1274:       02 ca 8c e2     add     r12, r12, #8192
-// DSO-NEXT:     1278:       74 f0 bc e5     ldr     pc, [r12, #116]!
+// (0x10270 + 8) + (0 RoR 12) + 8192 + 116 = 0x32ec
+// DSO-NEXT:     10270:       00 c6 8f e2     add     r12, pc, #0, #12
+// DSO-NEXT:     10274:       20 ca 8c e2     add     r12, r12, #32
+// DSO-NEXT:     10278:       74 f0 bc e5     ldr     pc, [r12, #116]!
 // DSO: <$d>:
-// DSO-NEXT:     127c:       d4 d4 d4 d4     .word   0xd4d4d4d4
+// DSO-NEXT:     1027c:       d4 d4 d4 d4     .word   0xd4d4d4d4
 
 // DSOREL:    Name: .got.plt
 // DSOREL-NEXT:    Type: SHT_PROGBITS
 // DSOREL-NEXT:    Flags [
 // DSOREL-NEXT:      SHF_ALLOC
 // DSOREL-NEXT:      SHF_WRITE
 // DSOREL-NEXT:    ]
-// DSOREL-NEXT:    Address: 0x32D8
+// DSOREL-NEXT:    Address: 0x302D8
 // DSOREL-NEXT:    Offset:
 // DSOREL-NEXT:    Size: 24
 // DSOREL-NEXT:    Link:
 // DSOREL-NEXT:    Info:
 // DSOREL-NEXT:    AddressAlignment: 4
 // DSOREL-NEXT:    EntrySize:
 // DSOREL:  Relocations [
 // DSOREL-NEXT:  Section (5) .rel.plt {
-// DSOREL-NEXT:    0x32E4 R_ARM_JUMP_SLOT func1 0x0
-// DSOREL-NEXT:    0x32E8 R_ARM_JUMP_SLOT func2 0x0
-// DSOREL-NEXT:    0x32EC R_ARM_JUMP_SLOT func3 0x0
+// DSOREL-NEXT:    0x302E4 R_ARM_JUMP_SLOT func1 0x0
+// DSOREL-NEXT:    0x302E8 R_ARM_JUMP_SLOT func2 0x0
+// DSOREL-NEXT:    0x302EC R_ARM_JUMP_SLOT func3 0x0

lld/test/ELF/arm-thumb-thunk-empty-pass.s

  .section .text.foo,"ax",%progbits
   .type foo, %function
 foo:
  bl _start
 
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
 // CHECK-NEXT: <_start>:
-// CHECK-NEXT:    110b4:       ff f7 fe ff     bl      #-4
+// CHECK-NEXT:    200b4:       ff f7 fe ff     bl      #-4
 // CHECK: <__Thumbv7ABSLongThunk__start>:
-// CHECK-NEXT:    110b8:       ff f7 fc bf     b.w     #-8 <_start>
+// CHECK-NEXT:    200b8:       ff f7 fc bf     b.w     #-8 <_start>
 
 // CHECK: <__Thumbv7ABSLongThunk__start>:
-// CHECK:       10110bc:       41 f2 b5 0c     movw    r12, #4277
-// CHECK-NEXT:  10110c0:       c0 f2 01 0c     movt    r12, #1
-// CHECK-NEXT:  10110c4:       60 47   bx      r12
+// CHECK:       10200bc:       40 f2 b5 0c     movw    r12, #181
+// CHECK-NEXT:  10200c0:       c0 f2 02 0c     movt    r12, #2
+// CHECK-NEXT:  10200c4:       60 47   bx      r12
 // CHECK: <foo>:
-// CHECK-NEXT:  10110c6:       ff f7 f9 ff     bl      #-14
+// CHECK-NEXT:  10200c6:       ff f7 f9 ff     bl      #-14

lld/test/ELF/arm-thumb-thunk-symbols.s

  .arm
  .balign 0x1000
  .globl arm_fn
  .type arm_fn, %function
 arm_fn:
  b thumb_fn
 
 // CHECK:     Name: __Thumbv7ABSLongThunk_arm_fn
-// CHECK-NEXT:     Value: 0x13005
+// CHECK-NEXT:     Value: 0x22005
 // CHECK-NEXT:     Size: 10
 // CHECK-NEXT:    Binding: Local (0x0)
 // CHECK-NEXT:    Type: Function (0x2)
 // CHECK:     Name: __ARMv7ABSLongThunk_thumb_fn
-// CHECK-NEXT:     Value: 0x13010
+// CHECK-NEXT:     Value: 0x22010
 // CHECK-NEXT:     Size: 12
 // CHECK-NEXT:    Binding: Local (0x0)
 // CHECK-NEXT:    Type: Function (0x2)
 
 // CHECK-PI:     Name: __ThumbV7PILongThunk_arm_fn
-// CHECK-PI-NEXT:     Value: 0x3005
+// CHECK-PI-NEXT:     Value: 0x12005
 // CHECK-PI-NEXT:     Size: 12
 // CHECK-PI-NEXT:    Binding: Local (0x0)
 // CHECK-PI-NEXT:    Type: Function (0x2)

lld/test/ELF/arm-undefined-weak.s

  movt r0, :upper16:target - .
 // R_ARM_MOVW_PREL_NC
  movw r0, :lower16:target - .
 // R_ARM_REL32
  .word target - .
 
 // CHECK: Disassembly of section .text:
 // CHECK-EMPTY:
-// CHECK-NEXT: 100010b4 <_start>:
-// CHECK-NEXT: 100010b4: b       #-4
-// CHECK-NEXT: 100010b8: bl      #-4
-// CHECK-NEXT: 100010bc: bl      #-4
-// CHECK-NEXT: 100010c0: movt    r0, #0
-// CHECK-NEXT: 100010c4: movw    r0, #0
-// CHECK:      100010c8: 00 00 00 00     .word   0x00000000
+// CHECK-NEXT: 100100b4 <_start>:
+// CHECK-NEXT: 100100b4: b       #-4
+// CHECK-NEXT: 100100b8: bl      #-4
+// CHECK-NEXT: 100100bc: bl      #-4
+// CHECK-NEXT: 100100c0: movt    r0, #0
+// CHECK-NEXT: 100100c4: movw    r0, #0
+// CHECK:      100100c8: 00 00 00 00     .word   0x00000000