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[AMDGPU] Implement CFI for CSR spills
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Authored by scott.linder on Mar 26 2020, 12:22 PM.



Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.

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scott.linder created this revision.Mar 26 2020, 12:22 PM

git clang-format

Re-add a test that got lost in a rebase somewhere

Rebase and update get{S,V}GPRSpillSaveOpcode (SIInstrInfo.cpp) as

Rebase onto LLVM master

I don't really have the expertise to approve this. The patch looks fine from a readability standpoint.


Does this comment need to be moved?

Rebase onto LLVM master and address feedback

Rebase onto LLVM trunk.