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[AMDGPU] Implement CFI for CSR spills
Needs RevisionPublic

Authored by scott.linder on Mar 26 2020, 12:22 PM.

Details

Summary

Introduce new SPILL pseudos to allow CFI to be generated for only CSR
spills, and to make ISA-instruction-level accurate information.

Other targets either generate slightly incorrect information or rely on
conventions for how spills are placed within the entry block. The
approach in this change produces larger unwind tables, with the
increased size being spent on additional DW_CFA_advance_location
instructions needed to describe the unwinding accurately.

Diff Detail

Unit TestsFailed

Event Timeline

scott.linder created this revision.Mar 26 2020, 12:22 PM

git clang-format

Re-add a test that got lost in a rebase somewhere

Rebase and update get{S,V}GPRSpillSaveOpcode (SIInstrInfo.cpp) as
per https://reviews.llvm.org/rG46579471fd2b9c00ba982325f53f30192cc5797f

Rebase onto LLVM master

I don't really have the expertise to approve this. The patch looks fine from a readability standpoint.

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
1379–1404

Does this comment need to be moved?

Rebase onto LLVM master and address feedback

Rebase onto LLVM trunk.

Rebase onto LLVM top of the tree.

Herald added a project: Restricted Project. · View Herald TranscriptAug 23 2022, 2:52 AM

Incorporated all the downstream changes.

arsenm added inline comments.Sep 16 2022, 9:12 AM
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
226

Should avoid using getMinimalPhysRegClass, should just hardcode a 64-bit scalar class

cdevadas added inline comments.
llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
1440

When do we have this case?
Can you point me to a test if it already exists?

arsenm requested changes to this revision.Aug 17 2023, 3:51 PM

Needs rebase

This revision now requires changes to proceed.Aug 17 2023, 3:51 PM