[AMDGPU] Emit entry function CFI

[scott.linder]

Summary

Entry functions represent the end of unwinding, as they are the
outer-most frame. This implies they can only have a meaningful
definition for the CFA, which AMDGPU defines using a memory location
description with a literal private address space address. The return
address is set to undefined as a sentinel value to signal the end of
unwinding.

[scott.linder]

git clang-format

[arsenm]

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

435

Why two levels of casting in all of these places? I also really don't like the constructor form of casts

1307–1318

I don't think this function buys you much since all of these thing are already in scope at the use.

llvm/lib/Target/AMDGPU/SIFrameLowering.h

76

Star with lowercase

[scott.linder]

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

435

Sorry, this is me copy-pasting from the only other use of createEscape in the code base and not thinking about it more. I'll clean all these up.

1307–1318

It is more just to cut down on the noise from having to get a CFI index and mark the instruction as FrameSetup. I'm OK inlining it everywhere, but things go from:

BuildCFI(MBB, I, DL,
           MCCFIInstruction::createUndefined(
               nullptr, MCRI->getDwarfRegNum(AMDGPU::PC_REG, false)));

to

BuildCFI(MBB, I, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
       .addCFIIndex(MF.addFrameInst(MCCFIInstruction::createUndefined(
           nullptr, MCRI->getDwarfRegNum(AMDGPU::PC_REG, false))))
       .setMIFlag(MachineInstr::FrameSetup);

llvm/lib/Target/AMDGPU/SIFrameLowering.h

76

I was trying to mimic BuildMI, which still has the wrong casing, but I'll update all of these.

[scott.linder]

Rebase and address feedback.

[scott.linder]

Rebase

[RamNalamothu]

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

1313

Missing MIR test checking relevant CFI_INSTRUCTIONs ?

[RamNalamothu]

Rebase and add an MIR test

[RamNalamothu]

Rebase

[RamNalamothu]

Rebase onto LLVM master

[cameron.mcinally]

LGTM with moderate confidence. Does anyone see a reason that this shouldn't land?

[greened]

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

1307

Needs a commnent explaining what this does.

[RamNalamothu]

Rebase onto LLVM master and address feedback

[RamNalamothu]

Rebase onto LLVM trunk.

[RamNalamothu]

Rebase onto LLVM top of the tree.

[RamNalamothu]

Incorporated all the downstream changes.

[arsenm]

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

1314

Should just pass in TII

[scott.linder]

Abandoned in favor of D147279 which avoids using most/all of the remaining user opcode

llvm/lib/Target/AMDGPU/SIFrameLowering.h

private:
   void emitEntryFunctionScratchRsrcRegSetup(
       MachineFunction &MF, MachineBasicBlock &MBB,
       MachineBasicBlock::iterator I, const DebugLoc &DL,
       Register PreloadedPrivateBufferReg, Register ScratchRsrcReg,
       Register ScratchWaveOffsetReg) const;
 
 public:
   bool hasFP(const MachineFunction &MF) const override;
+
+  /// Create a CFI index for CFIInst and build a MachineInstr around it.
+  void buildCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+                const DebugLoc &DL, const MCCFIInstruction &CFIInst) const;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H

llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

 #include "SIMachineFunctionInfo.h"
 #include "SIRegisterInfo.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 
 #include "llvm/CodeGen/LivePhysRegs.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/MC/MCDwarf.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "frame-info"
 
 
 // Find a scratch register that we can use at the start of the prologue to
 // re-align the stack pointer. We avoid using callee-save registers since they
void SIFrameLowering::emitEntryFunctionPrologue(MachineFunction &MF,
   // FIXME: Remove all of the isPhysRegUsed checks
 
   SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
   const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
   const SIInstrInfo *TII = ST.getInstrInfo();
   const SIRegisterInfo *TRI = &TII->getRegisterInfo();
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const Function &F = MF.getFunction();
+  const MCRegisterInfo *MCRI = MF.getMMI().getContext().getRegisterInfo();
 
   assert(MFI->isEntryFunction());
 
   Register PreloadedScratchWaveOffsetReg = MFI->getPreloadedReg(
       AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
   // FIXME: Hack to not crash in situations which emitted an error.
   if (!PreloadedScratchWaveOffsetReg)
     return;
if (ST.isAmdHsaOrMesa(F)) {
     }
   }
 
   // Debug location must be unknown since the first debug location is used to
   // determine the end of the prologue.
   DebugLoc DL;
   MachineBasicBlock::iterator I = MBB.begin();
 
+  // On entry the SP/FP are not set up, so we need to define the CFA in terms
+  // of a literal location expression.
+  static const char CFAEncodedInst[] = {
+      dwarf::DW_CFA_def_cfa_expression,
+      3, // length
+      static_cast<char>(dwarf::DW_OP_lit0),
+      static_cast<char>(
+          dwarf::DW_OP_lit6), // DW_ASPACE_AMDGPU_private_wave FIXME:
+                              // should be defined elsewhere
+      static_cast<char>(dwarf::DW_OP_LLVM_form_aspace_address)};
+  buildCFI(MBB, I, DL,
+           MCCFIInstruction::createEscape(
+               nullptr, StringRef(CFAEncodedInst, sizeof(CFAEncodedInst))));
+  // Unwinding halts when the return address (PC) is undefined.
+  buildCFI(MBB, I, DL,
+           MCCFIInstruction::createUndefined(
+               nullptr, MCRI->getDwarfRegNum(AMDGPU::PC_REG, false)));
+
   // We found the SRSRC first because it needs four registers and has an
   // alignment requirement. If the SRSRC that we found is clobbering with
   // the scratch wave offset, which may be in a fixed SGPR or a free SGPR
   // chosen by SITargetLowering::allocateSystemSGPRs, COPY the scratch
   // wave offset to a free SGPR.
   Register ScratchWaveOffsetReg;
   if (TRI->isSubRegisterEq(ScratchRsrcReg, PreloadedScratchWaveOffsetReg)) {
     ArrayRef<MCPhysReg> AllSGPRs = TRI->getAllSGPR32(MF);
if (MFI.hasCalls() &&
     return MFI.getStackSize() != 0;
   }
 
   return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() ||
     MFI.hasStackMap() || MFI.hasPatchPoint() ||
     MF.getSubtarget<GCNSubtarget>().getRegisterInfo()->needsStackRealignment(MF) ||
     MF.getTarget().Options.DisableFramePointerElim(MF);
 }
+
+void SIFrameLowering::buildCFI(MachineBasicBlock &MBB,
+                               MachineBasicBlock::iterator MBBI,
+                               const DebugLoc &DL,
+                               const MCCFIInstruction &CFIInst) const {
+  MachineFunction &MF = *MBB.getParent();
+  const SIInstrInfo *TII = MF.getSubtarget<GCNSubtarget>().getInstrInfo();
+  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+      .addCFIIndex(MF.addFrameInst(CFIInst))
+      .setMIFlag(MachineInstr::FrameSetup);
+}

llvm/test/CodeGen/AMDGPU/debug-frame.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=asm -o - %s | FileCheck %s
+
+; CHECK-LABEL: kern1:
+; CHECK: .cfi_startproc
+
+; CHECK-NOT: .cfi_{{.*}}
+
+; CHECK: %bb.0:
+; DW_CFA_def_cfa_expression [0x0f]
+;   BLOCK_LENGTH ULEB128(3)=[0x03]
+;     DW_OP_lit0 [0x30]
+;     DW_OP_lit6 [0x36]
+;     DW_OP_LLVM_form_aspace_address [0xe1]
+; CHECK-NEXT: .cfi_escape 0x0f, 0x03, 0x30, 0x36, 0xe1
+; PC_64 = 16
+; CHECK-NEXT: .cfi_undefined 16
+
+; CHECK-NOT: .cfi_{{.*}}
+
+; CHECK: .cfi_endproc
+define protected amdgpu_kernel void @kern1() #0 {
+entry:
+  ret void
+}
+
+attributes #0 = { nounwind }
+
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2, !3}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, emissionKind: FullDebug)
+!1 = !DIFile(filename: "filename", directory: "directory")
+!2 = !{i32 7, !"Dwarf Version", i32 4}
+!3 = !{i32 2, !"Debug Info Version", i32 3}

llvm/test/CodeGen/AMDGPU/entry-function-cfi.mir

+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=prologepilog -o - %s | FileCheck %s
+
+--- |
+
+  define protected amdgpu_kernel void @kern1() {
+  entry:
+    ret void
+  }
+...
+---
+name:            kern1
+alignment:       1
+tracksRegLiveness: true
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo:
+  maxKernArgAlign: 1
+  isEntryFunction: true
+  scratchRSrcReg:  '$sgpr100_sgpr101_sgpr102_sgpr103'
+  stackPtrOffsetReg: '$sgpr32'
+  argumentInfo:
+    workGroupIDX:    { reg: '$sgpr0' }
+    privateSegmentWaveByteOffset: { reg: '$sgpr1' }
+    workItemIDX:     { reg: '$vgpr0' }
+body:             |
+  bb.0:
+    ; CHECK: frame-setup CFI_INSTRUCTION escape 0x0f, 0x03, 0x30, 0x36, 0xe1
+    ; CHECK: frame-setup CFI_INSTRUCTION undefined $pc_reg
+    S_ENDPGM 0
+
+...

llvm/test/CodeGen/AMDGPU/llvm.dbg.value.ll

entry:
   ret void
 }
 
 ; Check for infinite loop in some cases with dbg_value in
 ; SIOptimizeExecMaskingPreRA (somehow related to undef argument).
 
 ; GCN-LABEL: {{^}}only_undef_dbg_value:
 ; NOOPT: ;DEBUG_VALUE: test_debug_value:globalptr_arg <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef] undef
+; NOOPT-NEXT: .cfi_escape 0x0f, 0x03, 0x30, 0x36, 0xe1
+; NOOPT-NEXT: .cfi_undefined 16
 ; NOOPT-NEXT: s_endpgm
 
 ; OPT: s_endpgm
 define amdgpu_kernel void @only_undef_dbg_value() #1 {
 bb:
   call void @llvm.dbg.value(metadata <4 x float> undef, metadata !10, metadata !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)) #2, !dbg !14
   ret void
 }