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Differential D72341

[FPEnv] Fix chain handling for fpexcept.strict nodes
ClosedPublic

Authored by uweigand on Jan 7 2020, 8:54 AM.

Details

Reviewers
craig.topper
cameron.mcinally
andrew.w.kaylor
kpn
arsenm
Commits
rG04a86966fbf4: [FPEnv] Fix chain handling for fpexcept.strict nodes
Summary

As pointed out in D70913, it turns out we need to ensure that fpexcept.strict nodes are not optimized away even if the result is unused. To do that, we need to chain them into the block's terminator nodes, like already done for PendingExcepts.

This patch adds two new lists of pending chains, PendingConstrainedFP and PendingConstrainedFPStrict to hold constrained FP intrinsic nodes without and with fpexcept.strict markers. This allows not only to solve the above problem, but also to relax chains a bit further by no longer flushing all FP nodes before a store or other memory access. (They are still flushed before nodes with other side effects.)

Note that this patch currently introduces test case failures:

LLVM :: CodeGen/X86/vec-strict-cmp-128.ll
LLVM :: CodeGen/X86/vec-strict-cmp-256.ll
LLVM :: CodeGen/X86/vec-strict-cmp-512.ll
LLVM :: CodeGen/X86/vec-strict-fptoint-128.ll
LLVM :: CodeGen/X86/vec-strict-fptoint-256.ll
LLVM :: CodeGen/X86/vec-strict-fptoint-512.ll

These appear to be caused by problems handling the outgoing chains of some strictfp nodes in the X86 back-end; these problems were unnoticed before this patch because the outgoing chains were simply unused with those simple tests otherwise.

It may be that this is actually the same problem to be addressed by D72224; @craig.topper , maybe you can have a look?

Diff Detail

Event Timeline

uweigand created this revision.Jan 7 2020, 8:54 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 7 2020, 8:54 AM
Herald added subscribers: llvm-commits, jsji, kbarton and 3 others. · View Herald Transcript
uweigand mentioned this in D70913: [FPEnv][SelectionDAG] Relax chain requirements.Jan 7 2020, 8:56 AM
craig.topper added inline comments.Jan 7 2020, 12:13 PM
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
1083

Can we just use PendingExports.append here? I think it will take care of the reserve. I think even insert will probably take care of the reserve. Might make sense for the code in getRoot() too unless you're concerned about 2 reserves in 2 separate append calls.

Herald added a subscriber: • wuzish. · View Herald TranscriptJan 7 2020, 12:13 PM
craig.topper added a comment.Jan 7 2020, 12:26 PM

Looks like D72224 fixes those failures and removes at least one of the diffs in this patch.

llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
7472

This diff is recovered with D72224

uweigand updated this revision to Diff 236804.Jan 8 2020, 6:02 AM

Use SmallVector::append instead of ::insert.

uweigand marked an inline comment as done.Jan 8 2020, 6:03 AM
In D72341#1808609, @craig.topper wrote:

Looks like D72224 fixes those failures and removes at least one of the diffs in this patch.

Ah, good -- thanks for testing!

Maybe the best would then be to wait for D72224 to be committed first.

pengfei added a subscriber: pengfei.Jan 8 2020, 5:13 PM
uweigand updated this revision to Diff 237400.Jan 10 2020, 11:31 AM
uweigand retitled this revision from [FPEnv][WIP] Fix chain handling for fpexcept.strict nodes to [FPEnv] Fix chain handling for fpexcept.strict nodes.

Updated patch now that D72224 has landed. At this point, there are no test suite failures remaining.

craig.topper added inline comments.Jan 11 2020, 5:53 PM
llvm/test/CodeGen/X86/fp128-libcalls-strict.ll
1131

This looks like a bug of some sort. I'll see if I can track it down.

craig.topper added inline comments.Jan 11 2020, 5:54 PM
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
7025

This is throwing a warning that the default is redundant in a fully covered switch.

craig.topper mentioned this in rGd692f0f6c8c1: [X86] Don't call LowerSETCC from LowerSELECT for STRICT_FSETCC/STRICT_FSETCCS….Jan 11 2020, 8:50 PM
craig.topper added inline comments.Jan 11 2020, 8:51 PM
llvm/test/CodeGen/X86/fp128-libcalls-strict.ll
1131

I think I've fixed this or at least hacked around it for now. Can you rebase this?

uweigand updated this revision to Diff 237540.Jan 12 2020, 8:57 AM

Address review comments and rebase.

uweigand marked 2 inline comments as done.Jan 12 2020, 9:00 AM

Looks like the remaining test case changes are strictly due to scheduling.

craig.topper accepted this revision.Jan 12 2020, 12:29 PM

LGTM

This revision is now accepted and ready to land.Jan 12 2020, 12:29 PM
Closed by commit rG04a86966fbf4: [FPEnv] Fix chain handling for fpexcept.strict nodes (authored by uweigand). · Explain WhyJan 13 2020, 5:39 AM
This revision was automatically updated to reflect the committed changes.
uweigand added a comment.Jan 14 2020, 5:13 AM

It turns out this patch introduced a regression with chain handling in code mixing constrained intrinsics and memory operations.

This is now fixed here in commit 81ee484: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20200113/729980.html

Using that commit, I'm now able to build and run all of test-suite on SystemZ with the -ftrapping-math flag.

Revision Contents

Diff 236606

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h

Show First 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
private: private:
/// CopyToReg nodes that copy values to virtual registers for export to other /// CopyToReg nodes that copy values to virtual registers for export to other
/// blocks need to be emitted before any terminator instruction, but they have /// blocks need to be emitted before any terminator instruction, but they have
/// no other ordering requirements. We bunch them up and the emit a single /// no other ordering requirements. We bunch them up and the emit a single
/// tokenfactor for them just before terminator instructions. /// tokenfactor for them just before terminator instructions.
SmallVector<SDValue, 8> PendingExports; SmallVector<SDValue, 8> PendingExports;
/// Similar to loads, nodes corresponding to constrained FP intrinsics are
/// bunched up and emitted when necessary. These can be moved across each
/// other and any (normal) memory operation (load or store), but not across
/// calls or instructions having unspecified side effects. As a special
/// case, constrained FP intrinsics using fpexcept.strict may not be deleted
/// even if otherwise unused, so they need to be chained before any
/// terminator instruction (like PendingExports). We track the latter
/// set of nodes in a separate list.
SmallVector<SDValue, 8> PendingConstrainedFP;
SmallVector<SDValue, 8> PendingConstrainedFPStrict;
/// A unique monotonically increasing number used to order the SDNodes we /// A unique monotonically increasing number used to order the SDNodes we
/// create. /// create.
unsigned SDNodeOrder; unsigned SDNodeOrder;
/// Determine the rank by weight of CC in [First,Last]. If CC has more weight /// Determine the rank by weight of CC in [First,Last]. If CC has more weight
/// than each cluster in the range, its rank is 0. /// than each cluster in the range, its rank is 0.
unsigned caseClusterRank(const SwitchCG::CaseCluster &CC, unsigned caseClusterRank(const SwitchCG::CaseCluster &CC,
SwitchCG::CaseClusterIt First, SwitchCG::CaseClusterIt First,
▲ Show 20 Lines • Show All 288 Lines • ▼ Show 20 Linespublic:
/// Clear the dangling debug information map. This function is separated from /// Clear the dangling debug information map. This function is separated from
/// the clear so that debug information that is dangling in a basic block can /// the clear so that debug information that is dangling in a basic block can
/// be properly resolved in a different basic block. This allows the /// be properly resolved in a different basic block. This allows the
/// SelectionDAG to resolve dangling debug information attached to PHI nodes. /// SelectionDAG to resolve dangling debug information attached to PHI nodes.
void clearDanglingDebugInfo(); void clearDanglingDebugInfo();
/// Return the current virtual root of the Selection DAG, flushing any /// Return the current virtual root of the Selection DAG, flushing any
/// PendingLoad items. This must be done before emitting a store or any other /// PendingLoad items. This must be done before emitting a store or any other
/// node that may need to be ordered after any prior load instructions. /// memory node that may need to be ordered after any prior load instructions.
SDValue getMemoryRoot();
/// Similar to getMemoryRoot, but also flushes PendingConstrainedFP(Strict)
/// items. This must be done before emitting any call other any other node
/// that may need to be ordered after FP instructions due to other side
/// effects.
SDValue getRoot(); SDValue getRoot();
/// Similar to getRoot, but instead of flushing all the PendingLoad items, /// Similar to getRoot, but instead of flushing all the PendingLoad items,
/// flush all the PendingExports items. It is necessary to do this before /// flush all the PendingExports (and PendingConstrainedFPStrict) items.
/// emitting a terminator instruction. /// It is necessary to do this before emitting a terminator instruction.
SDValue getControlRoot(); SDValue getControlRoot();
SDLoc getCurSDLoc() const { SDLoc getCurSDLoc() const {
return SDLoc(CurInst, SDNodeOrder); return SDLoc(CurInst, SDNodeOrder);
} }
DebugLoc getCurDebugLoc() const { DebugLoc getCurDebugLoc() const {
return CurInst ? CurInst->getDebugLoc() : DebugLoc(); return CurInst ? CurInst->getDebugLoc() : DebugLoc();
▲ Show 20 Lines • Show All 430 Lines • Show Last 20 Lines

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,019 Lines • ▼ Show 20 Linesvoid SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis *aa,
SL->init(DAG.getTargetLoweringInfo(), TM, DAG.getDataLayout()); SL->init(DAG.getTargetLoweringInfo(), TM, DAG.getDataLayout());
} }
void SelectionDAGBuilder::clear() { void SelectionDAGBuilder::clear() {
NodeMap.clear(); NodeMap.clear();
UnusedArgNodeMap.clear(); UnusedArgNodeMap.clear();
PendingLoads.clear(); PendingLoads.clear();
PendingExports.clear(); PendingExports.clear();
PendingConstrainedFP.clear();
PendingConstrainedFPStrict.clear();
CurInst = nullptr; CurInst = nullptr;
HasTailCall = false; HasTailCall = false;
SDNodeOrder = LowestSDNodeOrder; SDNodeOrder = LowestSDNodeOrder;
StatepointLowering.clear(); StatepointLowering.clear();
} }
void SelectionDAGBuilder::clearDanglingDebugInfo() { void SelectionDAGBuilder::clearDanglingDebugInfo() {
DanglingDebugInfoMap.clear(); DanglingDebugInfoMap.clear();
} }
SDValue SelectionDAGBuilder::getRoot() { SDValue SelectionDAGBuilder::getMemoryRoot() {
if (PendingLoads.empty()) if (PendingLoads.empty())
return DAG.getRoot(); return DAG.getRoot();
if (PendingLoads.size() == 1) { if (PendingLoads.size() == 1) {
SDValue Root = PendingLoads[0]; SDValue Root = PendingLoads[0];
DAG.setRoot(Root); DAG.setRoot(Root);
PendingLoads.clear(); PendingLoads.clear();
return Root; return Root;
} }
// Otherwise, we have to make a token factor node. // Otherwise, we have to make a token factor node.
SDValue Root = DAG.getTokenFactor(getCurSDLoc(), PendingLoads); SDValue Root = DAG.getTokenFactor(getCurSDLoc(), PendingLoads);
PendingLoads.clear(); PendingLoads.clear();
DAG.setRoot(Root); DAG.setRoot(Root);
return Root; return Root;
} }
SDValue SelectionDAGBuilder::getRoot() {
// Chain up all pending constrained intrinsics together with all
// pending loads, by simply appending them to PendingLoads and
// then calling getMemoryRoot().
PendingLoads.reserve(PendingLoads.size() +
PendingConstrainedFP.size() +
PendingConstrainedFPStrict.size());
PendingLoads.insert(PendingLoads.end(),
PendingConstrainedFP.begin(),
PendingConstrainedFP.end());
PendingLoads.insert(PendingLoads.end(),
PendingConstrainedFPStrict.begin(),
PendingConstrainedFPStrict.end());
PendingConstrainedFP.clear();
PendingConstrainedFPStrict.clear();
return getMemoryRoot();
}
SDValue SelectionDAGBuilder::getControlRoot() { SDValue SelectionDAGBuilder::getControlRoot() {
SDValue Root = DAG.getRoot(); SDValue Root = DAG.getRoot();
// We need to emit pending fpexcept.strict constrained intrinsics,
// so append them to the PendingExports list.
PendingExports.reserve(PendingExports.size() +
PendingConstrainedFPStrict.size());
PendingExports.insert(PendingExports.end(),
craig.topperUnsubmitted
Done
ReplyInline Actions

Can we just use PendingExports.append here? I think it will take care of the reserve. I think even insert will probably take care of the reserve. Might make sense for the code in getRoot() too unless you're concerned about 2 reserves in 2 separate append calls.

craig.topper: Can we just use PendingExports.append here? I think it will take care of the reserve. I think…
PendingConstrainedFPStrict.begin(),
PendingConstrainedFPStrict.end());
PendingConstrainedFPStrict.clear();
if (PendingExports.empty()) if (PendingExports.empty())
return Root; return Root;
// Turn all of the CopyToReg chains into one factored node. // Turn all of the CopyToReg chains into one factored node.
if (Root.getOpcode() != ISD::EntryToken) { if (Root.getOpcode() != ISD::EntryToken) {
unsigned i = 0, e = PendingExports.size(); unsigned i = 0, e = PendingExports.size();
for (; i != e; ++i) { for (; i != e; ++i) {
assert(PendingExports[i].getNode()->getNumOperands() > 1); assert(PendingExports[i].getNode()->getNumOperands() > 1);
▲ Show 20 Lines • Show All 2,988 Lines • ▼ Show 20 Linesvoid SelectionDAGBuilder::visitLoad(const LoadInst &I) {
SmallVector<uint64_t, 4> Offsets; SmallVector<uint64_t, 4> Offsets;
ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &MemVTs, &Offsets); ComputeValueVTs(TLI, DAG.getDataLayout(), Ty, ValueVTs, &MemVTs, &Offsets);
unsigned NumValues = ValueVTs.size(); unsigned NumValues = ValueVTs.size();
if (NumValues == 0) if (NumValues == 0)
return; return;
SDValue Root; SDValue Root;
bool ConstantMemory = false; bool ConstantMemory = false;
if (isVolatile || NumValues > MaxParallelChains) if (isVolatile)
// Serialize volatile loads with other side effects. // Serialize volatile loads with other side effects.
Root = getRoot(); Root = getRoot();
else if (NumValues > MaxParallelChains)
Root = getMemoryRoot();
else if (AA && else if (AA &&
AA->pointsToConstantMemory(MemoryLocation( AA->pointsToConstantMemory(MemoryLocation(
SV, SV,
LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)), LocationSize::precise(DAG.getDataLayout().getTypeStoreSize(Ty)),
AAInfo))) { AAInfo))) {
// Do not serialize (non-volatile) loads of constant memory with anything. // Do not serialize (non-volatile) loads of constant memory with anything.
Root = DAG.getEntryNode(); Root = DAG.getEntryNode();
ConstantMemory = true; ConstantMemory = true;
▲ Show 20 Lines • Show All 158 Lines • ▼ Show 20 Lines if (NumValues == 0)
return; return;
// Get the lowered operands. Note that we do this after // Get the lowered operands. Note that we do this after
// checking if NumResults is zero, because with zero results // checking if NumResults is zero, because with zero results
// the operands won't have values in the map. // the operands won't have values in the map.
SDValue Src = getValue(SrcV); SDValue Src = getValue(SrcV);
SDValue Ptr = getValue(PtrV); SDValue Ptr = getValue(PtrV);
SDValue Root = getRoot(); SDValue Root = I.isVolatile() ? getRoot() : getMemoryRoot();
SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues)); SmallVector<SDValue, 4> Chains(std::min(MaxParallelChains, NumValues));
SDLoc dl = getCurSDLoc(); SDLoc dl = getCurSDLoc();
unsigned Alignment = I.getAlignment(); unsigned Alignment = I.getAlignment();
AAMDNodes AAInfo; AAMDNodes AAInfo;
I.getAAMetadata(AAInfo); I.getAAMetadata(AAInfo);
auto MMOFlags = MachineMemOperand::MONone; auto MMOFlags = MachineMemOperand::MONone;
if (I.isVolatile()) if (I.isVolatile())
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines MachineMemOperand *MMO =
DAG.getMachineFunction(). DAG.getMachineFunction().
getMachineMemOperand(MachinePointerInfo(PtrOperand), getMachineMemOperand(MachinePointerInfo(PtrOperand),
MachineMemOperand::MOStore, MachineMemOperand::MOStore,
// TODO: Make MachineMemOperands aware of scalable // TODO: Make MachineMemOperands aware of scalable
// vectors. // vectors.
VT.getStoreSize().getKnownMinSize(), VT.getStoreSize().getKnownMinSize(),
Alignment, AAInfo); Alignment, AAInfo);
SDValue StoreNode = SDValue StoreNode =
DAG.getMaskedStore(getRoot(), sdl, Src0, Ptr, Offset, Mask, VT, MMO, DAG.getMaskedStore(getMemoryRoot(), sdl, Src0, Ptr, Offset, Mask, VT, MMO,
ISD::UNINDEXED, false /* Truncating */, IsCompressing); ISD::UNINDEXED, false /* Truncating */, IsCompressing);
DAG.setRoot(StoreNode); DAG.setRoot(StoreNode);
setValue(&I, StoreNode); setValue(&I, StoreNode);
} }
// Get a uniform base for the Gather/Scatter intrinsic. // Get a uniform base for the Gather/Scatter intrinsic.
// The first argument of the Gather/Scatter intrinsic is a vector of pointers. // The first argument of the Gather/Scatter intrinsic is a vector of pointers.
// We try to represent it as a base pointer + vector of indices. // We try to represent it as a base pointer + vector of indices.
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines getMachineMemOperand(MachinePointerInfo(MemOpBasePtr),
VT.getStoreSize().getKnownMinSize(), VT.getStoreSize().getKnownMinSize(),
Alignment, AAInfo); Alignment, AAInfo);
if (!UniformBase) { if (!UniformBase) {
Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())); Base = DAG.getConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout()));
Index = getValue(Ptr); Index = getValue(Ptr);
IndexType = ISD::SIGNED_SCALED; IndexType = ISD::SIGNED_SCALED;
Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout())); Scale = DAG.getTargetConstant(1, sdl, TLI.getPointerTy(DAG.getDataLayout()));
} }
SDValue Ops[] = { getRoot(), Src0, Mask, Base, Index, Scale }; SDValue Ops[] = { getMemoryRoot(), Src0, Mask, Base, Index, Scale };
SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl, SDValue Scatter = DAG.getMaskedScatter(DAG.getVTList(MVT::Other), VT, sdl,
Ops, MMO, IndexType); Ops, MMO, IndexType);
DAG.setRoot(Scatter); DAG.setRoot(Scatter);
setValue(&I, Scatter); setValue(&I, Scatter);
} }
void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) { void SelectionDAGBuilder::visitMaskedLoad(const CallInst &I, bool IsExpanding) {
SDLoc sdl = getCurSDLoc(); SDLoc sdl = getCurSDLoc();
▲ Show 20 Lines • Show All 1,308 Lines • ▼ Show 20 Lines case Intrinsic::memcpy: {
// @llvm.memcpy defines 0 and 1 to both mean no alignment. // @llvm.memcpy defines 0 and 1 to both mean no alignment.
unsigned DstAlign = std::max<unsigned>(MCI.getDestAlignment(), 1); unsigned DstAlign = std::max<unsigned>(MCI.getDestAlignment(), 1);
unsigned SrcAlign = std::max<unsigned>(MCI.getSourceAlignment(), 1); unsigned SrcAlign = std::max<unsigned>(MCI.getSourceAlignment(), 1);
unsigned Align = MinAlign(DstAlign, SrcAlign); unsigned Align = MinAlign(DstAlign, SrcAlign);
bool isVol = MCI.isVolatile(); bool isVol = MCI.isVolatile();
bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
// FIXME: Support passing different dest/src alignments to the memcpy DAG // FIXME: Support passing different dest/src alignments to the memcpy DAG
// node. // node.
SDValue MC = DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, SDValue Root = isVol ? getRoot() : getMemoryRoot();
SDValue MC = DAG.getMemcpy(Root, sdl, Op1, Op2, Op3, Align, isVol,
false, isTC, false, isTC,
MachinePointerInfo(I.getArgOperand(0)), MachinePointerInfo(I.getArgOperand(0)),
MachinePointerInfo(I.getArgOperand(1))); MachinePointerInfo(I.getArgOperand(1)));
updateDAGForMaybeTailCall(MC); updateDAGForMaybeTailCall(MC);
return; return;
} }
case Intrinsic::memset: { case Intrinsic::memset: {
const auto &MSI = cast<MemSetInst>(I); const auto &MSI = cast<MemSetInst>(I);
SDValue Op1 = getValue(I.getArgOperand(0)); SDValue Op1 = getValue(I.getArgOperand(0));
SDValue Op2 = getValue(I.getArgOperand(1)); SDValue Op2 = getValue(I.getArgOperand(1));
SDValue Op3 = getValue(I.getArgOperand(2)); SDValue Op3 = getValue(I.getArgOperand(2));
// @llvm.memset defines 0 and 1 to both mean no alignment. // @llvm.memset defines 0 and 1 to both mean no alignment.
unsigned Align = std::max<unsigned>(MSI.getDestAlignment(), 1); unsigned Align = std::max<unsigned>(MSI.getDestAlignment(), 1);
bool isVol = MSI.isVolatile(); bool isVol = MSI.isVolatile();
bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
SDValue MS = DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, SDValue Root = isVol ? getRoot() : getMemoryRoot();
SDValue MS = DAG.getMemset(Root, sdl, Op1, Op2, Op3, Align, isVol,
isTC, MachinePointerInfo(I.getArgOperand(0))); isTC, MachinePointerInfo(I.getArgOperand(0)));
updateDAGForMaybeTailCall(MS); updateDAGForMaybeTailCall(MS);
return; return;
} }
case Intrinsic::memmove: { case Intrinsic::memmove: {
const auto &MMI = cast<MemMoveInst>(I); const auto &MMI = cast<MemMoveInst>(I);
SDValue Op1 = getValue(I.getArgOperand(0)); SDValue Op1 = getValue(I.getArgOperand(0));
SDValue Op2 = getValue(I.getArgOperand(1)); SDValue Op2 = getValue(I.getArgOperand(1));
SDValue Op3 = getValue(I.getArgOperand(2)); SDValue Op3 = getValue(I.getArgOperand(2));
// @llvm.memmove defines 0 and 1 to both mean no alignment. // @llvm.memmove defines 0 and 1 to both mean no alignment.
unsigned DstAlign = std::max<unsigned>(MMI.getDestAlignment(), 1); unsigned DstAlign = std::max<unsigned>(MMI.getDestAlignment(), 1);
unsigned SrcAlign = std::max<unsigned>(MMI.getSourceAlignment(), 1); unsigned SrcAlign = std::max<unsigned>(MMI.getSourceAlignment(), 1);
unsigned Align = MinAlign(DstAlign, SrcAlign); unsigned Align = MinAlign(DstAlign, SrcAlign);
bool isVol = MMI.isVolatile(); bool isVol = MMI.isVolatile();
bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget()); bool isTC = I.isTailCall() && isInTailCallPosition(&I, DAG.getTarget());
// FIXME: Support passing different dest/src alignments to the memmove DAG // FIXME: Support passing different dest/src alignments to the memmove DAG
// node. // node.
SDValue MM = DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, SDValue Root = isVol ? getRoot() : getMemoryRoot();
SDValue MM = DAG.getMemmove(Root, sdl, Op1, Op2, Op3, Align, isVol,
isTC, MachinePointerInfo(I.getArgOperand(0)), isTC, MachinePointerInfo(I.getArgOperand(0)),
MachinePointerInfo(I.getArgOperand(1))); MachinePointerInfo(I.getArgOperand(1)));
updateDAGForMaybeTailCall(MM); updateDAGForMaybeTailCall(MM);
return; return;
} }
case Intrinsic::memcpy_element_unordered_atomic: { case Intrinsic::memcpy_element_unordered_atomic: {
const AtomicMemCpyInst &MI = cast<AtomicMemCpyInst>(I); const AtomicMemCpyInst &MI = cast<AtomicMemCpyInst>(I);
SDValue Dst = getValue(MI.getRawDest()); SDValue Dst = getValue(MI.getRawDest());
▲ Show 20 Lines • Show All 1,143 Lines • ▼ Show 20 Lines case ISD::STRICT_FSETCCS: {
break; break;
} }
} }
SDVTList VTs = DAG.getVTList(ValueVTs); SDVTList VTs = DAG.getVTList(ValueVTs);
SDValue Result = DAG.getNode(Opcode, sdl, VTs, Opers); SDValue Result = DAG.getNode(Opcode, sdl, VTs, Opers);
assert(Result.getNode()->getNumValues() == 2); assert(Result.getNode()->getNumValues() == 2);
// See above -- chain is handled like for loads here.
// Push node to the appropriate list so that future instructions can be
// chained up correctly.
SDValue OutChain = Result.getValue(1); SDValue OutChain = Result.getValue(1);
PendingLoads.push_back(OutChain); switch (FPI.getExceptionBehavior().getValue()) {
default:
llvm_unreachable("Unknown exception behavior");
craig.topperUnsubmitted
Done
ReplyInline Actions

This is throwing a warning that the default is redundant in a fully covered switch.

craig.topper: This is throwing a warning that the default is redundant in a fully covered switch.
case fp::ExceptionBehavior::ebIgnore:
// The only reason why ebIgnore nodes still need to be chained is that
// they might depend on the current rounding mode, and therefore must
// not be moved across instruction that may change that mode.
LLVM_FALLTHROUGH;
case fp::ExceptionBehavior::ebMayTrap:
// These must not be moved across calls or instructions that may change
// floating-point exception masks.
PendingConstrainedFP.push_back(OutChain);
break;
case fp::ExceptionBehavior::ebStrict:
// These must not be moved across calls or instructions that may change
// floating-point exception masks or read floating-point exception flags.
// In addition, they cannot be optimized out even if unused.
PendingConstrainedFPStrict.push_back(OutChain);
break;
}
SDValue FPResult = Result.getValue(0); SDValue FPResult = Result.getValue(0);
setValue(&FPI, FPResult); setValue(&FPI, FPResult);
} }
std::pair<SDValue, SDValue> std::pair<SDValue, SDValue>
SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI, SelectionDAGBuilder::lowerInvokable(TargetLowering::CallLoweringInfo &CLI,
const BasicBlock *EHPadBB) { const BasicBlock *EHPadBB) {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
▲ Show 20 Lines • Show All 366 Lines • ▼ Show 20 Lines if (Align == 0) // Alignment of one or both could not be inferred.
Align = 1; // 0 and 1 both specify no alignment, but 0 is reserved. Align = 1; // 0 and 1 both specify no alignment, but 0 is reserved.
bool isVol = false; bool isVol = false;
SDLoc sdl = getCurSDLoc(); SDLoc sdl = getCurSDLoc();
// In the mempcpy context we need to pass in a false value for isTailCall // In the mempcpy context we need to pass in a false value for isTailCall
// because the return pointer needs to be adjusted by the size of // because the return pointer needs to be adjusted by the size of
// the copied memory. // the copied memory.
SDValue MC = DAG.getMemcpy(getRoot(), sdl, Dst, Src, Size, Align, isVol, SDValue Root = isVol ? getRoot() : getMemoryRoot();
SDValue MC = DAG.getMemcpy(Root, sdl, Dst, Src, Size, Align, isVol,
false, /*isTailCall=*/false, false, /*isTailCall=*/false,
MachinePointerInfo(I.getArgOperand(0)), MachinePointerInfo(I.getArgOperand(0)),
MachinePointerInfo(I.getArgOperand(1))); MachinePointerInfo(I.getArgOperand(1)));
assert(MC.getNode() != nullptr && assert(MC.getNode() != nullptr &&
"** memcpy should not be lowered as TailCall in mempcpy context **"); "** memcpy should not be lowered as TailCall in mempcpy context **");
DAG.setRoot(MC); DAG.setRoot(MC);
// Check if Size needs to be truncated or extended. // Check if Size needs to be truncated or extended.
▲ Show 20 Lines • Show All 3,180 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll

Show First 20 Lines • Show All 1,352 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: fmr 3, 31 ; PC64LE-NEXT: fmr 3, 31
; PC64LE-NEXT: stfdx 31, 0, 4 ; PC64LE-NEXT: stfdx 31, 0, 4
; PC64LE-NEXT: bl __gcc_qadd ; PC64LE-NEXT: bl __gcc_qadd
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: fmr 3, 1 ; PC64LE-NEXT: fmr 3, 1
; PC64LE-NEXT: fmr 4, 2 ; PC64LE-NEXT: fmr 4, 2
; PC64LE-NEXT: fmr 30, 1 ; PC64LE-NEXT: fmr 30, 1
; PC64LE-NEXT: fmr 29, 2 ; PC64LE-NEXT: fmr 29, 2
; PC64LE-NEXT: stfd 1, 16(30)
; PC64LE-NEXT: stfd 2, 24(30) ; PC64LE-NEXT: stfd 2, 24(30)
; PC64LE-NEXT: stfd 1, 16(30)
; PC64LE-NEXT: bl __gcc_qmul ; PC64LE-NEXT: bl __gcc_qmul
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: fmr 1, 31 ; PC64LE-NEXT: fmr 1, 31
; PC64LE-NEXT: xxlxor 2, 2, 2 ; PC64LE-NEXT: xxlxor 2, 2, 2
; PC64LE-NEXT: li 5, 2 ; PC64LE-NEXT: li 5, 2
; PC64LE-NEXT: stfd 30, 32(30)
; PC64LE-NEXT: stfd 29, 40(30) ; PC64LE-NEXT: stfd 29, 40(30)
; PC64LE-NEXT: stfd 30, 32(30)
; PC64LE-NEXT: bl __powitf2 ; PC64LE-NEXT: bl __powitf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: frsp 0, 1 ; PC64LE-NEXT: frsp 0, 1
; PC64LE-NEXT: stfsx 0, 0, 29 ; PC64LE-NEXT: stfsx 0, 0, 29
; PC64LE-NEXT: stfd 2, -8(30)
; PC64LE-NEXT: stfd 1, -16(30) ; PC64LE-NEXT: stfd 1, -16(30)
; PC64LE-NEXT: stfd 2, -8(30)
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE-NEXT: ld 30, -40(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE-NEXT: ld 29, -48(1) # 8-byte Folded Reload ; PC64LE-NEXT: ld 29, -48(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0 ; PC64LE-NEXT: mtlr 0
Show All 20 Lines
; PC64LE9-NEXT: mr 30, 4 ; PC64LE9-NEXT: mr 30, 4
; PC64LE9-NEXT: stfd 31, 0(4) ; PC64LE9-NEXT: stfd 31, 0(4)
; PC64LE9-NEXT: bl __gcc_qadd ; PC64LE9-NEXT: bl __gcc_qadd
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: fmr 3, 1 ; PC64LE9-NEXT: fmr 3, 1
; PC64LE9-NEXT: fmr 4, 2 ; PC64LE9-NEXT: fmr 4, 2
; PC64LE9-NEXT: fmr 30, 2 ; PC64LE9-NEXT: fmr 30, 2
; PC64LE9-NEXT: fmr 29, 1 ; PC64LE9-NEXT: fmr 29, 1
; PC64LE9-NEXT: stfd 1, 16(30)
; PC64LE9-NEXT: stfd 2, 24(30) ; PC64LE9-NEXT: stfd 2, 24(30)
; PC64LE9-NEXT: stfd 1, 16(30)
; PC64LE9-NEXT: bl __gcc_qmul ; PC64LE9-NEXT: bl __gcc_qmul
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: fmr 1, 31 ; PC64LE9-NEXT: fmr 1, 31
; PC64LE9-NEXT: xxlxor 2, 2, 2 ; PC64LE9-NEXT: xxlxor 2, 2, 2
; PC64LE9-NEXT: li 5, 2 ; PC64LE9-NEXT: li 5, 2
; PC64LE9-NEXT: stfd 29, 32(30)
; PC64LE9-NEXT: stfd 30, 40(30) ; PC64LE9-NEXT: stfd 30, 40(30)
; PC64LE9-NEXT: stfd 29, 32(30)
; PC64LE9-NEXT: bl __powitf2 ; PC64LE9-NEXT: bl __powitf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: frsp 0, 1 ; PC64LE9-NEXT: frsp 0, 1
; PC64LE9-NEXT: stfs 0, 0(29) ; PC64LE9-NEXT: stfs 0, 0(29)
; PC64LE9-NEXT: stfd 2, -8(30)
; PC64LE9-NEXT: stfd 1, -16(30) ; PC64LE9-NEXT: stfd 1, -16(30)
; PC64LE9-NEXT: stfd 2, -8(30)
; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: addi 1, 1, 80
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE9-NEXT: ld 30, -40(1) # 8-byte Folded Reload
; PC64LE9-NEXT: ld 29, -48(1) # 8-byte Folded Reload ; PC64LE9-NEXT: ld 29, -48(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0 ; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
Show All 23 Lines
; PC64-NEXT: fmr 4, 30 ; PC64-NEXT: fmr 4, 30
; PC64-NEXT: stfd 31, 0(4) ; PC64-NEXT: stfd 31, 0(4)
; PC64-NEXT: bl __gcc_qadd ; PC64-NEXT: bl __gcc_qadd
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: fmr 3, 1 ; PC64-NEXT: fmr 3, 1
; PC64-NEXT: fmr 4, 2 ; PC64-NEXT: fmr 4, 2
; PC64-NEXT: fmr 29, 1 ; PC64-NEXT: fmr 29, 1
; PC64-NEXT: fmr 28, 2 ; PC64-NEXT: fmr 28, 2
; PC64-NEXT: stfd 1, 16(30)
; PC64-NEXT: stfd 2, 24(30) ; PC64-NEXT: stfd 2, 24(30)
; PC64-NEXT: stfd 1, 16(30)
; PC64-NEXT: bl __gcc_qmul ; PC64-NEXT: bl __gcc_qmul
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: fmr 1, 31 ; PC64-NEXT: fmr 1, 31
; PC64-NEXT: fmr 2, 30 ; PC64-NEXT: fmr 2, 30
; PC64-NEXT: li 5, 2 ; PC64-NEXT: li 5, 2
; PC64-NEXT: stfd 29, 32(30)
; PC64-NEXT: stfd 28, 40(30) ; PC64-NEXT: stfd 28, 40(30)
; PC64-NEXT: stfd 29, 32(30)
; PC64-NEXT: bl __powitf2 ; PC64-NEXT: bl __powitf2
; PC64-NEXT: nop ; PC64-NEXT: nop
; PC64-NEXT: frsp 0, 1 ; PC64-NEXT: frsp 0, 1
; PC64-NEXT: stfs 0, 0(29) ; PC64-NEXT: stfs 0, 0(29)
; PC64-NEXT: lfd 31, 168(1) # 8-byte Folded Reload ; PC64-NEXT: lfd 31, 168(1) # 8-byte Folded Reload
; PC64-NEXT: lfd 30, 160(1) # 8-byte Folded Reload ; PC64-NEXT: lfd 30, 160(1) # 8-byte Folded Reload
; PC64-NEXT: lfd 29, 152(1) # 8-byte Folded Reload ; PC64-NEXT: lfd 29, 152(1) # 8-byte Folded Reload
; PC64-NEXT: lfd 28, 144(1) # 8-byte Folded Reload ; PC64-NEXT: lfd 28, 144(1) # 8-byte Folded Reload
; PC64-NEXT: ld 29, 120(1) # 8-byte Folded Reload ; PC64-NEXT: ld 29, 120(1) # 8-byte Folded Reload
; PC64-NEXT: stfd 2, -8(30)
; PC64-NEXT: stfd 1, -16(30) ; PC64-NEXT: stfd 1, -16(30)
; PC64-NEXT: stfd 2, -8(30)
; PC64-NEXT: ld 30, 128(1) # 8-byte Folded Reload ; PC64-NEXT: ld 30, 128(1) # 8-byte Folded Reload
; PC64-NEXT: addi 1, 1, 176 ; PC64-NEXT: addi 1, 1, 176
; PC64-NEXT: ld 0, 16(1) ; PC64-NEXT: ld 0, 16(1)
; PC64-NEXT: mtlr 0 ; PC64-NEXT: mtlr 0
; PC64-NEXT: blr ; PC64-NEXT: blr
%load = load float, float* %firstptr %load = load float, float* %firstptr
%first = call ppc_fp128 @llvm.experimental.constrained.fpext.f32.ppcf128( %first = call ppc_fp128 @llvm.experimental.constrained.fpext.f32.ppcf128(
float %load, float %load,
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llvm/test/CodeGen/SystemZ/fp-strict-alias.ll

Show First 20 Lines • Show All 281 Lines • ▼ Show 20 Lines; CHECK: br %r14
call void @llvm.s390.sfpc(i32 0) #0 call void @llvm.s390.sfpc(i32 0) #0
store float %sqrt1, float *%ptr1 store float %sqrt1, float *%ptr1
store float %sqrt2, float *%ptr2 store float %sqrt2, float *%ptr2
ret void ret void
} }
; If the result of any FP operation is unused, it can be removed
; -- except for fpexcept.strict operations.
define void @f13(float %f1) {
; CHECK-LABEL: f13:
; CHECK-NOT: sqeb
; CHECK: br %r14
%sqrt = call float @llvm.sqrt.f32(float %f1)
ret void
}
define void @f14(float %f1) {
; CHECK-LABEL: f14:
; CHECK-NOT: sqeb
; CHECK: br %r14
%sqrt = call float @llvm.experimental.constrained.sqrt.f32(
float %f1,
metadata !"round.dynamic",
metadata !"fpexcept.ignore") #0
ret void
}
define void @f15(float %f1) {
; CHECK-LABEL: f15:
; CHECK-NOT: sqeb
; CHECK: br %r14
%sqrt = call float @llvm.experimental.constrained.sqrt.f32(
float %f1,
metadata !"round.dynamic",
metadata !"fpexcept.maytrap") #0
ret void
}
define void @f16(float %f1) {
; CHECK-LABEL: f16:
; CHECK: sqebr
; CHECK: br %r14
%sqrt = call float @llvm.experimental.constrained.sqrt.f32(
float %f1,
metadata !"round.dynamic",
metadata !"fpexcept.strict") #0
ret void
}
attributes #0 = { strictfp } attributes #0 = { strictfp }

llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll

Show All 27 Lines
} }
define <2 x double> @constrained_vector_fdiv_v2f64() #0 { define <2 x double> @constrained_vector_fdiv_v2f64() #0 {
; S390X-LABEL: constrained_vector_fdiv_v2f64: ; S390X-LABEL: constrained_vector_fdiv_v2f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI1_0 ; S390X-NEXT: larl %r1, .LCPI1_0
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI1_1 ; S390X-NEXT: larl %r1, .LCPI1_1
; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI1_2
; S390X-NEXT: ldeb %f2, 0(%r1) ; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: ddbr %f0, %f1 ; S390X-NEXT: larl %r1, .LCPI1_2
; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: ddbr %f2, %f1 ; S390X-NEXT: ddbr %f2, %f1
; S390X-NEXT: ddbr %f0, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fdiv_v2f64: ; SZ13-LABEL: constrained_vector_fdiv_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI1_0 ; SZ13-NEXT: larl %r1, .LCPI1_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI1_1 ; SZ13-NEXT: larl %r1, .LCPI1_1
; SZ13-NEXT: vl %v1, 0(%r1), 3 ; SZ13-NEXT: vl %v1, 0(%r1), 3
Show All 9 Lines
} }
define <3 x float> @constrained_vector_fdiv_v3f32() #0 { define <3 x float> @constrained_vector_fdiv_v3f32() #0 {
; S390X-LABEL: constrained_vector_fdiv_v3f32: ; S390X-LABEL: constrained_vector_fdiv_v3f32:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI2_0 ; S390X-NEXT: larl %r1, .LCPI2_0
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI2_1 ; S390X-NEXT: larl %r1, .LCPI2_1
; S390X-NEXT: le %f0, 0(%r1) ; S390X-NEXT: le %f4, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI2_2 ; S390X-NEXT: larl %r1, .LCPI2_2
; S390X-NEXT: le %f2, 0(%r1) ; S390X-NEXT: le %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI2_3 ; S390X-NEXT: larl %r1, .LCPI2_3
; S390X-NEXT: le %f4, 0(%r1) ; S390X-NEXT: le %f0, 0(%r1)
; S390X-NEXT: debr %f0, %f1
; S390X-NEXT: debr %f2, %f1
; S390X-NEXT: debr %f4, %f1 ; S390X-NEXT: debr %f4, %f1
; S390X-NEXT: debr %f2, %f1
; S390X-NEXT: debr %f0, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fdiv_v3f32: ; SZ13-LABEL: constrained_vector_fdiv_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI2_0 ; SZ13-NEXT: larl %r1, .LCPI2_0
; SZ13-NEXT: lde %f0, 0(%r1) ; SZ13-NEXT: lde %f0, 0(%r1)
; SZ13-NEXT: larl %r1, .LCPI2_1 ; SZ13-NEXT: larl %r1, .LCPI2_1
; SZ13-NEXT: lde %f1, 0(%r1) ; SZ13-NEXT: lde %f1, 0(%r1)
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
} }
define <4 x double> @constrained_vector_fdiv_v4f64() #0 { define <4 x double> @constrained_vector_fdiv_v4f64() #0 {
; S390X-LABEL: constrained_vector_fdiv_v4f64: ; S390X-LABEL: constrained_vector_fdiv_v4f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI4_0 ; S390X-NEXT: larl %r1, .LCPI4_0
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI4_1 ; S390X-NEXT: larl %r1, .LCPI4_1
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ldeb %f6, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI4_2 ; S390X-NEXT: larl %r1, .LCPI4_2
; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI4_3
; S390X-NEXT: ldeb %f4, 0(%r1) ; S390X-NEXT: ldeb %f4, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI4_3
; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI4_4 ; S390X-NEXT: larl %r1, .LCPI4_4
; S390X-NEXT: ldeb %f6, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: ddbr %f0, %f1
; S390X-NEXT: ddbr %f2, %f1
; S390X-NEXT: ddbr %f4, %f1
; S390X-NEXT: ddbr %f6, %f1 ; S390X-NEXT: ddbr %f6, %f1
; S390X-NEXT: ddbr %f4, %f1
; S390X-NEXT: ddbr %f2, %f1
; S390X-NEXT: ddbr %f0, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fdiv_v4f64: ; SZ13-LABEL: constrained_vector_fdiv_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI4_0 ; SZ13-NEXT: larl %r1, .LCPI4_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI4_1 ; SZ13-NEXT: larl %r1, .LCPI4_1
; SZ13-NEXT: vl %v1, 0(%r1), 3 ; SZ13-NEXT: vl %v1, 0(%r1), 3
; SZ13-NEXT: vfddb %v24, %v1, %v0 ; SZ13-NEXT: vfddb %v26, %v1, %v0
; SZ13-NEXT: larl %r1, .LCPI4_2 ; SZ13-NEXT: larl %r1, .LCPI4_2
; SZ13-NEXT: vl %v1, 0(%r1), 3 ; SZ13-NEXT: vl %v1, 0(%r1), 3
; SZ13-NEXT: vfddb %v26, %v1, %v0 ; SZ13-NEXT: vfddb %v24, %v1, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%div = call <4 x double> @llvm.experimental.constrained.fdiv.v4f64( %div = call <4 x double> @llvm.experimental.constrained.fdiv.v4f64(
<4 x double> <double 1.000000e+00, double 2.000000e+00, <4 x double> <double 1.000000e+00, double 2.000000e+00,
double 3.000000e+00, double 4.000000e+00>, double 3.000000e+00, double 4.000000e+00>,
<4 x double> <double 1.000000e+01, double 1.000000e+01, <4 x double> <double 1.000000e+01, double 1.000000e+01,
double 1.000000e+01, double 1.000000e+01>, double 1.000000e+01, double 1.000000e+01>,
metadata !"round.dynamic", metadata !"round.dynamic",
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines
; S390X-NEXT: ldr %f2, %f8 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: brasl %r14, fmod@PLT ; S390X-NEXT: brasl %r14, fmod@PLT
; S390X-NEXT: larl %r1, .LCPI6_2 ; S390X-NEXT: larl %r1, .LCPI6_2
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f9, %f0 ; S390X-NEXT: ldr %f9, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: ldr %f2, %f8 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: brasl %r14, fmod@PLT ; S390X-NEXT: brasl %r14, fmod@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f9
; S390X-NEXT: ldr %f0, %f9
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_frem_v2f64: ; SZ13-LABEL: constrained_vector_frem_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; S390X-NEXT: ler %f2, %f8 ; S390X-NEXT: ler %f2, %f8
; S390X-NEXT: brasl %r14, fmodf@PLT ; S390X-NEXT: brasl %r14, fmodf@PLT
; S390X-NEXT: larl %r1, .LCPI7_3 ; S390X-NEXT: larl %r1, .LCPI7_3
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f10, %f0 ; S390X-NEXT: ler %f10, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: ler %f2, %f8 ; S390X-NEXT: ler %f2, %f8
; S390X-NEXT: brasl %r14, fmodf@PLT ; S390X-NEXT: brasl %r14, fmodf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f9
; S390X-NEXT: ler %f2, %f10 ; S390X-NEXT: ler %f2, %f10
; S390X-NEXT: ler %f4, %f9
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_frem_v3f32: ; SZ13-LABEL: constrained_vector_frem_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
▲ Show 20 Lines • Show All 165 Lines • ▼ Show 20 Lines
; S390X-NEXT: ldr %f2, %f8 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: brasl %r14, fmod@PLT ; S390X-NEXT: brasl %r14, fmod@PLT
; S390X-NEXT: larl %r1, .LCPI9_4 ; S390X-NEXT: larl %r1, .LCPI9_4
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f11, %f0 ; S390X-NEXT: ldr %f11, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: ldr %f2, %f8 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: brasl %r14, fmod@PLT ; S390X-NEXT: brasl %r14, fmod@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f11
; S390X-NEXT: ldr %f0, %f9 ; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ldr %f2, %f10 ; S390X-NEXT: ldr %f6, %f9
; S390X-NEXT: ldr %f4, %f11
; S390X-NEXT: ld %f8, 184(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 184(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f11, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f11, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 304(%r15) ; S390X-NEXT: lmg %r14, %r15, 304(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_frem_v4f64: ; SZ13-LABEL: constrained_vector_frem_v4f64:
▲ Show 20 Lines • Show All 70 Lines • ▼ Show 20 Lines %mul = call <1 x float> @llvm.experimental.constrained.fmul.v1f32(
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <1 x float> %mul ret <1 x float> %mul
} }
define <2 x double> @constrained_vector_fmul_v2f64() #0 { define <2 x double> @constrained_vector_fmul_v2f64() #0 {
; S390X-LABEL: constrained_vector_fmul_v2f64: ; S390X-LABEL: constrained_vector_fmul_v2f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI11_0 ; S390X-NEXT: larl %r1, .LCPI11_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI11_1 ; S390X-NEXT: larl %r1, .LCPI11_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI11_2 ; S390X-NEXT: larl %r1, .LCPI11_2
; S390X-NEXT: ldeb %f2, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: mdbr %f0, %f1
; S390X-NEXT: mdbr %f2, %f1 ; S390X-NEXT: mdbr %f2, %f1
; S390X-NEXT: mdbr %f0, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fmul_v2f64: ; SZ13-LABEL: constrained_vector_fmul_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI11_0 ; SZ13-NEXT: larl %r1, .LCPI11_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI11_1 ; SZ13-NEXT: larl %r1, .LCPI11_1
; SZ13-NEXT: vl %v1, 0(%r1), 3 ; SZ13-NEXT: vl %v1, 0(%r1), 3
; SZ13-NEXT: vfmdb %v24, %v1, %v0 ; SZ13-NEXT: vfmdb %v24, %v1, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%mul = call <2 x double> @llvm.experimental.constrained.fmul.v2f64( %mul = call <2 x double> @llvm.experimental.constrained.fmul.v2f64(
<2 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>, <2 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<2 x double> <double 2.000000e+00, double 3.000000e+00>, <2 x double> <double 2.000000e+00, double 3.000000e+00>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x double> %mul ret <2 x double> %mul
} }
define <3 x float> @constrained_vector_fmul_v3f32() #0 { define <3 x float> @constrained_vector_fmul_v3f32() #0 {
; S390X-LABEL: constrained_vector_fmul_v3f32: ; S390X-LABEL: constrained_vector_fmul_v3f32:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI12_0 ; S390X-NEXT: larl %r1, .LCPI12_0
; S390X-NEXT: le %f4, 0(%r1) ; S390X-NEXT: le %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI12_1 ; S390X-NEXT: larl %r1, .LCPI12_1
; S390X-NEXT: ler %f0, %f4 ; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: meeb %f0, 0(%r1) ; S390X-NEXT: meeb %f4, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI12_2 ; S390X-NEXT: larl %r1, .LCPI12_2
; S390X-NEXT: ler %f2, %f4 ; S390X-NEXT: ler %f2, %f0
; S390X-NEXT: meeb %f2, 0(%r1) ; S390X-NEXT: meeb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI12_3 ; S390X-NEXT: larl %r1, .LCPI12_3
; S390X-NEXT: meeb %f4, 0(%r1) ; S390X-NEXT: meeb %f0, 0(%r1)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fmul_v3f32: ; SZ13-LABEL: constrained_vector_fmul_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: vgmf %v0, 1, 8 ; SZ13-NEXT: vgmf %v0, 1, 8
; SZ13-NEXT: larl %r1, .LCPI12_0 ; SZ13-NEXT: larl %r1, .LCPI12_0
; SZ13-NEXT: vgmf %v2, 2, 8 ; SZ13-NEXT: vgmf %v2, 2, 8
; SZ13-NEXT: vgmf %v1, 1, 8 ; SZ13-NEXT: vgmf %v1, 1, 8
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Linesentry:
store <3 x double> %mul, <3 x double>* %a store <3 x double> %mul, <3 x double>* %a
ret void ret void
} }
define <4 x double> @constrained_vector_fmul_v4f64() #0 { define <4 x double> @constrained_vector_fmul_v4f64() #0 {
; S390X-LABEL: constrained_vector_fmul_v4f64: ; S390X-LABEL: constrained_vector_fmul_v4f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI14_0 ; S390X-NEXT: larl %r1, .LCPI14_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ldeb %f6, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI14_1 ; S390X-NEXT: larl %r1, .LCPI14_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI14_2 ; S390X-NEXT: larl %r1, .LCPI14_2
; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI14_3
; S390X-NEXT: ldeb %f4, 0(%r1) ; S390X-NEXT: ldeb %f4, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI14_3
; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI14_4 ; S390X-NEXT: larl %r1, .LCPI14_4
; S390X-NEXT: ldeb %f6, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: mdbr %f0, %f1
; S390X-NEXT: mdbr %f2, %f1
; S390X-NEXT: mdbr %f4, %f1
; S390X-NEXT: mdbr %f6, %f1 ; S390X-NEXT: mdbr %f6, %f1
; S390X-NEXT: mdbr %f4, %f1
; S390X-NEXT: mdbr %f2, %f1
; S390X-NEXT: mdbr %f0, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fmul_v4f64: ; SZ13-LABEL: constrained_vector_fmul_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI14_0 ; SZ13-NEXT: larl %r1, .LCPI14_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI14_1 ; SZ13-NEXT: larl %r1, .LCPI14_1
; SZ13-NEXT: vl %v1, 0(%r1), 3 ; SZ13-NEXT: vl %v1, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI14_2 ; SZ13-NEXT: larl %r1, .LCPI14_2
; SZ13-NEXT: vfmdb %v24, %v1, %v0
; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vfmdb %v26, %v1, %v0 ; SZ13-NEXT: vfmdb %v26, %v1, %v0
; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vfmdb %v24, %v1, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%mul = call <4 x double> @llvm.experimental.constrained.fmul.v4f64( %mul = call <4 x double> @llvm.experimental.constrained.fmul.v4f64(
<4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF, <4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF,
double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>, double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<4 x double> <double 2.000000e+00, double 3.000000e+00, <4 x double> <double 2.000000e+00, double 3.000000e+00,
double 4.000000e+00, double 5.000000e+00>, double 4.000000e+00, double 5.000000e+00>,
metadata !"round.dynamic", metadata !"round.dynamic",
Show All 25 Lines %add = call <1 x float> @llvm.experimental.constrained.fadd.v1f32(
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <1 x float> %add ret <1 x float> %add
} }
define <2 x double> @constrained_vector_fadd_v2f64() #0 { define <2 x double> @constrained_vector_fadd_v2f64() #0 {
; S390X-LABEL: constrained_vector_fadd_v2f64: ; S390X-LABEL: constrained_vector_fadd_v2f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI16_0 ; S390X-NEXT: larl %r1, .LCPI16_0
; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI16_2
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI16_1 ; S390X-NEXT: larl %r1, .LCPI16_1
; S390X-NEXT: ld %f2, 0(%r1) ; S390X-NEXT: ldr %f2, %f1
; S390X-NEXT: adbr %f0, %f2
; S390X-NEXT: larl %r1, .LCPI16_2
; S390X-NEXT: adb %f2, 0(%r1) ; S390X-NEXT: adb %f2, 0(%r1)
; S390X-NEXT: adbr %f0, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fadd_v2f64: ; SZ13-LABEL: constrained_vector_fadd_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI16_0 ; SZ13-NEXT: larl %r1, .LCPI16_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI16_1 ; SZ13-NEXT: larl %r1, .LCPI16_1
; SZ13-NEXT: vl %v1, 0(%r1), 3 ; SZ13-NEXT: vl %v1, 0(%r1), 3
; SZ13-NEXT: vfadb %v24, %v1, %v0 ; SZ13-NEXT: vfadb %v24, %v1, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%add = call <2 x double> @llvm.experimental.constrained.fadd.v2f64( %add = call <2 x double> @llvm.experimental.constrained.fadd.v2f64(
<2 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>, <2 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<2 x double> <double 1.000000e+00, double 1.000000e-01>, <2 x double> <double 1.000000e+00, double 1.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x double> %add ret <2 x double> %add
} }
define <3 x float> @constrained_vector_fadd_v3f32() #0 { define <3 x float> @constrained_vector_fadd_v3f32() #0 {
; S390X-LABEL: constrained_vector_fadd_v3f32: ; S390X-LABEL: constrained_vector_fadd_v3f32:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI17_0 ; S390X-NEXT: larl %r1, .LCPI17_0
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f0, 0(%r1)
; S390X-NEXT: lzer %f4
; S390X-NEXT: aebr %f4, %f0
; S390X-NEXT: larl %r1, .LCPI17_1 ; S390X-NEXT: larl %r1, .LCPI17_1
; S390X-NEXT: ler %f2, %f1 ; S390X-NEXT: ler %f2, %f0
; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: aeb %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI17_2
; S390X-NEXT: aeb %f2, 0(%r1) ; S390X-NEXT: aeb %f2, 0(%r1)
; S390X-NEXT: lzer %f4 ; S390X-NEXT: larl %r1, .LCPI17_2
; S390X-NEXT: aebr %f4, %f1 ; S390X-NEXT: aeb %f0, 0(%r1)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fadd_v3f32: ; SZ13-LABEL: constrained_vector_fadd_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: vgbm %v0, 15 ; SZ13-NEXT: vgbm %v0, 15
; SZ13-NEXT: vgmf %v2, 1, 1 ; SZ13-NEXT: vgmf %v2, 1, 1
; SZ13-NEXT: vgmf %v3, 2, 8 ; SZ13-NEXT: vgmf %v3, 2, 8
; SZ13-NEXT: lzer %f1 ; SZ13-NEXT: lzer %f1
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Linesentry:
store <3 x double> %add, <3 x double>* %a store <3 x double> %add, <3 x double>* %a
ret void ret void
} }
define <4 x double> @constrained_vector_fadd_v4f64() #0 { define <4 x double> @constrained_vector_fadd_v4f64() #0 {
; S390X-LABEL: constrained_vector_fadd_v4f64: ; S390X-LABEL: constrained_vector_fadd_v4f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI19_0 ; S390X-NEXT: larl %r1, .LCPI19_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI19_1 ; S390X-NEXT: larl %r1, .LCPI19_1
; S390X-NEXT: ld %f6, 0(%r1) ; S390X-NEXT: ldr %f2, %f1
; S390X-NEXT: larl %r1, .LCPI19_3 ; S390X-NEXT: ldr %f6, %f1
; S390X-NEXT: ldeb %f4, 0(%r1) ; S390X-NEXT: adb %f6, 0(%r1)
; S390X-NEXT: adbr %f0, %f6
; S390X-NEXT: larl %r1, .LCPI19_2 ; S390X-NEXT: larl %r1, .LCPI19_2
; S390X-NEXT: ldr %f2, %f6 ; S390X-NEXT: ldeb %f4, 0(%r1)
; S390X-NEXT: adb %f2, 0(%r1)
; S390X-NEXT: adbr %f4, %f6
; S390X-NEXT: larl %r1, .LCPI19_4 ; S390X-NEXT: larl %r1, .LCPI19_4
; S390X-NEXT: adb %f6, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI19_3
; S390X-NEXT: adb %f2, 0(%r1)
; S390X-NEXT: adbr %f4, %f1
; S390X-NEXT: adbr %f0, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fadd_v4f64: ; SZ13-LABEL: constrained_vector_fadd_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI19_0 ; SZ13-NEXT: larl %r1, .LCPI19_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI19_1 ; SZ13-NEXT: larl %r1, .LCPI19_1
; SZ13-NEXT: vl %v1, 0(%r1), 3 ; SZ13-NEXT: vl %v1, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI19_2 ; SZ13-NEXT: larl %r1, .LCPI19_2
; SZ13-NEXT: vfadb %v24, %v1, %v0
; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vfadb %v26, %v1, %v0 ; SZ13-NEXT: vfadb %v26, %v1, %v0
; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vfadb %v24, %v1, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%add = call <4 x double> @llvm.experimental.constrained.fadd.v4f64( %add = call <4 x double> @llvm.experimental.constrained.fadd.v4f64(
<4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF, <4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF,
double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>, double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<4 x double> <double 1.000000e+00, double 1.000000e-01, <4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>, double 2.000000e+00, double 2.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
Show All 24 Lines %sub = call <1 x float> @llvm.experimental.constrained.fsub.v1f32(
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <1 x float> %sub ret <1 x float> %sub
} }
define <2 x double> @constrained_vector_fsub_v2f64() #0 { define <2 x double> @constrained_vector_fsub_v2f64() #0 {
; S390X-LABEL: constrained_vector_fsub_v2f64: ; S390X-LABEL: constrained_vector_fsub_v2f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI21_1
; S390X-NEXT: ld %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI21_0 ; S390X-NEXT: larl %r1, .LCPI21_0
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: ldr %f0, %f2
; S390X-NEXT: larl %r1, .LCPI21_2 ; S390X-NEXT: larl %r1, .LCPI21_2
; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI21_1
; S390X-NEXT: ldr %f2, %f0
; S390X-NEXT: sdb %f2, 0(%r1) ; S390X-NEXT: sdb %f2, 0(%r1)
; S390X-NEXT: sdbr %f0, %f1 ; S390X-NEXT: sdbr %f0, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fsub_v2f64: ; SZ13-LABEL: constrained_vector_fsub_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI21_0 ; SZ13-NEXT: larl %r1, .LCPI21_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vgmg %v1, 12, 10 ; SZ13-NEXT: vgmg %v1, 12, 10
; SZ13-NEXT: vfsdb %v24, %v1, %v0 ; SZ13-NEXT: vfsdb %v24, %v1, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64( %sub = call <2 x double> @llvm.experimental.constrained.fsub.v2f64(
<2 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>, <2 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<2 x double> <double 1.000000e+00, double 1.000000e-01>, <2 x double> <double 1.000000e+00, double 1.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x double> %sub ret <2 x double> %sub
} }
define <3 x float> @constrained_vector_fsub_v3f32() #0 { define <3 x float> @constrained_vector_fsub_v3f32() #0 {
; S390X-LABEL: constrained_vector_fsub_v3f32: ; S390X-LABEL: constrained_vector_fsub_v3f32:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI22_0 ; S390X-NEXT: larl %r1, .LCPI22_0
; S390X-NEXT: le %f4, 0(%r1) ; S390X-NEXT: le %f0, 0(%r1)
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: larl %r1, .LCPI22_1 ; S390X-NEXT: larl %r1, .LCPI22_1
; S390X-NEXT: ler %f0, %f4 ; S390X-NEXT: ler %f2, %f0
; S390X-NEXT: seb %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI22_2
; S390X-NEXT: ler %f2, %f4
; S390X-NEXT: seb %f2, 0(%r1) ; S390X-NEXT: seb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI22_2
; S390X-NEXT: seb %f0, 0(%r1)
; S390X-NEXT: lzer %f1 ; S390X-NEXT: lzer %f1
; S390X-NEXT: sebr %f4, %f1 ; S390X-NEXT: sebr %f4, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fsub_v3f32: ; SZ13-LABEL: constrained_vector_fsub_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: vgbm %v2, 15 ; SZ13-NEXT: vgbm %v2, 15
; SZ13-NEXT: lzer %f1 ; SZ13-NEXT: lzer %f1
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines %sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64(
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
store <3 x double> %sub, <3 x double>* %a store <3 x double> %sub, <3 x double>* %a
ret void ret void
} }
define <4 x double> @constrained_vector_fsub_v4f64() #0 { define <4 x double> @constrained_vector_fsub_v4f64() #0 {
; S390X-LABEL: constrained_vector_fsub_v4f64: ; S390X-LABEL: constrained_vector_fsub_v4f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI24_1
; S390X-NEXT: ld %f6, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI24_0 ; S390X-NEXT: larl %r1, .LCPI24_0
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: ldr %f0, %f6 ; S390X-NEXT: larl %r1, .LCPI24_1
; S390X-NEXT: ldr %f6, %f0
; S390X-NEXT: sdb %f6, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI24_2 ; S390X-NEXT: larl %r1, .LCPI24_2
; S390X-NEXT: ldr %f2, %f6 ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: sdb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI24_3
; S390X-NEXT: ldeb %f3, 0(%r1)
; S390X-NEXT: ldr %f4, %f6
; S390X-NEXT: larl %r1, .LCPI24_4 ; S390X-NEXT: larl %r1, .LCPI24_4
; S390X-NEXT: sdb %f6, 0(%r1) ; S390X-NEXT: ldeb %f3, 0(%r1)
; S390X-NEXT: sdbr %f0, %f1 ; S390X-NEXT: larl %r1, .LCPI24_3
; S390X-NEXT: sdbr %f4, %f3 ; S390X-NEXT: ldr %f2, %f0
; S390X-NEXT: sdb %f2, 0(%r1)
; S390X-NEXT: ldr %f4, %f0
; S390X-NEXT: sdbr %f4, %f1
; S390X-NEXT: sdbr %f0, %f3
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fsub_v4f64: ; SZ13-LABEL: constrained_vector_fsub_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI24_0 ; SZ13-NEXT: larl %r1, .LCPI24_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vgmg %v1, 12, 10 ; SZ13-NEXT: vgmg %v1, 12, 10
; SZ13-NEXT: larl %r1, .LCPI24_1 ; SZ13-NEXT: larl %r1, .LCPI24_1
; SZ13-NEXT: vfsdb %v24, %v1, %v0
; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vfsdb %v26, %v1, %v0 ; SZ13-NEXT: vfsdb %v26, %v1, %v0
; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vfsdb %v24, %v1, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64( %sub = call <4 x double> @llvm.experimental.constrained.fsub.v4f64(
<4 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF, <4 x double> <double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF,
double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>, double 0xFFEFFFFFFFFFFFFF, double 0xFFEFFFFFFFFFFFFF>,
<4 x double> <double 1.000000e+00, double 1.000000e-01, <4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>, double 2.000000e+00, double 2.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines %sqrt = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x double> %sqrt ret <2 x double> %sqrt
} }
define <3 x float> @constrained_vector_sqrt_v3f32() #0 { define <3 x float> @constrained_vector_sqrt_v3f32() #0 {
; S390X-LABEL: constrained_vector_sqrt_v3f32: ; S390X-LABEL: constrained_vector_sqrt_v3f32:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI27_0 ; S390X-NEXT: larl %r1, .LCPI27_0
; S390X-NEXT: sqeb %f0, 0(%r1) ; S390X-NEXT: sqeb %f4, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI27_1 ; S390X-NEXT: larl %r1, .LCPI27_1
; S390X-NEXT: sqeb %f2, 0(%r1) ; S390X-NEXT: sqeb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI27_2 ; S390X-NEXT: larl %r1, .LCPI27_2
; S390X-NEXT: sqeb %f4, 0(%r1) ; S390X-NEXT: sqeb %f0, 0(%r1)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_sqrt_v3f32: ; SZ13-LABEL: constrained_vector_sqrt_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI27_0 ; SZ13-NEXT: larl %r1, .LCPI27_0
; SZ13-NEXT: sqeb %f0, 0(%r1) ; SZ13-NEXT: sqeb %f0, 0(%r1)
; SZ13-NEXT: larl %r1, .LCPI27_1 ; SZ13-NEXT: larl %r1, .LCPI27_1
; SZ13-NEXT: vrepf %v0, %v0, 0 ; SZ13-NEXT: vrepf %v0, %v0, 0
Show All 39 Linesentry:
store <3 x double> %sqrt, <3 x double>* %a store <3 x double> %sqrt, <3 x double>* %a
ret void ret void
} }
define <4 x double> @constrained_vector_sqrt_v4f64() #0 { define <4 x double> @constrained_vector_sqrt_v4f64() #0 {
; S390X-LABEL: constrained_vector_sqrt_v4f64: ; S390X-LABEL: constrained_vector_sqrt_v4f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI29_0 ; S390X-NEXT: larl %r1, .LCPI29_0
; S390X-NEXT: sqdb %f2, 0(%r1) ; S390X-NEXT: sqdb %f6, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI29_1 ; S390X-NEXT: larl %r1, .LCPI29_1
; S390X-NEXT: sqdb %f4, 0(%r1) ; S390X-NEXT: sqdb %f4, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI29_3 ; S390X-NEXT: larl %r1, .LCPI29_3
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI29_2 ; S390X-NEXT: larl %r1, .LCPI29_2
; S390X-NEXT: sqdb %f6, 0(%r1) ; S390X-NEXT: sqdb %f2, 0(%r1)
; S390X-NEXT: sqdbr %f0, %f0 ; S390X-NEXT: sqdbr %f0, %f0
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_sqrt_v4f64: ; SZ13-LABEL: constrained_vector_sqrt_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI29_0 ; SZ13-NEXT: larl %r1, .LCPI29_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vfsqdb %v24, %v0 ; SZ13-NEXT: vfsqdb %v26, %v0
; SZ13-NEXT: larl %r1, .LCPI29_1 ; SZ13-NEXT: larl %r1, .LCPI29_1
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vfsqdb %v26, %v0 ; SZ13-NEXT: vfsqdb %v24, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%sqrt = call <4 x double> @llvm.experimental.constrained.sqrt.v4f64( %sqrt = call <4 x double> @llvm.experimental.constrained.sqrt.v4f64(
<4 x double> <double 42.0, double 42.1, <4 x double> <double 42.0, double 42.1,
double 42.2, double 42.3>, double 42.2, double 42.3>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x double> %sqrt ret <4 x double> %sqrt
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; S390X-NEXT: ldr %f2, %f8 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: brasl %r14, pow@PLT ; S390X-NEXT: brasl %r14, pow@PLT
; S390X-NEXT: larl %r1, .LCPI31_2 ; S390X-NEXT: larl %r1, .LCPI31_2
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f9, %f0 ; S390X-NEXT: ldr %f9, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: ldr %f2, %f8 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: brasl %r14, pow@PLT ; S390X-NEXT: brasl %r14, pow@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f9
; S390X-NEXT: ldr %f0, %f9
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_pow_v2f64: ; SZ13-LABEL: constrained_vector_pow_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; S390X-NEXT: ler %f2, %f8 ; S390X-NEXT: ler %f2, %f8
; S390X-NEXT: brasl %r14, powf@PLT ; S390X-NEXT: brasl %r14, powf@PLT
; S390X-NEXT: larl %r1, .LCPI32_3 ; S390X-NEXT: larl %r1, .LCPI32_3
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f10, %f0 ; S390X-NEXT: ler %f10, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: ler %f2, %f8 ; S390X-NEXT: ler %f2, %f8
; S390X-NEXT: brasl %r14, powf@PLT ; S390X-NEXT: brasl %r14, powf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f9
; S390X-NEXT: ler %f2, %f10 ; S390X-NEXT: ler %f2, %f10
; S390X-NEXT: ler %f4, %f9
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_pow_v3f32: ; SZ13-LABEL: constrained_vector_pow_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
▲ Show 20 Lines • Show All 171 Lines • ▼ Show 20 Lines
; S390X-NEXT: ldr %f2, %f8 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: brasl %r14, pow@PLT ; S390X-NEXT: brasl %r14, pow@PLT
; S390X-NEXT: larl %r1, .LCPI34_4 ; S390X-NEXT: larl %r1, .LCPI34_4
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f11, %f0 ; S390X-NEXT: ldr %f11, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: ldr %f2, %f8 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: brasl %r14, pow@PLT ; S390X-NEXT: brasl %r14, pow@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f11
; S390X-NEXT: ldr %f0, %f9 ; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ldr %f2, %f10 ; S390X-NEXT: ldr %f6, %f9
; S390X-NEXT: ldr %f4, %f11
; S390X-NEXT: ld %f8, 184(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 184(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f11, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f11, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 304(%r15) ; S390X-NEXT: lmg %r14, %r15, 304(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_pow_v4f64: ; SZ13-LABEL: constrained_vector_pow_v4f64:
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; S390X-NEXT: lghi %r2, 3 ; S390X-NEXT: lghi %r2, 3
; S390X-NEXT: brasl %r14, __powidf2@PLT ; S390X-NEXT: brasl %r14, __powidf2@PLT
; S390X-NEXT: larl %r1, .LCPI36_1 ; S390X-NEXT: larl %r1, .LCPI36_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: lghi %r2, 3 ; S390X-NEXT: lghi %r2, 3
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, __powidf2@PLT ; S390X-NEXT: brasl %r14, __powidf2@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_powi_v2f64: ; SZ13-LABEL: constrained_vector_powi_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
; SZ13-NEXT: .cfi_offset %r14, -48 ; SZ13-NEXT: .cfi_offset %r14, -48
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, __powisf2@PLT ; S390X-NEXT: brasl %r14, __powisf2@PLT
; S390X-NEXT: larl %r1, .LCPI37_2 ; S390X-NEXT: larl %r1, .LCPI37_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: lghi %r2, 3 ; S390X-NEXT: lghi %r2, 3
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, __powisf2@PLT ; S390X-NEXT: brasl %r14, __powisf2@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_powi_v3f32: ; SZ13-LABEL: constrained_vector_powi_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
▲ Show 20 Lines • Show All 146 Lines • ▼ Show 20 Lines
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, __powidf2@PLT ; S390X-NEXT: brasl %r14, __powidf2@PLT
; S390X-NEXT: larl %r1, .LCPI39_3 ; S390X-NEXT: larl %r1, .LCPI39_3
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f10, %f0 ; S390X-NEXT: ldr %f10, %f0
; S390X-NEXT: lghi %r2, 3 ; S390X-NEXT: lghi %r2, 3
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, __powidf2@PLT ; S390X-NEXT: brasl %r14, __powidf2@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f10
; S390X-NEXT: ldr %f0, %f8 ; S390X-NEXT: ldr %f4, %f9
; S390X-NEXT: ldr %f2, %f9 ; S390X-NEXT: ldr %f6, %f8
; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_powi_v4f64: ; SZ13-LABEL: constrained_vector_powi_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines
; S390X-NEXT: stmg %r14, %r15, 112(%r15) ; S390X-NEXT: stmg %r14, %r15, 112(%r15)
; S390X-NEXT: .cfi_offset %r14, -48 ; S390X-NEXT: .cfi_offset %r14, -48
; S390X-NEXT: .cfi_offset %r15, -40 ; S390X-NEXT: .cfi_offset %r15, -40
; S390X-NEXT: aghi %r15, -168 ; S390X-NEXT: aghi %r15, -168
; S390X-NEXT: .cfi_def_cfa_offset 328 ; S390X-NEXT: .cfi_def_cfa_offset 328
; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: larl %r1, .LCPI41_0 ; S390X-NEXT: larl %r1, .LCPI41_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, sin@PLT ; S390X-NEXT: brasl %r14, sin@PLT
; S390X-NEXT: larl %r1, .LCPI41_1 ; S390X-NEXT: larl %r1, .LCPI41_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, sin@PLT ; S390X-NEXT: brasl %r14, sin@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_sin_v2f64: ; SZ13-LABEL: constrained_vector_sin_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
; SZ13-NEXT: .cfi_offset %r14, -48 ; SZ13-NEXT: .cfi_offset %r14, -48
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, sinf@PLT ; S390X-NEXT: brasl %r14, sinf@PLT
; S390X-NEXT: larl %r1, .LCPI42_2 ; S390X-NEXT: larl %r1, .LCPI42_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, sinf@PLT ; S390X-NEXT: brasl %r14, sinf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_sin_v3f32: ; SZ13-LABEL: constrained_vector_sin_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; S390X-NEXT: .cfi_def_cfa_offset 344 ; S390X-NEXT: .cfi_def_cfa_offset 344
; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: .cfi_offset %f9, -176 ; S390X-NEXT: .cfi_offset %f9, -176
; S390X-NEXT: .cfi_offset %f10, -184 ; S390X-NEXT: .cfi_offset %f10, -184
; S390X-NEXT: larl %r1, .LCPI44_0 ; S390X-NEXT: larl %r1, .LCPI44_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, sin@PLT ; S390X-NEXT: brasl %r14, sin@PLT
; S390X-NEXT: larl %r1, .LCPI44_1 ; S390X-NEXT: larl %r1, .LCPI44_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, sin@PLT ; S390X-NEXT: brasl %r14, sin@PLT
; S390X-NEXT: larl %r1, .LCPI44_2 ; S390X-NEXT: larl %r1, .LCPI44_2
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f9, %f0 ; S390X-NEXT: ldr %f9, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, sin@PLT ; S390X-NEXT: brasl %r14, sin@PLT
; S390X-NEXT: larl %r1, .LCPI44_3 ; S390X-NEXT: larl %r1, .LCPI44_3
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f10, %f0 ; S390X-NEXT: ldr %f10, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, sin@PLT ; S390X-NEXT: brasl %r14, sin@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f10
; S390X-NEXT: ldr %f0, %f8 ; S390X-NEXT: ldr %f4, %f9
; S390X-NEXT: ldr %f2, %f9 ; S390X-NEXT: ldr %f6, %f8
; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_sin_v4f64: ; SZ13-LABEL: constrained_vector_sin_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; S390X-NEXT: stmg %r14, %r15, 112(%r15) ; S390X-NEXT: stmg %r14, %r15, 112(%r15)
; S390X-NEXT: .cfi_offset %r14, -48 ; S390X-NEXT: .cfi_offset %r14, -48
; S390X-NEXT: .cfi_offset %r15, -40 ; S390X-NEXT: .cfi_offset %r15, -40
; S390X-NEXT: aghi %r15, -168 ; S390X-NEXT: aghi %r15, -168
; S390X-NEXT: .cfi_def_cfa_offset 328 ; S390X-NEXT: .cfi_def_cfa_offset 328
; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: larl %r1, .LCPI46_0 ; S390X-NEXT: larl %r1, .LCPI46_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, cos@PLT ; S390X-NEXT: brasl %r14, cos@PLT
; S390X-NEXT: larl %r1, .LCPI46_1 ; S390X-NEXT: larl %r1, .LCPI46_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, cos@PLT ; S390X-NEXT: brasl %r14, cos@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_cos_v2f64: ; SZ13-LABEL: constrained_vector_cos_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
; SZ13-NEXT: .cfi_offset %r14, -48 ; SZ13-NEXT: .cfi_offset %r14, -48
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, cosf@PLT ; S390X-NEXT: brasl %r14, cosf@PLT
; S390X-NEXT: larl %r1, .LCPI47_2 ; S390X-NEXT: larl %r1, .LCPI47_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, cosf@PLT ; S390X-NEXT: brasl %r14, cosf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_cos_v3f32: ; SZ13-LABEL: constrained_vector_cos_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; S390X-NEXT: .cfi_def_cfa_offset 344 ; S390X-NEXT: .cfi_def_cfa_offset 344
; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: .cfi_offset %f9, -176 ; S390X-NEXT: .cfi_offset %f9, -176
; S390X-NEXT: .cfi_offset %f10, -184 ; S390X-NEXT: .cfi_offset %f10, -184
; S390X-NEXT: larl %r1, .LCPI49_0 ; S390X-NEXT: larl %r1, .LCPI49_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, cos@PLT ; S390X-NEXT: brasl %r14, cos@PLT
; S390X-NEXT: larl %r1, .LCPI49_1 ; S390X-NEXT: larl %r1, .LCPI49_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, cos@PLT ; S390X-NEXT: brasl %r14, cos@PLT
; S390X-NEXT: larl %r1, .LCPI49_2 ; S390X-NEXT: larl %r1, .LCPI49_2
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f9, %f0 ; S390X-NEXT: ldr %f9, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, cos@PLT ; S390X-NEXT: brasl %r14, cos@PLT
; S390X-NEXT: larl %r1, .LCPI49_3 ; S390X-NEXT: larl %r1, .LCPI49_3
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f10, %f0 ; S390X-NEXT: ldr %f10, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, cos@PLT ; S390X-NEXT: brasl %r14, cos@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f10
; S390X-NEXT: ldr %f0, %f8 ; S390X-NEXT: ldr %f4, %f9
; S390X-NEXT: ldr %f2, %f9 ; S390X-NEXT: ldr %f6, %f8
; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_cos_v4f64: ; SZ13-LABEL: constrained_vector_cos_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; S390X-NEXT: stmg %r14, %r15, 112(%r15) ; S390X-NEXT: stmg %r14, %r15, 112(%r15)
; S390X-NEXT: .cfi_offset %r14, -48 ; S390X-NEXT: .cfi_offset %r14, -48
; S390X-NEXT: .cfi_offset %r15, -40 ; S390X-NEXT: .cfi_offset %r15, -40
; S390X-NEXT: aghi %r15, -168 ; S390X-NEXT: aghi %r15, -168
; S390X-NEXT: .cfi_def_cfa_offset 328 ; S390X-NEXT: .cfi_def_cfa_offset 328
; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: larl %r1, .LCPI51_0 ; S390X-NEXT: larl %r1, .LCPI51_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, exp@PLT ; S390X-NEXT: brasl %r14, exp@PLT
; S390X-NEXT: larl %r1, .LCPI51_1 ; S390X-NEXT: larl %r1, .LCPI51_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, exp@PLT ; S390X-NEXT: brasl %r14, exp@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_exp_v2f64: ; SZ13-LABEL: constrained_vector_exp_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
; SZ13-NEXT: .cfi_offset %r14, -48 ; SZ13-NEXT: .cfi_offset %r14, -48
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, expf@PLT ; S390X-NEXT: brasl %r14, expf@PLT
; S390X-NEXT: larl %r1, .LCPI52_2 ; S390X-NEXT: larl %r1, .LCPI52_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, expf@PLT ; S390X-NEXT: brasl %r14, expf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_exp_v3f32: ; SZ13-LABEL: constrained_vector_exp_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; S390X-NEXT: .cfi_def_cfa_offset 344 ; S390X-NEXT: .cfi_def_cfa_offset 344
; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: .cfi_offset %f9, -176 ; S390X-NEXT: .cfi_offset %f9, -176
; S390X-NEXT: .cfi_offset %f10, -184 ; S390X-NEXT: .cfi_offset %f10, -184
; S390X-NEXT: larl %r1, .LCPI54_0 ; S390X-NEXT: larl %r1, .LCPI54_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, exp@PLT ; S390X-NEXT: brasl %r14, exp@PLT
; S390X-NEXT: larl %r1, .LCPI54_1 ; S390X-NEXT: larl %r1, .LCPI54_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, exp@PLT ; S390X-NEXT: brasl %r14, exp@PLT
; S390X-NEXT: larl %r1, .LCPI54_2 ; S390X-NEXT: larl %r1, .LCPI54_2
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f9, %f0 ; S390X-NEXT: ldr %f9, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, exp@PLT ; S390X-NEXT: brasl %r14, exp@PLT
; S390X-NEXT: larl %r1, .LCPI54_3 ; S390X-NEXT: larl %r1, .LCPI54_3
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f10, %f0 ; S390X-NEXT: ldr %f10, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, exp@PLT ; S390X-NEXT: brasl %r14, exp@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f10
; S390X-NEXT: ldr %f0, %f8 ; S390X-NEXT: ldr %f4, %f9
; S390X-NEXT: ldr %f2, %f9 ; S390X-NEXT: ldr %f6, %f8
; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_exp_v4f64: ; SZ13-LABEL: constrained_vector_exp_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; S390X-NEXT: stmg %r14, %r15, 112(%r15) ; S390X-NEXT: stmg %r14, %r15, 112(%r15)
; S390X-NEXT: .cfi_offset %r14, -48 ; S390X-NEXT: .cfi_offset %r14, -48
; S390X-NEXT: .cfi_offset %r15, -40 ; S390X-NEXT: .cfi_offset %r15, -40
; S390X-NEXT: aghi %r15, -168 ; S390X-NEXT: aghi %r15, -168
; S390X-NEXT: .cfi_def_cfa_offset 328 ; S390X-NEXT: .cfi_def_cfa_offset 328
; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: larl %r1, .LCPI56_0 ; S390X-NEXT: larl %r1, .LCPI56_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: brasl %r14, exp2@PLT ; S390X-NEXT: brasl %r14, exp2@PLT
; S390X-NEXT: larl %r1, .LCPI56_1 ; S390X-NEXT: larl %r1, .LCPI56_1
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, exp2@PLT ; S390X-NEXT: brasl %r14, exp2@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_exp2_v2f64: ; SZ13-LABEL: constrained_vector_exp2_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
; SZ13-NEXT: .cfi_offset %r14, -48 ; SZ13-NEXT: .cfi_offset %r14, -48
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, exp2f@PLT ; S390X-NEXT: brasl %r14, exp2f@PLT
; S390X-NEXT: larl %r1, .LCPI57_2 ; S390X-NEXT: larl %r1, .LCPI57_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, exp2f@PLT ; S390X-NEXT: brasl %r14, exp2f@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_exp2_v3f32: ; SZ13-LABEL: constrained_vector_exp2_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
▲ Show 20 Lines • Show All 136 Lines • ▼ Show 20 Lines
; S390X-NEXT: ldr %f9, %f0 ; S390X-NEXT: ldr %f9, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, exp2@PLT ; S390X-NEXT: brasl %r14, exp2@PLT
; S390X-NEXT: larl %r1, .LCPI59_3 ; S390X-NEXT: larl %r1, .LCPI59_3
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f10, %f0 ; S390X-NEXT: ldr %f10, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, exp2@PLT ; S390X-NEXT: brasl %r14, exp2@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f10
; S390X-NEXT: ldr %f0, %f8 ; S390X-NEXT: ldr %f4, %f9
; S390X-NEXT: ldr %f2, %f9 ; S390X-NEXT: ldr %f6, %f8
; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_exp2_v4f64: ; SZ13-LABEL: constrained_vector_exp2_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; S390X-NEXT: stmg %r14, %r15, 112(%r15) ; S390X-NEXT: stmg %r14, %r15, 112(%r15)
; S390X-NEXT: .cfi_offset %r14, -48 ; S390X-NEXT: .cfi_offset %r14, -48
; S390X-NEXT: .cfi_offset %r15, -40 ; S390X-NEXT: .cfi_offset %r15, -40
; S390X-NEXT: aghi %r15, -168 ; S390X-NEXT: aghi %r15, -168
; S390X-NEXT: .cfi_def_cfa_offset 328 ; S390X-NEXT: .cfi_def_cfa_offset 328
; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: larl %r1, .LCPI61_0 ; S390X-NEXT: larl %r1, .LCPI61_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, log@PLT ; S390X-NEXT: brasl %r14, log@PLT
; S390X-NEXT: larl %r1, .LCPI61_1 ; S390X-NEXT: larl %r1, .LCPI61_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log@PLT ; S390X-NEXT: brasl %r14, log@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_log_v2f64: ; SZ13-LABEL: constrained_vector_log_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
; SZ13-NEXT: .cfi_offset %r14, -48 ; SZ13-NEXT: .cfi_offset %r14, -48
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, logf@PLT ; S390X-NEXT: brasl %r14, logf@PLT
; S390X-NEXT: larl %r1, .LCPI62_2 ; S390X-NEXT: larl %r1, .LCPI62_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, logf@PLT ; S390X-NEXT: brasl %r14, logf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_log_v3f32: ; SZ13-LABEL: constrained_vector_log_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; S390X-NEXT: .cfi_def_cfa_offset 344 ; S390X-NEXT: .cfi_def_cfa_offset 344
; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: .cfi_offset %f9, -176 ; S390X-NEXT: .cfi_offset %f9, -176
; S390X-NEXT: .cfi_offset %f10, -184 ; S390X-NEXT: .cfi_offset %f10, -184
; S390X-NEXT: larl %r1, .LCPI64_0 ; S390X-NEXT: larl %r1, .LCPI64_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, log@PLT ; S390X-NEXT: brasl %r14, log@PLT
; S390X-NEXT: larl %r1, .LCPI64_1 ; S390X-NEXT: larl %r1, .LCPI64_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log@PLT ; S390X-NEXT: brasl %r14, log@PLT
; S390X-NEXT: larl %r1, .LCPI64_2 ; S390X-NEXT: larl %r1, .LCPI64_2
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f9, %f0 ; S390X-NEXT: ldr %f9, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log@PLT ; S390X-NEXT: brasl %r14, log@PLT
; S390X-NEXT: larl %r1, .LCPI64_3 ; S390X-NEXT: larl %r1, .LCPI64_3
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f10, %f0 ; S390X-NEXT: ldr %f10, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log@PLT ; S390X-NEXT: brasl %r14, log@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f10
; S390X-NEXT: ldr %f0, %f8 ; S390X-NEXT: ldr %f4, %f9
; S390X-NEXT: ldr %f2, %f9 ; S390X-NEXT: ldr %f6, %f8
; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_log_v4f64: ; SZ13-LABEL: constrained_vector_log_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; S390X-NEXT: stmg %r14, %r15, 112(%r15) ; S390X-NEXT: stmg %r14, %r15, 112(%r15)
; S390X-NEXT: .cfi_offset %r14, -48 ; S390X-NEXT: .cfi_offset %r14, -48
; S390X-NEXT: .cfi_offset %r15, -40 ; S390X-NEXT: .cfi_offset %r15, -40
; S390X-NEXT: aghi %r15, -168 ; S390X-NEXT: aghi %r15, -168
; S390X-NEXT: .cfi_def_cfa_offset 328 ; S390X-NEXT: .cfi_def_cfa_offset 328
; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: larl %r1, .LCPI66_0 ; S390X-NEXT: larl %r1, .LCPI66_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, log10@PLT ; S390X-NEXT: brasl %r14, log10@PLT
; S390X-NEXT: larl %r1, .LCPI66_1 ; S390X-NEXT: larl %r1, .LCPI66_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log10@PLT ; S390X-NEXT: brasl %r14, log10@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_log10_v2f64: ; SZ13-LABEL: constrained_vector_log10_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
; SZ13-NEXT: .cfi_offset %r14, -48 ; SZ13-NEXT: .cfi_offset %r14, -48
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, log10f@PLT ; S390X-NEXT: brasl %r14, log10f@PLT
; S390X-NEXT: larl %r1, .LCPI67_2 ; S390X-NEXT: larl %r1, .LCPI67_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, log10f@PLT ; S390X-NEXT: brasl %r14, log10f@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_log10_v3f32: ; SZ13-LABEL: constrained_vector_log10_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; S390X-NEXT: .cfi_def_cfa_offset 344 ; S390X-NEXT: .cfi_def_cfa_offset 344
; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: .cfi_offset %f9, -176 ; S390X-NEXT: .cfi_offset %f9, -176
; S390X-NEXT: .cfi_offset %f10, -184 ; S390X-NEXT: .cfi_offset %f10, -184
; S390X-NEXT: larl %r1, .LCPI69_0 ; S390X-NEXT: larl %r1, .LCPI69_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, log10@PLT ; S390X-NEXT: brasl %r14, log10@PLT
; S390X-NEXT: larl %r1, .LCPI69_1 ; S390X-NEXT: larl %r1, .LCPI69_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log10@PLT ; S390X-NEXT: brasl %r14, log10@PLT
; S390X-NEXT: larl %r1, .LCPI69_2 ; S390X-NEXT: larl %r1, .LCPI69_2
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f9, %f0 ; S390X-NEXT: ldr %f9, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log10@PLT ; S390X-NEXT: brasl %r14, log10@PLT
; S390X-NEXT: larl %r1, .LCPI69_3 ; S390X-NEXT: larl %r1, .LCPI69_3
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f10, %f0 ; S390X-NEXT: ldr %f10, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log10@PLT ; S390X-NEXT: brasl %r14, log10@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f10
; S390X-NEXT: ldr %f0, %f8 ; S390X-NEXT: ldr %f4, %f9
; S390X-NEXT: ldr %f2, %f9 ; S390X-NEXT: ldr %f6, %f8
; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_log10_v4f64: ; SZ13-LABEL: constrained_vector_log10_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
▲ Show 20 Lines • Show All 79 Lines • ▼ Show 20 Lines
; S390X-NEXT: stmg %r14, %r15, 112(%r15) ; S390X-NEXT: stmg %r14, %r15, 112(%r15)
; S390X-NEXT: .cfi_offset %r14, -48 ; S390X-NEXT: .cfi_offset %r14, -48
; S390X-NEXT: .cfi_offset %r15, -40 ; S390X-NEXT: .cfi_offset %r15, -40
; S390X-NEXT: aghi %r15, -168 ; S390X-NEXT: aghi %r15, -168
; S390X-NEXT: .cfi_def_cfa_offset 328 ; S390X-NEXT: .cfi_def_cfa_offset 328
; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: larl %r1, .LCPI71_0 ; S390X-NEXT: larl %r1, .LCPI71_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, log2@PLT ; S390X-NEXT: brasl %r14, log2@PLT
; S390X-NEXT: larl %r1, .LCPI71_1 ; S390X-NEXT: larl %r1, .LCPI71_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log2@PLT ; S390X-NEXT: brasl %r14, log2@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_log2_v2f64: ; SZ13-LABEL: constrained_vector_log2_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
; SZ13-NEXT: .cfi_offset %r14, -48 ; SZ13-NEXT: .cfi_offset %r14, -48
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, log2f@PLT ; S390X-NEXT: brasl %r14, log2f@PLT
; S390X-NEXT: larl %r1, .LCPI72_2 ; S390X-NEXT: larl %r1, .LCPI72_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, log2f@PLT ; S390X-NEXT: brasl %r14, log2f@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_log2_v3f32: ; SZ13-LABEL: constrained_vector_log2_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; S390X-NEXT: .cfi_def_cfa_offset 344 ; S390X-NEXT: .cfi_def_cfa_offset 344
; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: .cfi_offset %f9, -176 ; S390X-NEXT: .cfi_offset %f9, -176
; S390X-NEXT: .cfi_offset %f10, -184 ; S390X-NEXT: .cfi_offset %f10, -184
; S390X-NEXT: larl %r1, .LCPI74_0 ; S390X-NEXT: larl %r1, .LCPI74_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, log2@PLT ; S390X-NEXT: brasl %r14, log2@PLT
; S390X-NEXT: larl %r1, .LCPI74_1 ; S390X-NEXT: larl %r1, .LCPI74_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log2@PLT ; S390X-NEXT: brasl %r14, log2@PLT
; S390X-NEXT: larl %r1, .LCPI74_2 ; S390X-NEXT: larl %r1, .LCPI74_2
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f9, %f0 ; S390X-NEXT: ldr %f9, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log2@PLT ; S390X-NEXT: brasl %r14, log2@PLT
; S390X-NEXT: larl %r1, .LCPI74_3 ; S390X-NEXT: larl %r1, .LCPI74_3
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: ldr %f10, %f0 ; S390X-NEXT: ldr %f10, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, log2@PLT ; S390X-NEXT: brasl %r14, log2@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f10
; S390X-NEXT: ldr %f0, %f8 ; S390X-NEXT: ldr %f4, %f9
; S390X-NEXT: ldr %f2, %f9 ; S390X-NEXT: ldr %f6, %f8
; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_log2_v4f64: ; SZ13-LABEL: constrained_vector_log2_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
▲ Show 20 Lines • Show All 59 Lines • ▼ Show 20 Lines %rint = call <1 x float> @llvm.experimental.constrained.rint.v1f32(
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <1 x float> %rint ret <1 x float> %rint
} }
define <2 x double> @constrained_vector_rint_v2f64() #0 { define <2 x double> @constrained_vector_rint_v2f64() #0 {
; S390X-LABEL: constrained_vector_rint_v2f64: ; S390X-LABEL: constrained_vector_rint_v2f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI76_0 ; S390X-NEXT: larl %r1, .LCPI76_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI76_1 ; S390X-NEXT: larl %r1, .LCPI76_1
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: fidbr %f0, 0, %f0 ; S390X-NEXT: fidbr %f2, 0, %f0
; S390X-NEXT: fidbr %f2, 0, %f1 ; S390X-NEXT: fidbr %f0, 0, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_rint_v2f64: ; SZ13-LABEL: constrained_vector_rint_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI76_0 ; SZ13-NEXT: larl %r1, .LCPI76_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: vfidb %v24, %v0, 0, 0 ; SZ13-NEXT: vfidb %v24, %v0, 0, 0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
Show All 9 Lines
; S390X-LABEL: constrained_vector_rint_v3f32: ; S390X-LABEL: constrained_vector_rint_v3f32:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI77_0 ; S390X-NEXT: larl %r1, .LCPI77_0
; S390X-NEXT: le %f0, 0(%r1) ; S390X-NEXT: le %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI77_1 ; S390X-NEXT: larl %r1, .LCPI77_1
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI77_2 ; S390X-NEXT: larl %r1, .LCPI77_2
; S390X-NEXT: le %f3, 0(%r1) ; S390X-NEXT: le %f3, 0(%r1)
; S390X-NEXT: fiebr %f0, 0, %f0 ; S390X-NEXT: fiebr %f4, 0, %f0
; S390X-NEXT: fiebr %f2, 0, %f1 ; S390X-NEXT: fiebr %f2, 0, %f1
; S390X-NEXT: fiebr %f4, 0, %f3 ; S390X-NEXT: fiebr %f0, 0, %f3
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_rint_v3f32: ; SZ13-LABEL: constrained_vector_rint_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI77_0 ; SZ13-NEXT: larl %r1, .LCPI77_0
; SZ13-NEXT: lde %f0, 0(%r1) ; SZ13-NEXT: lde %f0, 0(%r1)
; SZ13-NEXT: larl %r1, .LCPI77_1 ; SZ13-NEXT: larl %r1, .LCPI77_1
; SZ13-NEXT: lde %f1, 0(%r1) ; SZ13-NEXT: lde %f1, 0(%r1)
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
define <4 x double> @constrained_vector_rint_v4f64() #0 { define <4 x double> @constrained_vector_rint_v4f64() #0 {
; S390X-LABEL: constrained_vector_rint_v4f64: ; S390X-LABEL: constrained_vector_rint_v4f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI79_0 ; S390X-NEXT: larl %r1, .LCPI79_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI79_1 ; S390X-NEXT: larl %r1, .LCPI79_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI79_2 ; S390X-NEXT: larl %r1, .LCPI79_2
; S390X-NEXT: ld %f3, 0(%r1) ; S390X-NEXT: ld %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI79_3 ; S390X-NEXT: larl %r1, .LCPI79_3
; S390X-NEXT: ld %f5, 0(%r1) ; S390X-NEXT: ld %f3, 0(%r1)
; S390X-NEXT: fidbr %f0, 0, %f0 ; S390X-NEXT: fidbr %f6, 0, %f0
; S390X-NEXT: fidbr %f2, 0, %f1 ; S390X-NEXT: fidbr %f4, 0, %f1
; S390X-NEXT: fidbr %f4, 0, %f3 ; S390X-NEXT: fidbr %f2, 0, %f2
; S390X-NEXT: fidbr %f6, 0, %f5 ; S390X-NEXT: fidbr %f0, 0, %f3
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_rint_v4f64: ; SZ13-LABEL: constrained_vector_rint_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI79_0 ; SZ13-NEXT: larl %r1, .LCPI79_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
; SZ13-NEXT: larl %r1, .LCPI79_1 ; SZ13-NEXT: larl %r1, .LCPI79_1
; SZ13-NEXT: vfidb %v24, %v0, 0, 0 ; SZ13-NEXT: vfidb %v24, %v0, 0, 0
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; S390X-NEXT: stmg %r14, %r15, 112(%r15) ; S390X-NEXT: stmg %r14, %r15, 112(%r15)
; S390X-NEXT: .cfi_offset %r14, -48 ; S390X-NEXT: .cfi_offset %r14, -48
; S390X-NEXT: .cfi_offset %r15, -40 ; S390X-NEXT: .cfi_offset %r15, -40
; S390X-NEXT: aghi %r15, -168 ; S390X-NEXT: aghi %r15, -168
; S390X-NEXT: .cfi_def_cfa_offset 328 ; S390X-NEXT: .cfi_def_cfa_offset 328
; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: larl %r1, .LCPI81_0 ; S390X-NEXT: larl %r1, .LCPI81_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: brasl %r14, nearbyint@PLT ; S390X-NEXT: brasl %r14, nearbyint@PLT
; S390X-NEXT: larl %r1, .LCPI81_1 ; S390X-NEXT: larl %r1, .LCPI81_1
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, nearbyint@PLT ; S390X-NEXT: brasl %r14, nearbyint@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_nearbyint_v2f64: ; SZ13-LABEL: constrained_vector_nearbyint_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI81_0 ; SZ13-NEXT: larl %r1, .LCPI81_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
Show All 27 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, nearbyintf@PLT ; S390X-NEXT: brasl %r14, nearbyintf@PLT
; S390X-NEXT: larl %r1, .LCPI82_2 ; S390X-NEXT: larl %r1, .LCPI82_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, nearbyintf@PLT ; S390X-NEXT: brasl %r14, nearbyintf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_nearbyint_v3f32: ; SZ13-LABEL: constrained_vector_nearbyint_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI82_0 ; SZ13-NEXT: larl %r1, .LCPI82_0
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; S390X-NEXT: ldr %f9, %f0 ; S390X-NEXT: ldr %f9, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, nearbyint@PLT ; S390X-NEXT: brasl %r14, nearbyint@PLT
; S390X-NEXT: larl %r1, .LCPI84_3 ; S390X-NEXT: larl %r1, .LCPI84_3
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f10, %f0 ; S390X-NEXT: ldr %f10, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, nearbyint@PLT ; S390X-NEXT: brasl %r14, nearbyint@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f10
; S390X-NEXT: ldr %f0, %f8 ; S390X-NEXT: ldr %f4, %f9
; S390X-NEXT: ldr %f2, %f9 ; S390X-NEXT: ldr %f6, %f8
; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_nearbyint_v4f64: ; SZ13-LABEL: constrained_vector_nearbyint_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
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; S390X-NEXT: brasl %r14, fmax@PLT ; S390X-NEXT: brasl %r14, fmax@PLT
; S390X-NEXT: larl %r1, .LCPI86_2 ; S390X-NEXT: larl %r1, .LCPI86_2
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI86_3 ; S390X-NEXT: larl %r1, .LCPI86_3
; S390X-NEXT: ldeb %f2, 0(%r1) ; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, fmax@PLT ; S390X-NEXT: brasl %r14, fmax@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_maxnum_v2f64: ; SZ13-LABEL: constrained_vector_maxnum_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
; SZ13-NEXT: .cfi_offset %r14, -48 ; SZ13-NEXT: .cfi_offset %r14, -48
Show All 35 Lines
; S390X-NEXT: .cfi_def_cfa_offset 344 ; S390X-NEXT: .cfi_def_cfa_offset 344
; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: .cfi_offset %f9, -176 ; S390X-NEXT: .cfi_offset %f9, -176
; S390X-NEXT: .cfi_offset %f10, -184 ; S390X-NEXT: .cfi_offset %f10, -184
; S390X-NEXT: larl %r1, .LCPI87_0 ; S390X-NEXT: larl %r1, .LCPI87_0
; S390X-NEXT: le %f8, 0(%r1) ; S390X-NEXT: le %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI87_1 ; S390X-NEXT: larl %r1, .LCPI87_1
; S390X-NEXT: le %f2, 0(%r1) ; S390X-NEXT: le %f8, 0(%r1)
; S390X-NEXT: ler %f0, %f8 ; S390X-NEXT: ler %f2, %f8
; S390X-NEXT: brasl %r14, fmaxf@PLT ; S390X-NEXT: brasl %r14, fmaxf@PLT
; S390X-NEXT: larl %r1, .LCPI87_2 ; S390X-NEXT: larl %r1, .LCPI87_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI87_3 ; S390X-NEXT: larl %r1, .LCPI87_3
; S390X-NEXT: le %f2, 0(%r1) ; S390X-NEXT: le %f2, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, fmaxf@PLT ; S390X-NEXT: brasl %r14, fmaxf@PLT
; S390X-NEXT: larl %r1, .LCPI87_4 ; S390X-NEXT: larl %r1, .LCPI87_4
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f2, 0(%r1)
; S390X-NEXT: ler %f10, %f0 ; S390X-NEXT: ler %f10, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f8
; S390X-NEXT: brasl %r14, fmaxf@PLT ; S390X-NEXT: brasl %r14, fmaxf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f9
; S390X-NEXT: ler %f2, %f10 ; S390X-NEXT: ler %f2, %f10
; S390X-NEXT: ler %f4, %f9
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_maxnum_v3f32: ; SZ13-LABEL: constrained_vector_maxnum_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
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; S390X-NEXT: brasl %r14, fmax@PLT ; S390X-NEXT: brasl %r14, fmax@PLT
; S390X-NEXT: larl %r1, .LCPI89_6 ; S390X-NEXT: larl %r1, .LCPI89_6
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI89_7 ; S390X-NEXT: larl %r1, .LCPI89_7
; S390X-NEXT: ldeb %f2, 0(%r1) ; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: ldr %f10, %f0 ; S390X-NEXT: ldr %f10, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, fmax@PLT ; S390X-NEXT: brasl %r14, fmax@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f10
; S390X-NEXT: ldr %f0, %f8 ; S390X-NEXT: ldr %f4, %f9
; S390X-NEXT: ldr %f2, %f9 ; S390X-NEXT: ldr %f6, %f8
; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_maxnum_v4f64: ; SZ13-LABEL: constrained_vector_maxnum_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
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; S390X-NEXT: brasl %r14, fmin@PLT ; S390X-NEXT: brasl %r14, fmin@PLT
; S390X-NEXT: larl %r1, .LCPI91_2 ; S390X-NEXT: larl %r1, .LCPI91_2
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI91_3 ; S390X-NEXT: larl %r1, .LCPI91_3
; S390X-NEXT: ldeb %f2, 0(%r1) ; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, fmin@PLT ; S390X-NEXT: brasl %r14, fmin@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_minnum_v2f64: ; SZ13-LABEL: constrained_vector_minnum_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: stmg %r14, %r15, 112(%r15) ; SZ13-NEXT: stmg %r14, %r15, 112(%r15)
; SZ13-NEXT: .cfi_offset %r14, -48 ; SZ13-NEXT: .cfi_offset %r14, -48
Show All 35 Lines
; S390X-NEXT: .cfi_def_cfa_offset 344 ; S390X-NEXT: .cfi_def_cfa_offset 344
; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f8, 176(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f9, 168(%r15) # 8-byte Folded Spill
; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill ; S390X-NEXT: std %f10, 160(%r15) # 8-byte Folded Spill
; S390X-NEXT: .cfi_offset %f8, -168 ; S390X-NEXT: .cfi_offset %f8, -168
; S390X-NEXT: .cfi_offset %f9, -176 ; S390X-NEXT: .cfi_offset %f9, -176
; S390X-NEXT: .cfi_offset %f10, -184 ; S390X-NEXT: .cfi_offset %f10, -184
; S390X-NEXT: larl %r1, .LCPI92_0 ; S390X-NEXT: larl %r1, .LCPI92_0
; S390X-NEXT: le %f8, 0(%r1) ; S390X-NEXT: le %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI92_1 ; S390X-NEXT: larl %r1, .LCPI92_1
; S390X-NEXT: le %f2, 0(%r1) ; S390X-NEXT: le %f8, 0(%r1)
; S390X-NEXT: ler %f0, %f8 ; S390X-NEXT: ler %f2, %f8
; S390X-NEXT: brasl %r14, fminf@PLT ; S390X-NEXT: brasl %r14, fminf@PLT
; S390X-NEXT: larl %r1, .LCPI92_2 ; S390X-NEXT: larl %r1, .LCPI92_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI92_3 ; S390X-NEXT: larl %r1, .LCPI92_3
; S390X-NEXT: le %f2, 0(%r1) ; S390X-NEXT: le %f2, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, fminf@PLT ; S390X-NEXT: brasl %r14, fminf@PLT
; S390X-NEXT: larl %r1, .LCPI92_4 ; S390X-NEXT: larl %r1, .LCPI92_4
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f2, 0(%r1)
; S390X-NEXT: ler %f10, %f0 ; S390X-NEXT: ler %f10, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f8
; S390X-NEXT: brasl %r14, fminf@PLT ; S390X-NEXT: brasl %r14, fminf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f9
; S390X-NEXT: ler %f2, %f10 ; S390X-NEXT: ler %f2, %f10
; S390X-NEXT: ler %f4, %f9
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_minnum_v3f32: ; SZ13-LABEL: constrained_vector_minnum_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
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; S390X-NEXT: brasl %r14, fmin@PLT ; S390X-NEXT: brasl %r14, fmin@PLT
; S390X-NEXT: larl %r1, .LCPI94_6 ; S390X-NEXT: larl %r1, .LCPI94_6
; S390X-NEXT: ldeb %f1, 0(%r1) ; S390X-NEXT: ldeb %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI94_7 ; S390X-NEXT: larl %r1, .LCPI94_7
; S390X-NEXT: ldeb %f2, 0(%r1) ; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: ldr %f10, %f0 ; S390X-NEXT: ldr %f10, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, fmin@PLT ; S390X-NEXT: brasl %r14, fmin@PLT
; S390X-NEXT: ldr %f6, %f0 ; S390X-NEXT: ldr %f2, %f10
; S390X-NEXT: ldr %f0, %f8 ; S390X-NEXT: ldr %f4, %f9
; S390X-NEXT: ldr %f2, %f9 ; S390X-NEXT: ldr %f6, %f8
; S390X-NEXT: ldr %f4, %f10
; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 176(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f10, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 296(%r15) ; S390X-NEXT: lmg %r14, %r15, 296(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_minnum_v4f64: ; SZ13-LABEL: constrained_vector_minnum_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
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define <2 x float> @constrained_vector_fptrunc_v2f64() #0 { define <2 x float> @constrained_vector_fptrunc_v2f64() #0 {
; S390X-LABEL: constrained_vector_fptrunc_v2f64: ; S390X-LABEL: constrained_vector_fptrunc_v2f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI96_0 ; S390X-NEXT: larl %r1, .LCPI96_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI96_1 ; S390X-NEXT: larl %r1, .LCPI96_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ledbr %f0, %f0 ; S390X-NEXT: ledbr %f2, %f0
; S390X-NEXT: ledbr %f2, %f1 ; S390X-NEXT: ledbr %f0, %f1
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fptrunc_v2f64: ; SZ13-LABEL: constrained_vector_fptrunc_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI96_0 ; SZ13-NEXT: larl %r1, .LCPI96_0
; SZ13-NEXT: ld %f0, 0(%r1) ; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: larl %r1, .LCPI96_1 ; SZ13-NEXT: larl %r1, .LCPI96_1
; SZ13-NEXT: ld %f1, 0(%r1) ; SZ13-NEXT: ld %f1, 0(%r1)
▲ Show 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
define <4 x float> @constrained_vector_fptrunc_v4f64() #0 { define <4 x float> @constrained_vector_fptrunc_v4f64() #0 {
; S390X-LABEL: constrained_vector_fptrunc_v4f64: ; S390X-LABEL: constrained_vector_fptrunc_v4f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI98_0 ; S390X-NEXT: larl %r1, .LCPI98_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI98_1 ; S390X-NEXT: larl %r1, .LCPI98_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI98_2 ; S390X-NEXT: larl %r1, .LCPI98_2
; S390X-NEXT: ld %f3, 0(%r1) ; S390X-NEXT: ld %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI98_3 ; S390X-NEXT: larl %r1, .LCPI98_3
; S390X-NEXT: ld %f5, 0(%r1) ; S390X-NEXT: ld %f3, 0(%r1)
; S390X-NEXT: ledbr %f0, %f0 ; S390X-NEXT: ledbr %f6, %f0
; S390X-NEXT: ledbr %f2, %f1 ; S390X-NEXT: ledbr %f4, %f1
; S390X-NEXT: ledbr %f4, %f3 ; S390X-NEXT: ledbr %f2, %f2
; S390X-NEXT: ledbr %f6, %f5 ; S390X-NEXT: ledbr %f0, %f3
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fptrunc_v4f64: ; SZ13-LABEL: constrained_vector_fptrunc_v4f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI98_0 ; SZ13-NEXT: larl %r1, .LCPI98_0
; SZ13-NEXT: ld %f0, 0(%r1) ; SZ13-NEXT: ld %f0, 0(%r1)
; SZ13-NEXT: larl %r1, .LCPI98_1 ; SZ13-NEXT: larl %r1, .LCPI98_1
; SZ13-NEXT: ld %f1, 0(%r1) ; SZ13-NEXT: ld %f1, 0(%r1)
Show All 37 Lines %result = call <1 x double> @llvm.experimental.constrained.fpext.v1f64.v1f32(
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <1 x double> %result ret <1 x double> %result
} }
define <2 x double> @constrained_vector_fpext_v2f32() #0 { define <2 x double> @constrained_vector_fpext_v2f32() #0 {
; S390X-LABEL: constrained_vector_fpext_v2f32: ; S390X-LABEL: constrained_vector_fpext_v2f32:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI100_0 ; S390X-NEXT: larl %r1, .LCPI100_0
; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI100_1
; S390X-NEXT: ldeb %f2, 0(%r1) ; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI100_1
; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fpext_v2f32: ; SZ13-LABEL: constrained_vector_fpext_v2f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI100_0 ; SZ13-NEXT: larl %r1, .LCPI100_0
; SZ13-NEXT: ldeb %f0, 0(%r1) ; SZ13-NEXT: ldeb %f0, 0(%r1)
; SZ13-NEXT: larl %r1, .LCPI100_1 ; SZ13-NEXT: larl %r1, .LCPI100_1
; SZ13-NEXT: ldeb %f1, 0(%r1) ; SZ13-NEXT: ldeb %f1, 0(%r1)
; SZ13-NEXT: vmrhg %v24, %v1, %v0 ; SZ13-NEXT: vmrhg %v24, %v1, %v0
; SZ13-NEXT: br %r14 ; SZ13-NEXT: br %r14
entry: entry:
%result = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32( %result = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(
<2 x float><float 42.0, float 43.0>, <2 x float><float 42.0, float 43.0>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x double> %result ret <2 x double> %result
} }
define void @constrained_vector_fpext_v3f64(<3 x float>* %src, <3 x double>* %dest) #0 { define void @constrained_vector_fpext_v3f64(<3 x float>* %src, <3 x double>* %dest) #0 {
; S390X-LABEL: constrained_vector_fpext_v3f64: ; S390X-LABEL: constrained_vector_fpext_v3f64:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: lg %r0, 0(%r2) ; S390X-NEXT: lg %r0, 0(%r2)
; S390X-NEXT: sllg %r1, %r0, 32 ; S390X-NEXT: sllg %r1, %r0, 32
; S390X-NEXT: ldgr %f0, %r1 ; S390X-NEXT: ldgr %f0, %r1
; S390X-NEXT: nilf %r0, 0 ; S390X-NEXT: nilf %r0, 0
; S390X-NEXT: ldgr %f1, %r0 ; S390X-NEXT: ldeb %f1, 8(%r2)
; S390X-NEXT: ldeb %f2, 8(%r2) ; S390X-NEXT: ldgr %f2, %r0
; S390X-NEXT: ldebr %f1, %f1 ; S390X-NEXT: ldebr %f2, %f2
; S390X-NEXT: ldebr %f0, %f0 ; S390X-NEXT: ldebr %f0, %f0
; S390X-NEXT: std %f1, 16(%r3)
; S390X-NEXT: std %f0, 8(%r3) ; S390X-NEXT: std %f0, 8(%r3)
; S390X-NEXT: std %f2, 16(%r3) ; S390X-NEXT: std %f2, 0(%r3)
; S390X-NEXT: std %f1, 0(%r3)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fpext_v3f64: ; SZ13-LABEL: constrained_vector_fpext_v3f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: vl %v0, 0(%r2), 4 ; SZ13-NEXT: vl %v0, 0(%r2), 4
; SZ13-NEXT: vrepf %v1, %v0, 1 ; SZ13-NEXT: vrepf %v1, %v0, 1
; SZ13-NEXT: vldeb %v0, %v0 ; SZ13-NEXT: vldeb %v0, %v0
; SZ13-NEXT: ldebr %f1, %f1 ; SZ13-NEXT: ldebr %f1, %f1
Show All 9 Linesentry:
store <3 x double> %result, <3 x double>* %dest store <3 x double> %result, <3 x double>* %dest
ret void ret void
} }
define <4 x double> @constrained_vector_fpext_v4f32() #0 { define <4 x double> @constrained_vector_fpext_v4f32() #0 {
; S390X-LABEL: constrained_vector_fpext_v4f32: ; S390X-LABEL: constrained_vector_fpext_v4f32:
; S390X: # %bb.0: # %entry ; S390X: # %bb.0: # %entry
; S390X-NEXT: larl %r1, .LCPI102_0 ; S390X-NEXT: larl %r1, .LCPI102_0
; S390X-NEXT: ldeb %f0, 0(%r1) ; S390X-NEXT: ldeb %f6, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI102_1 ; S390X-NEXT: larl %r1, .LCPI102_1
; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI102_2
; S390X-NEXT: ldeb %f4, 0(%r1) ; S390X-NEXT: ldeb %f4, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI102_2
; S390X-NEXT: ldeb %f2, 0(%r1)
; S390X-NEXT: larl %r1, .LCPI102_3 ; S390X-NEXT: larl %r1, .LCPI102_3
; S390X-NEXT: ldeb %f6, 0(%r1) ; S390X-NEXT: ldeb %f0, 0(%r1)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_fpext_v4f32: ; SZ13-LABEL: constrained_vector_fpext_v4f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI102_0 ; SZ13-NEXT: larl %r1, .LCPI102_0
; SZ13-NEXT: ldeb %f0, 0(%r1) ; SZ13-NEXT: ldeb %f0, 0(%r1)
; SZ13-NEXT: larl %r1, .LCPI102_1 ; SZ13-NEXT: larl %r1, .LCPI102_1
; SZ13-NEXT: ldeb %f1, 0(%r1) ; SZ13-NEXT: ldeb %f1, 0(%r1)
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; S390X-NEXT: larl %r1, .LCPI104_0 ; S390X-NEXT: larl %r1, .LCPI104_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, ceil@PLT ; S390X-NEXT: brasl %r14, ceil@PLT
; S390X-NEXT: larl %r1, .LCPI104_1 ; S390X-NEXT: larl %r1, .LCPI104_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, ceil@PLT ; S390X-NEXT: brasl %r14, ceil@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_ceil_v2f64: ; SZ13-LABEL: constrained_vector_ceil_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI104_0 ; SZ13-NEXT: larl %r1, .LCPI104_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
Show All 26 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, ceilf@PLT ; S390X-NEXT: brasl %r14, ceilf@PLT
; S390X-NEXT: larl %r1, .LCPI105_2 ; S390X-NEXT: larl %r1, .LCPI105_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, ceilf@PLT ; S390X-NEXT: brasl %r14, ceilf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_ceil_v3f32: ; SZ13-LABEL: constrained_vector_ceil_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI105_0 ; SZ13-NEXT: larl %r1, .LCPI105_0
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; S390X-NEXT: larl %r1, .LCPI108_0 ; S390X-NEXT: larl %r1, .LCPI108_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, floor@PLT ; S390X-NEXT: brasl %r14, floor@PLT
; S390X-NEXT: larl %r1, .LCPI108_1 ; S390X-NEXT: larl %r1, .LCPI108_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, floor@PLT ; S390X-NEXT: brasl %r14, floor@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_floor_v2f64: ; SZ13-LABEL: constrained_vector_floor_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI108_0 ; SZ13-NEXT: larl %r1, .LCPI108_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
Show All 26 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, floorf@PLT ; S390X-NEXT: brasl %r14, floorf@PLT
; S390X-NEXT: larl %r1, .LCPI109_2 ; S390X-NEXT: larl %r1, .LCPI109_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, floorf@PLT ; S390X-NEXT: brasl %r14, floorf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_floor_v3f32: ; SZ13-LABEL: constrained_vector_floor_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI109_0 ; SZ13-NEXT: larl %r1, .LCPI109_0
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
; S390X-NEXT: larl %r1, .LCPI112_0 ; S390X-NEXT: larl %r1, .LCPI112_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, round@PLT ; S390X-NEXT: brasl %r14, round@PLT
; S390X-NEXT: larl %r1, .LCPI112_1 ; S390X-NEXT: larl %r1, .LCPI112_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, round@PLT ; S390X-NEXT: brasl %r14, round@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_round_v2f64: ; SZ13-LABEL: constrained_vector_round_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI112_0 ; SZ13-NEXT: larl %r1, .LCPI112_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
Show All 26 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, roundf@PLT ; S390X-NEXT: brasl %r14, roundf@PLT
; S390X-NEXT: larl %r1, .LCPI113_2 ; S390X-NEXT: larl %r1, .LCPI113_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, roundf@PLT ; S390X-NEXT: brasl %r14, roundf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_round_v3f32: ; SZ13-LABEL: constrained_vector_round_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI113_0 ; SZ13-NEXT: larl %r1, .LCPI113_0
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; S390X-NEXT: larl %r1, .LCPI116_0 ; S390X-NEXT: larl %r1, .LCPI116_0
; S390X-NEXT: ld %f0, 0(%r1) ; S390X-NEXT: ld %f0, 0(%r1)
; S390X-NEXT: brasl %r14, trunc@PLT ; S390X-NEXT: brasl %r14, trunc@PLT
; S390X-NEXT: larl %r1, .LCPI116_1 ; S390X-NEXT: larl %r1, .LCPI116_1
; S390X-NEXT: ld %f1, 0(%r1) ; S390X-NEXT: ld %f1, 0(%r1)
; S390X-NEXT: ldr %f8, %f0 ; S390X-NEXT: ldr %f8, %f0
; S390X-NEXT: ldr %f0, %f1 ; S390X-NEXT: ldr %f0, %f1
; S390X-NEXT: brasl %r14, trunc@PLT ; S390X-NEXT: brasl %r14, trunc@PLT
; S390X-NEXT: ldr %f2, %f0 ; S390X-NEXT: ldr %f2, %f8
; S390X-NEXT: ldr %f0, %f8
; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 280(%r15) ; S390X-NEXT: lmg %r14, %r15, 280(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_trunc_v2f64: ; SZ13-LABEL: constrained_vector_trunc_v2f64:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI116_0 ; SZ13-NEXT: larl %r1, .LCPI116_0
; SZ13-NEXT: vl %v0, 0(%r1), 3 ; SZ13-NEXT: vl %v0, 0(%r1), 3
Show All 26 Lines
; S390X-NEXT: ler %f8, %f0 ; S390X-NEXT: ler %f8, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, truncf@PLT ; S390X-NEXT: brasl %r14, truncf@PLT
; S390X-NEXT: larl %r1, .LCPI117_2 ; S390X-NEXT: larl %r1, .LCPI117_2
; S390X-NEXT: le %f1, 0(%r1) ; S390X-NEXT: le %f1, 0(%r1)
; S390X-NEXT: ler %f9, %f0 ; S390X-NEXT: ler %f9, %f0
; S390X-NEXT: ler %f0, %f1 ; S390X-NEXT: ler %f0, %f1
; S390X-NEXT: brasl %r14, truncf@PLT ; S390X-NEXT: brasl %r14, truncf@PLT
; S390X-NEXT: ler %f4, %f0
; S390X-NEXT: ler %f0, %f8
; S390X-NEXT: ler %f2, %f9 ; S390X-NEXT: ler %f2, %f9
; S390X-NEXT: ler %f4, %f8
; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f8, 168(%r15) # 8-byte Folded Reload
; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload ; S390X-NEXT: ld %f9, 160(%r15) # 8-byte Folded Reload
; S390X-NEXT: lmg %r14, %r15, 288(%r15) ; S390X-NEXT: lmg %r14, %r15, 288(%r15)
; S390X-NEXT: br %r14 ; S390X-NEXT: br %r14
; ;
; SZ13-LABEL: constrained_vector_trunc_v3f32: ; SZ13-LABEL: constrained_vector_trunc_v3f32:
; SZ13: # %bb.0: # %entry ; SZ13: # %bb.0: # %entry
; SZ13-NEXT: larl %r1, .LCPI117_0 ; SZ13-NEXT: larl %r1, .LCPI117_0
▲ Show 20 Lines • Show All 199 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/fp-intrinsics.ll

Show First 20 Lines • Show All 1,098 Lines • ▼ Show 20 Lines
; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl %eax, (%esp) ; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: calll __fixdfti ; X87-NEXT: calll __fixdfti
; X87-NEXT: subl $4, %esp ; X87-NEXT: subl $4, %esp
; X87-NEXT: movl {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X87-NEXT: movl %edi, 12(%esi) ; X87-NEXT: movl %edi, 8(%esi)
; X87-NEXT: movl %edx, 8(%esi) ; X87-NEXT: movl %edx, 12(%esi)
; X87-NEXT: movl %ecx, 4(%esi)
; X87-NEXT: movl %eax, (%esi) ; X87-NEXT: movl %eax, (%esi)
; X87-NEXT: movl %ecx, 4(%esi)
; X87-NEXT: movl %esi, %eax ; X87-NEXT: movl %esi, %eax
; X87-NEXT: addl $36, %esp ; X87-NEXT: addl $36, %esp
; X87-NEXT: popl %esi ; X87-NEXT: popl %esi
; X87-NEXT: popl %edi ; X87-NEXT: popl %edi
; X87-NEXT: retl $4 ; X87-NEXT: retl $4
; ;
; X86-SSE-LABEL: f20s128: ; X86-SSE-LABEL: f20s128:
; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: pushl %edi ; X86-SSE-NEXT: pushl %edi
; X86-SSE-NEXT: pushl %esi ; X86-SSE-NEXT: pushl %esi
; X86-SSE-NEXT: subl $36, %esp ; X86-SSE-NEXT: subl $36, %esp
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %eax, (%esp) ; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: calll __fixdfti ; X86-SSE-NEXT: calll __fixdfti
; X86-SSE-NEXT: subl $4, %esp ; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: movl %edi, 12(%esi) ; X86-SSE-NEXT: movl %edi, 8(%esi)
; X86-SSE-NEXT: movl %edx, 8(%esi) ; X86-SSE-NEXT: movl %edx, 12(%esi)
; X86-SSE-NEXT: movl %ecx, 4(%esi)
; X86-SSE-NEXT: movl %eax, (%esi) ; X86-SSE-NEXT: movl %eax, (%esi)
; X86-SSE-NEXT: movl %ecx, 4(%esi)
; X86-SSE-NEXT: movl %esi, %eax ; X86-SSE-NEXT: movl %esi, %eax
; X86-SSE-NEXT: addl $36, %esp ; X86-SSE-NEXT: addl $36, %esp
; X86-SSE-NEXT: popl %esi ; X86-SSE-NEXT: popl %esi
; X86-SSE-NEXT: popl %edi ; X86-SSE-NEXT: popl %edi
; X86-SSE-NEXT: retl $4 ; X86-SSE-NEXT: retl $4
; ;
; SSE-LABEL: f20s128: ; SSE-LABEL: f20s128:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
▲ Show 20 Lines • Show All 293 Lines • ▼ Show 20 Lines
; X87-NEXT: leal {{[0-9]+}}(%esp), %eax ; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl %eax, (%esp) ; X87-NEXT: movl %eax, (%esp)
; X87-NEXT: calll __fixunsdfti ; X87-NEXT: calll __fixunsdfti
; X87-NEXT: subl $4, %esp ; X87-NEXT: subl $4, %esp
; X87-NEXT: movl {{[0-9]+}}(%esp), %eax ; X87-NEXT: movl {{[0-9]+}}(%esp), %eax
; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X87-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X87-NEXT: movl {{[0-9]+}}(%esp), %edx ; X87-NEXT: movl {{[0-9]+}}(%esp), %edx
; X87-NEXT: movl {{[0-9]+}}(%esp), %edi ; X87-NEXT: movl {{[0-9]+}}(%esp), %edi
; X87-NEXT: movl %edi, 12(%esi) ; X87-NEXT: movl %edi, 8(%esi)
; X87-NEXT: movl %edx, 8(%esi) ; X87-NEXT: movl %edx, 12(%esi)
; X87-NEXT: movl %ecx, 4(%esi)
; X87-NEXT: movl %eax, (%esi) ; X87-NEXT: movl %eax, (%esi)
; X87-NEXT: movl %ecx, 4(%esi)
; X87-NEXT: movl %esi, %eax ; X87-NEXT: movl %esi, %eax
; X87-NEXT: addl $36, %esp ; X87-NEXT: addl $36, %esp
; X87-NEXT: popl %esi ; X87-NEXT: popl %esi
; X87-NEXT: popl %edi ; X87-NEXT: popl %edi
; X87-NEXT: retl $4 ; X87-NEXT: retl $4
; ;
; X86-SSE-LABEL: f20u128: ; X86-SSE-LABEL: f20u128:
; X86-SSE: # %bb.0: # %entry ; X86-SSE: # %bb.0: # %entry
; X86-SSE-NEXT: pushl %edi ; X86-SSE-NEXT: pushl %edi
; X86-SSE-NEXT: pushl %esi ; X86-SSE-NEXT: pushl %esi
; X86-SSE-NEXT: subl $36, %esp ; X86-SSE-NEXT: subl $36, %esp
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp) ; X86-SSE-NEXT: movsd %xmm0, {{[0-9]+}}(%esp)
; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl %eax, (%esp) ; X86-SSE-NEXT: movl %eax, (%esp)
; X86-SSE-NEXT: calll __fixunsdfti ; X86-SSE-NEXT: calll __fixunsdfti
; X86-SSE-NEXT: subl $4, %esp ; X86-SSE-NEXT: subl $4, %esp
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-SSE-NEXT: movl %edi, 12(%esi) ; X86-SSE-NEXT: movl %edi, 8(%esi)
; X86-SSE-NEXT: movl %edx, 8(%esi) ; X86-SSE-NEXT: movl %edx, 12(%esi)
; X86-SSE-NEXT: movl %ecx, 4(%esi)
; X86-SSE-NEXT: movl %eax, (%esi) ; X86-SSE-NEXT: movl %eax, (%esi)
; X86-SSE-NEXT: movl %ecx, 4(%esi)
; X86-SSE-NEXT: movl %esi, %eax ; X86-SSE-NEXT: movl %esi, %eax
; X86-SSE-NEXT: addl $36, %esp ; X86-SSE-NEXT: addl $36, %esp
; X86-SSE-NEXT: popl %esi ; X86-SSE-NEXT: popl %esi
; X86-SSE-NEXT: popl %edi ; X86-SSE-NEXT: popl %edi
; X86-SSE-NEXT: retl $4 ; X86-SSE-NEXT: retl $4
; ;
; SSE-LABEL: f20u128: ; SSE-LABEL: f20u128:
; SSE: # %bb.0: # %entry ; SSE: # %bb.0: # %entry
▲ Show 20 Lines • Show All 1,260 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/fp128-cast-strict.ll

Show First 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, (%esp) ; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: calll __extendsftf2 ; X86-NEXT: calll __extendsftf2
; X86-NEXT: subl $4, %esp ; X86-NEXT: subl $4, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %esi, vf128+8 ; X86-NEXT: movl %esi, vf128+12
; X86-NEXT: movl %edx, vf128+12 ; X86-NEXT: movl %edx, vf128+8
; X86-NEXT: movl %eax, vf128
; X86-NEXT: movl %ecx, vf128+4 ; X86-NEXT: movl %ecx, vf128+4
; X86-NEXT: movl %eax, vf128
; X86-NEXT: addl $24, %esp ; X86-NEXT: addl $24, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: retl ; X86-NEXT: retl
entry: entry:
%0 = load float, float* @vf32, align 4 %0 = load float, float* @vf32, align 4
%conv = call fp128 @llvm.experimental.constrained.fpext.f128.f32(float %0, metadata !"fpexcept.strict") #0 %conv = call fp128 @llvm.experimental.constrained.fpext.f128.f32(float %0, metadata !"fpexcept.strict") #0
store fp128 %conv, fp128* @vf128, align 16 store fp128 %conv, fp128* @vf128, align 16
ret void ret void
Show All 27 Lines
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, (%esp) ; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: calll __extenddftf2 ; X86-NEXT: calll __extenddftf2
; X86-NEXT: subl $4, %esp ; X86-NEXT: subl $4, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %esi, vf128+8 ; X86-NEXT: movl %esi, vf128+12
; X86-NEXT: movl %edx, vf128+12 ; X86-NEXT: movl %edx, vf128+8
; X86-NEXT: movl %eax, vf128
; X86-NEXT: movl %ecx, vf128+4 ; X86-NEXT: movl %ecx, vf128+4
; X86-NEXT: movl %eax, vf128
; X86-NEXT: addl $40, %esp ; X86-NEXT: addl $40, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: retl ; X86-NEXT: retl
entry: entry:
%0 = load double, double* @vf64, align 8 %0 = load double, double* @vf64, align 8
%conv = call fp128 @llvm.experimental.constrained.fpext.f128.f64(double %0, metadata !"fpexcept.strict") #0 %conv = call fp128 @llvm.experimental.constrained.fpext.f128.f64(double %0, metadata !"fpexcept.strict") #0
store fp128 %conv, fp128* @vf128, align 16 store fp128 %conv, fp128* @vf128, align 16
ret void ret void
Show All 29 Lines
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax ; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl %eax, (%esp) ; X86-NEXT: movl %eax, (%esp)
; X86-NEXT: calll __extendxftf2 ; X86-NEXT: calll __extendxftf2
; X86-NEXT: subl $4, %esp ; X86-NEXT: subl $4, %esp
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-NEXT: movl %esi, vf128+8 ; X86-NEXT: movl %esi, vf128+12
; X86-NEXT: movl %edx, vf128+12 ; X86-NEXT: movl %edx, vf128+8
; X86-NEXT: movl %eax, vf128
; X86-NEXT: movl %ecx, vf128+4 ; X86-NEXT: movl %ecx, vf128+4
; X86-NEXT: movl %eax, vf128
; X86-NEXT: addl $40, %esp ; X86-NEXT: addl $40, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: retl ; X86-NEXT: retl
entry: entry:
%0 = load x86_fp80, x86_fp80* @vf80, align 8 %0 = load x86_fp80, x86_fp80* @vf80, align 8
%conv = call fp128 @llvm.experimental.constrained.fpext.f128.f80(x86_fp80 %0, metadata !"fpexcept.strict") #0 %conv = call fp128 @llvm.experimental.constrained.fpext.f128.f80(x86_fp80 %0, metadata !"fpexcept.strict") #0
store fp128 %conv, fp128* @vf128, align 16 store fp128 %conv, fp128* @vf128, align 16
ret void ret void
▲ Show 20 Lines • Show All 233 Lines • ▼ Show 20 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll __fixtfti ; X86-NEXT: calll __fixtfti
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%conv = call i128 @llvm.experimental.constrained.fptosi.i128.f128(fp128 %x, metadata !"fpexcept.strict") #0 %conv = call i128 @llvm.experimental.constrained.fptosi.i128.f128(fp128 %x, metadata !"fpexcept.strict") #0
ret i128 %conv ret i128 %conv
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll __fixunstfti ; X86-NEXT: calll __fixunstfti
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%conv = call i128 @llvm.experimental.constrained.fptoui.i128.f128(fp128 %x, metadata !"fpexcept.strict") #0 %conv = call i128 @llvm.experimental.constrained.fptoui.i128.f128(fp128 %x, metadata !"fpexcept.strict") #0
ret i128 %conv ret i128 %conv
Show All 20 Lines

llvm/test/CodeGen/X86/fp128-libcalls-strict.ll

Show All 36 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll __addtf3 ; X86-NEXT: calll __addtf3
; X86-NEXT: addl $44, %esp ; X86-NEXT: addl $44, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%add = call fp128 @llvm.experimental.constrained.fadd.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %add = call fp128 @llvm.experimental.constrained.fadd.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %add ret fp128 %add
Show All 25 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll __subtf3 ; X86-NEXT: calll __subtf3
; X86-NEXT: addl $44, %esp ; X86-NEXT: addl $44, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%sub = call fp128 @llvm.experimental.constrained.fsub.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %sub = call fp128 @llvm.experimental.constrained.fsub.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %sub ret fp128 %sub
Show All 25 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll __multf3 ; X86-NEXT: calll __multf3
; X86-NEXT: addl $44, %esp ; X86-NEXT: addl $44, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%mul = call fp128 @llvm.experimental.constrained.fmul.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %mul = call fp128 @llvm.experimental.constrained.fmul.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %mul ret fp128 %mul
Show All 25 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll __divtf3 ; X86-NEXT: calll __divtf3
; X86-NEXT: addl $44, %esp ; X86-NEXT: addl $44, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%div = call fp128 @llvm.experimental.constrained.fdiv.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %div = call fp128 @llvm.experimental.constrained.fdiv.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %div ret fp128 %div
Show All 29 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll fmal ; X86-NEXT: calll fmal
; X86-NEXT: addl $60, %esp ; X86-NEXT: addl $60, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%fma = call fp128 @llvm.experimental.constrained.fma.f128(fp128 %x, fp128 %y, fp128 %z, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %fma = call fp128 @llvm.experimental.constrained.fma.f128(fp128 %x, fp128 %y, fp128 %z, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %fma ret fp128 %fma
Show All 25 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll fmodl ; X86-NEXT: calll fmodl
; X86-NEXT: addl $44, %esp ; X86-NEXT: addl $44, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%div = call fp128 @llvm.experimental.constrained.frem.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %div = call fp128 @llvm.experimental.constrained.frem.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %div ret fp128 %div
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll ceill ; X86-NEXT: calll ceill
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%ceil = call fp128 @llvm.experimental.constrained.ceil.f128(fp128 %x, metadata !"fpexcept.strict") #0 %ceil = call fp128 @llvm.experimental.constrained.ceil.f128(fp128 %x, metadata !"fpexcept.strict") #0
ret fp128 %ceil ret fp128 %ceil
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll cosl ; X86-NEXT: calll cosl
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%cos = call fp128 @llvm.experimental.constrained.cos.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %cos = call fp128 @llvm.experimental.constrained.cos.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %cos ret fp128 %cos
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll expl ; X86-NEXT: calll expl
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%exp = call fp128 @llvm.experimental.constrained.exp.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %exp = call fp128 @llvm.experimental.constrained.exp.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %exp ret fp128 %exp
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll exp2l ; X86-NEXT: calll exp2l
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%exp2 = call fp128 @llvm.experimental.constrained.exp2.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %exp2 = call fp128 @llvm.experimental.constrained.exp2.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %exp2 ret fp128 %exp2
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll floorl ; X86-NEXT: calll floorl
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%floor = call fp128 @llvm.experimental.constrained.floor.f128(fp128 %x, metadata !"fpexcept.strict") #0 %floor = call fp128 @llvm.experimental.constrained.floor.f128(fp128 %x, metadata !"fpexcept.strict") #0
ret fp128 %floor ret fp128 %floor
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll logl ; X86-NEXT: calll logl
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%log = call fp128 @llvm.experimental.constrained.log.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %log = call fp128 @llvm.experimental.constrained.log.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %log ret fp128 %log
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll log10l ; X86-NEXT: calll log10l
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%log10 = call fp128 @llvm.experimental.constrained.log10.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %log10 = call fp128 @llvm.experimental.constrained.log10.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %log10 ret fp128 %log10
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll log2l ; X86-NEXT: calll log2l
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%log2 = call fp128 @llvm.experimental.constrained.log2.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %log2 = call fp128 @llvm.experimental.constrained.log2.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %log2 ret fp128 %log2
Show All 25 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll fmaxl ; X86-NEXT: calll fmaxl
; X86-NEXT: addl $44, %esp ; X86-NEXT: addl $44, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%maxnum = call fp128 @llvm.experimental.constrained.maxnum.f128(fp128 %x, fp128 %y, metadata !"fpexcept.strict") #0 %maxnum = call fp128 @llvm.experimental.constrained.maxnum.f128(fp128 %x, fp128 %y, metadata !"fpexcept.strict") #0
ret fp128 %maxnum ret fp128 %maxnum
Show All 25 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll fminl ; X86-NEXT: calll fminl
; X86-NEXT: addl $44, %esp ; X86-NEXT: addl $44, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%minnum = call fp128 @llvm.experimental.constrained.minnum.f128(fp128 %x, fp128 %y, metadata !"fpexcept.strict") #0 %minnum = call fp128 @llvm.experimental.constrained.minnum.f128(fp128 %x, fp128 %y, metadata !"fpexcept.strict") #0
ret fp128 %minnum ret fp128 %minnum
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll nearbyintl ; X86-NEXT: calll nearbyintl
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%nearbyint = call fp128 @llvm.experimental.constrained.nearbyint.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %nearbyint = call fp128 @llvm.experimental.constrained.nearbyint.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %nearbyint ret fp128 %nearbyint
Show All 25 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll powl ; X86-NEXT: calll powl
; X86-NEXT: addl $44, %esp ; X86-NEXT: addl $44, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%pow = call fp128 @llvm.experimental.constrained.pow.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %pow = call fp128 @llvm.experimental.constrained.pow.f128(fp128 %x, fp128 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %pow ret fp128 %pow
Show All 22 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll __powitf2 ; X86-NEXT: calll __powitf2
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%powi = call fp128 @llvm.experimental.constrained.powi.f128(fp128 %x, i32 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %powi = call fp128 @llvm.experimental.constrained.powi.f128(fp128 %x, i32 %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %powi ret fp128 %powi
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll rintl ; X86-NEXT: calll rintl
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%rint = call fp128 @llvm.experimental.constrained.rint.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %rint = call fp128 @llvm.experimental.constrained.rint.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %rint ret fp128 %rint
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll roundl ; X86-NEXT: calll roundl
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%round = call fp128 @llvm.experimental.constrained.round.f128(fp128 %x, metadata !"fpexcept.strict") #0 %round = call fp128 @llvm.experimental.constrained.round.f128(fp128 %x, metadata !"fpexcept.strict") #0
ret fp128 %round ret fp128 %round
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll sinl ; X86-NEXT: calll sinl
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%sin = call fp128 @llvm.experimental.constrained.sin.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %sin = call fp128 @llvm.experimental.constrained.sin.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %sin ret fp128 %sin
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll sqrtl ; X86-NEXT: calll sqrtl
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%sqrt = call fp128 @llvm.experimental.constrained.sqrt.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 %sqrt = call fp128 @llvm.experimental.constrained.sqrt.f128(fp128 %x, metadata !"round.dynamic", metadata !"fpexcept.strict") #0
ret fp128 %sqrt ret fp128 %sqrt
Show All 21 Lines
; X86-NEXT: pushl {{[0-9]+}}(%esp) ; X86-NEXT: pushl {{[0-9]+}}(%esp)
; X86-NEXT: pushl %eax ; X86-NEXT: pushl %eax
; X86-NEXT: calll truncl ; X86-NEXT: calll truncl
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: movl (%esp), %eax ; X86-NEXT: movl (%esp), %eax
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-NEXT: movl %edi, 12(%esi) ; X86-NEXT: movl %edi, 8(%esi)
; X86-NEXT: movl %edx, 8(%esi) ; X86-NEXT: movl %edx, 12(%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %eax, (%esi) ; X86-NEXT: movl %eax, (%esi)
; X86-NEXT: movl %ecx, 4(%esi)
; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl %esi, %eax
; X86-NEXT: addl $20, %esp ; X86-NEXT: addl $20, %esp
; X86-NEXT: popl %esi ; X86-NEXT: popl %esi
; X86-NEXT: popl %edi ; X86-NEXT: popl %edi
; X86-NEXT: retl $4 ; X86-NEXT: retl $4
entry: entry:
%trunc = call fp128 @llvm.experimental.constrained.trunc.f128(fp128 %x, metadata !"fpexcept.strict") #0 %trunc = call fp128 @llvm.experimental.constrained.trunc.f128(fp128 %x, metadata !"fpexcept.strict") #0
ret fp128 %trunc ret fp128 %trunc
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; X86-NEXT: calll llroundl ; X86-NEXT: calll llroundl
; X86-NEXT: addl $28, %esp ; X86-NEXT: addl $28, %esp
; X86-NEXT: retl ; X86-NEXT: retl
entry: entry:
%round = call i64 @llvm.experimental.constrained.llround.i64.f128(fp128 %x, metadata !"fpexcept.strict") #0 %round = call i64 @llvm.experimental.constrained.llround.i64.f128(fp128 %x, metadata !"fpexcept.strict") #0
ret i64 %round ret i64 %round
} }
attributes #0 = { strictfp } attributes #0 = { strictfp }
craig.topperUnsubmitted
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This looks like a bug of some sort. I'll see if I can track it down.

craig.topper: This looks like a bug of some sort. I'll see if I can track it down.
craig.topperUnsubmitted
Done
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I think I've fixed this or at least hacked around it for now. Can you rebase this?

craig.topper: I think I've fixed this or at least hacked around it for now. Can you rebase this?
declare fp128 @llvm.experimental.constrained.fadd.f128(fp128, fp128, metadata, metadata) declare fp128 @llvm.experimental.constrained.fadd.f128(fp128, fp128, metadata, metadata)
declare fp128 @llvm.experimental.constrained.fsub.f128(fp128, fp128, metadata, metadata) declare fp128 @llvm.experimental.constrained.fsub.f128(fp128, fp128, metadata, metadata)
declare fp128 @llvm.experimental.constrained.fmul.f128(fp128, fp128, metadata, metadata) declare fp128 @llvm.experimental.constrained.fmul.f128(fp128, fp128, metadata, metadata)
declare fp128 @llvm.experimental.constrained.fdiv.f128(fp128, fp128, metadata, metadata) declare fp128 @llvm.experimental.constrained.fdiv.f128(fp128, fp128, metadata, metadata)
declare fp128 @llvm.experimental.constrained.fma.f128(fp128, fp128, fp128, metadata, metadata) declare fp128 @llvm.experimental.constrained.fma.f128(fp128, fp128, fp128, metadata, metadata)
declare fp128 @llvm.experimental.constrained.frem.f128(fp128, fp128, metadata, metadata) declare fp128 @llvm.experimental.constrained.frem.f128(fp128, fp128, metadata, metadata)
declare fp128 @llvm.experimental.constrained.ceil.f128(fp128, metadata) declare fp128 @llvm.experimental.constrained.ceil.f128(fp128, metadata)
Show All 21 Lines

llvm/test/CodeGen/X86/vec-strict-inttofp-256.ll

Show First 20 Lines • Show All 1,042 Lines • ▼ Show 20 Lines
; ;
; AVX1-64-LABEL: uitofp_v4i64_v4f32: ; AVX1-64-LABEL: uitofp_v4i64_v4f32:
; AVX1-64: # %bb.0: ; AVX1-64: # %bb.0:
; AVX1-64-NEXT: vpsrlq $1, %xmm0, %xmm1 ; AVX1-64-NEXT: vpsrlq $1, %xmm0, %xmm1
; AVX1-64-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-64-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-64-NEXT: vpsrlq $1, %xmm2, %xmm3 ; AVX1-64-NEXT: vpsrlq $1, %xmm2, %xmm3
; AVX1-64-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 ; AVX1-64-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
; AVX1-64-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3 ; AVX1-64-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3
; AVX1-64-NEXT: vorpd %ymm3, %ymm1, %ymm1 ; AVX1-64-NEXT: vorpd %ymm3, %ymm1, %ymm3
; AVX1-64-NEXT: vblendvpd %xmm0, %xmm1, %xmm0, %xmm3 ; AVX1-64-NEXT: vblendvpd %xmm0, %xmm3, %xmm0, %xmm1
; AVX1-64-NEXT: vpextrq $1, %xmm3, %rax ; AVX1-64-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 ; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4
; AVX1-64-NEXT: vmovq %xmm3, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[2,3]
; AVX1-64-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-64-NEXT: vblendvpd %xmm2, %xmm1, %xmm2, %xmm1
; AVX1-64-NEXT: vmovq %xmm1, %rax ; AVX1-64-NEXT: vmovq %xmm1, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3]
; AVX1-64-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0] ; AVX1-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[2,3]
; AVX1-64-NEXT: vaddps %xmm1, %xmm1, %xmm3 ; AVX1-64-NEXT: vextractf128 $1, %ymm3, %xmm4
; AVX1-64-NEXT: vxorps %xmm4, %xmm4, %xmm4 ; AVX1-64-NEXT: vblendvpd %xmm2, %xmm4, %xmm2, %xmm4
; AVX1-64-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm2 ; AVX1-64-NEXT: vmovq %xmm4, %rax
; AVX1-64-NEXT: vpackssdw %xmm2, %xmm0, %xmm0 ; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm5, %xmm5
; AVX1-64-NEXT: vblendvps %xmm0, %xmm3, %xmm1, %xmm0 ; AVX1-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm5[0],xmm1[3]
; AVX1-64-NEXT: vpextrq $1, %xmm4, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm6, %xmm4
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
; AVX1-64-NEXT: vaddps %xmm1, %xmm1, %xmm4
; AVX1-64-NEXT: vxorps %xmm5, %xmm5, %xmm5
; AVX1-64-NEXT: vpcmpgtq %xmm2, %xmm5, %xmm2
; AVX1-64-NEXT: vpackssdw %xmm2, %xmm0, %xmm2
; AVX1-64-NEXT: vblendvps %xmm2, %xmm4, %xmm1, %xmm1
; AVX1-64-NEXT: vblendvpd %ymm0, %ymm3, %ymm0, %ymm0
; AVX1-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm6, %xmm2
; AVX1-64-NEXT: vmovq %xmm0, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm6, %xmm3
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX1-64-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-64-NEXT: vmovq %xmm0, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm6, %xmm3
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX1-64-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-64-NEXT: vcvtsi2ss %rax, %xmm6, %xmm0
; AVX1-64-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX1-64-NEXT: vaddps %xmm0, %xmm0, %xmm0
; AVX1-64-NEXT: vmovaps %xmm1, %xmm0
; AVX1-64-NEXT: vzeroupper ; AVX1-64-NEXT: vzeroupper
; AVX1-64-NEXT: retq ; AVX1-64-NEXT: retq
; ;
; AVX2-64-LABEL: uitofp_v4i64_v4f32: ; AVX2-64-LABEL: uitofp_v4i64_v4f32:
; AVX2-64: # %bb.0: ; AVX2-64: # %bb.0:
; AVX2-64-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX2-64-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX2-64-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm1 ; AVX2-64-NEXT: vpcmpgtq %ymm0, %ymm1, %ymm1
; AVX2-64-NEXT: vextracti128 $1, %ymm1, %xmm2 ; AVX2-64-NEXT: vextracti128 $1, %ymm1, %xmm2
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines

llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics-flags.ll

Show All 34 Linesentry:
ret <3 x float> %add ret <3 x float> %add
} }
define <4 x double> @constrained_vector_fadd_v4f64() #0 { define <4 x double> @constrained_vector_fadd_v4f64() #0 {
; CHECK-LABEL: name: constrained_vector_fadd_v4f64 ; CHECK-LABEL: name: constrained_vector_fadd_v4f64
; CHECK: [[MOVAPDrm:%[0-9]+]]:vr128 = MOVAPDrm $rip, 1, $noreg, %const.0, $noreg :: (load 16 from constant-pool) ; CHECK: [[MOVAPDrm:%[0-9]+]]:vr128 = MOVAPDrm $rip, 1, $noreg, %const.0, $noreg :: (load 16 from constant-pool)
; CHECK: [[ADDPDrm:%[0-9]+]]:vr128 = fpexcept ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 16 from constant-pool) ; CHECK: [[ADDPDrm:%[0-9]+]]:vr128 = fpexcept ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.1, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
; CHECK: [[ADDPDrm1:%[0-9]+]]:vr128 = fpexcept ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 16 from constant-pool) ; CHECK: [[ADDPDrm1:%[0-9]+]]:vr128 = fpexcept ADDPDrm [[MOVAPDrm]], $rip, 1, $noreg, %const.2, $noreg, implicit $mxcsr :: (load 16 from constant-pool)
; CHECK: $xmm0 = COPY [[ADDPDrm]] ; CHECK: $xmm0 = COPY [[ADDPDrm1]]
; CHECK: $xmm1 = COPY [[ADDPDrm1]] ; CHECK: $xmm1 = COPY [[ADDPDrm]]
; CHECK: RET 0, $xmm0, $xmm1 ; CHECK: RET 0, $xmm0, $xmm1
entry: entry:
%add = call <4 x double> @llvm.experimental.constrained.fadd.v4f64( %add = call <4 x double> @llvm.experimental.constrained.fadd.v4f64(
<4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF, <4 x double> <double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF,
double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>, double 0x7FEFFFFFFFFFFFFF, double 0x7FEFFFFFFFFFFFFF>,
<4 x double> <double 1.000000e+00, double 1.000000e-01, <4 x double> <double 1.000000e+00, double 1.000000e-01,
double 2.000000e+00, double 2.000000e-01>, double 2.000000e+00, double 2.000000e-01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x double> %add ret <4 x double> %add
} }
declare <1 x float> @llvm.experimental.constrained.fadd.v1f32(<1 x float>, <1 x float>, metadata, metadata) declare <1 x float> @llvm.experimental.constrained.fadd.v1f32(<1 x float>, <1 x float>, metadata, metadata)
declare <3 x float> @llvm.experimental.constrained.fadd.v3f32(<3 x float>, <3 x float>, metadata, metadata) declare <3 x float> @llvm.experimental.constrained.fadd.v3f32(<3 x float>, <3 x float>, metadata, metadata)
declare <4 x double> @llvm.experimental.constrained.fadd.v4f64(<4 x double>, <4 x double>, metadata, metadata) declare <4 x double> @llvm.experimental.constrained.fadd.v4f64(<4 x double>, <4 x double>, metadata, metadata)

llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines %div = call <3 x double> @llvm.experimental.constrained.fdiv.v3f64(
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x double> %div ret <3 x double> %div
} }
define <4 x double> @constrained_vector_fdiv_v4f64() #0 { define <4 x double> @constrained_vector_fdiv_v4f64() #0 {
; CHECK-LABEL: constrained_vector_fdiv_v4f64: ; CHECK-LABEL: constrained_vector_fdiv_v4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movapd {{.*#+}} xmm2 = [1.0E+1,1.0E+1] ; CHECK-NEXT: movapd {{.*#+}} xmm2 = [1.0E+1,1.0E+1]
; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.0E+0,2.0E+0]
; CHECK-NEXT: divpd %xmm2, %xmm0
; CHECK-NEXT: movapd {{.*#+}} xmm1 = [3.0E+0,4.0E+0] ; CHECK-NEXT: movapd {{.*#+}} xmm1 = [3.0E+0,4.0E+0]
; CHECK-NEXT: divpd %xmm2, %xmm1 ; CHECK-NEXT: divpd %xmm2, %xmm1
; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.0E+0,2.0E+0]
; CHECK-NEXT: divpd %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_fdiv_v4f64: ; AVX1-LABEL: constrained_vector_fdiv_v4f64:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0] ; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
; AVX1-NEXT: vdivpd {{.*}}(%rip), %ymm0, %ymm0 ; AVX1-NEXT: vdivpd {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
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; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: callq fmod ; CHECK-NEXT: callq fmod
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: callq fmod ; CHECK-NEXT: callq fmod
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_frem_v3f64: ; AVX-LABEL: constrained_vector_frem_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
▲ Show 20 Lines • Show All 196 Lines • ▼ Show 20 Lines %mul = call <3 x double> @llvm.experimental.constrained.fmul.v3f64(
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x double> %mul ret <3 x double> %mul
} }
define <4 x double> @constrained_vector_fmul_v4f64() #0 { define <4 x double> @constrained_vector_fmul_v4f64() #0 {
; CHECK-LABEL: constrained_vector_fmul_v4f64: ; CHECK-LABEL: constrained_vector_fmul_v4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movapd {{.*#+}} xmm1 = [1.7976931348623157E+308,1.7976931348623157E+308] ; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
; CHECK-NEXT: movapd {{.*#+}} xmm0 = [2.0E+0,3.0E+0] ; CHECK-NEXT: movapd {{.*#+}} xmm1 = [4.0E+0,5.0E+0]
; CHECK-NEXT: mulpd %xmm1, %xmm0 ; CHECK-NEXT: mulpd %xmm0, %xmm1
; CHECK-NEXT: mulpd {{.*}}(%rip), %xmm1 ; CHECK-NEXT: mulpd {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_fmul_v4f64: ; AVX1-LABEL: constrained_vector_fmul_v4f64:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308] ; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308]
; AVX1-NEXT: vmulpd {{.*}}(%rip), %ymm0, %ymm0 ; AVX1-NEXT: vmulpd {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines %add = call <3 x double> @llvm.experimental.constrained.fadd.v3f64(
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x double> %add ret <3 x double> %add
} }
define <4 x double> @constrained_vector_fadd_v4f64() #0 { define <4 x double> @constrained_vector_fadd_v4f64() #0 {
; CHECK-LABEL: constrained_vector_fadd_v4f64: ; CHECK-LABEL: constrained_vector_fadd_v4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movapd {{.*#+}} xmm1 = [1.7976931348623157E+308,1.7976931348623157E+308] ; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.7976931348623157E+308,1.7976931348623157E+308]
; CHECK-NEXT: movapd {{.*#+}} xmm0 = [1.0E+0,1.0000000000000001E-1] ; CHECK-NEXT: movapd {{.*#+}} xmm1 = [2.0E+0,2.0000000000000001E-1]
; CHECK-NEXT: addpd %xmm1, %xmm0 ; CHECK-NEXT: addpd %xmm0, %xmm1
; CHECK-NEXT: addpd {{.*}}(%rip), %xmm1 ; CHECK-NEXT: addpd {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_fadd_v4f64: ; AVX1-LABEL: constrained_vector_fadd_v4f64:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308] ; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308,1.7976931348623157E+308]
; AVX1-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0 ; AVX1-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines %sub = call <3 x double> @llvm.experimental.constrained.fsub.v3f64(
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x double> %sub ret <3 x double> %sub
} }
define <4 x double> @constrained_vector_fsub_v4f64() #0 { define <4 x double> @constrained_vector_fsub_v4f64() #0 {
; CHECK-LABEL: constrained_vector_fsub_v4f64: ; CHECK-LABEL: constrained_vector_fsub_v4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movapd {{.*#+}} xmm1 = [-1.7976931348623157E+308,-1.7976931348623157E+308] ; CHECK-NEXT: movapd {{.*#+}} xmm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308]
; CHECK-NEXT: movapd %xmm1, %xmm0 ; CHECK-NEXT: movapd %xmm0, %xmm1
; CHECK-NEXT: subpd {{.*}}(%rip), %xmm0
; CHECK-NEXT: subpd {{.*}}(%rip), %xmm1 ; CHECK-NEXT: subpd {{.*}}(%rip), %xmm1
; CHECK-NEXT: subpd {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_fsub_v4f64: ; AVX1-LABEL: constrained_vector_fsub_v4f64:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308] ; AVX1-NEXT: vmovapd {{.*#+}} ymm0 = [-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308,-1.7976931348623157E+308]
; AVX1-NEXT: vsubpd {{.*}}(%rip), %ymm0, %ymm0 ; AVX1-NEXT: vsubpd {{.*}}(%rip), %ymm0, %ymm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
▲ Show 20 Lines • Show All 108 Lines • ▼ Show 20 Lines %sqrt = call <3 x double> @llvm.experimental.constrained.sqrt.v3f64(
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x double> %sqrt ret <3 x double> %sqrt
} }
define <4 x double> @constrained_vector_sqrt_v4f64() #0 { define <4 x double> @constrained_vector_sqrt_v4f64() #0 {
; CHECK-LABEL: constrained_vector_sqrt_v4f64: ; CHECK-LABEL: constrained_vector_sqrt_v4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sqrtpd {{.*}}(%rip), %xmm0
; CHECK-NEXT: sqrtpd {{.*}}(%rip), %xmm1 ; CHECK-NEXT: sqrtpd {{.*}}(%rip), %xmm1
; CHECK-NEXT: sqrtpd {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_sqrt_v4f64: ; AVX-LABEL: constrained_vector_sqrt_v4f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vsqrtpd {{.*}}(%rip), %ymm0 ; AVX-NEXT: vsqrtpd {{.*}}(%rip), %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%sqrt = call <4 x double> @llvm.experimental.constrained.sqrt.v4f64( %sqrt = call <4 x double> @llvm.experimental.constrained.sqrt.v4f64(
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: callq pow ; CHECK-NEXT: callq pow
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: callq pow ; CHECK-NEXT: callq pow
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_pow_v3f64: ; AVX-LABEL: constrained_vector_pow_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
▲ Show 20 Lines • Show All 237 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: movl $3, %edi
; CHECK-NEXT: callq __powidf2 ; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movl $3, %edi ; CHECK-NEXT: movl $3, %edi
; CHECK-NEXT: callq __powidf2 ; CHECK-NEXT: callq __powidf2
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_powi_v3f64: ; AVX-LABEL: constrained_vector_powi_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
▲ Show 20 Lines • Show All 218 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq sin ; CHECK-NEXT: callq sin
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq sin ; CHECK-NEXT: callq sin
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_sin_v3f64: ; AVX-LABEL: constrained_vector_sin_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
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; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq cos ; CHECK-NEXT: callq cos
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq cos ; CHECK-NEXT: callq cos
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_cos_v3f64: ; AVX-LABEL: constrained_vector_cos_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
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; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq exp ; CHECK-NEXT: callq exp
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq exp ; CHECK-NEXT: callq exp
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_exp_v3f64: ; AVX-LABEL: constrained_vector_exp_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
▲ Show 20 Lines • Show All 205 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq exp2 ; CHECK-NEXT: callq exp2
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq exp2 ; CHECK-NEXT: callq exp2
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_exp2_v3f64: ; AVX-LABEL: constrained_vector_exp2_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
▲ Show 20 Lines • Show All 205 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq log ; CHECK-NEXT: callq log
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq log ; CHECK-NEXT: callq log
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_log_v3f64: ; AVX-LABEL: constrained_vector_log_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
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; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq log10 ; CHECK-NEXT: callq log10
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq log10 ; CHECK-NEXT: callq log10
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_log10_v3f64: ; AVX-LABEL: constrained_vector_log10_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
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; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq log2 ; CHECK-NEXT: callq log2
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq log2 ; CHECK-NEXT: callq log2
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_log2_v3f64: ; AVX-LABEL: constrained_vector_log2_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
▲ Show 20 Lines • Show All 183 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq rint ; CHECK-NEXT: callq rint
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq rint ; CHECK-NEXT: callq rint
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_rint_v3f64: ; AVX-LABEL: constrained_vector_rint_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
▲ Show 20 Lines • Show All 151 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq nearbyint ; CHECK-NEXT: callq nearbyint
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq nearbyint ; CHECK-NEXT: callq nearbyint
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_nearby_v3f64: ; AVX-LABEL: constrained_vector_nearby_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
▲ Show 20 Lines • Show All 187 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: callq fmax ; CHECK-NEXT: callq fmax
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: callq fmax ; CHECK-NEXT: callq fmax
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_max_v3f64: ; AVX-LABEL: constrained_vector_max_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
▲ Show 20 Lines • Show All 231 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: callq fmin ; CHECK-NEXT: callq fmin
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
; CHECK-NEXT: callq fmin ; CHECK-NEXT: callq fmin
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_min_v3f64: ; AVX-LABEL: constrained_vector_min_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
▲ Show 20 Lines • Show All 214 Lines • ▼ Show 20 Lines %result = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f32(
<2 x float><float 42.0, float 43.0>, <2 x float><float 42.0, float 43.0>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x i64> %result ret <2 x i64> %result
} }
define <3 x i64> @constrained_vector_fptosi_v3i64_v3f32() #0 { define <3 x i64> @constrained_vector_fptosi_v3i64_v3f32() #0 {
; CHECK-LABEL: constrained_vector_fptosi_v3i64_v3f32: ; CHECK-LABEL: constrained_vector_fptosi_v3i64_v3f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si {{.*}}(%rip), %rax
; CHECK-NEXT: cvttss2si {{.*}}(%rip), %rdx
; CHECK-NEXT: cvttss2si {{.*}}(%rip), %rcx ; CHECK-NEXT: cvttss2si {{.*}}(%rip), %rcx
; CHECK-NEXT: cvttss2si {{.*}}(%rip), %rdx
; CHECK-NEXT: cvttss2si {{.*}}(%rip), %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_fptosi_v3i64_v3f32: ; AVX1-LABEL: constrained_vector_fptosi_v3i64_v3f32:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vcvttss2si {{.*}}(%rip), %rax ; AVX1-NEXT: vcvttss2si {{.*}}(%rip), %rax
; AVX1-NEXT: vmovq %rax, %xmm0 ; AVX1-NEXT: vmovq %rax, %xmm0
; AVX1-NEXT: vcvttss2si {{.*}}(%rip), %rax ; AVX1-NEXT: vcvttss2si {{.*}}(%rip), %rax
; AVX1-NEXT: vmovq %rax, %xmm1 ; AVX1-NEXT: vmovq %rax, %xmm1
▲ Show 20 Lines • Show All 223 Lines • ▼ Show 20 Lines %result = call <2 x i64> @llvm.experimental.constrained.fptosi.v2i64.v2f64(
<2 x double><double 42.1, double 42.2>, <2 x double><double 42.1, double 42.2>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x i64> %result ret <2 x i64> %result
} }
define <3 x i64> @constrained_vector_fptosi_v3i64_v3f64() #0 { define <3 x i64> @constrained_vector_fptosi_v3i64_v3f64() #0 {
; CHECK-LABEL: constrained_vector_fptosi_v3i64_v3f64: ; CHECK-LABEL: constrained_vector_fptosi_v3i64_v3f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si {{.*}}(%rip), %rax
; CHECK-NEXT: cvttsd2si {{.*}}(%rip), %rdx
; CHECK-NEXT: cvttsd2si {{.*}}(%rip), %rcx ; CHECK-NEXT: cvttsd2si {{.*}}(%rip), %rcx
; CHECK-NEXT: cvttsd2si {{.*}}(%rip), %rdx
; CHECK-NEXT: cvttsd2si {{.*}}(%rip), %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_fptosi_v3i64_v3f64: ; AVX1-LABEL: constrained_vector_fptosi_v3i64_v3f64:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vcvttsd2si {{.*}}(%rip), %rax ; AVX1-NEXT: vcvttsd2si {{.*}}(%rip), %rax
; AVX1-NEXT: vmovq %rax, %xmm0 ; AVX1-NEXT: vmovq %rax, %xmm0
; AVX1-NEXT: vcvttsd2si {{.*}}(%rip), %rax ; AVX1-NEXT: vcvttsd2si {{.*}}(%rip), %rax
; AVX1-NEXT: vmovq %rax, %xmm1 ; AVX1-NEXT: vmovq %rax, %xmm1
▲ Show 20 Lines • Show All 1,306 Lines • ▼ Show 20 Lines %result = call <2 x double> @llvm.experimental.constrained.fpext.v2f64.v2f32(
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <2 x double> %result ret <2 x double> %result
} }
define <3 x double> @constrained_vector_fpext_v3f32() #0 { define <3 x double> @constrained_vector_fpext_v3f32() #0 {
; CHECK-LABEL: constrained_vector_fpext_v3f32: ; CHECK-LABEL: constrained_vector_fpext_v3f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: cvtss2sd %xmm0, %xmm1
; CHECK-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; CHECK-NEXT: cvtss2sd %xmm0, %xmm0 ; CHECK-NEXT: cvtss2sd %xmm0, %xmm0
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
; CHECK-NEXT: cvtss2sd %xmm1, %xmm1
; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero ; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: cvtss2sd %xmm2, %xmm2 ; CHECK-NEXT: cvtss2sd %xmm2, %xmm2
; CHECK-NEXT: movsd %xmm2, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm2, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_fpext_v3f32: ; AVX-LABEL: constrained_vector_fpext_v3f32:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
Show All 12 Lines %result = call <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f32(
float 44.0>, float 44.0>,
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x double> %result ret <3 x double> %result
} }
define <4 x double> @constrained_vector_fpext_v4f32() #0 { define <4 x double> @constrained_vector_fpext_v4f32() #0 {
; CHECK-LABEL: constrained_vector_fpext_v4f32: ; CHECK-LABEL: constrained_vector_fpext_v4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvtps2pd {{.*}}(%rip), %xmm0
; CHECK-NEXT: cvtps2pd {{.*}}(%rip), %xmm1 ; CHECK-NEXT: cvtps2pd {{.*}}(%rip), %xmm1
; CHECK-NEXT: cvtps2pd {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_fpext_v4f32: ; AVX-LABEL: constrained_vector_fpext_v4f32:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vcvtps2pd {{.*}}(%rip), %ymm0 ; AVX-NEXT: vcvtps2pd {{.*}}(%rip), %ymm0
; AVX-NEXT: retq ; AVX-NEXT: retq
entry: entry:
%result = call <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f32( %result = call <4 x double> @llvm.experimental.constrained.fpext.v4f64.v4f32(
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; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq ceil ; CHECK-NEXT: callq ceil
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq ceil ; CHECK-NEXT: callq ceil
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_ceil_v3f64: ; AVX-LABEL: constrained_vector_ceil_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq floor ; CHECK-NEXT: callq floor
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq floor ; CHECK-NEXT: callq floor
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_floor_v3f64: ; AVX-LABEL: constrained_vector_floor_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq round ; CHECK-NEXT: callq round
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq round ; CHECK-NEXT: callq round
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_round_v3f64: ; AVX-LABEL: constrained_vector_round_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: subq $56, %rsp ; AVX-NEXT: subq $56, %rsp
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; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq trunc ; CHECK-NEXT: callq trunc
; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill ; CHECK-NEXT: movsd %xmm0, (%rsp) # 8-byte Spill
; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero ; CHECK-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; CHECK-NEXT: callq trunc ; CHECK-NEXT: callq trunc
; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm0, {{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl {{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl {{[0-9]+}}(%rsp)
; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 8-byte Reload ; CHECK-NEXT: movsd (%rsp), %xmm0 # 8-byte Reload
; CHECK-NEXT: # xmm0 = mem[0],zero ; CHECK-NEXT: # xmm0 = mem[0],zero
; CHECK-NEXT: movsd (%rsp), %xmm1 # 8-byte Reload ; CHECK-NEXT: movsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 8-byte Reload
; CHECK-NEXT: # xmm1 = mem[0],zero ; CHECK-NEXT: # xmm1 = mem[0],zero
; CHECK-NEXT: addq $24, %rsp ; CHECK-NEXT: addq $24, %rsp
; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX-LABEL: constrained_vector_trunc_v3f64: ; AVX-LABEL: constrained_vector_trunc_v3f64:
; AVX: # %bb.0: # %entry ; AVX: # %bb.0: # %entry
; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
▲ Show 20 Lines • Show All 265 Lines • ▼ Show 20 Lines %result = call <3 x float>
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x float> %result ret <3 x float> %result
} }
define <3 x double> @constrained_vector_sitofp_v3f64_v3i64(<3 x i64> %x) #0 { define <3 x double> @constrained_vector_sitofp_v3f64_v3i64(<3 x i64> %x) #0 {
; CHECK-LABEL: constrained_vector_sitofp_v3f64_v3i64: ; CHECK-LABEL: constrained_vector_sitofp_v3f64_v3i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvtsi2sd %rdi, %xmm0
; CHECK-NEXT: cvtsi2sd %rsi, %xmm1 ; CHECK-NEXT: cvtsi2sd %rsi, %xmm1
; CHECK-NEXT: cvtsi2sd %rdi, %xmm0
; CHECK-NEXT: cvtsi2sd %rdx, %xmm2 ; CHECK-NEXT: cvtsi2sd %rdx, %xmm2
; CHECK-NEXT: movsd %xmm2, -{{[0-9]+}}(%rsp) ; CHECK-NEXT: movsd %xmm2, -{{[0-9]+}}(%rsp)
; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp) ; CHECK-NEXT: fldl -{{[0-9]+}}(%rsp)
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_sitofp_v3f64_v3i64: ; AVX1-LABEL: constrained_vector_sitofp_v3f64_v3i64:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vpextrq $1, %xmm0, %rax ; AVX1-NEXT: vpextrq $1, %xmm0, %rax
▲ Show 20 Lines • Show All 841 Lines • ▼ Show 20 Lines %result = call <3 x float>
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <3 x float> %result ret <3 x float> %result
} }
define <4 x double> @constrained_vector_uitofp_v4f64_v4i32(<4 x i32> %x) #0 { define <4 x double> @constrained_vector_uitofp_v4f64_v4i32(<4 x i32> %x) #0 {
; CHECK-LABEL: constrained_vector_uitofp_v4f64_v4i32: ; CHECK-LABEL: constrained_vector_uitofp_v4f64_v4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movapd %xmm0, %xmm1
; CHECK-NEXT: xorpd %xmm2, %xmm2 ; CHECK-NEXT: xorpd %xmm2, %xmm2
; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; CHECK-NEXT: movapd %xmm0, %xmm1
; CHECK-NEXT: movapd {{.*#+}} xmm3 = [4.503599627370496E+15,4.503599627370496E+15]
; CHECK-NEXT: orpd %xmm3, %xmm0
; CHECK-NEXT: subpd %xmm3, %xmm0
; CHECK-NEXT: unpckhps {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3] ; CHECK-NEXT: unpckhps {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
; CHECK-NEXT: movapd {{.*#+}} xmm3 = [4.503599627370496E+15,4.503599627370496E+15]
; CHECK-NEXT: orpd %xmm3, %xmm1 ; CHECK-NEXT: orpd %xmm3, %xmm1
; CHECK-NEXT: subpd %xmm3, %xmm1 ; CHECK-NEXT: subpd %xmm3, %xmm1
; CHECK-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
; CHECK-NEXT: orpd %xmm3, %xmm0
; CHECK-NEXT: subpd %xmm3, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_uitofp_v4f64_v4i32: ; AVX1-LABEL: constrained_vector_uitofp_v4f64_v4i32:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3] ; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm1 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0 ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines %result = call <4 x float>
metadata !"fpexcept.strict") #0 metadata !"fpexcept.strict") #0
ret <4 x float> %result ret <4 x float> %result
} }
define <4 x double> @constrained_vector_uitofp_v4f64_v4i64(<4 x i64> %x) #0 { define <4 x double> @constrained_vector_uitofp_v4f64_v4i64(<4 x i64> %x) #0 {
; CHECK-LABEL: constrained_vector_uitofp_v4f64_v4i64: ; CHECK-LABEL: constrained_vector_uitofp_v4f64_v4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,4294967295] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [4294967295,4294967295]
; CHECK-NEXT: movdqa %xmm0, %xmm3 ; CHECK-NEXT: movdqa %xmm1, %xmm3
; CHECK-NEXT: pand %xmm2, %xmm3 ; CHECK-NEXT: pand %xmm2, %xmm3
; CHECK-NEXT: movdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200] ; CHECK-NEXT: movdqa {{.*#+}} xmm4 = [4841369599423283200,4841369599423283200]
; CHECK-NEXT: por %xmm4, %xmm3 ; CHECK-NEXT: por %xmm4, %xmm3
; CHECK-NEXT: psrlq $32, %xmm0
; CHECK-NEXT: movdqa {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072]
; CHECK-NEXT: por %xmm5, %xmm0
; CHECK-NEXT: movapd {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25]
; CHECK-NEXT: subpd %xmm6, %xmm0
; CHECK-NEXT: addpd %xmm3, %xmm0
; CHECK-NEXT: pand %xmm1, %xmm2
; CHECK-NEXT: por %xmm4, %xmm2
; CHECK-NEXT: psrlq $32, %xmm1 ; CHECK-NEXT: psrlq $32, %xmm1
; CHECK-NEXT: movdqa {{.*#+}} xmm5 = [4985484787499139072,4985484787499139072]
; CHECK-NEXT: por %xmm5, %xmm1 ; CHECK-NEXT: por %xmm5, %xmm1
; CHECK-NEXT: movapd {{.*#+}} xmm6 = [1.9342813118337666E+25,1.9342813118337666E+25]
; CHECK-NEXT: subpd %xmm6, %xmm1 ; CHECK-NEXT: subpd %xmm6, %xmm1
; CHECK-NEXT: addpd %xmm2, %xmm1 ; CHECK-NEXT: addpd %xmm3, %xmm1
; CHECK-NEXT: pand %xmm0, %xmm2
; CHECK-NEXT: por %xmm4, %xmm2
; CHECK-NEXT: psrlq $32, %xmm0
; CHECK-NEXT: por %xmm5, %xmm0
; CHECK-NEXT: subpd %xmm6, %xmm0
; CHECK-NEXT: addpd %xmm2, %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
; ;
; AVX1-LABEL: constrained_vector_uitofp_v4f64_v4i64: ; AVX1-LABEL: constrained_vector_uitofp_v4f64_v4i64:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; AVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7] ; AVX1-NEXT: vblendps {{.*#+}} ymm1 = ymm0[0],ymm1[1],ymm0[2],ymm1[3],ymm0[4],ymm1[5],ymm0[6],ymm1[7]
; AVX1-NEXT: vorps {{.*}}(%rip), %ymm1, %ymm1 ; AVX1-NEXT: vorps {{.*}}(%rip), %ymm1, %ymm1
; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm2 ; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm2
▲ Show 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
; ;
; AVX1-LABEL: constrained_vector_uitofp_v4f32_v4i64: ; AVX1-LABEL: constrained_vector_uitofp_v4f32_v4i64:
; AVX1: # %bb.0: # %entry ; AVX1: # %bb.0: # %entry
; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm1 ; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm1
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; AVX1-NEXT: vpsrlq $1, %xmm2, %xmm3 ; AVX1-NEXT: vpsrlq $1, %xmm2, %xmm3
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1 ; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm1, %ymm1
; AVX1-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3 ; AVX1-NEXT: vandpd {{.*}}(%rip), %ymm0, %ymm3
; AVX1-NEXT: vorpd %ymm3, %ymm1, %ymm1 ; AVX1-NEXT: vorpd %ymm3, %ymm1, %ymm3
; AVX1-NEXT: vblendvpd %xmm0, %xmm1, %xmm0, %xmm3 ; AVX1-NEXT: vblendvpd %xmm0, %xmm3, %xmm0, %xmm1
; AVX1-NEXT: vpextrq $1, %xmm3, %rax ; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm4, %xmm4
; AVX1-NEXT: vmovq %xmm3, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm3
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
; AVX1-NEXT: vblendvpd %xmm2, %xmm1, %xmm2, %xmm1
; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: vmovq %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm4
; AVX1-NEXT: vinsertps {{.*#+}} xmm3 = xmm3[0,1],xmm4[0],xmm3[3]
; AVX1-NEXT: vpextrq $1, %xmm1, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm1
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[0] ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[2,3]
craig.topperUnsubmitted
Not Done
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This diff is recovered with D72224

craig.topper: This diff is recovered with D72224
; AVX1-NEXT: vaddps %xmm1, %xmm1, %xmm3 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
; AVX1-NEXT: vxorps %xmm4, %xmm4, %xmm4 ; AVX1-NEXT: vblendvpd %xmm2, %xmm4, %xmm2, %xmm4
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm4, %xmm2 ; AVX1-NEXT: vmovq %xmm4, %rax
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm0 ; AVX1-NEXT: vcvtsi2ss %rax, %xmm5, %xmm5
; AVX1-NEXT: vblendvps %xmm0, %xmm3, %xmm1, %xmm0 ; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1],xmm5[0],xmm1[3]
; AVX1-NEXT: vpextrq $1, %xmm4, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm6, %xmm4
; AVX1-NEXT: vinsertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
; AVX1-NEXT: vaddps %xmm1, %xmm1, %xmm4
; AVX1-NEXT: vxorps %xmm5, %xmm5, %xmm5
; AVX1-NEXT: vpcmpgtq %xmm2, %xmm5, %xmm2
; AVX1-NEXT: vpackssdw %xmm2, %xmm0, %xmm2
; AVX1-NEXT: vblendvps %xmm2, %xmm4, %xmm1, %xmm1
; AVX1-NEXT: vblendvpd %ymm0, %ymm3, %ymm0, %ymm0
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm6, %xmm2
; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm6, %xmm3
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm3[0],xmm2[0],xmm3[2,3]
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm6, %xmm3
; AVX1-NEXT: vinsertps {{.*#+}} xmm2 = xmm2[0,1],xmm3[0],xmm2[3]
; AVX1-NEXT: vpextrq $1, %xmm0, %rax
; AVX1-NEXT: vcvtsi2ss %rax, %xmm6, %xmm0
; AVX1-NEXT: vinsertps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[0]
; AVX1-NEXT: vaddps %xmm0, %xmm0, %xmm0
; AVX1-NEXT: vmovaps %xmm1, %xmm0
; AVX1-NEXT: vzeroupper ; AVX1-NEXT: vzeroupper
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX512F-LABEL: constrained_vector_uitofp_v4f32_v4i64: ; AVX512F-LABEL: constrained_vector_uitofp_v4f32_v4i64:
; AVX512F: # %bb.0: # %entry ; AVX512F: # %bb.0: # %entry
; AVX512F-NEXT: vpextrq $1, %xmm0, %rax ; AVX512F-NEXT: vpextrq $1, %xmm0, %rax
; AVX512F-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1 ; AVX512F-NEXT: vcvtusi2ss %rax, %xmm1, %xmm1
; AVX512F-NEXT: vmovq %xmm0, %rax ; AVX512F-NEXT: vmovq %xmm0, %rax
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