[RISCV] Implement canRealignStack

[lenary]

Summary

The implementation of RISCVRegisterInfo::canRealignStack was left out of the
implementation of Stack Realignment in D62007.

I think this is the root cause of the issues we've seen in D70401 around the
spilling of fp64 registers in the ILP32E ABI. Applying this patch seems to
solve those issues.

Unfortunately, I think that failure requires spilling a register with a spill
alignment that is larger than the current stack alignment. Until ILP32E has
landed, we have no registers which satisfy these constraints, so no testcases
have changed with this commit (but, we want to land this patche separately to
ILP32E support).

[lenary]

This might have to be backported to 9.0.1 as stack realignment has got into 9.0.1.

[shiva0217]

With the patch, double load/store instructions may unaligned-access with -mabi=ilp32e -mattr=+d flags. Could the load/store support unaligned-access?

[lenary]

In D70670#1759877, @shiva0217 wrote:

With the patch, double load/store instructions may unaligned-access with -mabi=ilp32e -mattr=+d flags. Could the load/store support unaligned-access?

My understanding was that RISC-V mandated that misaligned loads/stores had to be supported, even if that was via emulation in a trap handler. Having re-read the specification, I realise I am wrong (the trap handler, if used, is not required to emulate the misaligned load/store using aligned loads and stores).

I think this solution "works" because needsStackRealignment only returns true if canRealignStack returns true. I shall go back to the solution involving detecting ILP32E and the D extension (and potentially the sizes of the used registers).

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

struct RISCVRegisterInfo : public RISCVGenRegisterInfo {
   const uint32_t *getNoPreservedMask() const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   Register getFrameRegister(const MachineFunction &MF) const override;
 
+  bool canRealignStack(const MachineFunction &) const override;
+
   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
     return true;
   }
 

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
 }
 
 Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = getFrameLowering(MF);
   return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
 }
 
+bool RISCVRegisterInfo::canRealignStack(const MachineFunction &MF) const {
+  if (!TargetRegisterInfo::canRealignStack(MF))
+    return false;
+
+  // We need the frame pointer (fp) to restore the stack pointer (sp) when
+  // realigning the stack in the epilog.
+  Register FPReg = RISCV::X8;
+
+  // In order to use fp, it must not be reserved by the user.
+  if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(FPReg))
+    return false;
+
+  // In order to use fp, we must be able to reserve it.
+  const MachineRegisterInfo *MRI = &MF.getRegInfo();
+  return MRI->canReserveReg(FPReg);
+}
+
 const uint32_t *
 RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
                                         CallingConv::ID /*CC*/) const {
   auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
   if (MF.getFunction().hasFnAttribute("interrupt")) {
     if (Subtarget.hasStdExtD())
       return CSR_XLEN_F64_Interrupt_RegMask;
     if (Subtarget.hasStdExtF())