[DAGCombine] Don't check the legality of type when combine the SIGN_EXTEND_INREG

[steven.zhang]

Summary

This is the DAG node for SIGN_EXTEND_INREG :

t21: v4i32 = sign_extend_inreg t18, ValueType:ch:v4i16

It has two operands. The first one is the value it want to extend, and the second one is the type to specify how to extend the value. For this example, it means that, it is signed extend the t18(v4i32) from v4i16 to v4i32. That is the semantics of c code:

vector int foo(vector int m) {
   return m << 16 >> 16;
}

And it could be any vector type that hardware support the operation, though the type 'v4i16' is NOT legal for the target. When we are trying to combine the srl + sra, what we did now is calling the TLI.isOperationLegal(), which will also check the legality of the type. That doesn't make sense.

Notice that, this patch is dependent on https://reviews.llvm.org/D69601 to expose the PowerPC missing opportunity. And it is also dependent on https://reviews.llvm.org/D70000, as we are relaxing the combine condition, which might hit the assertion for some targets if they are NOT set it as expand by default.

[arsenm]

LGTM

[dmgreen]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

7738

Remember to clang-format before committing.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitSRA(SDNode *N) {
   // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
   // sext_inreg.
   if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
     unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue();
     EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
     if (VT.isVector())
       ExtVT = EVT::getVectorVT(*DAG.getContext(),
                                ExtVT, VT.getVectorNumElements());
-    if ((!LegalOperations ||
-         TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
+    if (!LegalOperations ||
+        TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) ==
+        TargetLowering::Legal)
       return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT,
                          N0.getOperand(0), DAG.getValueType(ExtVT));
   }
 
   // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
   // clamp (add c1, c2) to max shift.
   if (N0.getOpcode() == ISD::SRA) {
     SDLoc DL(N);

llvm/test/CodeGen/PowerPC/sext-vector-inreg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck -check-prefix=CHECK-P9 %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck -check-prefix=CHECK-P8 %s
 define <4 x i32> @test_signext_vector_inreg(<4 x i16> %n) {
 ; CHECK-P9-LABEL: test_signext_vector_inreg:
 ; CHECK-P9:       # %bb.0: # %entry
-; CHECK-P9-NEXT:    vspltisw 3, 8
 ; CHECK-P9-NEXT:    vmrglh 2, 2, 2
-; CHECK-P9-NEXT:    vadduwm 3, 3, 3
-; CHECK-P9-NEXT:    vslw 2, 2, 3
-; CHECK-P9-NEXT:    vsraw 2, 2, 3
+; CHECK-P9-NEXT:    vextsh2w 2, 2
 ; CHECK-P9-NEXT:    blr
 ;
 ; CHECK-P8-LABEL: test_signext_vector_inreg:
 ; CHECK-P8:       # %bb.0: # %entry
 ; CHECK-P8-NEXT:    vmrglh 2, 2, 2
 ; CHECK-P8-NEXT:    vspltisw 3, 8
 ; CHECK-P8-NEXT:    vadduwm 3, 3, 3
 ; CHECK-P8-NEXT:    vslw 2, 2, 3
 ; CHECK-P8-NEXT:    vsraw 2, 2, 3
 ; CHECK-P8-NEXT:    blr
 entry:
   %0 = sext <4 x i16> %n to <4 x i32>
   ret <4 x i32> %0
 }