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[Power9] Implement the vector extend sign instruction pattern match
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Authored by steven.zhang on Oct 29 2019, 7:29 PM.

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Summary

Power9 has instructions to implement the semantics of SIGN_EXTEND_INREG for vector type. Mark it as legal and add the match pattern.

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Event Timeline

steven.zhang created this revision.Oct 29 2019, 7:29 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 29 2019, 7:29 PM
amyk added a subscriber: amyk.Nov 3 2019, 7:25 PM
amyk added inline comments.
llvm/test/CodeGen/PowerPC/vector-extend-sign.ll
3

I think it would be better to separate the run lines so it is not over 80 characters.

Update the test run line.

steven.zhang marked an inline comment as done.Nov 5 2019, 7:04 PM
steven.zhang added inline comments.
llvm/test/CodeGen/PowerPC/vector-extend-sign.ll
3

Done.

Gentle ping ... Thank you!

nemanjai added inline comments.Nov 9 2019, 8:06 AM
llvm/lib/Target/PowerPC/PPCInstrVSX.td
4305 ↗(On Diff #227994)

I don't really see a reason to put this into PPCInstrVSX.td. Seems like PPCInstrAltivec.td would be a more appropriate place for it.

steven.zhang marked an inline comment as done.Nov 10 2019, 6:35 PM
steven.zhang added inline comments.
llvm/lib/Target/PowerPC/PPCInstrVSX.td
4305 ↗(On Diff #227994)

Hmm, make sense. It is interesting that, we put the match pattern from build_vector to VEXTSB2D here too ...

Address Nemanjai's comments.

Gentle ping ...

lkail accepted this revision as: Restricted Project.Nov 19 2019, 7:12 PM
lkail added a subscriber: lkail.

LGTM considering patterns added for SIGN_EXTENDED_INREG also follow its atomic semantics.

steven.zhang added a comment.EditedNov 20 2019, 2:38 AM

Hmm, it is still in the "need review" state. 😢

shchenz accepted this revision.Nov 20 2019, 10:49 PM
shchenz added a subscriber: shchenz.

Thanks for this exploitation. LGTM too.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp
936

Do we need these lines? The default action is Legal. If this is necessary, then maybe we need another NFC patch to add operation action for ISD::SIGN_EXTEND_INREG for type {i8, i16, i32} to make actions for ISD::SIGN_EXTEND_INREG be consistent? Up to you to change it or not.

This revision is now accepted and ready to land.Nov 20 2019, 10:49 PM
steven.zhang marked an inline comment as done.Nov 21 2019, 7:54 PM
steven.zhang added inline comments.
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
936

Explicit specify it to legal didn't hurt anything, I think. And we have another patch to specify the default action for SIGN_EXTEND_INREG as Expand for vector type.

This revision was automatically updated to reflect the committed changes.