Instead of generating two i32 instructions for each load or store of a volatile
i64 value (two LDRs or STRs), now try to emit wide loads or stores.
The CodeGen in this patch attempts to produce LDRD/STRD instructions for
these wide memory accesses. However, this is not always possible because
these instructions require an even/odd, consecutive pair of register
After register allocation, if this requirement is not met, the ARM
Load/Store Optimizer transforms ill-formed LDRD/STRD into LDM/STM
Do note that the requirement above is only present in AArch32. In
Thumb-2, the two register operands of LDRD/STRD are not restrained to be a
consecutive pair of registers.
These improvements cover architectures implementing ARMv5TE or Thumb-2.