[Xtensa 7/10] Add Xtensa instruction printer.

[andreisfr]

Summary

Add printer for current instructions and operands subsets.
Also add basic tests of the Xtensa instructions.

[andreisfr]

Register names are capitalized.

[andreisfr]

Patch is updated according to latest upstream version. Updated licenses.

[andreisfr]

Patch is updated according to latest upstream version

[andreisfr]

Patch is updated according to LLVM upstream version and latest Xtensa backend version.

[andreisfr]

The llvm_unreachable is substituted to report_fatal_error

[andreisfr]

Remove redundant whitespaces.

[andreisfr]

Patch is updated according to LLVM upstream version.

[andreisfr]

Patch is updated according to LLVM upstream version

[saugustine]

llvm/test/MC/Xtensa/xtensa-invalid.s

14

It would be good to check instruction arguments out of order, and invalid register names.

llvm/test/MC/Xtensa/xtensa-valid.s

4 ↗

(On Diff #425076)

It would be good here to comments marking which instruction formats (RRR, RRI4, RRI8 and so on). re covered, as the difference between them is a common source of bugs. Perhaps next to one of the instructions.

I assume that eventually there will be comprehensive coverage of all the different formats.

61 ↗

(On Diff #425076)

Spaces after the commas in this file is inconsistent.

[andreisfr]

Minor changes: corrected comment

[andreisfr]

llvm/test/MC/Xtensa/xtensa-invalid.s

14

You mean for each instruction implement extended tests with argument out of order and invalid register names?

[saugustine]

llvm/test/MC/Xtensa/xtensa-invalid.s

14

Probably just once for each format, but yes.

[arsenm]

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp

34–35

Just use cast<>

[MaskRay]

llvm/test/MC/Xtensa/elf-header.s

6

Add -NEXT when applicable.

llvm/test/MC/Xtensa/xtensa-valid.s

1 ↗

(On Diff #455444)

Split this into multiple files.

MC/AArch64/armv8* and MC/LoongArch/Basic can give some insights how tests are organized.

[MaskRay]

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp

90

isInt<8> from MathExtras.h

94

Add braces. then uses braces and else should use, too.

101

isInt<16> from MathExtras.h

[andreisfr]

Minor code corrections. Test file xtensa-valid.s is splitted to several files by instructions groups.

[andreisfr]

Remove xtensa-valid.s

[andreisfr]

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp

34–35

Corrected

90

Corrected

94

Corrected

101

Corrected

llvm/test/MC/Xtensa/elf-header.s

6

Corrected

llvm/test/MC/Xtensa/xtensa-invalid.s

14

I added more tests for different instruction formats.

llvm/test/MC/Xtensa/xtensa-valid.s

1 ↗

(On Diff #455444)

Thank you for advice, I've splitted file to several files by commands groups.

4 ↗

(On Diff #425076)

Added format information to each instruction.

[andreisfr]

@MaskRay , may I ask you about new test structure of the instructions set? I divided test file xtensa-valid.s to several files by instructions groups. Whether such division matches to your suggestions?

[arsenm]

LGTM with nit

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp

35

Also means you can get rid of the assert(false) and if

[jrtc27]

llvm/test/MC/Xtensa/elf-header.s

3

Why not just use CHECK? And please keep these uppercase so they stand out.

[andreisfr]

Fixed "elf-header.s" test according to comments

[andreisfr]

llvm/test/MC/Xtensa/elf-header.s

3

Thank you for comment, test is fixed.

[MaskRay]

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h

52

llvm/test/MC/Xtensa/elf-header.s

6

Not done.

llvm/test/MC/Xtensa/xtensa-invalid.s

1

llvm-mc doesn't need <

delete excess spaces

9

Add locations for all diagnostics ( [[#@LINE+1]])

19

[[#LINE]] is legacy syntax. Use [[#@LINE]]. Fix this everywhere.

[barannikov88]

llvm/lib/Target/Xtensa/Xtensa.td

56

I think this bit does not affect anything.

[MaskRay]

The xtensa- prefix in test filenames like llvm/test/MC/Xtensa/xtensa-arith.s is unnecessary.
You may look at M68k and LoongArch for how ISA tests are organized in subdirectories. I think the two newer ports have more organized hierarchy.

[andreisfr]

Added fixes according to comments

[andreisfr]

llvm/lib/Target/Xtensa/Xtensa.td

56

Fixed

[andreisfr]

@MaskRay , I changed Xtensa tests structure according to your suggestions, PTAL.

llvm/lib/Target/Xtensa/CMakeLists.txt

 add_llvm_component_group(Xtensa)
 
 set(LLVM_TARGET_DEFINITIONS Xtensa.td)
 
 tablegen(LLVM XtensaGenAsmMatcher.inc -gen-asm-matcher)
+tablegen(LLVM XtensaGenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM XtensaGenMCCodeEmitter.inc -gen-emitter)
 tablegen(LLVM XtensaGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM XtensaGenSubtargetInfo.inc -gen-subtarget)
 
 add_public_tablegen_target(XtensaCommonTableGen)
 
 add_llvm_target(XtensaCodeGen
   XtensaTargetMachine.cpp
 
   LINK_COMPONENTS
+  AsmPrinter
   CodeGen
   Core
+  MC
   Support
   Target
+  XtensaDesc
   XtensaInfo
 
   ADD_TO_COMPONENT
   Xtensa
   )
 
 add_subdirectory(AsmParser)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(TargetInfo)
 

llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt

 add_llvm_component_library(LLVMXtensaDesc
   XtensaAsmBackend.cpp
   XtensaELFObjectWriter.cpp
+  XtensaInstPrinter.cpp
   XtensaMCAsmInfo.cpp
   XtensaMCCodeEmitter.cpp
   XtensaMCTargetDesc.cpp
 
   LINK_COMPONENTS
   MC
   Support
   XtensaInfo
 
   ADD_TO_COMPONENT
   Xtensa
  )

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.h

+//===- XtensaInstPrinter.h - Convert Xtensa MCInst to asm syntax -*- C++ -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an Xtensa MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAINSTPRINTER_H
+#define LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAINSTPRINTER_H
+
+#include "llvm/MC/MCInstPrinter.h"
+#include "llvm/Support/Compiler.h"
+
+namespace llvm {
+class MCOperand;
+
+class XtensaInstPrinter : public MCInstPrinter {
+public:
+  XtensaInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
+                    const MCRegisterInfo &MRI)
+      : MCInstPrinter(MAI, MII, MRI) {}
+
+  // Automatically generated by tblgen.
+  std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
+  void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &O);
+  static const char *getRegisterName(unsigned RegNo);
+
+  // Print the given operand.
+  static void printOperand(const MCOperand &MO, raw_ostream &O);
+
+  // Override MCInstPrinter.
+  void printRegName(raw_ostream &O, unsigned RegNo) const override;
+  void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
+                 const MCSubtargetInfo &STI, raw_ostream &O) override;
+
+private:
+  // Print various types of operand.
+  void printOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+
+  void printImm8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+  void printImm8_sh8_AsmOperand(const MCInst *MI, int OpNum, raw_ostream &O);
+};
+} // end namespace llvm
+
+#endif /* LLVM_LIB_TARGET_XTENSA_MCTARGETDESC_XTENSAINSTPRINTER_H */

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaInstPrinter.cpp

+//===- XtensaInstPrinter.cpp - Convert Xtensa MCInst to asm syntax --------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This class prints an Xtensa MCInst to a .s file.
+//
+//===----------------------------------------------------------------------===//
+
+#include "XtensaInstPrinter.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCInstrInfo.h"
+#include "llvm/MC/MCSymbol.h"
+#include "llvm/Support/Casting.h"
+#include "llvm/Support/raw_ostream.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "asm-printer"
+
+#include "XtensaGenAsmWriter.inc"
+
+static void printExpr(const MCExpr *Expr, raw_ostream &OS) {
+  int Offset = 0;
+  const MCSymbolRefExpr *SRE;
+
+  if (!(SRE = cast<MCSymbolRefExpr>(Expr)))
+    assert(false && "Unexpected MCExpr type.");
+
+  MCSymbolRefExpr::VariantKind Kind = SRE->getKind();
+
+  switch (Kind) {
+  case MCSymbolRefExpr::VK_None:
+    break;
+  // TODO
+  default:
+    report_fatal_error("Invalid kind!");
+  }
+
+  OS << SRE->getSymbol();
+
+  if (Offset) {
+    if (Offset > 0)
+      OS << '+';
+    OS << Offset;
+  }
+
+  if (Kind != MCSymbolRefExpr::VK_None)
+    OS << ')';
+}
+
+void XtensaInstPrinter::printOperand(const MCOperand &MC, raw_ostream &O) {
+  if (MC.isReg())
+    O << getRegisterName(MC.getReg());
+  else if (MC.isImm())
+    O << MC.getImm();
+  else if (MC.isExpr())
+    printExpr(MC.getExpr(), O);
+  else
+    report_fatal_error("Invalid operand");
+}
+
+void XtensaInstPrinter::printInst(const MCInst *MI, uint64_t Address,
+                                  StringRef Annot, const MCSubtargetInfo &STI,
+                                  raw_ostream &O) {
+  printInstruction(MI, Address, O);
+  printAnnotation(O, Annot);
+}
+
+void XtensaInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
+  O << getRegisterName(RegNo);
+}
+
+void XtensaInstPrinter::printOperand(const MCInst *MI, int OpNum,
+                                     raw_ostream &O) {
+  printOperand(MI->getOperand(OpNum), O);
+}
+
+void XtensaInstPrinter::printImm8_AsmOperand(const MCInst *MI, int OpNum,
+                                             raw_ostream &O) {
+  if (MI->getOperand(OpNum).isImm()) {
+    int64_t Value = MI->getOperand(OpNum).getImm();
+    assert(isInt<8>(Value) &&
+           "Invalid argument, value must be in ranges [-128,127]");
+    O << Value;
+  } else {
+    printOperand(MI, OpNum, O);
+  }
+}
+
+void XtensaInstPrinter::printImm8_sh8_AsmOperand(const MCInst *MI, int OpNum,
+                                                 raw_ostream &O) {
+  if (MI->getOperand(OpNum).isImm()) {
+    int64_t Value = MI->getOperand(OpNum).getImm();
+    assert((isInt<16>(Value) && ((Value & 0xFF) == 0)) &&
+           "Invalid argument, value must be multiples of 256 in range "
+           "[-32768,32512]");
+    O << Value;
+  } else
+    printOperand(MI, OpNum, O);
+}

llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp

 //===-- XtensaMCTargetDesc.cpp - Xtensa target descriptions ---------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #include "XtensaMCTargetDesc.h"
+#include "XtensaInstPrinter.h"
 #include "XtensaMCAsmInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/ErrorHandling.h"
 
 #define GET_INSTRINFO_MC_DESC
 #include "XtensaGenInstrInfo.inc"
 
 #define GET_REGINFO_MC_DESC
 #include "XtensaGenRegisterInfo.inc"
 
+#define GET_SUBTARGETINFO_MC_DESC
+#include "XtensaGenSubtargetInfo.inc"
+
 using namespace llvm;
 
 static MCAsmInfo *createXtensaMCAsmInfo(const MCRegisterInfo &MRI,
                                         const Triple &TT,
                                         const MCTargetOptions &Options) {
   MCAsmInfo *MAI = new XtensaMCAsmInfo(TT);
   return MAI;
 }
 
 static MCInstrInfo *createXtensaMCInstrInfo() {
   MCInstrInfo *X = new MCInstrInfo();
   InitXtensaMCInstrInfo(X);
   return X;
 }
 
+static MCInstPrinter *createXtensaMCInstPrinter(const Triple &TT,
+                                                unsigned SyntaxVariant,
+                                                const MCAsmInfo &MAI,
+                                                const MCInstrInfo &MII,
+                                                const MCRegisterInfo &MRI) {
+  return new XtensaInstPrinter(MAI, MII, MRI);
+}
+
 static MCRegisterInfo *createXtensaMCRegisterInfo(const Triple &TT) {
   MCRegisterInfo *X = new MCRegisterInfo();
   InitXtensaMCRegisterInfo(X, Xtensa::SP);
   return X;
 }
 
+static MCSubtargetInfo *
+createXtensaMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
+  return createXtensaMCSubtargetInfoImpl(TT, CPU, CPU, FS);
+}
+
 extern "C" void LLVMInitializeXtensaTargetMC() {
   // Register the MCAsmInfo.
   TargetRegistry::RegisterMCAsmInfo(TheXtensaTarget, createXtensaMCAsmInfo);
 
   // Register the MCCodeEmitter.
   TargetRegistry::RegisterMCCodeEmitter(TheXtensaTarget,
                                         createXtensaMCCodeEmitter);
 
   // Register the MCInstrInfo.
   TargetRegistry::RegisterMCInstrInfo(TheXtensaTarget, createXtensaMCInstrInfo);
 
+  // Register the MCInstPrinter.
+  TargetRegistry::RegisterMCInstPrinter(TheXtensaTarget,
+                                        createXtensaMCInstPrinter);
+
   // Register the MCRegisterInfo.
   TargetRegistry::RegisterMCRegInfo(TheXtensaTarget,
                                     createXtensaMCRegisterInfo);
 
+  // Register the MCSubtargetInfo.
+  TargetRegistry::RegisterMCSubtargetInfo(TheXtensaTarget,
+                                          createXtensaMCSubtargetInfo);
+
   // Register the MCAsmBackend.
   TargetRegistry::RegisterMCAsmBackend(TheXtensaTarget,
                                        createXtensaMCAsmBackend);
 }

llvm/lib/Target/Xtensa/Xtensa.td

 //===----------------------------------------------------------------------===//
 // Target Declaration
 //===----------------------------------------------------------------------===//
 
 def XtensaAsmParser : AsmParser {
   let ShouldEmitMatchRegisterAltName = 1;
 }
 
+def XtensaInstPrinter : AsmWriter {
+  string AsmWriterClassName  = "InstPrinter";
+  bit isMCAsmWriter = 1;
+}
+
 def Xtensa : Target {
   let InstructionSet = XtensaInstrInfo;
+  let AssemblyWriters = [XtensaInstPrinter];
   let AssemblyParsers = [XtensaAsmParser];
 }
+

llvm/test/MC/Xtensa/elf-header.s

+# RUN: llvm-mc %s -filetype=obj -triple=xtensa | llvm-readobj -h - \
+# RUN:     | FileCheck %s
+
+# CHECK: Format: elf32-xtensa
+# CHECK: Arch: xtensa
+# CHECK: AddressSize: 32bit
+# CHECK: ElfHeader {
+# CHECK:   Ident {
+# CHECK:     Magic: (7F 45 4C 46)
+# CHECK:     Class: 32-bit (0x1)
+# CHECK:     DataEncoding: LittleEndian (0x1)
+# CHECK:     FileVersion: 1
+# CHECK:     OS/ABI: SystemV (0x0)
+# CHECK:     ABIVersion: 0
+# CHECK:     Unused: (00 00 00 00 00 00 00)
+# CHECK:   }
+# CHECK:   Type: Relocatable (0x1)
+# CHECK:   Machine: EM_XTENSA (0x5E)
+# CHECK:   Version: 1
+# CHECK:   Entry: 0x0
+# CHECK:   ProgramHeaderOffset: 0x0
+# CHECK:   SectionHeaderOffset: 0x5C
+# CHECK:   Flags [ (0x0)
+# CHECK:   ]
+# CHECK:   HeaderSize: 52
+# CHECK:   ProgramHeaderEntrySize: 0
+# CHECK:   ProgramHeaderCount: 0
+# CHECK:   SectionHeaderEntrySize: 40
+# CHECK:   SectionHeaderCount: 4
+# CHECK:   StringTableSectionIndex: 1
+# CHECK: }

llvm/test/MC/Xtensa/lit.local.cfg

+if not 'Xtensa' in config.root.targets:
+    config.unsupported = True

llvm/test/MC/Xtensa/xtensa-arith.s

+# RUN: llvm-mc %s -triple=xtensa -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+
+.align  4
+LBL0:
+
+# Instruction format RRR
+# CHECK-INST: abs a5, a6
+# CHECK: encoding: [0x60,0x51,0x60]
+abs a5, a6
+
+# Instruction format RRR
+# CHECK-INST: add a3, a9, a4
+# CHECK: encoding: [0x40,0x39,0x80]
+add a3, a9, a4
+
+# CHECK-INST: add a15, a9, a1
+# CHECK: encoding: [0x10,0xf9,0x80]
+add a15, a9, sp
+
+# Instruction format RRI8
+# CHECK-INST: addi a8, a1, -128
+# CHECK: encoding: [0x82,0xc1,0x80]
+addi a8, sp, -128
+
+# CHECK-INST: addi a8, a1, -12
+# CHECK: encoding: [0x82,0xc1,0xf4]
+addi a8, a1, -12
+
+# Instruction format RRI8
+# CHECK-INST:  addmi a1, a2, 32512
+# CHECK: encoding: [0x12,0xd2,0x7f]
+addmi a1, a2, 32512
+
+# Instruction format RRR
+# CHECK-INST: addx2 a2, a1, a5
+# CHECK: encoding: [0x50,0x21,0x90]
+addx2 a2, sp, a5
+
+# Instruction format RRR
+# CHECK-INST: addx4 a3, a1, a6
+# CHECK: encoding: [0x60,0x31,0xa0]
+addx4 a3, sp, a6
+
+# Instruction format RRR
+# CHECK-INST: addx8 a4, a1, a7
+# CHECK: encoding: [0x70,0x41,0xb0]
+addx8 a4, sp, a7
+
+# Instruction format RRR
+# CHECK-INST: neg a1, a3
+# CHECK: encoding: [0x30,0x10,0x60]
+neg a1, a3
+
+# Instruction format RRR
+# CHECK-INST: or a4, a5, a6
+# CHECK: encoding: [0x60,0x45,0x20]
+or a4, a5, a6
+
+# Instruction format RRR
+# CHECK-INST: sub a8, a2, a1
+# CHECK: encoding: [0x10,0x82,0xc0]
+sub  a8, a2, a1
+
+# Instruction format RRR
+# CHECK-INST: subx2 a2, a1, a5
+# CHECK: encoding: [0x50,0x21,0xd0]
+subx2 a2, sp, a5
+
+# Instruction format RRR
+# CHECK-INST: subx4 a3, a1, a6
+# CHECK: encoding: [0x60,0x31,0xe0]
+subx4 a3, sp, a6
+
+# Instruction format RRR
+# CHECK-INST: subx8 a4, a1, a7
+# CHECK: encoding: [0x70,0x41,0xf0]
+subx8 a4, sp, a7
+
+# Instruction format RRR
+# CHECK-INST: xor a6, a4, a5
+# CHECK: encoding: [0x50,0x64,0x30]
+xor a6, a4, a5

llvm/test/MC/Xtensa/xtensa-invalid.s

+# RUN: not llvm-mc  -triple xtensa < %s 2>&1 | FileCheck %s
+
+# Out of range immediates
+
+LBL0:
+
+# imm8
+addi a1, a2, 300
+# CHECK:      error: expected immediate in range [-128, 127]
+
+addi a1, a2, -129
+# CHECK:      error: expected immediate in range [-128, 127]
+
+# imm8_sh8
+addmi a1, a2, 33
+# CHECK:      error: expected immediate in range [-32768, 32512], first 8 bits should be zero
+
+# Invalid number of operands
+addi a1, a2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
+addi a1, a2, 4, 4 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction
+
+# Invalid mnemonics
+aaa a10, a12 # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
+
+# Invalid operand types
+and sp, a2, 10 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+addi sp, a1, a2 # CHECK: :[[@LINE]]:14: error: expected immediate in range [-128, 127]
+
+# Invalid register names
+# Instruction format RRR
+or r2, sp, a3 # CHECK: :[[@LINE]]:4: error: invalid operand for instruction
+and a1, r10, a3 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+sub a1, sp, a100 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
+# Instruction format RRI8
+addi a101, sp, 10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
+addi a1, r10, 10 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+
+# Invalid operands order
+# Instruction format RRI8
+addi a1, 10, a2 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction

llvm/test/MC/Xtensa/xtensa-memorder.s

+# RUN: llvm-mc %s -triple=xtensa -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+
+.align  4
+LBL0:
+
+# Instruction format RRR
+# CHECK-INST: extw
+# CHECK: encoding: [0xd0,0x20,0x00]
+extw
+
+# Instruction format RRR
+# CHECK-INST: memw
+# CHECK: encoding: [0xc0,0x20,0x00]
+memw

llvm/test/MC/Xtensa/xtensa-move.s

+# RUN: llvm-mc %s -triple=xtensa -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+
+.align  4
+LBL0:
+
+# Instruction format RRR
+# CHECK-INST: moveqz a2, a3, a4
+# CHECK: encoding: [0x40,0x23,0x83]
+moveqz a2, a3, a4
+
+# Instruction format RRR
+# CHECK-INST: movgez a3, a11, a12
+# CHECK: encoding: [0xc0,0x3b,0xb3]
+movgez a3, a11, a12
+
+# Instruction format RRR
+# CHECK-INST: movltz a7, a8, a9
+# CHECK: encoding: [0x90,0x78,0xa3]
+movltz a7, a8, a9
+
+# Instruction format RRR
+# CHECK-INST: movnez a10, a11, a12
+# CHECK: encoding: [0xc0,0xab,0x93]
+movnez a10, a11, a12

llvm/test/MC/Xtensa/xtensa-processor-control.s

+# RUN: llvm-mc %s -triple=xtensa -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+
+
+.align  4
+LBL0:
+
+# Instruction format RRR
+# CHECK-INST: dsync
+# CHECK: encoding: [0x30,0x20,0x00]
+dsync
+
+# Instruction format RRR
+# CHECK-INST: esync
+# CHECK: encoding: [0x20,0x20,0x00]
+esync
+
+# Instruction format RRR
+# CHECK-INST: isync
+# CHECK: encoding: [0x00,0x20,0x00]
+isync
+
+# Instruction format RRR
+# CHECK-INST: nop
+# CHECK: encoding: [0xf0,0x20,0x00]
+nop
+
+# Instruction format RRR
+# CHECK-INST: rsync
+# CHECK: encoding: [0x10,0x20,0x00]
+rsync