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Differential D62599

[AArch64][SVE2] Asm: support SVE2 store instructions
ClosedPublic

Authored by c-rhodes on May 29 2019, 8:21 AM.

Details

Reviewers
sdesmalen
SjoerdMeijer
rovka
chill
Commits
rG2e870011b620: [AArch64][SVE2] Asm: support SVE2 store instructions
rL362213: [AArch64][SVE2] Asm: support SVE2 store instructions
Summary

Patch adds support for the following instructions:

  • STNT1B, STNT1H, STNT1S, STNT1D

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Diff Detail

Repository
rL LLVM

Event Timeline

c-rhodes created this revision.May 29 2019, 8:21 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 29 2019, 8:21 AM
Herald added subscribers: kristof.beyls, tschuett, javed.absar. · View Herald Transcript
c-rhodes added a parent revision: D62530: [AArch64][SVE2] Asm: support SVE2 vector splice (constructive).May 29 2019, 8:22 AM
c-rhodes added a child revision: D62600: [AArch64][SVE2] Asm: support TBL/TBX instructions.May 29 2019, 8:26 AM
chill added inline comments.May 29 2019, 10:49 AM
test/MC/AArch64/SVE/stnt1b-diagnostics.s
26 ↗(On Diff #201921)

Is my understanding correct that we're interpreting an alias in a different way, but this happens only on error?

c-rhodes added inline comments.May 30 2019, 2:16 AM
test/MC/AArch64/SVE/stnt1b-diagnostics.s
26 ↗(On Diff #201921)

The error has changed because a vector plus scalar form of stnt1b has been added and it's being matched differently.

stnt1b z0.s, p0, [x0] is now valid until the base [x0], the following output from the asm-matcher might better explain it:

Before

echo "stnt1b z0.s, p0, [x0]" | ./bin/llvm-mc -triple aarch64 -mattr=+sve2 -debug-only=asm-matcher
        .text
AsmMatcher: found 6 encodings with mnemonic 'stnt1b'
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 245>): Opcode result: multiple operand mismatches, ignoring this opcode
<stdin>:1:8: error: invalid element width
stnt1b z0.s, p0, [x0]
       ^

After

echo "stnt1b z0.s, p0, [x0]" | ./bin/llvm-mc -triple aarch64 -mattr=+sve2 -debug-only=asm-matcher                                                                                                               
        .text
AsmMatcher: found 16 encodings with mnemonic 'stnt1b'
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 1 (<register 246>): match success using generic matcher
  Matching formal operand class MCK_SVEPredicate3bAnyReg against actual operand at index 2 (<register 106>): match success using generic matcher
  Matching formal operand class MCK__91_ against actual operand at index 3 ('['): match success using generic matcher
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 4 (<register 217>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorDReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorList132 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorList164 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 1 (<register 246>): match success using generic matcher
  Matching formal operand class MCK_SVEPredicate3bAnyReg against actual operand at index 2 (<register 106>): match success using generic matcher
  Matching formal operand class MCK__91_ against actual operand at index 3 ('['): match success using generic matcher
  Matching formal operand class MCK_SVEVectorSReg against actual operand at index 4 (<register 217>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorDReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRR
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorList132 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_S_REAL
  Matching formal operand class MCK_SVEVectorList132 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorList164 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZZR_D_REAL
  Matching formal operand class MCK_SVEVectorList164 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorBReg against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
Trying to match opcode STNT1B_ZRI
  Matching formal operand class MCK_SVEVectorList18 against actual operand at index 1 (<register 246>): Opcode result: multiple operand mismatches, ignoring this opcode
<stdin>:1:19: error: invalid operand for instruction
stnt1b z0.s, p0, [x0]
                  ^
chill accepted this revision.May 30 2019, 2:48 AM

LGTM

This revision is now accepted and ready to land.May 30 2019, 2:48 AM
Closed by commit rL362213: [AArch64][SVE2] Asm: support SVE2 store instructions (authored by c-rhodes). · Explain WhyMay 31 2019, 1:58 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
10 lines
37 lines
test/
MC/
AArch64/
SVE/
4 lines
SVE2/
82 lines
80 lines
82 lines
44 lines
82 lines
80 lines
82 lines
80 lines

Diff 202392

llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 1,351 Lines • ▼ Show 20 Lineslet Predicates = [HasSVE2] in {
defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice">; defm SPLICE_ZPZZ : sve2_int_perm_splice_cons<"splice">;
// Predicated shifts // Predicated shifts
defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">; defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">; defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">; defm SRSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">; defm URSHR_ZPmI : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">; defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
// Non-temporal contiguous stores (vector + register)
defm STNT1B_ZZR_S : sve2_mem_cstnt_vs<0b001, "stnt1b", Z_s, ZPR32>;
defm STNT1H_ZZR_S : sve2_mem_cstnt_vs<0b011, "stnt1h", Z_s, ZPR32>;
defm STNT1W_ZZR_S : sve2_mem_cstnt_vs<0b101, "stnt1w", Z_s, ZPR32>;
defm STNT1B_ZZR_D : sve2_mem_cstnt_vs<0b000, "stnt1b", Z_d, ZPR64>;
defm STNT1H_ZZR_D : sve2_mem_cstnt_vs<0b010, "stnt1h", Z_d, ZPR64>;
defm STNT1W_ZZR_D : sve2_mem_cstnt_vs<0b100, "stnt1w", Z_d, ZPR64>;
defm STNT1D_ZZR_D : sve2_mem_cstnt_vs<0b110, "stnt1d", Z_d, ZPR64>;
} }
let Predicates = [HasSVE2AES] in { let Predicates = [HasSVE2AES] in {
// SVE2 crypto destructive binary operations // SVE2 crypto destructive binary operations
def AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8>; def AESE_ZZZ_B : sve2_crypto_des_bin_op<0b00, "aese", ZPR8>;
def AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8>; def AESD_ZZZ_B : sve2_crypto_des_bin_op<0b01, "aesd", ZPR8>;
// SVE2 crypto unary operations // SVE2 crypto unary operations
Show All 30 Lines

llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td

Show First 20 Lines • Show All 3,821 Lines • ▼ Show 20 Lines
multiclass sve_mem_cstnt_ss<bits<2> msz, string asm, RegisterOperand listty, multiclass sve_mem_cstnt_ss<bits<2> msz, string asm, RegisterOperand listty,
ZPRRegOp zprty, RegisterOperand gprty> { ZPRRegOp zprty, RegisterOperand gprty> {
def NAME : sve_mem_cstnt_ss_base<msz, asm, listty, gprty>; def NAME : sve_mem_cstnt_ss_base<msz, asm, listty, gprty>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]", def : InstAlias<asm # "\t$Zt, $Pg, [$Rn, $Rm]",
(!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>; (!cast<Instruction>(NAME) zprty:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, gprty:$Rm), 0>;
} }
class sve2_mem_cstnt_vs_base<bits<3> opc, dag iops, string asm,
RegisterOperand VecList>
: I<(outs VecList:$Zt), iops,
asm, "\t$Zt, $Pg, [$Zn, $Rm]",
"",
[]>, Sched<[]> {
bits<3> Pg;
bits<5> Rm;
bits<5> Zn;
bits<5> Zt;
let Inst{31-25} = 0b1110010;
let Inst{24-22} = opc;
let Inst{21} = 0b0;
let Inst{20-16} = Rm;
let Inst{15-13} = 0b001;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zt;
let mayStore = 1;
}
multiclass sve2_mem_cstnt_vs<bits<3> opc, string asm,
RegisterOperand listty, ZPRRegOp zprty> {
def _REAL : sve2_mem_cstnt_vs_base<opc, (ins PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm),
asm, listty>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
(!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
(!cast<Instruction>(NAME # _REAL) zprty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 0>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $Rm]",
(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, GPR64:$Rm), 0>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
(!cast<Instruction>(NAME # _REAL) listty:$Zt, PPR3bAny:$Pg, zprty:$Zn, XZR), 1>;
}
class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm, class sve_mem_sst_sv<bits<3> opc, bit xs, bit scaled, string asm,
RegisterOperand VecList, RegisterOperand zprext> RegisterOperand VecList, RegisterOperand zprext>
: I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm), : I<(outs), (ins VecList:$Zt, PPR3bAny:$Pg, GPR64sp:$Rn, zprext:$Zm),
asm, "\t$Zt, $Pg, [$Rn, $Zm]", asm, "\t$Zt, $Pg, [$Rn, $Zm]",
"", "",
[]>, Sched<[]> { []>, Sched<[]> {
bits<3> Pg; bits<3> Pg;
bits<5> Rn; bits<5> Rn;
▲ Show 20 Lines • Show All 1,783 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AArch64/SVE/stnt1b-diagnostics.s

Show All 17 Lines
// Invalid source type. // Invalid source type.
stnt1b z0.h, p0, [x0] stnt1b z0.h, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1b z0.h, p0, [x0] // CHECK-NEXT: stnt1b z0.h, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b z0.s, p0, [x0] stnt1b z0.s, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b z0.s, p0, [x0] // CHECK-NEXT: stnt1b z0.s, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b z0.d, p0, [x0] stnt1b z0.d, p0, [x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b z0.d, p0, [x0] // CHECK-NEXT: stnt1b z0.d, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------// // --------------------------------------------------------------------------//
// invalid predicate // invalid predicate
stnt1b z27.b, p8, [x0] stnt1b z27.b, p8, [x0]
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AArch64/SVE2/stnt1b-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
stnt1b { z0.b }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b { z0.b }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b { z0.h }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b { z0.h }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
stnt1b { z0.s }, p0, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1b { z0.s }, p0, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b { z0.d }, p0, [z0.h]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.h]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
stnt1b { z0.d }, p0, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
stnt1b { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: stnt1b { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
stnt1b { }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: stnt1b { }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b { z0.d, z1.d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b { z0.d, z1.d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1b { v0.2d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1b { v0.2d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
stnt1b { z0.d }, p0, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1b { z0.d }, p0, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1b { z0.s }, p0, [z0.s, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1b { z0.s }, p0, [z0.s, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE2/stnt1b.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
stnt1b z0.s, p0, [z1.s]
// CHECK-INST: stnt1b { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0x5f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 5f e4 <unknown>
stnt1b z31.s, p7, [z31.s, xzr]
// CHECK-INST: stnt1b { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 5f e4 <unknown>
stnt1b z31.s, p7, [z31.s, x0]
// CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0x40,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 40 e4 <unknown>
stnt1b z0.d, p0, [z1.d]
// CHECK-INST: stnt1b { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x1f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 1f e4 <unknown>
stnt1b z31.d, p7, [z31.d, xzr]
// CHECK-INST: stnt1b { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 1f e4 <unknown>
stnt1b z31.d, p7, [z31.d, x0]
// CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x00,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 00 e4 <unknown>
stnt1b { z0.s }, p0, [z1.s]
// CHECK-INST: stnt1b { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0x5f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 5f e4 <unknown>
stnt1b { z31.s }, p7, [z31.s, xzr]
// CHECK-INST: stnt1b { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 5f e4 <unknown>
stnt1b { z31.s }, p7, [z31.s, x0]
// CHECK-INST: stnt1b { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0x40,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 40 e4 <unknown>
stnt1b { z0.d }, p0, [z1.d]
// CHECK-INST: stnt1b { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x1f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 1f e4 <unknown>
stnt1b { z31.d }, p7, [z31.d, xzr]
// CHECK-INST: stnt1b { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 1f e4 <unknown>
stnt1b { z31.d }, p7, [z31.d, x0]
// CHECK-INST: stnt1b { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x00,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 00 e4 <unknown>

llvm/trunk/test/MC/AArch64/SVE2/stnt1d-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
stnt1d { z0.b }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { z0.b }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1d { z0.h }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { z0.h }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1d { z0.s }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { z0.s }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
stnt1d { z0.d }, p0, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
stnt1d { z0.d }, p0, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
stnt1d { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: stnt1d { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
stnt1d { }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: stnt1d { }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1d { z0.d, z1.d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { z0.d, z1.d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1d { v0.2d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1d { v0.2d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
stnt1d { z0.d }, p0, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1d { z0.d }, p0, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1d { z0.d }, p0, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE2/stnt1d.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
stnt1d z0.d, p0, [z1.d]
// CHECK-INST: stnt1d { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x9f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 9f e5 <unknown>
stnt1d z31.d, p7, [z31.d, xzr]
// CHECK-INST: stnt1d { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 9f e5 <unknown>
stnt1d z31.d, p7, [z31.d, x0]
// CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x80,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 80 e5 <unknown>
stnt1d { z0.d }, p0, [z1.d]
// CHECK-INST: stnt1d { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x9f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 9f e5 <unknown>
stnt1d { z31.d }, p7, [z31.d, xzr]
// CHECK-INST: stnt1d { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 9f e5 <unknown>
stnt1d { z31.d }, p7, [z31.d, x0]
// CHECK-INST: stnt1d { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x80,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 80 e5 <unknown>

llvm/trunk/test/MC/AArch64/SVE2/stnt1h-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
stnt1h { z0.b }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1h { z0.b }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1h { z0.h }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1h { z0.h }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
stnt1h { z0.s }, p0, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1h { z0.s }, p0, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1h { z0.d }, p0, [z0.h]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.h]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
stnt1h { z0.d }, p0, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
stnt1h { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: stnt1h { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
stnt1h { }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: stnt1h { }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1h { z0.d, z1.d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1h { z0.d, z1.d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1h { v0.2d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1h { v0.2d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
stnt1h { z0.d }, p0, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1h { z0.d }, p0, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1h { z0.s }, p0, [z0.s, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1h { z0.s }, p0, [z0.s, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE2/stnt1h.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
stnt1h z0.s, p0, [z1.s]
// CHECK-INST: stnt1h { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0xdf,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 df e4 <unknown>
stnt1h z31.s, p7, [z31.s, xzr]
// CHECK-INST: stnt1h { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f df e4 <unknown>
stnt1h z31.s, p7, [z31.s, x0]
// CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f c0 e4 <unknown>
stnt1h z0.d, p0, [z1.d]
// CHECK-INST: stnt1h { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x9f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 9f e4 <unknown>
stnt1h z31.d, p7, [z31.d, xzr]
// CHECK-INST: stnt1h { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 9f e4 <unknown>
stnt1h z31.d, p7, [z31.d, x0]
// CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x80,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 80 e4 <unknown>
stnt1h { z0.s }, p0, [z1.s]
// CHECK-INST: stnt1h { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0xdf,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 df e4 <unknown>
stnt1h { z31.s }, p7, [z31.s, xzr]
// CHECK-INST: stnt1h { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0xdf,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f df e4 <unknown>
stnt1h { z31.s }, p7, [z31.s, x0]
// CHECK-INST: stnt1h { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0xc0,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f c0 e4 <unknown>
stnt1h { z0.d }, p0, [z1.d]
// CHECK-INST: stnt1h { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x9f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 9f e4 <unknown>
stnt1h { z31.d }, p7, [z31.d, xzr]
// CHECK-INST: stnt1h { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x9f,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 9f e4 <unknown>
stnt1h { z31.d }, p7, [z31.d, x0]
// CHECK-INST: stnt1h { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x80,0xe4]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 80 e4 <unknown>

llvm/trunk/test/MC/AArch64/SVE2/stnt1w-diagnostics.s

// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// --------------------------------------------------------------------------//
// Invalid result type.
stnt1w { z0.b }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1w { z0.b }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1w { z0.h }, p0, [z0.s]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1w { z0.h }, p0, [z0.s]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid base vector.
stnt1w { z0.s }, p0, [z0.b]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1w { z0.s }, p0, [z0.b]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1w { z0.d }, p0, [z0.h]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.h]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid offset type.
stnt1w { z0.d }, p0, [z0.d, z1.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.d, z1.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// restricted predicate has range [0, 7].
stnt1w { z27.d }, p8, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: stnt1w { z27.d }, p8, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector list.
stnt1w { }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: stnt1w { }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1w { z0.d, z1.d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1w { z0.d, z1.d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
stnt1w { v0.2d }, p0, [z0.d]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: stnt1w { v0.2d }, p0, [z0.d]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Negative tests for instructions that are incompatible with movprfx
movprfx z0.d, p0/z, z7.d
stnt1w { z0.d }, p0, [z0.d, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1w { z0.d }, p0, [z0.d, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
movprfx z0, z7
stnt1w { z0.s }, p0, [z0.s, x0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
// CHECK-NEXT: stnt1w { z0.s }, p0, [z0.s, x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/trunk/test/MC/AArch64/SVE2/stnt1w.s

// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
stnt1w z0.s, p0, [z1.s]
// CHECK-INST: stnt1w { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0x5f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 5f e5 <unknown>
stnt1w z31.s, p7, [z31.s, xzr]
// CHECK-INST: stnt1w { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 5f e5 <unknown>
stnt1w z31.s, p7, [z31.s, x0]
// CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0x40,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 40 e5 <unknown>
stnt1w z0.d, p0, [z1.d]
// CHECK-INST: stnt1w { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x1f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 1f e5 <unknown>
stnt1w z31.d, p7, [z31.d, xzr]
// CHECK-INST: stnt1w { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 1f e5 <unknown>
stnt1w z31.d, p7, [z31.d, x0]
// CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x00,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 00 e5 <unknown>
stnt1w { z0.s }, p0, [z1.s]
// CHECK-INST: stnt1w { z0.s }, p0, [z1.s]
// CHECK-ENCODING: [0x20,0x20,0x5f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 5f e5 <unknown>
stnt1w { z31.s }, p7, [z31.s, xzr]
// CHECK-INST: stnt1w { z31.s }, p7, [z31.s]
// CHECK-ENCODING: [0xff,0x3f,0x5f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 5f e5 <unknown>
stnt1w { z31.s }, p7, [z31.s, x0]
// CHECK-INST: stnt1w { z31.s }, p7, [z31.s, x0]
// CHECK-ENCODING: [0xff,0x3f,0x40,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 40 e5 <unknown>
stnt1w { z0.d }, p0, [z1.d]
// CHECK-INST: stnt1w { z0.d }, p0, [z1.d]
// CHECK-ENCODING: [0x20,0x20,0x1f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: 20 20 1f e5 <unknown>
stnt1w { z31.d }, p7, [z31.d, xzr]
// CHECK-INST: stnt1w { z31.d }, p7, [z31.d]
// CHECK-ENCODING: [0xff,0x3f,0x1f,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 1f e5 <unknown>
stnt1w { z31.d }, p7, [z31.d, x0]
// CHECK-INST: stnt1w { z31.d }, p7, [z31.d, x0]
// CHECK-ENCODING: [0xff,0x3f,0x00,0xe5]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff 3f 00 e5 <unknown>