[PPC32] Improve the 32-bit PowerPC port

[MaskRay]

Summary

Many -static/-no-pie/-shared/-pie applications linked against glibc or musl
should work with this patch. This also helps FreeBSD PowerPC64 to migrate
their lib32 (PR40888).

• Fix default image base and max page size.
• Support new-style Secure PLT (see below). Old-style BSS PLT is not implemented, so it is not suitable for FreeBSD rtld now because it doesn't support Secure PLT yet.
• Support more initial relocation types: R_PPC_ADDR32, R_PPC_REL16*, R_PPC_LOCAL24PC, R_PPC_PLTREL24, and R_PPC_GOT16. The addend of R_PPC_PLTREL24 is special: it decides the call stub PLT type but it should be ignored for the computation of target symbol VA.
• Support GNU ifunc
• Support .glink used for lazy PLT resolution in glibc
• Add a new thunk type: PPC32PltCallStub that is similar to PPC64PltCallStub. It is used by R_PPC_REL24 and R_PPC_PLTREL24.

A PLT stub used in -fPIE/-fPIC usually loads an address relative to
.got2+0x8000 (-fpie/-fpic code uses _GLOBAL_OFFSET_TABLE_ relative
addresses).
Two .got2 sections in two object files have different addresses, thus a PLT stub
can't be shared by two object files. To handle this incompatibility,
change the parameters of Thunk::isCompatibleWith to
const InputSection &, const Relocation &.

PowerPC psABI specified an old-style .plt (BSS PLT) that is both
writable and executable. Linkers don't make separate RW- and RWE segments,
which causes all initially writable memory (think .data) executable.
This is a big security concern so a new PLT scheme (secure PLT) was developed to
address the security issue.

TLS will be implemented in D62940.

glibc older than ~2012 requires .rela.dyn to include .rela.plt, it can
not handle the DT_RELA+DT_RELASZ == DT_JMPREL case correctly. A hack
(not included in this patch) in LinkerScript.cpp addOrphanSections() is
required:

if (Config->EMachine == EM_PPC) {
  // Older glibc assumes .rela.dyn includes .rela.plt
  Add(In.RelaDyn);
  if (In.RelaPlt->isLive() && !In.RelaPlt->Parent)
    In.RelaDyn->getParent()->addSection(In.RelaPlt);
}

[MaskRay]

Fix a typo

[ruiu]

I think that the commit message is a bit too terse. Could you explain the current status of ppc32 if you can? How much is it usable and how much does this patch improve?

[MaskRay]

.

[MaskRay]

Reword

[ruiu]

Generally looking great.

ELF/Options.td

30

nit: powerpc32 → PowerPC32

311

Ditto

ELF/SyntheticSections.cpp

1039

Can you add return here? Or maybe you want to make this a switch whose each "case" ends with a return.

1052

This magic number needs a comment.

2275

nit: add parentheses before ?.

3236

Can you add a comment?

[MaskRay]

Add some support for BSS-PLT ABI

Will add some more tests.

[MaskRay]

ELF/SyntheticSections.cpp

2275

I think PowerPC32 doesn't need .glink. I'll just delete this change.

[MaskRay]

Address review comments

[ruiu]

What is a motivation to support the old-style PLT? If a program really expects that the PLT is in a writable segment, something is wrong with the program...

[MaskRay]

In D62464#1529079, @ruiu wrote:

What is a motivation to support the old-style PLT? If a program really expects that the PLT is in a writable segment, something is wrong with the program...

I didn't want to support BSS PLT (old-style PLT).

For Secure PLT, I can get musl -no-pie/-pie/-shared and glibc -no-pie work with this patch.

For BSS PLT, because musl doesn't support it, I have to debug glibc in qemu-system-ppc -hda debian_wheezy_powerpc_standard.qcow2, which is a pain... (glibc cannot be compiled without -O2 => the quality of debug info is at gcc's mercy).

On FreeBSD's side, I believe its rtld doesn't support Secure PLT.

@adalava @emaste It would be great if you can migrate from BSS PLT to Secure PLT (-msecure-plt; default in gcc if it is configured with --enable-secure-plt; many Linux gcc packages are configured this way).

[MaskRay]

Ready for review.

Many -no-pie/-pie/-shared linked against musl or glibc should work now.

[ruiu]

ELF/Arch/PPC.cpp

110

Is this a nop? Can you add a comment?

ELF/SyntheticSections.cpp

2290

Hmm, so we don't call writePlt() if a target is PPC32?

ELF/Thunks.cpp

241

nit: usually we write public members before private members.

700

nit: flip the condition and return early so that the indentation is one level shallower?

708–709

format.

[MaskRay]

ELF/SyntheticSections.cpp

2290

On PPC32, how PLT works is different from targets (it is still similar to PPC64). I've added more comments in PPC::writePltHeader.

[MaskRay]

Address review comments

[ruiu]

ELF/SyntheticSections.cpp

2290

So, this is not really a PLT header but a PPC32-specific mechanism. Is writePltHeader a correct name? Maybe we should rename this writePPC32PltResolver or something like that?

[MaskRay]

Also add R_PPC_ADDR16

[MaskRay]

ELF/SyntheticSections.cpp

2290

.glink is indeed a PPC-specific mechanism (PPC64 moves the "footer" (PLTresolve) to the "header" so it looks more conventional).

The PPC class is in an unnamed namespace so I cannot access it from SyntheticSections.cpp. If you still think writePPC32PltResolver is the way to go, I can extract it from the class and place it into the lld::elf:: namespace. I still feel it may not worth the trouble.

namespace {
class PPC final : public TargetInfo {
public:
...
  void writePltHeader(uint8_t *Buf) const override;

[ruiu]

ELF/SyntheticSections.cpp

2290

I feel like a PPC32-specific knowledge such as the actual machine instruction code leaks here, which is I think not ideal. How about moving the code to write b PLTresolve to writePltHeader and rename it writePPC32PltSection? Currently, a concrete implementation to write the first half of PPC32's PLT section is in this function while the other is in writePltHeader, which is not actually a header but a trailer. Nothing is really complicated, but there are perhaps too many things that are slightly confusing.

[MaskRay]

Add Target::writePPC32PltSection and let PPC::writePPC32PltSection override it.
This is to isolate the PPC32 knowledge.

[ruiu]

ELF/Arch/PPC.cpp

32

To make it clear that we write a PLT section in a different way, I'd define writePlt and writePltHeader which just call llvm_unreachable().

ELF/Target.h

45 ↗

(On Diff #203295)

This function doesn't have to be in this class because no dynamic dispatching is necessary. Only PPC32 implements this as its name implies. I'd make this a non-member function.

[MaskRay]

Forgot to add Buf += 4 * NumEntries;

[MaskRay]

Remove Target::writePPC32GlinkSection()
Add elf::writePPC32GlinkSection()

[ruiu]

LGTM

[MaskRay]

I cross compiled libc-test with powerpc-linux-gnu-gcc + lld.

% cd ~/libc-test # config.mak is below
% make > /tmp/libc-test.lld
# /tmp/libc-test.bfd was created in a similar way
% grep -c FAIL /tmp/libc-test.bfd /tmp/libc-test.lld
/tmp/libc-test.bfd:112
/tmp/libc-test.lld:112

So lld linked libc-test doesn't have more failures than bfd linked libc-test :)
(Tests ran under qemu-static-ppc. The situation may get better on real hardware.)

CROSS_COMPILE=powerpc-linux-gnu-
CFLAGS += -mlong-double-64 -msecure-plt
CC = powerpc-linux-gnu-gcc

CFLAGS += -specs ~/musl/powerpc/lib/musl-gcc.specs
LDFLAGS += -specs ~/musl/powerpc/lib/musl-gcc.specs
...
LDFLAGS += -fuse-ld=gold -g  # my /usr/powerpc-linux-gnu/bin/ld.gold points to lld... gcc 9 starts to understand -fuse-ld=lld

[MaskRay]

Implement R_PPC_GLOB_DAT and improve a R_PPC_GOT16 test while testing libc-test with glibc

[adalava]

Great job, @MaskRay !!

By initial tests, it seems that the PPC 32 bit FreeBSD "loader/bootloader" is now working fine when compiled with clang-8 and linked with LLD-9 with this patch. It is a static-stand-alone binary that doesn't depend on *crt*stuff.

For the 32 compatibility packages I now receive the error: "<unknown>:0: error: Undefined temporary symbol" when compiling everything with -msecure-plt. I'll retest with D62940 patch applyed

[MaskRay]

Add more tests

ELF/Arch/PPC.cpp

 //===- PPC.cpp ------------------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
+#include "OutputSections.h"
 #include "Symbols.h"
+#include "SyntheticSections.h"
 #include "Target.h"
 #include "lld/Common/ErrorHandler.h"
 #include "llvm/Support/Endian.h"
 
 using namespace llvm;
 using namespace llvm::support::endian;
 using namespace llvm::ELF;
 using namespace lld;
 using namespace lld::elf;
 
 namespace {
 class PPC final : public TargetInfo {
 public:
   PPC();
+  void writeGotHeader(uint8_t *Buf) const override;
+  bool needsThunk(RelExpr Expr, RelType RelocType, const InputFile *File,
+                  uint64_t BranchAddr, const Symbol &S) const override;
+  uint32_t getThunkSectionSpacing() const override;
+  bool inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const override;
   void relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const override;
   RelExpr getRelExpr(RelType Type, const Symbol &S,
                      const uint8_t *Loc) const override;
 };
 } // namespace
 
 PPC::PPC() {
+  GotRel = R_PPC_GLOB_DAT;
   NoneRel = R_PPC_NONE;
+  PltRel = R_PPC_JMP_SLOT;
+  RelativeRel = R_PPC_RELATIVE;
   GotBaseSymInGotPlt = false;
+  RelativeRel = R_PPC_RELATIVE;
+  GotHeaderEntriesNum = Config->SecurePlt ? 3 : 4;
+  GotPltHeaderEntriesNum = 0;
+
+  NeedsThunks = true;
+
+  DefaultMaxPageSize = 65536;
+  DefaultImageBase = 0x10000000;
+
+  write32(TrapInstr.data(), 0x7fe00008);
+}
+
+void PPC::writeGotHeader(uint8_t *Buf) const {
+  if (!Config->SecurePlt) {
+    // _GLOBAL_OFFSET_TABLE[-1] = blrl
+    write32(Buf, 0x4e800021);
+    Buf += 4;
+  }
+
+  // _GLOBAL_OFFSET_TABLE_[0] = _DYNAMIC
+  write32(Buf, In.Dynamic->getVA());
+  // _GLOBAL_OFFSET_TABLE_[1,2] are reserved.
+}
+
+bool PPC::needsThunk(RelExpr Expr, RelType Type, const InputFile *File,
+                     uint64_t BranchAddr, const Symbol &S) const {
+  if (!Config->SecurePlt || (Type != R_PPC_REL24 && Type != R_PPC_PLTREL24))
+    return false;
+  return Expr == R_PLT_PC || !PPC::inBranchRange(Type, BranchAddr, S.getVA());
+}
+
+uint32_t PPC::getThunkSectionSpacing() const { return 0x2000000; }
+
+bool PPC::inBranchRange(RelType Type, uint64_t Src, uint64_t Dst) const {
+  uint64_t Offset = Dst - Src;
+  if (Type == R_PPC_REL24 || R_PPC_PLTREL24)
+    return isInt<26>(Offset);
+  llvm_unreachable("unsupported relocation type used in branch");
 }
 
 RelExpr PPC::getRelExpr(RelType Type, const Symbol &S,
                         const uint8_t *Loc) const {
   switch (Type) {
   case R_PPC_REL14:
-  case R_PPC_REL24:
   case R_PPC_REL32:
+  case R_PPC_LOCAL24PC:
+  case R_PPC_REL16_LO:
+  case R_PPC_REL16_HI:
+  case R_PPC_REL16_HA:
     return R_PC;
+  case R_PPC_GOT16:
+    return R_GOT_OFF;
+  case R_PPC_REL24:
   case R_PPC_PLTREL24:
     return R_PLT_PC;
   default:
     return R_ABS;
   }
 }
 
 void PPC::relocateOne(uint8_t *Loc, RelType Type, uint64_t Val) const {
   switch (Type) {
   case R_PPC_ADDR16_HA:
-    write16be(Loc, (Val + 0x8000) >> 16);
+  case R_PPC_REL16_HA:
+    write16(Loc, (Val + 0x8000) >> 16);
     break;
   case R_PPC_ADDR16_HI:
-    write16be(Loc, Val >> 16);
+  case R_PPC_REL16_HI:
+    write16(Loc, Val >> 16);
     break;
   case R_PPC_ADDR16_LO:
-    write16be(Loc, Val);
+  case R_PPC_REL16_LO:
+    write16(Loc, Val);
     break;
   case R_PPC_ADDR32:
   case R_PPC_REL32:
-    write32be(Loc, Val);
+    write32(Loc, Val);
     break;
-  case R_PPC_REL14:
-    write32be(Loc, read32be(Loc) | (Val & 0xFFFC));
+  case R_PPC_REL14: {
+    uint32_t Mask = 0x0000FFFC;
+    checkInt(Loc, Val, 16, Type);
+    checkAlignment(Loc, Val, 4, Type);
+    write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
+    break;
+  }
+  case R_PPC_GOT16:
+    checkInt(Loc, Val, 16, Type);
+    write16(Loc, Val);
     break;
-  case R_PPC_PLTREL24:
   case R_PPC_REL24:
-    write32be(Loc, read32be(Loc) | (Val & 0x3FFFFFC));
+  case R_PPC_LOCAL24PC:
+  case R_PPC_PLTREL24: {
+    uint32_t Mask = 0x03FFFFFC;
+    if (Type == R_PPC_PLTREL24 && Config->SecurePlt)
+      Val -= 0x8000;
+    checkInt(Loc, Val, 26, Type);
+    checkAlignment(Loc, Val, 4, Type);
+    write32(Loc, (read32(Loc) & ~Mask) | (Val & Mask));
     break;
+  }
   default:
     error(getErrorLocation(Loc) + "unrecognized relocation " + toString(Type));
   }
 }
 
 TargetInfo *elf::getPPCTargetInfo() {
   static PPC Target;
   return &Target;
 }

ELF/Config.h

struct Configuration {
   bool OptRemarksWithHotness;
   bool PicThunk;
   bool Pie;
   bool PrintGcSections;
   bool PrintIcfSections;
   bool Relocatable;
   bool RelrPackDynRelocs;
   bool SaveTemps;
+  bool SecurePlt;
   bool SingleRoRx;
   bool Shared;
   bool Static = false;
   bool SysvHash = false;
   bool Target1Rel;
   bool Trace;
   bool ThinLTOEmitImportsFiles;
   bool ThinLTOIndexOnly;

ELF/Driver.cpp

Config->PrintGcSections =
       Args.hasFlag(OPT_print_gc_sections, OPT_no_print_gc_sections, false);
   Config->PrintSymbolOrder =
       Args.getLastArgValue(OPT_print_symbol_order);
   Config->Rpath = getRpath(Args);
   Config->Relocatable = Args.hasArg(OPT_relocatable);
   Config->SaveTemps = Args.hasArg(OPT_save_temps);
   Config->SearchPaths = args::getStrings(Args, OPT_library_path);
   Config->SectionStartMap = getSectionStartMap(Args);
+  Config->SecurePlt = Args.hasArg(OPT_secure_plt, OPT_bss_plt, false);
   Config->Shared = Args.hasArg(OPT_shared);
   Config->SingleRoRx = Args.hasArg(OPT_no_rosegment);
   Config->SoName = Args.getLastArgValue(OPT_soname);
   Config->SortSection = getSortSection(Args);
   Config->SplitStackAdjustSize = args::getInteger(Args, OPT_split_stack_adjust_size, 16384);
   Config->Strip = getStrip(Args);
   Config->Sysroot = Args.getLastArgValue(OPT_sysroot);
   Config->Target1Rel = Args.hasFlag(OPT_target1_rel, OPT_target1_abs, false);

ELF/InputFiles.h

public:
   mutable std::string ToStringCache;
 
   std::string getSrcMsg(const Symbol &Sym, InputSectionBase &Sec,
                         uint64_t Offset);
 
   // True if this is an argument for --just-symbols. Usually false.
   bool JustSymbols = false;
 
+  // OutSecOff of .got2 in the current file. This is used by PPC32 secure PLT to
+  // compute offsets in PLT call stubs.
+  uint32_t PPC32Got2OutSecOff = 0;
+
   // On PPC64 we need to keep track of which files contain small code model
   // relocations that access the .toc section. To minimize the chance of a
   // relocation overflow, files that do contain said relocations should have
   // their .toc sections sorted closer to the .got section than files that do
   // not contain any small code model relocations. Thats because the toc-pointer
   // is defined to point at .got + 0x8000 and the instructions used with small
   // code model relocations support immediates in the range [-0x8000, 0x7FFC],
   // making the addressable range relative to the toc pointer

ELF/InputSection.cpp

case R_PC: {
     uint64_t Dest;
     if (Sym.isUndefWeak()) {
       // On ARM and AArch64 a branch to an undefined weak resolves to the
       // next instruction, otherwise the place.
       if (Config->EMachine == EM_ARM)
         Dest = getARMUndefinedRelativeWeakVA(Type, A, P);
       else if (Config->EMachine == EM_AARCH64)
         Dest = getAArch64UndefinedRelativeWeakVA(Type, A, P);
+      else if (Config->EMachine == EM_PPC && !Config->Pic)
+        Dest = Target->getImageBase();
       else
         Dest = Sym.getVA(A);
     } else {
       Dest = Sym.getVA(A);
     }
     return Dest - P;
   }
   case R_PLT:

ELF/Options.td

 
 def Bsymbolic_functions: F<"Bsymbolic-functions">,
   HelpText<"Bind defined function symbols locally">;
 
 def Bdynamic: F<"Bdynamic">, HelpText<"Link against shared libraries (default)">;
 
 def Bstatic: F<"Bstatic">, HelpText<"Do not link against shared libraries">;
 
+def bss_plt: F<"bss-plt">, HelpText<"Use old-style BSS PLT for PowerPC32">;
+
 def build_id: F<"build-id">, HelpText<"Alias for --build-id=fast">;
 
 def build_id_eq: J<"build-id=">, HelpText<"Generate build ID note">,
   MetaVarName<"[fast,md5,sha1,uuid,0x<hexstring>]">;
 
 defm check_sections: B<"check-sections",
     "Check section addresses for overlaps (default)",
     "Do not check section addresses for overlaps">;

 defm rpath: Eq<"rpath", "Add a DT_RUNPATH to the output">;
 
 def relocatable: F<"relocatable">, HelpText<"Create relocatable object file">;
 
 defm retain_symbols_file:
   Eq<"retain-symbols-file", "Retain only the symbols listed in the file">,
   MetaVarName<"<file>">;
 
+def secure_plt: F<"secure-plt">, HelpText<"Use new-style PLT for PowerPC32 (default)">;
+
 defm script: Eq<"script", "Read linker script">;
 
 defm section_start: Eq<"section-start", "Set address of section">,
   MetaVarName<"<address>">;
 
 def shared: F<"shared">, HelpText<"Build a shared object">;
 
 defm soname: Eq<"soname", "Set DT_SONAME">;

ELF/Relocations.cpp

In.RelaDyn->addReloc(Target->RelativeRel, IS, OffsetInSec, Sym, Addend, Expr,
                        Type);
 }
 
 template <class ELFT, class GotPltSection>
 static void addPltEntry(PltSection *Plt, GotPltSection *GotPlt,
                         RelocationBaseSection *Rel, RelType Type, Symbol &Sym) {
   Plt->addEntry<ELFT>(Sym);
   GotPlt->addEntry(Sym);
-  Rel->addReloc(
-      {Type, GotPlt, Sym.getGotPltOffset(), !Sym.IsPreemptible, &Sym, 0});
+  uint64_t Offset;
+  if (Config->EMachine == EM_PPC && !Config->SecurePlt) {
+    // PPC32 BSS-PLT ABI encodes PLT differently. See the comment in
+    // GotPltSection::getSize().
+    Offset = 72 + 8 * Sym.PltIndex;
+    if (Sym.PltIndex > 8192)
+      Offset += 4 * (Sym.PltIndex - 8192);
+  } else {
+    Offset = Sym.getGotPltOffset();
+  }
+  Rel->addReloc({Type, GotPlt, Offset, !Sym.IsPreemptible, &Sym, 0});
 }
 
 static void addGotEntry(Symbol &Sym) {
   In.Got->addEntry(Sym);
 
   RelExpr Expr = Sym.isTls() ? R_TLS : R_ABS;
   uint64_t Off = Sym.getGotOffset();
 
if (auto *D = dyn_cast<Defined>(&Sym))
     if (!D->isInPlt() && D->Section)
       ThunkVec = &ThunkedSymbolsBySection[{D->Section->Repl, D->Value}];
   if (!ThunkVec)
     ThunkVec = &ThunkedSymbols[&Sym];
 
   // Check existing Thunks for Sym to see if they can be reused
   for (Thunk *T : *ThunkVec)
     if (isThunkSectionCompatible(IS, T->getThunkTargetSym()->Section) &&
-        T->isCompatibleWith(Type) &&
+        T->isCompatibleWith(*IS, Type) &&
         Target->inBranchRange(Type, Src, T->getThunkTargetSym()->getVA()))
       return std::make_pair(T, false);
 
   // No existing compatible Thunk in range, create a new one
-  Thunk *T = addThunk(Type, Sym);
+  Thunk *T = addThunk(*IS, Type, Sym);
   ThunkVec->push_back(T);
   return std::make_pair(T, true);
 }
 
 // Return true if the relocation target is an in range Thunk.
 // Return false if the relocation is not to a Thunk. If the relocation target
 // was originally to a Thunk, but is no longer in range we revert the
 // relocation back to its original non-Thunk target.

ELF/SyntheticSections.h

 // header as its first entry that is used at run-time to resolve lazy binding.
 // The latter is used for GNU Ifunc symbols, that will be subject to a
 // Target->IRelativeRel.
 class PltSection : public SyntheticSection {
 public:
   PltSection(bool IsIplt);
   void writeTo(uint8_t *Buf) override;
   size_t getSize() const override;
-  bool isNeeded() const override { return !Entries.empty(); }
+  bool isNeeded() const override;
   void addSymbols();
   template <class ELFT> void addEntry(Symbol &Sym);
 
   size_t HeaderSize;
 
 private:
   std::vector<const Symbol *> Entries;
   bool IsIplt;
public:
   InputSection *getTargetInputSection() const;
   bool assignOffsets();
 
 private:
   std::vector<Thunk *> Thunks;
   size_t Size = 0;
 };
 
+// Used to compute OutSecOff of .got2 in each object file. This is needed to
+// synthesize PLT entries for PPC32 secure PLT ABI.
+class PPC32Got2Section final : public SyntheticSection {
+public:
+  PPC32Got2Section();
+  size_t getSize() const override { return 0; }
+  bool isNeeded() const override { return true; }
+  void finalizeContents() override;
+  void writeTo(uint8_t *Buf) override {}
+};
+
 // This section is used to store the addresses of functions that are called
 // in range-extending thunks on PowerPC64. When producing position dependant
 // code the addresses are link-time constants and the table is written out to
 // the binary. When producing position-dependant code the table is allocated and
 // filled in by the dynamic linker.
 class PPC64LongBranchTargetSection final : public SyntheticSection {
 public:
   PPC64LongBranchTargetSection();
struct InStruct {
   GotSection *Got;
   GotPltSection *GotPlt;
   IgotPltSection *IgotPlt;
   PPC64LongBranchTargetSection *PPC64LongBranchTarget;
   MipsGotSection *MipsGot;
   MipsRldMapSection *MipsRldMap;
   PltSection *Plt;
   PltSection *Iplt;
+  PPC32Got2Section *PPC32Got2;
   RelocationBaseSection *RelaDyn;
   RelrBaseSection *RelrDyn;
   RelocationBaseSection *RelaPlt;
   RelocationBaseSection *RelaIplt;
   StringTableSection *ShStrTab;
   StringTableSection *StrTab;
   SymbolTableBaseSection *SymTab;
   SymtabShndxSection *SymTabShndx;

ELF/SyntheticSections.cpp

void MipsGotSection::writeTo(uint8_t *Buf) {
   }
 }
 
 // On PowerPC the .plt section is used to hold the table of function addresses
 // instead of the .got.plt, and the type is SHT_NOBITS similar to a .bss
 // section. I don't know why we have a BSS style type for the section but it is
 // consitent across both 64-bit PowerPC ABIs as well as the 32-bit PowerPC ABI.
 GotPltSection::GotPltSection()
-    : SyntheticSection(SHF_ALLOC | SHF_WRITE,
-                       Config->EMachine == EM_PPC64 ? SHT_NOBITS : SHT_PROGBITS,
-                       Config->Wordsize,
-                       Config->EMachine == EM_PPC64 ? ".plt" : ".got.plt") {}
+    : SyntheticSection(SHF_ALLOC | SHF_WRITE, SHT_PROGBITS, Config->Wordsize,
+                       ".got.plt") {
+  if (Config->EMachine == EM_PPC) {
+    if (!Config->SecurePlt) {
+      Flags |= SHF_EXECINSTR;
+      Type = SHT_NOBITS;
+    }
+    Name = ".plt";
+  } else if (Config->EMachine == EM_PPC64) {
+    Type = SHT_NOBITS;
+    Name = ".plt";
+  }
+}
 
 void GotPltSection::addEntry(Symbol &Sym) {
   assert(Sym.PltIndex == Entries.size());
   Entries.push_back(&Sym);
 }
 
 size_t GotPltSection::getSize() const {
+  if (Config->EMachine == EM_PPC && !Config->SecurePlt) {
+    // In PPC32 BSS-PLT ABI, first 72 bytes are reserved for the dynamic loader.
+    // For the first 8192 entries, each needs 12 bytes. Other entries need 20
+    // bytes.
+    return 72 + 12 * Entries.size() +
+           (Entries.size() > 8192 ? 8 * (Entries.size() - 8192) : 0);
+  }
   return (Target->GotPltHeaderEntriesNum + Entries.size()) * Config->Wordsize;
 }
 
 void GotPltSection::writeTo(uint8_t *Buf) {
   Target->writeGotPltHeader(Buf);
   Buf += Target->GotPltHeaderEntriesNum * Config->Wordsize;
   for (const Symbol *B : Entries) {
     Target->writeGotPlt(Buf, *B);
if (In.MipsRldMap) {
       if (!Config->Pie)
         addInSec(DT_MIPS_RLD_MAP, In.MipsRldMap);
       // Store the offset to the .rld_map section
       // relative to the address of the tag.
       addInSecRelative(DT_MIPS_RLD_MAP_REL, In.MipsRldMap);
     }
   }
 
+  if (Config->EMachine == EM_PPC && Config->SecurePlt)
+    addInt(DT_LOPROC + 1, ElfSym::GlobalOffsetTable->getVA());
+
   // Glink dynamic tag is required by the V2 abi if the plt section isn't empty.
   if (Config->EMachine == EM_PPC64 && In.Plt->isNeeded()) {
     // The Glink tag points to 32 bytes before the first lazy symbol resolution
     // stub, which starts directly after the header.
     Entries.push_back({DT_PPC64_GLINK, [=] {
                          unsigned Offset = Target->PltHeaderSize - 32;
                          return In.Plt->getVA(0) + Offset;
                        }});

 }
 
 // On PowerPC64 the lazy symbol resolvers go into the `global linkage table`
 // in the .glink section, rather then the typical .plt section.
 PltSection::PltSection(bool IsIplt)
     : SyntheticSection(SHF_ALLOC | SHF_EXECINSTR, SHT_PROGBITS, 16,
                        Config->EMachine == EM_PPC64 ? ".glink" : ".plt"),
       HeaderSize(!IsIplt || Config->ZRetpolineplt ? Target->PltHeaderSize : 0),
       IsIplt(IsIplt) {
   // The PLT needs to be writable on SPARC as the dynamic linker will
   // modify the instructions in the PLT entries.
   if (Config->EMachine == EM_SPARCV9)
     this->Flags |= SHF_WRITE;
 }
 
 void PltSection::writeTo(uint8_t *Buf) {
   // At beginning of PLT or retpoline IPLT, we have code to call the dynamic
   // linker to resolve dynsyms at runtime. Write such code.
   if (HeaderSize)
     Target->writePltHeader(Buf);
   size_t Off = HeaderSize;
 
   RelocationBaseSection *RelSec = IsIplt ? In.RelaIplt : In.RelaPlt;
 
   // The IPlt is immediately after the Plt, account for this in RelOff
   size_t PltOff = IsIplt ? In.Plt->getSize() : 0;
 
   for (size_t I = 0, E = Entries.size(); I != E; ++I) {
     const Symbol *B = Entries[I];
     unsigned RelOff = RelSec->Entsize * I + PltOff;
     uint64_t Got = B->getGotPltVA();
     uint64_t Plt = this->getVA() + Off;
     Target->writePlt(Buf + Off, Got, Plt, B->PltIndex, RelOff);
     Off += Target->PltEntrySize;
   }
 }
 
 template <class ELFT> void PltSection::addEntry(Symbol &Sym) {
   Sym.PltIndex = Entries.size();
   Entries.push_back(&Sym);
 }
 
 size_t PltSection::getSize() const {
   return HeaderSize + Entries.size() * Target->PltEntrySize;
 }
 
+bool PltSection::isNeeded() const {
+  return Config->EMachine != EM_PPC && !Entries.empty();
+}
+
 // Some architectures such as additional symbols in the PLT section. For
 // example ARM uses mapping symbols to aid disassembly
 void PltSection::addSymbols() {
   // The PLT may have symbols defined for the Header, the IPLT has no header
   if (!IsIplt)
     Target->addPltHeaderSymbols(*this);
 
   size_t Off = HeaderSize;
for (Thunk *T : Thunks) {
     T->getThunkTargetSym()->Size = Size;
     Off += Size;
   }
   bool Changed = Off != Size;
   Size = Off;
   return Changed;
 }
 
+PPC32Got2Section::PPC32Got2Section()
+    : SyntheticSection(SHF_ALLOC | SHF_WRITE, SHT_PROGBITS, 4, ".got2") {}
+
+void PPC32Got2Section::finalizeContents() {
+  // In PIC code, PPC32 may have multiple GOT sections, one per file in .got2 .
+  // This function computes OutSecOff of each .got2 to be used in
+  // PPC32PltCallStub::writeTo(). The purpose of this empty synthetic section is
+  // to collect input sections named ".got2".
+  uint32_t Offset = 0;
+  for (BaseCommand *Base : getParent()->SectionCommands)
+    if (auto *ISD = dyn_cast<InputSectionDescription>(Base)) {
+      for (InputSection *IS : ISD->Sections) {
+        if (IS == this)
+          continue;
+        IS->File->PPC32Got2OutSecOff = Offset;
+        Offset += (uint32_t)IS->getSize();
+      }
+    }
+}
+
 // If linking position-dependent code then the table will store the addresses
 // directly in the binary so the section has type SHT_PROGBITS. If linking
 // position-independent code the section has type SHT_NOBITS since it will be
 // allocated and filled in by the dynamic linker.
 PPC64LongBranchTargetSection::PPC64LongBranchTargetSection()
     : SyntheticSection(SHF_ALLOC | SHF_WRITE,
                        Config->Pic ? SHT_NOBITS : SHT_PROGBITS, 8,
                        ".branch_lt") {}

ELF/Thunks.h

Defined *addSymbol(StringRef Name, uint8_t Type, uint64_t Value,
                      InputSectionBase &Section);
 
   // Some Thunks must be placed immediately before their Target as they elide
   // a branch and fall through to the first Symbol in the Target.
   virtual InputSection *getTargetInputSection() const { return nullptr; }
 
   // To reuse a Thunk the caller as identified by the Type must be
   // compatible with it.
-  virtual bool isCompatibleWith(RelType Type) const { return true; }
+  virtual bool isCompatibleWith(const InputSection &IS, RelType Type) const {
+    return true;
+  }
 
   Defined *getThunkTargetSym() const { return Syms[0]; }
 
   // The alignment requirement for this Thunk, defaults to the size of the
   // typical code section alignment.
   Symbol &Destination;
   llvm::SmallVector<Defined *, 3> Syms;
   uint64_t Offset = 0;
   uint32_t Alignment = 4;
 };
 
 // For a Relocation to symbol S create a Thunk to be added to a synthetic
-// ThunkSection. At present there are implementations for ARM and Mips Thunks.
-Thunk *addThunk(RelType Type, Symbol &S);
+// ThunkSection.
+Thunk *addThunk(const InputSection &IS, RelType Type, Symbol &S);
 
 } // namespace elf
 } // namespace lld
 
 #endif

ELF/Thunks.cpp

 // if the target is in range, otherwise it creates a long thunk.
 class ARMThunk : public Thunk {
 public:
   ARMThunk(Symbol &Dest) : Thunk(Dest) {}
 
   bool mayUseShortThunk();
   uint32_t size() override { return mayUseShortThunk() ? 4 : sizeLong(); }
   void writeTo(uint8_t *Buf) override;
-  bool isCompatibleWith(RelType Type) const override;
+  bool isCompatibleWith(const InputSection &IS, RelType Type) const override;
 
   // Returns the size of a long thunk.
   virtual uint32_t sizeLong() = 0;
 
   // Writes a long thunk to Buf.
   virtual void writeLong(uint8_t *Buf) = 0;
 
 private:

 // which has a range of 16MB.
 class ThumbThunk : public Thunk {
 public:
   ThumbThunk(Symbol &Dest) : Thunk(Dest) { Alignment = 2; }
 
   bool mayUseShortThunk();
   uint32_t size() override { return mayUseShortThunk() ? 4 : sizeLong(); }
   void writeTo(uint8_t *Buf) override;
-  bool isCompatibleWith(RelType Type) const override;
+  bool isCompatibleWith(const InputSection &IS, RelType Type) const override;
 
   // Returns the size of a long thunk.
   virtual uint32_t sizeLong() = 0;
 
   // Writes a long thunk to Buf.
   virtual void writeLong(uint8_t *Buf) = 0;
 
 private:

 // can result in a thunk
 class ARMV5ABSLongThunk final : public ARMThunk {
 public:
   ARMV5ABSLongThunk(Symbol &Dest) : ARMThunk(Dest) {}
 
   uint32_t sizeLong() override { return 8; }
   void writeLong(uint8_t *Buf) override;
   void addSymbols(ThunkSection &IS) override;
-  bool isCompatibleWith(uint32_t RelocType) const override;
+  bool isCompatibleWith(const InputSection &IS,
+                        uint32_t RelocType) const override;
 };
 
 class ARMV5PILongThunk final : public ARMThunk {
 public:
   ARMV5PILongThunk(Symbol &Dest) : ARMThunk(Dest) {}
 
   uint32_t sizeLong() override { return 16; }
   void writeLong(uint8_t *Buf) override;
   void addSymbols(ThunkSection &IS) override;
-  bool isCompatibleWith(uint32_t RelocType) const override;
+  bool isCompatibleWith(const InputSection &IS,
+                        uint32_t RelocType) const override;
 };
 
 // Implementations of Thunks for Arm v6-M. Only Thumb instructions are permitted
 class ThumbV6MABSLongThunk final : public ThumbThunk {
 public:
   ThumbV6MABSLongThunk(Symbol &Dest) : ThumbThunk(Dest) {}
 
   uint32_t sizeLong() override { return 12; }
public:
   MicroMipsR6Thunk(Symbol &Dest) : Thunk(Dest) {}
 
   uint32_t size() override { return 12; }
   void writeTo(uint8_t *Buf) override;
   void addSymbols(ThunkSection &IS) override;
   InputSection *getTargetInputSection() const override;
 };
 
+class PPC32PltCallStub final : public Thunk {
+  const InputFile *File;
+
+public:
+  PPC32PltCallStub(const InputSection &IS, Symbol &Dest)
+      : Thunk(Dest), File(IS.File) {}
+  uint32_t size() override { return 16; }
+  void writeTo(uint8_t *Buf) override;
+  void addSymbols(ThunkSection &IS) override;
+  bool isCompatibleWith(const InputSection &IS, RelType Type) const override;
+};
 
 // PPC64 Plt call stubs.
 // Any call site that needs to call through a plt entry needs a call stub in
 // the .text section. The call stub is responsible for:
 // 1) Saving the toc-pointer to the stack.
 // 2) Loading the target functions address from the procedure linkage table into
 //    r12 for use by the target functions global entry point, and into the count
 //    register.
void ARMThunk::writeTo(uint8_t *Buf) {
   int64_t Offset = S - P - 8;
   const uint8_t Data[] = {
     0x00, 0x00, 0x00, 0xea, // b S
   };
   memcpy(Buf, Data, sizeof(Data));
   Target->relocateOne(Buf, R_ARM_JUMP24, Offset);
 }
 
-bool ARMThunk::isCompatibleWith(RelType Type) const {
+bool ARMThunk::isCompatibleWith(const InputSection &IS, RelType Type) const {
   // Thumb branch relocations can't use BLX
   return Type != R_ARM_THM_JUMP19 && Type != R_ARM_THM_JUMP24;
 }
 
 // This function returns true if the target is Thumb and is within 2^25, and
 // it has not previously returned false (see comment for MayUseShortThunk).
 bool ThumbThunk::mayUseShortThunk() {
   if (!MayUseShortThunk)
void ThumbThunk::writeTo(uint8_t *Buf) {
   int64_t Offset = S - P - 4;
   const uint8_t Data[] = {
       0x00, 0xf0, 0x00, 0xb0, // b.w S
   };
   memcpy(Buf, Data, sizeof(Data));
   Target->relocateOne(Buf, R_ARM_THM_JUMP24, Offset);
 }
 
-bool ThumbThunk::isCompatibleWith(RelType Type) const {
+bool ThumbThunk::isCompatibleWith(const InputSection &IS, RelType Type) const {
   // ARM branch relocations can't use BLX
   return Type != R_ARM_JUMP24 && Type != R_ARM_PC24 && Type != R_ARM_PLT32;
 }
 
 void ARMV7ABSLongThunk::writeLong(uint8_t *Buf) {
   const uint8_t Data[] = {
       0x00, 0xc0, 0x00, 0xe3, // movw         ip,:lower16:S
       0x00, 0xc0, 0x40, 0xe3, // movt         ip,:upper16:S

 
 void ARMV5ABSLongThunk::addSymbols(ThunkSection &IS) {
   addSymbol(Saver.save("__ARMv5ABSLongThunk_" + Destination.getName()),
             STT_FUNC, 0, IS);
   addSymbol("$a", STT_NOTYPE, 0, IS);
   addSymbol("$d", STT_NOTYPE, 4, IS);
 }
 
-bool ARMV5ABSLongThunk::isCompatibleWith(uint32_t RelocType) const {
+bool ARMV5ABSLongThunk::isCompatibleWith(const InputSection &IS,
+                                         uint32_t RelocType) const {
   // Thumb branch relocations can't use BLX
   return RelocType != R_ARM_THM_JUMP19 && RelocType != R_ARM_THM_JUMP24;
 }
 
 void ARMV5PILongThunk::writeLong(uint8_t *Buf) {
   const uint8_t Data[] = {
       0x04, 0xc0, 0x9f, 0xe5, // P:  ldr ip, [pc,#4] ; L2
       0x0c, 0xc0, 0x8f, 0xe0, // L1: add ip, pc, ip
       0x1c, 0xff, 0x2f, 0xe1, //     bx ip
       0x00, 0x00, 0x00, 0x00, // L2: .word S - (P + (L1 - P) + 8)
   };
   uint64_t S = getARMThunkDestVA(Destination);
   uint64_t P = getThunkTargetSym()->getVA() & ~0x1;
   memcpy(Buf, Data, sizeof(Data));
   Target->relocateOne(Buf + 12, R_ARM_REL32, S - P - 12);
 }
 
 void ARMV5PILongThunk::addSymbols(ThunkSection &IS) {
   addSymbol(Saver.save("__ARMV5PILongThunk_" + Destination.getName()), STT_FUNC,
             0, IS);
   addSymbol("$a", STT_NOTYPE, 0, IS);
   addSymbol("$d", STT_NOTYPE, 12, IS);
 }
 
-bool ARMV5PILongThunk::isCompatibleWith(uint32_t RelocType) const {
+bool ARMV5PILongThunk::isCompatibleWith(const InputSection &IS,
+                                        uint32_t RelocType) const {
   // Thumb branch relocations can't use BLX
   return RelocType != R_ARM_THM_JUMP19 && RelocType != R_ARM_THM_JUMP24;
 }
 
 void ThumbV6MABSLongThunk::writeLong(uint8_t *Buf) {
   // Most Thumb instructions cannot access the high registers r8 - r15. As the
   // only register we can corrupt is r12 we must instead spill a low register
   // to the stack to use as a scratch register. We push r1 even though we
void MicroMipsR6Thunk::addSymbols(ThunkSection &IS) {
   D->StOther |= STO_MIPS_MICROMIPS;
 }
 
 InputSection *MicroMipsR6Thunk::getTargetInputSection() const {
   auto &DR = cast<Defined>(Destination);
   return dyn_cast<InputSection>(DR.Section);
 }
 
+void PPC32PltCallStub::writeTo(uint8_t *Buf) {
+  if (Config->Pic) {
+    // In PIC mode, the stub loads an address relative to r30 (.got2+0x8000).
+    // The address of .got2 is different in another object file, so a stub
+    // cannot be shared.
+    uint32_t Offset =
+        Destination.getGotPltVA() - (In.PPC32Got2->getParent()->getVA() +
+                                     File->PPC32Got2OutSecOff + 0x8000);
+    uint16_t HA = (Offset + 0x8000) >> 16, L = (uint16_t)Offset;
+    if (HA == 0) {
+      write32(Buf + 0, 0x817e0000 | L); // lwz r11,l(r30)
+      write32(Buf + 4, 0x7d6903a6);     // mtctr r11
+      write32(Buf + 8, 0x4e800420);     // bctr
+      write32(Buf + 12, 0x60000000);    // nop
+    } else {
+      write32(Buf + 0, 0x3d7e0000 | HA); // addis r11,r30,ha
+      write32(Buf + 4, 0x816b0000 | L);  // lwz r11,l(r11)
+      write32(Buf + 8, 0x7d6903a6);      // mtctr r11
+      write32(Buf + 12, 0x4e800420);     // bctr
+    }
+  } else {
+    uint64_t VA = Destination.getGotPltVA();
+    write32(Buf + 0, 0x3d600000 | (VA + 0x8000) >> 16); // lis r11,ha
+    write32(Buf + 4, 0x816b0000 | (uint16_t)VA);        // lwz r11,l(r11)
+    write32(Buf + 8, 0x7d6903a6);                       // mtctr r11
+    write32(Buf + 12, 0x4e800420);                      // bctr
+  }
+}
+
+void PPC32PltCallStub::addSymbols(ThunkSection &IS) {
+  addSymbol(Saver.save("__plt_" + Destination.getName()), STT_FUNC, 0, IS);
+}
+
+bool PPC32PltCallStub::isCompatibleWith(const InputSection &IS,
+                                        uint32_t RelocType) const {
+  return IS.File == File || !Config->Pic;
+}
+
 static void writePPCLoadAndBranch(uint8_t *Buf, int64_t Offset) {
   uint16_t OffHa = (Offset + 0x8000) >> 16;
   uint16_t OffLo = Offset & 0xffff;
 
   write32(Buf + 0, 0x3d820000 | OffHa); // addis r12, r2, OffHa
   write32(Buf + 4, 0xe98c0000 | OffLo); // ld    r12, OffLo(r12)
   write32(Buf + 8, 0x7d8903a6);         // mtctr r12
   write32(Buf + 12, 0x4e800420);        // bctr

 static Thunk *addThunkMips(RelType Type, Symbol &S) {
   if ((S.StOther & STO_MIPS_MICROMIPS) && isMipsR6())
     return make<MicroMipsR6Thunk>(S);
   if (S.StOther & STO_MIPS_MICROMIPS)
     return make<MicroMipsThunk>(S);
   return make<MipsThunk>(S);
 }
 
+static Thunk *addThunkPPC32(const InputSection &IS, RelType Type, Symbol &S) {
+  assert((Type == R_PPC_REL24 || Type == R_PPC_PLTREL24) &&
+         "unexpected relocation type for thunk");
+  return make<PPC32PltCallStub>(IS, S);
+}
+
 static Thunk *addThunkPPC64(RelType Type, Symbol &S) {
   assert(Type == R_PPC64_REL24 && "unexpected relocation type for thunk");
   if (S.isInPlt())
     return make<PPC64PltCallStub>(S);
 
   if (Config->PicThunk)
     return make<PPC64PILongBranchThunk>(S);
 
   return make<PPC64PDLongBranchThunk>(S);
 }
 
-Thunk *addThunk(RelType Type, Symbol &S) {
+Thunk *addThunk(const InputSection &IS, RelType Type, Symbol &S) {
   if (Config->EMachine == EM_AARCH64)
     return addThunkAArch64(Type, S);
 
   if (Config->EMachine == EM_ARM)
     return addThunkArm(Type, S);
 
   if (Config->EMachine == EM_MIPS)
     return addThunkMips(Type, S);
 
+  if (Config->EMachine == EM_PPC && Config->SecurePlt)
+    return addThunkPPC32(IS, Type, S);
+
   if (Config->EMachine == EM_PPC64)
     return addThunkPPC64(Type, S);
 
   llvm_unreachable("add Thunk only supported for ARM, Mips and PowerPC");
 }
 
 } // end namespace elf
 } // end namespace lld

ELF/Writer.cpp

void elf::addReservedSymbols() {
   // _GLOBAL_OFFSET_TABLE_ and _SDA_BASE_ from the 32-bit ABI. It is used to
   // represent the TOC base which is offset by 0x8000 bytes from the start of
   // the .got section.
   // We do not allow _GLOBAL_OFFSET_TABLE_ to be defined by input objects as the
   // correctness of some relocations depends on its value.
   StringRef GotSymName =
       (Config->EMachine == EM_PPC64) ? ".TOC." : "_GLOBAL_OFFSET_TABLE_";
 
-  if (Symbol *S = Symtab->find(GotSymName)) {
+  if (Config->EMachine == EM_PPC) {
+    ElfSym::GlobalOffsetTable = cast<Defined>(Symtab->addSymbol(
+        Defined{/*File=*/nullptr, GotSymName, STB_GLOBAL, STV_HIDDEN,
+                STT_NOTYPE, uint64_t(Config->SecurePlt ? 0 : 4),
+                /*Size=*/0, Out::ElfHeader}));
+  } else if (Symbol *S = Symtab->find(GotSymName)) {
     if (S->isDefined()) {
       error(toString(S->File) + " cannot redefine linker defined symbol '" +
             GotSymName + "'");
       return;
     }
 
     uint64_t GotOff = 0;
-    if (Config->EMachine == EM_PPC || Config->EMachine == EM_PPC64)
+    if (Config->EMachine == EM_PPC64)
       GotOff = 0x8000;
-
     S->resolve(Defined{/*File=*/nullptr, GotSymName, STB_GLOBAL, STV_HIDDEN,
                        STT_NOTYPE, GotOff, /*Size=*/0, Out::ElfHeader});
     ElfSym::GlobalOffsetTable = cast<Defined>(S);
   }
 
   // __ehdr_start is the location of ELF file headers. Note that we define
   // this symbol unconditionally even when using a linker script, which
   // differs from the behavior implemented by GNU linker which only define
template <class ELFT> static void createSyntheticSections() {
   if (Config->EMachine == EM_MIPS) {
     In.MipsGot = make<MipsGotSection>();
     Add(In.MipsGot);
   } else {
     In.Got = make<GotSection>();
     Add(In.Got);
   }
 
+  if (Config->EMachine == EM_PPC) {
+    In.PPC32Got2 = make<PPC32Got2Section>();
+    Add(In.PPC32Got2);
+  }
+
   if (Config->EMachine == EM_PPC64) {
     In.PPC64LongBranchTarget = make<PPC64LongBranchTargetSection>();
     Add(In.PPC64LongBranchTarget);
   }
 
   In.GotPlt = make<GotPltSection>();
   Add(In.GotPlt);
   In.IgotPlt = make<IgotPltSection>();
template <class ELFT> void Writer<ELFT>::finalizeSections() {
   finalizeSynthetic(In.IgotPlt);
   finalizeSynthetic(In.GotPlt);
   finalizeSynthetic(In.RelaDyn);
   finalizeSynthetic(In.RelrDyn);
   finalizeSynthetic(In.RelaIplt);
   finalizeSynthetic(In.RelaPlt);
   finalizeSynthetic(In.Plt);
   finalizeSynthetic(In.Iplt);
+  finalizeSynthetic(In.PPC32Got2);
   finalizeSynthetic(In.EhFrameHdr);
   finalizeSynthetic(In.VerSym);
   finalizeSynthetic(In.VerNeed);
   finalizeSynthetic(In.Dynamic);
 
   if (!Script->HasSectionsCommand && !Config->Relocatable)
     fixSectionAlignments();
 

 }
 
 // Compute an in-file position for a given section. The file offset must be the
 // same with its virtual address modulo the page size, so that the loader can
 // load executables without any address adjustment.
 static uint64_t computeFileOffset(OutputSection *OS, uint64_t Off) {
   // File offsets are not significant for .bss sections. By convention, we keep
   // section offsets monotonically increasing rather than setting to zero.
-  if (OS->Type == SHT_NOBITS)
+  if (OS->Type == SHT_NOBITS && !(OS->PtLoad && OS->PtLoad->FirstSec == OS))
     return Off;
 
   // If the section is not in a PT_LOAD, we just have to align it.
   if (!OS->PtLoad)
     return alignTo(Off, OS->Alignment);
 
   // The first section in a PT_LOAD has to have congruent offset and address
   // module the page size.

test/ELF/basic-ppc64.s

 // CHECK-NEXT:    ABIVersion: 0
 // CHECK-NEXT:    Unused: (00 00 00 00 00 00 00)
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Type: SharedObject (0x3)
 // CHECK-NEXT:  Machine: EM_PPC64 (0x15)
 // CHECK-NEXT:  Version: 1
 // CHECK-NEXT:  Entry: 0x10000
 // CHECK-NEXT:  ProgramHeaderOffset: 0x40
-// CHECK-NEXT:  SectionHeaderOffset: 0x200F8
+// CHECK-NEXT:  SectionHeaderOffset: 0x30098
 // CHECK-NEXT:  Flags [ (0x2)
 // CHECK-NEXT:    0x2
 // CHECK-NEXT:  ]
 // CHECK-NEXT:  HeaderSize: 64
 // CHECK-NEXT:  ProgramHeaderEntrySize: 56
 // CHECK-NEXT:  ProgramHeaderCount: 7
 // CHECK-NEXT:  SectionHeaderEntrySize: 64
 // CHECK-NEXT:  SectionHeaderCount: 11

 // CHECK-NEXT:    Index: 6
 // CHECK-NEXT:    Name: .branch_lt (38)
 // CHECK-NEXT:    Type: SHT_NOBITS (0x8)
 // CHECK-NEXT:    Flags [ (0x3)
 // CHECK-NEXT:      SHF_ALLOC (0x2)
 // CHECK-NEXT:      SHF_WRITE (0x1)
 // CHECK-NEXT:    ]
 // CHECK-NEXT:    Address: 0x30000
-// CHECK-NEXT:    Offset: 0x20060
+// CHECK-NEXT:    Offset: 0x30000
 // CHECK-NEXT:    Size: 0
 // CHECK-NEXT:    Link: 0
 // CHECK-NEXT:    Info: 0
 // CHECK-NEXT:    AddressAlignment: 8
 // CHECK-NEXT:    EntrySize: 0
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Section {
 // CHECK-NEXT:    Index: 7
 // CHECK-NEXT:    Name: .comment (49)
 // CHECK-NEXT:    Type: SHT_PROGBITS (0x1)
 // CHECK-NEXT:    Flags [ (0x30)
 // CHECK-NEXT:      SHF_MERGE (0x10)
 // CHECK-NEXT:      SHF_STRINGS (0x20)
 // CHECK-NEXT:    ]
 // CHECK-NEXT:    Address: 0x0
-// CHECK-NEXT:    Offset: 0x20060
+// CHECK-NEXT:    Offset: 0x30000
 // CHECK-NEXT:    Size: 8
 // CHECK-NEXT:    Link: 0
 // CHECK-NEXT:    Info: 0
 // CHECK-NEXT:    AddressAlignment: 1
 // CHECK-NEXT:    EntrySize: 1
 // CHECK-NEXT:    SectionData (
 // CHECK-NEXT:      0000: 4C4C4420 312E3000                    |LLD 1.0.|
 // CHECK-NEXT:    )
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Section {
 // CHECK-NEXT:    Index: 8
 // CHECK-NEXT:    Name: .symtab (58)
 // CHECK-NEXT:    Type: SHT_SYMTAB (0x2)
 // CHECK-NEXT:    Flags [ (0x0)
 // CHECK-NEXT:    ]
 // CHECK-NEXT:    Address: 0x0
-// CHECK-NEXT:    Offset: 0x20068
+// CHECK-NEXT:    Offset: 0x30008
 // CHECK-NEXT:    Size: 48
 // CHECK-NEXT:    Link: 10
 // CHECK-NEXT:    Info: 2
 // CHECK-NEXT:    AddressAlignment: 8
 // CHECK-NEXT:    EntrySize: 24
 // CHECK-NEXT:    SectionData (
 // CHECK-NEXT:      0000: 00000000 00000000 00000000 00000000  |................|
 // CHECK-NEXT:      0010: 00000000 00000000 01000000 00020500  |................|
 // CHECK-NEXT:      0020: 00000200 00000000 00000000 00000000  |................|
 // CHECK-NEXT:    )
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Section {
 // CHECK-NEXT:    Index: 9
 // CHECK-NEXT:    Name: .shstrtab (66)
 // CHECK-NEXT:    Type: SHT_STRTAB (0x3)
 // CHECK-NEXT:    Flags [ (0x0)
 // CHECK-NEXT:    ]
 // CHECK-NEXT:    Address: 0x0
-// CHECK-NEXT:    Offset: 0x20098
+// CHECK-NEXT:    Offset: 0x30038
 // CHECK-NEXT:    Size: 84
 // CHECK-NEXT:    Link: 0
 // CHECK-NEXT:    Info: 0
 // CHECK-NEXT:    AddressAlignment: 1
 // CHECK-NEXT:    EntrySize: 0
 // CHECK-NEXT:    SectionData (
 // CHECK-NEXT:      0000: 002E6479 6E73796D 002E6861 7368002E  |..dynsym..hash..|
 // CHECK-NEXT:      0010: 64796E73 7472002E 74657874 002E6479  |dynstr..text..dy|
 // CHECK-NEXT:      0020: 6E616D69 63002E62 72616E63 685F6C74  |namic..branch_lt|
 // CHECK-NEXT:      0030: 002E636F 6D6D656E 74002E73 796D7461  |..comment..symta|
 // CHECK-NEXT:      0040: 62002E73 68737472 74616200 2E737472  |b..shstrtab..str|
 // CHECK-NEXT:      0050: 74616200                             |tab.|
 // CHECK-NEXT:    )
 // CHECK-NEXT:  }
 // CHECK-NEXT:  Section {
 // CHECK-NEXT:    Index: 10
 // CHECK-NEXT:    Name: .strtab (76)
 // CHECK-NEXT:    Type: SHT_STRTAB (0x3)
 // CHECK-NEXT:    Flags [ (0x0)
 // CHECK-NEXT:    ]
 // CHECK-NEXT:    Address: 0x0
-// CHECK-NEXT:    Offset: 0x200EC
+// CHECK-NEXT:    Offset: 0x3008C
 // CHECK-NEXT:    Size: 10
 // CHECK-NEXT:    Link: 0
 // CHECK-NEXT:    Info: 0
 // CHECK-NEXT:    AddressAlignment: 1
 // CHECK-NEXT:    EntrySize: 0
 // CHECK-NEXT:    SectionData (
 // CHECK-NEXT:      0000: 005F4459 4E414D49 4300               |._DYNAMIC.|
 // CHECK-NEXT:    )

test/ELF/ppc-rela.s

 # REQUIRES: ppc
 # RUN: llvm-mc -filetype=obj -triple=powerpc-unknown-freebsd %s -o %t
 # RUN: ld.lld %t -o %t2 -shared
 # RUN: llvm-readobj -r %t2 | FileCheck %s
 
 .data
   .long foo
 
 // CHECK:      Section ({{.*}}) .rela.dyn {
-// CHECK-NEXT:   0x2000 R_PPC_ADDR32 foo 0x0
+// CHECK-NEXT:   0x20000 R_PPC_ADDR32 foo 0x0
 // CHECK-NEXT: }

test/ELF/ppc-relocs.s

-# REQUIRES: ppc
-# RUN: llvm-mc -filetype=obj -triple=powerpc-unknown-freebsd %s -o %t.o
-# RUN: ld.lld %t.o -o %t
-# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
-# RUN: llvm-objdump -s --no-show-raw-insn %t | FileCheck --check-prefix=HEX %s
-
-.section .R_PPC_ADDR16_HA,"ax",@progbits
-.globl _start
-_start:
-  lis 4, msg@ha
-msg:
-  .string "foo"
-  len = . - msg
-
-# CHECK: Disassembly of section .R_PPC_ADDR16_HA:
-# CHECK-EMPTY:
-# CHECK: _start:
-# CHECK:    11000:       lis 4, 1
-# CHECK: msg:
-# CHECK:    11004:       oris 15, 19, 28416
-
-.section .R_PPC_ADDR16_HI,"ax",@progbits
-.globl _starti
-_starti:
-  lis 4,msgi@h
-msgi:
-  .string "foo"
-  leni = . - msgi
-
-# CHECK: Disassembly of section .R_PPC_ADDR16_HI:
-# CHECK-EMPTY:
-# CHECK: _starti:
-# CHECK:    11008:       lis 4, 1
-# CHECK: msgi:
-# CHECK:    1100c:       oris 15, 19, 28416
-
-.section .R_PPC_ADDR16_LO,"ax",@progbits
-  addi 4, 4, msg@l
-mystr:
-  .asciz "blah"
-  len = . - mystr
-
-# CHECK: Disassembly of section .R_PPC_ADDR16_LO:
-# CHECK-EMPTY:
-# CHECK: .R_PPC_ADDR16_LO:
-# CHECK:    11010:       addi 4, 4, 4100
-# CHECK: mystr:
-# CHECK:    11014:       ori 12, 19, 24936
-
-.align  2
-.section .R_PPC_REL24,"ax",@progbits
-.globl .FR_PPC_REL24
-.FR_PPC_REL24:
-  b .Lfoox
-.section .R_PPC_REL24_2,"ax",@progbits
-.Lfoox:
-
-# CHECK: Disassembly of section .R_PPC_REL24:
-# CHECK-EMPTY:
-# CHECK: .FR_PPC_REL24:
-# CHECK:    1101c:       b .+4
-
-.section .R_PPC_REL14,"ax",@progbits
-.globl .FR_PPC_REL14
-.FR_PPC_REL14:
-  beq .Lfooy
-.section .R_PPC_REL14_2,"ax",@progbits
-.Lfooy:
-
-# CHECK: Disassembly of section .R_PPC_REL14:
-# CHECK-EMPTY:
-# CHECK: .FR_PPC_REL14:
-# CHECK:    11020:       bt 2, .+4
-
-.section .R_PPC_REL32,"ax",@progbits
-.globl .FR_PPC_REL32
-.FR_PPC_REL32:
-  .long .Lfoox3 - .
-.section .R_PPC_REL32_2,"ax",@progbits
-.Lfoox3:
-
-# HEX:     .R_PPC_REL32:
-# HEX-NEXT: 11024 00000004
-
-.section .R_PPC_ADDR32,"ax",@progbits
-.globl .FR_PPC_ADDR32
-.FR_PPC_ADDR32:
-  .long .Lfoox2
-.section .R_PPC_ADDR32_2,"ax",@progbits
-.Lfoox2:
-
-# HEX:     .R_PPC_ADDR32:
-# HEX-NEXT: 11028 0001102c
-
-.align  2
-.section .R_PPC_PLTREL24,"ax",@progbits
-.globl .R_PPC_PLTREL24
-.FR_PPC_PLTREL24:
-  b .Lfoox4@PLT
-.section .R_PPC_PLTREL24_2,"ax",@progbits
-.Lfoox4:
-
-# CHECK: Disassembly of section .R_PPC_PLTREL24:
-# CHECK-EMPTY:
-# CHECK: .R_PPC_PLTREL24:
-# CHECK:    1102c:       b .+4

test/ELF/ppc32-call-pic.s

+# REQUIRES: ppc
+# RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o
+# RUN: echo '.globl f, g, h; f: g: h:' | llvm-mc -filetype=obj -triple=powerpc - -o %t1.o
+# RUN: ld.lld -shared %t1.o -o %t1.so
+
+# RUN: ld.lld -pie %t.o %t1.so -o %t
+# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
+
+# RUN: ld.lld -shared %t.o %t1.so -o %t
+# RUN: llvm-readobj -r %t | FileCheck --check-prefix=RELOC %s
+# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
+
+# RELOC:      .rela.dyn {
+# RELOC-NEXT:   R_PPC_ADDR32 f 0x0
+# RELOC-NEXT:   R_PPC_ADDR32 g 0x0
+# RELOC-NEXT:   R_PPC_ADDR32 h 0x0
+# RELOC-NEXT: }
+# RELOC-NEXT: .rela.plt {
+# RELOC-NEXT:   R_PPC_JMP_SLOT f 0x0
+# RELOC-NEXT:   R_PPC_JMP_SLOT g 0x0
+# RELOC-NEXT:   R_PPC_JMP_SLOT h 0x0
+# RELOC-NEXT: }
+
+## .got2+0x8000-0x10004 = 0x30000+0x8000-0x10004 = 65536*2+32764
+# CHECK-LABEL: _start:
+# CHECK-NEXT:    bcl 20, 31, .+4
+# CHECK-NEXT:  10004: mflr 30
+# CHECK-NEXT:    addis 30, 30, 2
+# CHECK-NEXT:    addi 30, 30, 32764
+
+## Two bl __plt_f
+# CHECK-NEXT:    bl .+24
+# CHECK-NEXT:    bl .+20
+## Two bl __plt_g
+# CHECK-NEXT:    bl .+32
+# CHECK-NEXT:    bl .+28
+## Two bl __plt_h
+# CHECK-NEXT:    bl .+40
+# CHECK-NEXT:    bl .+36
+# CHECK-EMPTY:
+
+# CHECK-NEXT:  __plt_f:
+# CHECK-NEXT:    lwz 11, 32760(30)
+# CHECK-NEXT:    mtctr 11
+# CHECK-NEXT:    bctr
+# CHECK-NEXT:    nop
+# CHECK-EMPTY:
+# CHECK-NEXT:  __plt_g:
+# CHECK-NEXT:    lwz 11, 32764(30)
+# CHECK-NEXT:    mtctr 11
+# CHECK-NEXT:    bctr
+# CHECK-NEXT:    nop
+# CHECK-EMPTY:
+
+## __plt_h needs two instructions addis+lwz to represent the offset 65536*1-32768.
+# CHECK-NEXT:  __plt_h:
+# CHECK-NEXT:    addis 11, 30, 1
+# CHECK-NEXT:    lwz 11, -32768(11)
+# CHECK-NEXT:    mtctr 11
+# CHECK-NEXT:    bctr
+
+.section .got2,"aw"
+.space 65516
+.long f
+.long g
+.long h
+
+.text
+.globl _start
+_start:
+  bcl 20,31,.L
+.L:
+  mflr 30
+  addis 30, 30, .got2+0x8000-.L@ha
+  addi 30, 30, .got2+0x8000-.L@l
+  bl f+32768@plt
+  bl f+32768@plt
+  bl g+32768@plt
+  bl g+32768@plt
+  bl h+32768@plt
+  bl h+32768@plt

test/ELF/ppc32-reloc-addr.s

+# REQUIRES: ppc
+# RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
+# RUN: llvm-objdump -s --no-show-raw-insn %t | FileCheck --check-prefix=HEX %s
+
+.section .R_PPC_ADDR16_HA,"ax",@progbits
+1:
+  lis 4, 1b@ha
+# CHECK-LABEL: section .R_PPC_ADDR16_HA:
+# CHECK: 10010000: lis 4, 4097
+
+.section .R_PPC_ADDR16_HI,"ax",@progbits
+1:
+  lis 4,1b@h
+# CHECK-LABEL: section .R_PPC_ADDR16_HI:
+# CHECK: 10010004: lis 4, 4097
+
+.section .R_PPC_ADDR16_LO,"ax",@progbits
+1:
+  addi 4, 4, 1b@l
+# CHECK-LABEL: section .R_PPC_ADDR16_LO:
+# CHECK: 10010008: addi 4, 4, 8
+
+.section .R_PPC_ADDR32,"a",@progbits
+.Lfoo:
+  .long .Lfoo
+# HEX-LABEL: section .R_PPC_ADDR32:
+# HEX-NEXT: 1001000c 1001000c

test/ELF/ppc32-reloc-rel.s

+# REQUIRES: ppc
+# RUN: llvm-mc -filetype=obj -triple=powerpc %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: llvm-objdump -d --no-show-raw-insn %t | FileCheck %s
+
+.section .R_PPC_REL14,"ax",@progbits
+  beq 1f
+1:
+# CHECK-LABEL: section .R_PPC_REL14:
+# CHECK: bt 2, .+4
+
+.section .R_PPC_REL24,"ax",@progbits
+  b 1f
+1:
+# CHECK-LABEL: section .R_PPC_REL24:
+# CHECK: b .+4
+
+.section .R_PPC_REL32,"ax",@progbits
+  .long 1f - .
+1:
+# HEX-LABEL: section .R_PPC_REL32:
+# HEX-NEXT: 10010008 00000004
+
+.section .R_PPC_PLTREL24,"ax",@progbits
+  b 1f@PLT+32768
+1:
+# CHECK-LABEL: section .R_PPC_PLTREL24:
+# CHECK: b .+4

test/ELF/relocation-copy-align-common.s

 # CHECK:        Index:
 # CHECK:        Name: .bss
 # CHECK-NEXT:   Type: SHT_NOBITS
 # CHECK-NEXT:   Flags [
 # CHECK-NEXT:     SHF_ALLOC
 # CHECK-NEXT:     SHF_WRITE
 # CHECK-NEXT:   ]
 # CHECK-NEXT:   Address: 0x203000
-# CHECK-NEXT:   Offset: 0x20B0
+# CHECK-NEXT:   Offset: 0x3000
 # CHECK-NEXT:   Size: 16
 # CHECK-NEXT:   Link: 0
 # CHECK-NEXT:   Info: 0
 # CHECK-NEXT:   AddressAlignment: 8
 # CHECK-NEXT:   EntrySize: 0
 # CHECK-NEXT: }
 
 # CHECK:      Relocations [