[AArch64][SVE2] Asm: support SVE2 Accumulate Group

[c-rhodes]

Summary

Patch adds support for the following instructions:

SVE2 bitwise shift and insert:

• SRI, SLI

SVE2 bitwise shift right and accumulate:

• SSRA, USRA, SRSRA, URSRA

SVE2 complex integer add:

• CADD, SQCADD

SVE2 integer absolute difference and accumulate:

• SABA, UABA

SVE2 integer absolute difference and accumulate long:

• SABALB, SABALT, UABALB, UABALT

SVE2 integer add/subtract long with carry:

• ADCLB, ADCLT, SBCLB, SBCLT

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

[SjoerdMeijer]

LGTM

lib/Target/AArch64/AArch64SVEInstrInfo.td

let Predicates = [HasSVE2] in {
   defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">;
   defm SMULLB_ZZZ   : sve2_wide_int_arith_long<0b11100, "smullb">;
   defm SMULLT_ZZZ   : sve2_wide_int_arith_long<0b11101, "smullt">;
   defm UMULLB_ZZZ   : sve2_wide_int_arith_long<0b11110, "umullb">;
   defm UMULLT_ZZZ   : sve2_wide_int_arith_long<0b11111, "umullt">;
   defm PMULLB_ZZZ   : sve2_pmul_long<0b0, "pmullb">;
   defm PMULLT_ZZZ   : sve2_pmul_long<0b1, "pmullt">;
 
+  // SVE2 bitwise shift and insert
+  defm SRI_ZZI : sve2_int_bin_cons_shift_imm_right<0b0, "sri">;
+  defm SLI_ZZI : sve2_int_bin_cons_shift_imm_left< 0b1, "sli">;
+
+  // SVE2 bitwise shift right and accumulate
+  defm SSRA_ZZI  : sve2_int_bin_accum_cons_shift_imm_right<0b00, "ssra">;
+  defm USRA_ZZI  : sve2_int_bin_accum_cons_shift_imm_right<0b01, "usra">;
+  defm SRSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b10, "srsra">;
+  defm URSRA_ZZI : sve2_int_bin_accum_cons_shift_imm_right<0b11, "ursra">;
+
+  // SVE2 complex integer add
+  defm CADD_ZZI   : sve2_int_cadd<0b0, "cadd">;
+  defm SQCADD_ZZI : sve2_int_cadd<0b1, "sqcadd">;
+
+  // SVE2 integer absolute difference and accumulate
+  defm SABA_ZZZ : sve2_int_absdiff_accum<0b0, "saba">;
+  defm UABA_ZZZ : sve2_int_absdiff_accum<0b1, "uaba">;
+
+  // SVE2 integer absolute difference and accumulate long
+  defm SABALB_ZZZ : sve2_int_absdiff_accum_long<0b00, "sabalb">;
+  defm SABALT_ZZZ : sve2_int_absdiff_accum_long<0b01, "sabalt">;
+  defm UABALB_ZZZ : sve2_int_absdiff_accum_long<0b10, "uabalb">;
+  defm UABALT_ZZZ : sve2_int_absdiff_accum_long<0b11, "uabalt">;
+
+  // SVE2 integer add/subtract long with carry
+  defm ADCLB_ZZZ : sve2_int_addsub_long_carry<0b00, "adclb">;
+  defm ADCLT_ZZZ : sve2_int_addsub_long_carry<0b01, "adclt">;
+  defm SBCLB_ZZZ : sve2_int_addsub_long_carry<0b10, "sbclb">;
+  defm SBCLT_ZZZ : sve2_int_addsub_long_carry<0b11, "sbclt">;
+
   // Predicated shifts
   defm SQSHL_ZPmI  : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
   defm UQSHL_ZPmI  : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
   defm SRSHR_ZPmI  : sve_int_bin_pred_shift_imm_right<0b1100, "srshr">;
   defm URSHR_ZPmI  : sve_int_bin_pred_shift_imm_right<0b1101, "urshr">;
   defm SQSHLU_ZPmI : sve_int_bin_pred_shift_imm_left< 0b1111, "sqshlu">;
 }
 

lib/Target/AArch64/SVEInstrFormats.td

 }
 
 multiclass sve2_pmul_long<bits<1> opc, string asm> {
   def _H : sve2_wide_int_arith<0b01, {0b1101, opc}, asm, ZPR16, ZPR8, ZPR8>;
   def _D : sve2_wide_int_arith<0b11, {0b1101, opc}, asm, ZPR64, ZPR32, ZPR32>;
 }
 
 //===----------------------------------------------------------------------===//
+// SVE2 Accumulate Group
+//===----------------------------------------------------------------------===//
+
+class sve2_int_bin_cons_shift_imm<bits<4> tsz8_64, bit opc, string asm,
+                                  ZPRRegOp zprty, Operand immtype>
+: I<(outs zprty:$Zd), (ins zprty:$Zn, immtype:$imm),
+  asm, "\t$Zd, $Zn, $imm",
+  "", []>, Sched<[]> {
+  bits<5> Zd;
+  bits<5> Zn;
+  bits<6> imm;
+  let Inst{31-24} = 0b01000101;
+  let Inst{23-22} = tsz8_64{3-2};
+  let Inst{21}    = 0b0;
+  let Inst{20-19} = tsz8_64{1-0};
+  let Inst{18-16} = imm{2-0}; // imm3
+  let Inst{15-11} = 0b11110;
+  let Inst{10}    = opc;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zd;
+}
+
+multiclass sve2_int_bin_cons_shift_imm_left<bit opc, string asm> {
+  def _B : sve2_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftL8>;
+  def _H : sve2_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftL16> {
+    let Inst{19} = imm{3};
+  }
+  def _S : sve2_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftL32> {
+    let Inst{20-19} = imm{4-3};
+  }
+  def _D : sve2_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftL64> {
+    let Inst{22}    = imm{5};
+    let Inst{20-19} = imm{4-3};
+  }
+}
+
+multiclass sve2_int_bin_cons_shift_imm_right<bit opc, string asm> {
+  def _B : sve2_int_bin_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
+  def _H : sve2_int_bin_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
+    let Inst{19} = imm{3};
+  }
+  def _S : sve2_int_bin_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
+    let Inst{20-19} = imm{4-3};
+  }
+  def _D : sve2_int_bin_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
+    let Inst{22}    = imm{5};
+    let Inst{20-19} = imm{4-3};
+  }
+}
+
+class sve2_int_bin_accum_cons_shift_imm<bits<4> tsz8_64, bits<2> opc, string asm,
+                                        ZPRRegOp zprty, Operand immtype>
+: I<(outs zprty:$Zda), (ins zprty:$_Zda, zprty:$Zn, immtype:$imm),
+  asm, "\t$Zda, $Zn, $imm",
+  "", []>, Sched<[]> {
+  bits<5> Zda;
+  bits<5> Zn;
+  bits<6> imm;
+  let Inst{31-24} = 0b01000101;
+  let Inst{23-22} = tsz8_64{3-2};
+  let Inst{21}    = 0b0;
+  let Inst{20-19} = tsz8_64{1-0};
+  let Inst{18-16} = imm{2-0}; // imm3
+  let Inst{15-12} = 0b1110;
+  let Inst{11-10} = opc;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zda;
+
+  let Constraints = "$Zda = $_Zda";
+  let DestructiveInstType = Destructive;
+  let ElementSize = ElementSizeNone;
+}
+
+multiclass sve2_int_bin_accum_cons_shift_imm_right<bits<2> opc, string asm> {
+  def _B : sve2_int_bin_accum_cons_shift_imm<{0,0,0,1}, opc, asm, ZPR8, vecshiftR8>;
+  def _H : sve2_int_bin_accum_cons_shift_imm<{0,0,1,?}, opc, asm, ZPR16, vecshiftR16> {
+    let Inst{19} = imm{3};
+  }
+  def _S : sve2_int_bin_accum_cons_shift_imm<{0,1,?,?}, opc, asm, ZPR32, vecshiftR32> {
+    let Inst{20-19} = imm{4-3};
+  }
+  def _D : sve2_int_bin_accum_cons_shift_imm<{1,?,?,?}, opc, asm, ZPR64, vecshiftR64> {
+    let Inst{22}    = imm{5};
+    let Inst{20-19} = imm{4-3};
+  }
+}
+
+class sve2_int_cadd<bits<2> sz, bit opc, string asm, ZPRRegOp zprty>
+: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, zprty:$Zm, complexrotateopodd:$rot),
+  asm, "\t$Zdn, $_Zdn, $Zm, $rot", "", []>, Sched<[]> {
+  bits<5> Zdn;
+  bits<5> Zm;
+  bit rot;
+  let Inst{31-24} = 0b01000101;
+  let Inst{23-22} = sz;
+  let Inst{21-17} = 0b00000;
+  let Inst{16}    = opc;
+  let Inst{15-11} = 0b11011;
+  let Inst{10}    = rot;
+  let Inst{9-5}   = Zm;
+  let Inst{4-0}   = Zdn;
+
+  let Constraints = "$Zdn = $_Zdn";
+  let DestructiveInstType = Destructive;
+  let ElementSize = ElementSizeNone;
+}
+
+multiclass sve2_int_cadd<bit opc, string asm> {
+  def _B : sve2_int_cadd<0b00, opc, asm, ZPR8>;
+  def _H : sve2_int_cadd<0b01, opc, asm, ZPR16>;
+  def _S : sve2_int_cadd<0b10, opc, asm, ZPR32>;
+  def _D : sve2_int_cadd<0b11, opc, asm, ZPR64>;
+}
+
+class sve2_int_absdiff_accum<bits<2> sz, bits<4> opc, string asm,
+                             ZPRRegOp zprty1, ZPRRegOp zprty2>
+: I<(outs zprty1:$Zda), (ins zprty1:$_Zda, zprty2:$Zn, zprty2:$Zm),
+  asm, "\t$Zda, $Zn, $Zm", "", []>, Sched<[]> {
+  bits<5> Zda;
+  bits<5> Zn;
+  bits<5> Zm;
+  let Inst{31-24} = 0b01000101;
+  let Inst{23-22} = sz;
+  let Inst{21}    = 0b0;
+  let Inst{20-16} = Zm;
+  let Inst{15-14} = 0b11;
+  let Inst{13-10} = opc;
+  let Inst{9-5}   = Zn;
+  let Inst{4-0}   = Zda;
+
+  let Constraints = "$Zda = $_Zda";
+  let DestructiveInstType = Destructive;
+  let ElementSize = ElementSizeNone;
+}
+
+multiclass sve2_int_absdiff_accum<bit opc, string asm> {
+  def _B : sve2_int_absdiff_accum<0b00, { 0b111, opc }, asm, ZPR8, ZPR8>;
+  def _H : sve2_int_absdiff_accum<0b01, { 0b111, opc }, asm, ZPR16, ZPR16>;
+  def _S : sve2_int_absdiff_accum<0b10, { 0b111, opc }, asm, ZPR32, ZPR32>;
+  def _D : sve2_int_absdiff_accum<0b11, { 0b111, opc }, asm, ZPR64, ZPR64>;
+}
+
+multiclass sve2_int_absdiff_accum_long<bits<2> opc, string asm> {
+  def _H : sve2_int_absdiff_accum<0b01, { 0b00, opc }, asm, ZPR16, ZPR8>;
+  def _S : sve2_int_absdiff_accum<0b10, { 0b00, opc }, asm, ZPR32, ZPR16>;
+  def _D : sve2_int_absdiff_accum<0b11, { 0b00, opc }, asm, ZPR64, ZPR32>;
+}
+
+multiclass sve2_int_addsub_long_carry<bits<2> opc, string asm> {
+  def _S : sve2_int_absdiff_accum<{ opc{1}, 0b0 }, { 0b010, opc{0} }, asm,
+                                  ZPR32, ZPR32>;
+  def _D : sve2_int_absdiff_accum<{ opc{1}, 0b1 }, { 0b010, opc{0} }, asm,
+                                  ZPR64, ZPR64>;
+}
+
+//===----------------------------------------------------------------------===//
 // SVE Integer Arithmetic - Unary Predicated Group
 //===----------------------------------------------------------------------===//
 
 class sve_int_un_pred_arit<bits<2> sz8_64, bits<4> opc,
                              string asm, ZPRRegOp zprty>
 : I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
   asm, "\t$Zd, $Pg/m, $Zn",
   "",

test/MC/AArch64/SVE2/adclb-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+adclb z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: adclb z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+adclb z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: adclb z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+adclb z0.d, z1.d, z7.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: adclb z0.d, z1.d, z7.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/adclb.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+adclb z0.s, z1.s, z31.s
+// CHECK-INST: adclb z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xd0,0x1f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d0 1f 45 <unknown>
+
+adclb z0.d, z1.d, z31.d
+// CHECK-INST: adclb z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xd0,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d0 5f 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z0, z7
+// CHECK-INST: movprfx  z0, z7
+// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+
+adclb z0.d, z1.d, z31.d
+// CHECK-INST: adclb z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xd0,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d0 5f 45 <unknown>

test/MC/AArch64/SVE2/adclt-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+adclt z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: adclt z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+adclt z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: adclt z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+adclt z0.d, z1.d, z7.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: adclt z0.d, z1.d, z7.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/adclt.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+adclt z0.s, z1.s, z31.s
+// CHECK-INST: adclt z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xd4,0x1f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d4 1f 45 <unknown>
+
+adclt z0.d, z1.d, z31.d
+// CHECK-INST: adclt z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xd4,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d4 5f 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z0, z7
+// CHECK-INST: movprfx  z0, z7
+// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+
+adclt z0.d, z1.d, z31.d
+// CHECK-INST: adclt z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xd4,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d4 5f 45 <unknown>

test/MC/AArch64/SVE2/cadd-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+cadd z0.d, z1.d, z2.d, #90
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: cadd z0.d, z1.d, z2.d, #90
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid rotation
+
+cadd z0.d, z0.d, z1.d, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
+// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cadd z0.d, z0.d, z1.d, #180
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
+// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #180
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+cadd z0.d, z0.d, z1.d, #450
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
+// CHECK-NEXT: cadd z0.d, z0.d, z1.d, #450
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+cadd z0.d, z0.d, z31.d, #90
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: cadd z0.d, z0.d, z31.d, #90
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/cadd.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+cadd   z0.b, z0.b, z0.b, #90
+// CHECK-INST: cadd   z0.b, z0.b, z0.b, #90
+// CHECK-ENCODING: [0x00,0xd8,0x00,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 d8 00 45 <unknown>
+
+cadd   z0.h, z0.h, z0.h, #90
+// CHECK-INST: cadd   z0.h, z0.h, z0.h, #90
+// CHECK-ENCODING: [0x00,0xd8,0x40,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 d8 40 45 <unknown>
+
+cadd   z0.s, z0.s, z0.s, #90
+// CHECK-INST: cadd   z0.s, z0.s, z0.s, #90
+// CHECK-ENCODING: [0x00,0xd8,0x80,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 d8 80 45 <unknown>
+
+cadd   z0.d, z0.d, z0.d, #90
+// CHECK-INST: cadd   z0.d, z0.d, z0.d, #90
+// CHECK-ENCODING: [0x00,0xd8,0xc0,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 d8 c0 45 <unknown>
+
+cadd   z31.b, z31.b, z31.b, #270
+// CHECK-INST: cadd   z31.b, z31.b, z31.b, #270
+// CHECK-ENCODING: [0xff,0xdf,0x00,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff df 00 45 <unknown>
+
+cadd   z31.h, z31.h, z31.h, #270
+// CHECK-INST: cadd   z31.h, z31.h, z31.h, #270
+// CHECK-ENCODING: [0xff,0xdf,0x40,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff df 40 45 <unknown>
+
+cadd   z31.s, z31.s, z31.s, #270
+// CHECK-INST: cadd   z31.s, z31.s, z31.s, #270
+// CHECK-ENCODING: [0xff,0xdf,0x80,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff df 80 45 <unknown>
+
+cadd   z31.d, z31.d, z31.d, #270
+// CHECK-INST: cadd   z31.d, z31.d, z31.d, #270
+// CHECK-ENCODING: [0xff,0xdf,0xc0,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff df c0 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z4, z6
+// CHECK-INST: movprfx  z4, z6
+// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+
+cadd   z4.d, z4.d, z31.d, #270
+// CHECK-INST: cadd z4.d, z4.d, z31.d, #270
+// CHECK-ENCODING: [0xe4,0xdf,0xc0,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: e4 df c0 45 <unknown>

test/MC/AArch64/SVE2/saba-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+saba z0.b, z1.h, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: saba z0.b, z1.h, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+saba z0.d, z1.d, z7.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: saba z0.d, z1.d, z7.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/saba.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+saba z0.b, z1.b, z31.b
+// CHECK-INST: saba z0.b, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0xf8,0x1f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 f8 1f 45 <unknown>
+
+saba z0.h, z1.h, z31.h
+// CHECK-INST: saba z0.h, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0xf8,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 f8 5f 45 <unknown>
+
+saba z0.s, z1.s, z31.s
+// CHECK-INST: saba z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xf8,0x9f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 f8 9f 45 <unknown>
+
+saba z0.d, z1.d, z31.d
+// CHECK-INST: saba z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xf8,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 f8 df 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z0, z7
+// CHECK-INST: movprfx  z0, z7
+// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+
+saba z0.d, z1.d, z31.d
+// CHECK-INST: saba z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xf8,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 f8 df 45 <unknown>

test/MC/AArch64/SVE2/sabalb-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+sabalb z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sabalb z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sabalb z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sabalb z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sabalb z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sabalb z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sabalb z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sabalb z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+sabalb  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: sabalb  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sabalb.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+sabalb z0.h, z1.b, z31.b
+// CHECK-INST: sabalb z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0xc0,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 c0 5f 45 <unknown>
+
+sabalb z0.s, z1.h, z31.h
+// CHECK-INST: sabalb z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0xc0,0x9f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 c0 9f 45 <unknown>
+
+sabalb z0.d, z1.s, z31.s
+// CHECK-INST: sabalb z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xc0,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 c0 df 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx  z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+sabalb z21.d, z1.s, z31.s
+// CHECK-INST: sabalb z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0xc0,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 c0 df 45 <unknown>

test/MC/AArch64/SVE2/sabalt-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+sabalt z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sabalt z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sabalt z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sabalt z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sabalt z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sabalt z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sabalt z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sabalt z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+sabalt  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: sabalt  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sabalt.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+sabalt z0.h, z1.b, z31.b
+// CHECK-INST: sabalt z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0xc4,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 c4 5f 45 <unknown>
+
+sabalt z0.s, z1.h, z31.h
+// CHECK-INST: sabalt z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0xc4,0x9f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 c4 9f 45 <unknown>
+
+sabalt z0.d, z1.s, z31.s
+// CHECK-INST: sabalt z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xc4,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 c4 df 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx  z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+sabalt z21.d, z1.s, z31.s
+// CHECK-INST: sabalt z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0xc4,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 c4 df 45 <unknown>

test/MC/AArch64/SVE2/sbclb-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+sbclb z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sbclb z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sbclb z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sbclb z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+sbclb z0.d, z1.d, z7.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: sbclb z0.d, z1.d, z7.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sbclb.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sbclb z0.s, z1.s, z31.s
+// CHECK-INST: sbclb z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xd0,0x9f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d0 9f 45 <unknown>
+
+sbclb z0.d, z1.d, z31.d
+// CHECK-INST: sbclb z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xd0,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d0 df 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z0, z7
+// CHECK-INST: movprfx  z0, z7
+// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+
+sbclb z0.d, z1.d, z31.d
+// CHECK-INST: sbclb z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xd0,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d0 df 45 <unknown>

test/MC/AArch64/SVE2/sbclt-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+sbclt z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sbclt z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sbclt z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sbclt z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+sbclt z0.d, z1.d, z7.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: sbclt z0.d, z1.d, z7.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sbclt.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sbclt z0.s, z1.s, z31.s
+// CHECK-INST: sbclt z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xd4,0x9f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d4 9f 45 <unknown>
+
+sbclt z0.d, z1.d, z31.d
+// CHECK-INST: sbclt z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xd4,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d4 df 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z0, z7
+// CHECK-INST: movprfx  z0, z7
+// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+
+sbclt z0.d, z1.d, z31.d
+// CHECK-INST: sbclt z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xd4,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 d4 df 45 <unknown>

test/MC/AArch64/SVE2/sli-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+sli z18.b, z28.b, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
+// CHECK-NEXT: sli z18.b, z28.b, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sli z1.b, z9.b, #8
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7]
+// CHECK-NEXT: sli z1.b, z9.b, #8
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sli z21.h, z2.h, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
+// CHECK-NEXT: sli z21.h, z2.h, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sli z14.h, z30.h, #16
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15]
+// CHECK-NEXT: sli z14.h, z30.h, #16
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sli z6.s, z12.s, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
+// CHECK-NEXT: sli z6.s, z12.s, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sli z23.s, z19.s, #32
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 31]
+// CHECK-NEXT: sli z23.s, z19.s, #32
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sli z3.d, z24.d, #-1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
+// CHECK-NEXT: sli z3.d, z24.d, #-1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sli z25.d, z16.d, #64
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
+// CHECK-NEXT: sli z25.d, z16.d, #64
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+sli z0.b, z0.h, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sli z0.b, z0.h, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z31, z6
+sli     z31.d, z31.d, #63
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: sli     z31.d, z31.d, #63
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sli.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sli     z0.b, z0.b, #0
+// CHECK-INST: sli  z0.b, z0.b, #0
+// CHECK-ENCODING: [0x00,0xf4,0x08,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 f4 08 45 <unknown>
+
+sli     z31.b, z31.b, #7
+// CHECK-INST: sli  z31.b, z31.b, #7
+// CHECK-ENCODING: [0xff,0xf7,0x0f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff f7 0f 45 <unknown>
+
+sli     z0.h, z0.h, #0
+// CHECK-INST: sli  z0.h, z0.h, #0
+// CHECK-ENCODING: [0x00,0xf4,0x10,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 f4 10 45 <unknown>
+
+sli     z31.h, z31.h, #15
+// CHECK-INST: sli  z31.h, z31.h, #15
+// CHECK-ENCODING: [0xff,0xf7,0x1f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff f7 1f 45 <unknown>
+
+sli     z0.s, z0.s, #0
+// CHECK-INST: sli  z0.s, z0.s, #0
+// CHECK-ENCODING: [0x00,0xf4,0x40,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 f4 40 45 <unknown>
+
+sli     z31.s, z31.s, #31
+// CHECK-INST: sli  z31.s, z31.s, #31
+// CHECK-ENCODING: [0xff,0xf7,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff f7 5f 45 <unknown>
+
+sli     z0.d, z0.d, #0
+// CHECK-INST: sli  z0.d, z0.d, #0
+// CHECK-ENCODING: [0x00,0xf4,0x80,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 f4 80 45 <unknown>
+
+sli     z31.d, z31.d, #63
+// CHECK-INST: sli  z31.d, z31.d, #63
+// CHECK-ENCODING: [0xff,0xf7,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff f7 df 45 <unknown>

test/MC/AArch64/SVE2/sqcadd-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Source and Destination Registers must match
+
+sqcadd z0.d, z1.d, z2.d, #90
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: sqcadd z0.d, z1.d, z2.d, #90
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Invalid rotation
+
+sqcadd z0.d, z0.d, z1.d, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
+// CHECK-NEXT: sqcadd z0.d, z0.d, z1.d, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqcadd z0.d, z0.d, z1.d, #180
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
+// CHECK-NEXT: sqcadd z0.d, z0.d, z1.d, #180
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqcadd z0.d, z0.d, z1.d, #450
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: complex rotation must be 90 or 270.
+// CHECK-NEXT: sqcadd z0.d, z0.d, z1.d, #450
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+sqcadd z0.d, z0.d, z31.d, #90
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: sqcadd z0.d, z0.d, z31.d, #90
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqcadd.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sqcadd   z0.b, z0.b, z0.b, #90
+// CHECK-INST: sqcadd   z0.b, z0.b, z0.b, #90
+// CHECK-ENCODING: [0x00,0xd8,0x01,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 d8 01 45 <unknown>
+
+sqcadd   z0.h, z0.h, z0.h, #90
+// CHECK-INST: sqcadd   z0.h, z0.h, z0.h, #90
+// CHECK-ENCODING: [0x00,0xd8,0x41,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 d8 41 45 <unknown>
+
+sqcadd   z0.s, z0.s, z0.s, #90
+// CHECK-INST: sqcadd   z0.s, z0.s, z0.s, #90
+// CHECK-ENCODING: [0x00,0xd8,0x81,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 d8 81 45 <unknown>
+
+sqcadd   z0.d, z0.d, z0.d, #90
+// CHECK-INST: sqcadd   z0.d, z0.d, z0.d, #90
+// CHECK-ENCODING: [0x00,0xd8,0xc1,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 d8 c1 45 <unknown>
+
+sqcadd   z31.b, z31.b, z31.b, #270
+// CHECK-INST: sqcadd   z31.b, z31.b, z31.b, #270
+// CHECK-ENCODING: [0xff,0xdf,0x01,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff df 01 45 <unknown>
+
+sqcadd   z31.h, z31.h, z31.h, #270
+// CHECK-INST: sqcadd   z31.h, z31.h, z31.h, #270
+// CHECK-ENCODING: [0xff,0xdf,0x41,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff df 41 45 <unknown>
+
+sqcadd   z31.s, z31.s, z31.s, #270
+// CHECK-INST: sqcadd   z31.s, z31.s, z31.s, #270
+// CHECK-ENCODING: [0xff,0xdf,0x81,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff df 81 45 <unknown>
+
+sqcadd   z31.d, z31.d, z31.d, #270
+// CHECK-INST: sqcadd   z31.d, z31.d, z31.d, #270
+// CHECK-ENCODING: [0xff,0xdf,0xc1,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff df c1 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z4, z6
+// CHECK-INST: movprfx  z4, z6
+// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
+
+sqcadd   z4.d, z4.d, z31.d, #270
+// CHECK-INST: sqcadd z4.d, z4.d, z31.d, #270
+// CHECK-ENCODING: [0xe4,0xdf,0xc1,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: e4 df c1 45 <unknown>

test/MC/AArch64/SVE2/sri-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+sri z30.b, z10.b, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: sri z30.b, z10.b, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sri z18.b, z27.b, #9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: sri z18.b, z27.b, #9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sri z26.h, z4.h, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sri z26.h, z4.h, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sri z25.h, z10.h, #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: sri z25.h, z10.h, #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sri z17.s, z0.s, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: sri z17.s, z0.s, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sri z0.s, z15.s, #33
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: sri z0.s, z15.s, #33
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sri z4.d, z13.d, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: sri z4.d, z13.d, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sri z26.d, z26.d, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: sri z26.d, z26.d, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+sri z0.b, z0.d, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sri z0.b, z0.d, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z31, z6
+sri     z31.d, z31.d, #64
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
+// CHECK-NEXT: sri     z31.d, z31.d, #64
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sri.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sri     z0.b, z0.b, #1
+// CHECK-INST: sri  z0.b, z0.b, #1
+// CHECK-ENCODING: [0x00,0xf0,0x0f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 f0 0f 45 <unknown>
+
+sri     z31.b, z31.b, #8
+// CHECK-INST: sri  z31.b, z31.b, #8
+// CHECK-ENCODING: [0xff,0xf3,0x08,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff f3 08 45 <unknown>
+
+sri     z0.h, z0.h, #1
+// CHECK-INST: sri  z0.h, z0.h, #1
+// CHECK-ENCODING: [0x00,0xf0,0x1f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 f0 1f 45 <unknown>
+
+sri     z31.h, z31.h, #16
+// CHECK-INST: sri  z31.h, z31.h, #16
+// CHECK-ENCODING: [0xff,0xf3,0x10,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff f3 10 45 <unknown>
+
+sri     z0.s, z0.s, #1
+// CHECK-INST: sri  z0.s, z0.s, #1
+// CHECK-ENCODING: [0x00,0xf0,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 f0 5f 45 <unknown>
+
+sri     z31.s, z31.s, #32
+// CHECK-INST: sri  z31.s, z31.s, #32
+// CHECK-ENCODING: [0xff,0xf3,0x40,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff f3 40 45 <unknown>
+
+sri     z0.d, z0.d, #1
+// CHECK-INST: sri  z0.d, z0.d, #1
+// CHECK-ENCODING: [0x00,0xf0,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 f0 df 45 <unknown>
+
+sri     z31.d, z31.d, #64
+// CHECK-INST: sri  z31.d, z31.d, #64
+// CHECK-ENCODING: [0xff,0xf3,0x80,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff f3 80 45 <unknown>

test/MC/AArch64/SVE2/srsra-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+srsra z30.b, z10.b, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: srsra z30.b, z10.b, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srsra z18.b, z27.b, #9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: srsra z18.b, z27.b, #9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srsra z26.h, z4.h, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: srsra z26.h, z4.h, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srsra z25.h, z10.h, #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: srsra z25.h, z10.h, #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srsra z17.s, z0.s, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: srsra z17.s, z0.s, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srsra z0.s, z15.s, #33
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: srsra z0.s, z15.s, #33
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srsra z4.d, z13.d, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: srsra z4.d, z13.d, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+srsra z26.d, z26.d, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: srsra z26.d, z26.d, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+srsra z0.b, z0.d, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: srsra z0.b, z0.d, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+srsra     z0.d, z1.d, #64
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: srsra     z0.d, z1.d, #64
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/srsra.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+srsra     z0.b, z0.b, #1
+// CHECK-INST: srsra  z0.b, z0.b, #1
+// CHECK-ENCODING: [0x00,0xe8,0x0f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e8 0f 45 <unknown>
+
+srsra     z31.b, z31.b, #8
+// CHECK-INST: srsra  z31.b, z31.b, #8
+// CHECK-ENCODING: [0xff,0xeb,0x08,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff eb 08 45 <unknown>
+
+srsra     z0.h, z0.h, #1
+// CHECK-INST: srsra  z0.h, z0.h, #1
+// CHECK-ENCODING: [0x00,0xe8,0x1f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e8 1f 45 <unknown>
+
+srsra     z31.h, z31.h, #16
+// CHECK-INST: srsra  z31.h, z31.h, #16
+// CHECK-ENCODING: [0xff,0xeb,0x10,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff eb 10 45 <unknown>
+
+srsra     z0.s, z0.s, #1
+// CHECK-INST: srsra  z0.s, z0.s, #1
+// CHECK-ENCODING: [0x00,0xe8,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e8 5f 45 <unknown>
+
+srsra     z31.s, z31.s, #32
+// CHECK-INST: srsra  z31.s, z31.s, #32
+// CHECK-ENCODING: [0xff,0xeb,0x40,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff eb 40 45 <unknown>
+
+srsra     z0.d, z0.d, #1
+// CHECK-INST: srsra  z0.d, z0.d, #1
+// CHECK-ENCODING: [0x00,0xe8,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e8 df 45 <unknown>
+
+srsra     z31.d, z31.d, #64
+// CHECK-INST: srsra  z31.d, z31.d, #64
+// CHECK-ENCODING: [0xff,0xeb,0x80,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff eb 80 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z0, z7
+// CHECK-INST: movprfx  z0, z7
+// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+
+srsra     z0.d, z1.d, #1
+// CHECK-INST: srsra  z0.d, z1.d, #1
+// CHECK-ENCODING: [0x20,0xe8,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 e8 df 45 <unknown>

test/MC/AArch64/SVE2/ssra-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+ssra z30.b, z10.b, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: ssra z30.b, z10.b, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ssra z18.b, z27.b, #9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: ssra z18.b, z27.b, #9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ssra z26.h, z4.h, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: ssra z26.h, z4.h, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ssra z25.h, z10.h, #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: ssra z25.h, z10.h, #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ssra z17.s, z0.s, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: ssra z17.s, z0.s, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ssra z0.s, z15.s, #33
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: ssra z0.s, z15.s, #33
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ssra z4.d, z13.d, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: ssra z4.d, z13.d, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ssra z26.d, z26.d, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: ssra z26.d, z26.d, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+ssra z0.b, z0.d, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ssra z0.b, z0.d, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+ssra     z0.d, z1.d, #64
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: ssra     z0.d, z1.d, #64
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ssra.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ssra     z0.b, z0.b, #1
+// CHECK-INST: ssra z0.b, z0.b, #1
+// CHECK-ENCODING: [0x00,0xe0,0x0f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e0 0f 45 <unknown>
+
+ssra     z31.b, z31.b, #8
+// CHECK-INST: ssra z31.b, z31.b, #8
+// CHECK-ENCODING: [0xff,0xe3,0x08,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff e3 08 45 <unknown>
+
+ssra     z0.h, z0.h, #1
+// CHECK-INST: ssra z0.h, z0.h, #1
+// CHECK-ENCODING: [0x00,0xe0,0x1f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e0 1f 45 <unknown>
+
+ssra     z31.h, z31.h, #16
+// CHECK-INST: ssra z31.h, z31.h, #16
+// CHECK-ENCODING: [0xff,0xe3,0x10,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff e3 10 45 <unknown>
+
+ssra     z0.s, z0.s, #1
+// CHECK-INST: ssra z0.s, z0.s, #1
+// CHECK-ENCODING: [0x00,0xe0,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e0 5f 45 <unknown>
+
+ssra     z31.s, z31.s, #32
+// CHECK-INST: ssra z31.s, z31.s, #32
+// CHECK-ENCODING: [0xff,0xe3,0x40,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff e3 40 45 <unknown>
+
+ssra     z0.d, z0.d, #1
+// CHECK-INST: ssra z0.d, z0.d, #1
+// CHECK-ENCODING: [0x00,0xe0,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e0 df 45 <unknown>
+
+ssra     z31.d, z31.d, #64
+// CHECK-INST: ssra z31.d, z31.d, #64
+// CHECK-ENCODING: [0xff,0xe3,0x80,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff e3 80 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z0, z7
+// CHECK-INST: movprfx  z0, z7
+// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+
+ssra     z0.d, z1.d, #1
+// CHECK-INST: ssra z0.d, z1.d, #1
+// CHECK-ENCODING: [0x20,0xe0,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 e0 df 45 <unknown>

test/MC/AArch64/SVE2/uaba-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+uaba z0.b, z1.h, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uaba z0.b, z1.h, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+uaba z0.d, z1.d, z7.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: uaba z0.d, z1.d, z7.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uaba.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+uaba z0.b, z1.b, z31.b
+// CHECK-INST: uaba z0.b, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0xfc,0x1f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 fc 1f 45 <unknown>
+
+uaba z0.h, z1.h, z31.h
+// CHECK-INST: uaba z0.h, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0xfc,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 fc 5f 45 <unknown>
+
+uaba z0.s, z1.s, z31.s
+// CHECK-INST: uaba z0.s, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xfc,0x9f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 fc 9f 45 <unknown>
+
+uaba z0.d, z1.d, z31.d
+// CHECK-INST: uaba z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xfc,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 fc df 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z0, z7
+// CHECK-INST: movprfx  z0, z7
+// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+
+uaba z0.d, z1.d, z31.d
+// CHECK-INST: uaba z0.d, z1.d, z31.d
+// CHECK-ENCODING: [0x20,0xfc,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 fc df 45 <unknown>

test/MC/AArch64/SVE2/uabalb-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+uabalb z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uabalb z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uabalb z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uabalb z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uabalb z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uabalb z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uabalb z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uabalb z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+uabalb  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: uabalb  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uabalb.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+uabalb z0.h, z1.b, z31.b
+// CHECK-INST: uabalb z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0xc8,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 c8 5f 45 <unknown>
+
+uabalb z0.s, z1.h, z31.h
+// CHECK-INST: uabalb z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0xc8,0x9f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 c8 9f 45 <unknown>
+
+uabalb z0.d, z1.s, z31.s
+// CHECK-INST: uabalb z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xc8,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 c8 df 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx  z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+uabalb z21.d, z1.s, z31.s
+// CHECK-INST: uabalb z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0xc8,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 c8 df 45 <unknown>

test/MC/AArch64/SVE2/uabalt-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element width
+
+uabalt z0.b, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uabalt z0.b, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uabalt z0.h, z1.h, z2.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uabalt z0.h, z1.h, z2.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uabalt z0.s, z1.s, z2.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uabalt z0.s, z1.s, z2.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uabalt z0.d, z1.d, z2.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uabalt z0.d, z1.d, z2.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+uabalt  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: uabalt  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/uabalt.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+
+uabalt z0.h, z1.b, z31.b
+// CHECK-INST: uabalt z0.h, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0xcc,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 cc 5f 45 <unknown>
+
+uabalt z0.s, z1.h, z31.h
+// CHECK-INST: uabalt z0.s, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0xcc,0x9f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 cc 9f 45 <unknown>
+
+uabalt z0.d, z1.s, z31.s
+// CHECK-INST: uabalt z0.d, z1.s, z31.s
+// CHECK-ENCODING: [0x20,0xcc,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 cc df 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z21, z28
+// CHECK-INST: movprfx  z21, z28
+// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
+
+uabalt z21.d, z1.s, z31.s
+// CHECK-INST: uabalt z21.d, z1.s, z31.s
+// CHECK-ENCODING: [0x35,0xcc,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 35 cc df 45 <unknown>

test/MC/AArch64/SVE2/ursra-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+ursra z30.b, z10.b, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: ursra z30.b, z10.b, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ursra z18.b, z27.b, #9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: ursra z18.b, z27.b, #9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ursra z26.h, z4.h, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: ursra z26.h, z4.h, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ursra z25.h, z10.h, #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: ursra z25.h, z10.h, #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ursra z17.s, z0.s, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: ursra z17.s, z0.s, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ursra z0.s, z15.s, #33
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: ursra z0.s, z15.s, #33
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ursra z4.d, z13.d, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: ursra z4.d, z13.d, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ursra z26.d, z26.d, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: ursra z26.d, z26.d, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+ursra z0.b, z0.d, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ursra z0.b, z0.d, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+ursra     z0.d, z1.d, #64
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: ursra     z0.d, z1.d, #64
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ursra.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+ursra     z0.b, z0.b, #1
+// CHECK-INST: ursra  z0.b, z0.b, #1
+// CHECK-ENCODING: [0x00,0xec,0x0f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 ec 0f 45 <unknown>
+
+ursra     z31.b, z31.b, #8
+// CHECK-INST: ursra  z31.b, z31.b, #8
+// CHECK-ENCODING: [0xff,0xef,0x08,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff ef 08 45 <unknown>
+
+ursra     z0.h, z0.h, #1
+// CHECK-INST: ursra  z0.h, z0.h, #1
+// CHECK-ENCODING: [0x00,0xec,0x1f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 ec 1f 45 <unknown>
+
+ursra     z31.h, z31.h, #16
+// CHECK-INST: ursra  z31.h, z31.h, #16
+// CHECK-ENCODING: [0xff,0xef,0x10,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff ef 10 45 <unknown>
+
+ursra     z0.s, z0.s, #1
+// CHECK-INST: ursra  z0.s, z0.s, #1
+// CHECK-ENCODING: [0x00,0xec,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 ec 5f 45 <unknown>
+
+ursra     z31.s, z31.s, #32
+// CHECK-INST: ursra  z31.s, z31.s, #32
+// CHECK-ENCODING: [0xff,0xef,0x40,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff ef 40 45 <unknown>
+
+ursra     z0.d, z0.d, #1
+// CHECK-INST: ursra  z0.d, z0.d, #1
+// CHECK-ENCODING: [0x00,0xec,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 ec df 45 <unknown>
+
+ursra     z31.d, z31.d, #64
+// CHECK-INST: ursra  z31.d, z31.d, #64
+// CHECK-ENCODING: [0xff,0xef,0x80,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff ef 80 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z0, z7
+// CHECK-INST: movprfx  z0, z7
+// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+
+ursra     z0.d, z1.d, #1
+// CHECK-INST: ursra  z0.d, z1.d, #1
+// CHECK-ENCODING: [0x20,0xec,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 ec df 45 <unknown>

test/MC/AArch64/SVE2/usra-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2  2>&1 < %s| FileCheck %s
+
+usra z30.b, z10.b, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: usra z30.b, z10.b, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usra z18.b, z27.b, #9
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 8]
+// CHECK-NEXT: usra z18.b, z27.b, #9
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usra z26.h, z4.h, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: usra z26.h, z4.h, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usra z25.h, z10.h, #17
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 16]
+// CHECK-NEXT: usra z25.h, z10.h, #17
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usra z17.s, z0.s, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: usra z17.s, z0.s, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usra z0.s, z15.s, #33
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 32]
+// CHECK-NEXT: usra z0.s, z15.s, #33
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usra z4.d, z13.d, #0
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: usra z4.d, z13.d, #0
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+usra z26.d, z26.d, #65
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
+// CHECK-NEXT: usra z26.d, z26.d, #65
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Element sizes must match
+
+usra z0.b, z0.d, #1
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: usra z0.b, z0.d, #1
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Negative tests for instructions that are incompatible with movprfx
+
+movprfx z0.d, p0/z, z7.d
+usra     z0.d, z1.d, #64
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
+// CHECK-NEXT: usra     z0.d, z1.d, #64
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/usra.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+usra     z0.b, z0.b, #1
+// CHECK-INST: usra z0.b, z0.b, #1
+// CHECK-ENCODING: [0x00,0xe4,0x0f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e4 0f 45 <unknown>
+
+usra     z31.b, z31.b, #8
+// CHECK-INST: usra z31.b, z31.b, #8
+// CHECK-ENCODING: [0xff,0xe7,0x08,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff e7 08 45 <unknown>
+
+usra     z0.h, z0.h, #1
+// CHECK-INST: usra z0.h, z0.h, #1
+// CHECK-ENCODING: [0x00,0xe4,0x1f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e4 1f 45 <unknown>
+
+usra     z31.h, z31.h, #16
+// CHECK-INST: usra z31.h, z31.h, #16
+// CHECK-ENCODING: [0xff,0xe7,0x10,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff e7 10 45 <unknown>
+
+usra     z0.s, z0.s, #1
+// CHECK-INST: usra z0.s, z0.s, #1
+// CHECK-ENCODING: [0x00,0xe4,0x5f,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e4 5f 45 <unknown>
+
+usra     z31.s, z31.s, #32
+// CHECK-INST: usra z31.s, z31.s, #32
+// CHECK-ENCODING: [0xff,0xe7,0x40,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff e7 40 45 <unknown>
+
+usra     z0.d, z0.d, #1
+// CHECK-INST: usra z0.d, z0.d, #1
+// CHECK-ENCODING: [0x00,0xe4,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 00 e4 df 45 <unknown>
+
+usra     z31.d, z31.d, #64
+// CHECK-INST: usra z31.d, z31.d, #64
+// CHECK-ENCODING: [0xff,0xe7,0x80,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: ff e7 80 45 <unknown>
+
+
+// --------------------------------------------------------------------------//
+// Test compatibility with MOVPRFX instruction.
+
+movprfx z0, z7
+// CHECK-INST: movprfx  z0, z7
+// CHECK-ENCODING: [0xe0,0xbc,0x20,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 bc 20 04 <unknown>
+
+usra     z0.d, z1.d, #1
+// CHECK-INST: usra z0.d, z1.d, #1
+// CHECK-ENCODING: [0x20,0xe4,0xdf,0x45]
+// CHECK-ERROR: instruction requires: sve2
+// CHECK-UNKNOWN: 20 e4 df 45 <unknown>