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Differential D62129

[AArch64][SVE2] Asm: add integer unary instructions (predicated)
ClosedPublic

Authored by c-rhodes on May 20 2019, 2:57 AM.

Details

Reviewers
sdesmalen
SjoerdMeijer
rovka
Commits
rZORGe1f4b5e92123: [AArch64][SVE2] Asm: add integer unary instructions (predicated)
rGe1f4b5e92123: [AArch64][SVE2] Asm: add integer unary instructions (predicated)
rG7f47b75d185a: [AArch64][SVE2] Asm: add integer unary instructions (predicated)
rL361230: [AArch64][SVE2] Asm: add integer unary instructions (predicated)
Summary

Patch adds support for the following instructions:

  • URECPE, URSQRTE, SQABS, SQNEG

The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest

Diff Detail

Event Timeline

c-rhodes created this revision.May 20 2019, 2:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptMay 20 2019, 2:57 AM
Herald added subscribers: kristof.beyls, tschuett, javed.absar. · View Herald Transcript
c-rhodes added a parent revision: D62128: [AArch64][SVE2] Asm: add integer pairwise arithmetic instructions.May 20 2019, 2:57 AM
c-rhodes added a child revision: D62130: [AArch64][SVE2] Asm: add saturating add/sub instructions.May 20 2019, 3:00 AM
SjoerdMeijer accepted this revision.May 20 2019, 3:04 AM

LGTM

This revision is now accepted and ready to land.May 20 2019, 3:04 AM
Closed by commit rL361230: [AArch64][SVE2] Asm: add integer unary instructions (predicated) (authored by c-rhodes). · Explain WhyMay 21 2019, 2:04 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AArch64/
6 lines
36 lines
test/
MC/
AArch64/
SVE2/
23 lines
60 lines
23 lines
60 lines
33 lines
42 lines
33 lines
42 lines

Diff 200228

lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 1,128 Lines • ▼ Show 20 Lineslet Predicates = [HasSVE2] in {
// SVE2 integer pairwise arithmetic // SVE2 integer pairwise arithmetic
defm ADDP_ZPmZ : sve2_int_arith_pred<0b100011, "addp">; defm ADDP_ZPmZ : sve2_int_arith_pred<0b100011, "addp">;
defm SMAXP_ZPmZ : sve2_int_arith_pred<0b101001, "smaxp">; defm SMAXP_ZPmZ : sve2_int_arith_pred<0b101001, "smaxp">;
defm UMAXP_ZPmZ : sve2_int_arith_pred<0b101011, "umaxp">; defm UMAXP_ZPmZ : sve2_int_arith_pred<0b101011, "umaxp">;
defm SMINP_ZPmZ : sve2_int_arith_pred<0b101101, "sminp">; defm SMINP_ZPmZ : sve2_int_arith_pred<0b101101, "sminp">;
defm UMINP_ZPmZ : sve2_int_arith_pred<0b101111, "uminp">; defm UMINP_ZPmZ : sve2_int_arith_pred<0b101111, "uminp">;
// SVE2 integer unary operations (predicated)
defm URECPE_ZPmZ : sve2_int_un_pred_arit_s<0b000, "urecpe">;
defm URSQRTE_ZPmZ : sve2_int_un_pred_arit_s<0b001, "ursqrte">;
defm SQABS_ZPmZ : sve2_int_un_pred_arit<0b100, "sqabs">;
defm SQNEG_ZPmZ : sve2_int_un_pred_arit<0b101, "sqneg">;
// SVE2 integer multiply long // SVE2 integer multiply long
defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">; defm SQDMULLB_ZZZ : sve2_wide_int_arith_long<0b11000, "sqdmullb">;
defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">; defm SQDMULLT_ZZZ : sve2_wide_int_arith_long<0b11001, "sqdmullt">;
defm SMULLB_ZZZ : sve2_wide_int_arith_long<0b11100, "smullb">; defm SMULLB_ZZZ : sve2_wide_int_arith_long<0b11100, "smullb">;
defm SMULLT_ZZZ : sve2_wide_int_arith_long<0b11101, "smullt">; defm SMULLT_ZZZ : sve2_wide_int_arith_long<0b11101, "smullt">;
defm UMULLB_ZZZ : sve2_wide_int_arith_long<0b11110, "umullb">; defm UMULLB_ZZZ : sve2_wide_int_arith_long<0b11110, "umullb">;
defm UMULLT_ZZZ : sve2_wide_int_arith_long<0b11111, "umullt">; defm UMULLT_ZZZ : sve2_wide_int_arith_long<0b11111, "umullt">;
} }

lib/Target/AArch64/SVEInstrFormats.td

Show First 20 Lines • Show All 2,111 Lines • ▼ Show 20 Lines
} }
multiclass sve2_int_sadd_long_accum_pairwise<bit U, string asm> { multiclass sve2_int_sadd_long_accum_pairwise<bit U, string asm> {
def _H : sve2_int_sadd_long_accum_pairwise<0b01, U, asm, ZPR16, ZPR8>; def _H : sve2_int_sadd_long_accum_pairwise<0b01, U, asm, ZPR16, ZPR8>;
def _S : sve2_int_sadd_long_accum_pairwise<0b10, U, asm, ZPR32, ZPR16>; def _S : sve2_int_sadd_long_accum_pairwise<0b10, U, asm, ZPR32, ZPR16>;
def _D : sve2_int_sadd_long_accum_pairwise<0b11, U, asm, ZPR64, ZPR32>; def _D : sve2_int_sadd_long_accum_pairwise<0b11, U, asm, ZPR64, ZPR32>;
} }
class sve2_int_un_pred_arit<bits<2> sz, bit Q, bits<2> opc,
string asm, ZPRRegOp zprty>
: I<(outs zprty:$Zd), (ins zprty:$_Zd, PPR3bAny:$Pg, zprty:$Zn),
asm, "\t$Zd, $Pg/m, $Zn",
"",
[]>, Sched<[]> {
bits<3> Pg;
bits<5> Zd;
bits<5> Zn;
let Inst{31-24} = 0b01000100;
let Inst{23-22} = sz;
let Inst{21-20} = 0b00;
let Inst{19} = Q;
let Inst{18} = 0b0;
let Inst{17-16} = opc;
let Inst{15-13} = 0b101;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Zd;
let Constraints = "$Zd = $_Zd";
let DestructiveInstType = Destructive;
let ElementSize = zprty.ElementSize;
}
multiclass sve2_int_un_pred_arit_s<bits<3> opc, string asm> {
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>;
}
multiclass sve2_int_un_pred_arit<bits<3> opc, string asm> {
def _B : sve2_int_un_pred_arit<0b00, opc{2}, opc{1-0}, asm, ZPR8>;
def _H : sve2_int_un_pred_arit<0b01, opc{2}, opc{1-0}, asm, ZPR16>;
def _S : sve2_int_un_pred_arit<0b10, opc{2}, opc{1-0}, asm, ZPR32>;
def _D : sve2_int_un_pred_arit<0b11, opc{2}, opc{1-0}, asm, ZPR64>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE2 Widening Integer Arithmetic Group // SVE2 Widening Integer Arithmetic Group
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class sve2_wide_int_arith<bits<2> sz, bits<5> opc, string asm, class sve2_wide_int_arith<bits<2> sz, bits<5> opc, string asm,
ZPRRegOp zprty1, ZPRRegOp zprty2, ZPRRegOp zprty3> ZPRRegOp zprty1, ZPRRegOp zprty2, ZPRRegOp zprty3>
: I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm), : I<(outs zprty1:$Zd), (ins zprty2:$Zn, zprty3:$Zm),
asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> { asm, "\t$Zd, $Zn, $Zm", "", []>, Sched<[]> {
▲ Show 20 Lines • Show All 2,722 Lines • Show Last 20 Lines

test/MC/AArch64/SVE2/sqabs-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid predicate
sqabs z0.s, p0/z, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqabs z0.s, p0/z, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqabs z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqabs z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqabs z0.b, p7/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqabs z0.b, p7/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqabs.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqabs z31.b, p7/m, z31.b
// CHECK-INST: sqabs z31.b, p7/m, z31.b
// CHECK-ENCODING: [0xff,0xbf,0x08,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 08 44 <unknown>
sqabs z31.h, p7/m, z31.h
// CHECK-INST: sqabs z31.h, p7/m, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x48,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 48 44 <unknown>
sqabs z31.s, p7/m, z31.s
// CHECK-INST: sqabs z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x88,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 88 44 <unknown>
sqabs z31.d, p7/m, z31.d
// CHECK-INST: sqabs z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xc8,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf c8 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.s, p7/z, z6.s
// CHECK-INST: movprfx z4.s, p7/z, z6.s
// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
sqabs z4.s, p7/m, z31.s
// CHECK-INST: sqabs z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x88,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 88 44 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
sqabs z4.s, p7/m, z31.s
// CHECK-INST: sqabs z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x88,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 88 44 <unknown>

test/MC/AArch64/SVE2/sqneg-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid predicate
sqneg z0.s, p0/z, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sqneg z0.s, p0/z, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sqneg z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: sqneg z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
sqneg z0.b, p7/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sqneg z0.b, p7/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/sqneg.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
sqneg z31.b, p7/m, z31.b
// CHECK-INST: sqneg z31.b, p7/m, z31.b
// CHECK-ENCODING: [0xff,0xbf,0x09,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 09 44 <unknown>
sqneg z31.h, p7/m, z31.h
// CHECK-INST: sqneg z31.h, p7/m, z31.h
// CHECK-ENCODING: [0xff,0xbf,0x49,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 49 44 <unknown>
sqneg z31.s, p7/m, z31.s
// CHECK-INST: sqneg z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x89,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 89 44 <unknown>
sqneg z31.d, p7/m, z31.d
// CHECK-INST: sqneg z31.d, p7/m, z31.d
// CHECK-ENCODING: [0xff,0xbf,0xc9,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf c9 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.s, p7/z, z6.s
// CHECK-INST: movprfx z4.s, p7/z, z6.s
// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
sqneg z4.s, p7/m, z31.s
// CHECK-INST: sqneg z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x89,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 89 44 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
sqneg z4.s, p7/m, z31.s
// CHECK-INST: sqneg z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x89,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 89 44 <unknown>

test/MC/AArch64/SVE2/urecpe-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid predicate
urecpe z0.s, p0/z, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: urecpe z0.s, p0/z, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urecpe z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: urecpe z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
urecpe z0.b, p7/m, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urecpe z0.b, p7/m, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urecpe z0.h, p7/m, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urecpe z0.h, p7/m, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
urecpe z0.d, p7/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: urecpe z0.d, p7/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/urecpe.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
urecpe z31.s, p7/m, z31.s
// CHECK-INST: urecpe z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x80,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 80 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.s, p7/z, z6.s
// CHECK-INST: movprfx z4.s, p7/z, z6.s
// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
urecpe z4.s, p7/m, z31.s
// CHECK-INST: urecpe z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x80,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 80 44 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
urecpe z4.s, p7/m, z31.s
// CHECK-INST: urecpe z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x80,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 80 44 <unknown>

test/MC/AArch64/SVE2/ursqrte-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
// ------------------------------------------------------------------------- //
// Invalid predicate
ursqrte z0.s, p0/z, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ursqrte z0.s, p0/z, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursqrte z0.s, p8/m, z1.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
// CHECK-NEXT: ursqrte z0.s, p8/m, z1.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// ------------------------------------------------------------------------- //
// Invalid element width
ursqrte z0.b, p7/m, z1.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ursqrte z0.b, p7/m, z1.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursqrte z0.h, p7/m, z1.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ursqrte z0.h, p7/m, z1.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
ursqrte z0.d, p7/m, z1.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: ursqrte z0.d, p7/m, z1.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

test/MC/AArch64/SVE2/ursqrte.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
ursqrte z31.s, p7/m, z31.s
// CHECK-INST: ursqrte z31.s, p7/m, z31.s
// CHECK-ENCODING: [0xff,0xbf,0x81,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: ff bf 81 44 <unknown>
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.s, p7/z, z6.s
// CHECK-INST: movprfx z4.s, p7/z, z6.s
// CHECK-ENCODING: [0xc4,0x3c,0x90,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 3c 90 04 <unknown>
ursqrte z4.s, p7/m, z31.s
// CHECK-INST: ursqrte z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x81,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 81 44 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
ursqrte z4.s, p7/m, z31.s
// CHECK-INST: ursqrte z4.s, p7/m, z31.s
// CHECK-ENCODING: [0xe4,0xbf,0x81,0x44]
// CHECK-ERROR: instruction requires: sve2
// CHECK-UNKNOWN: e4 bf 81 44 <unknown>