[RISCV] Lower calls through PLT

[lewis-revill]

Summary

This patch adds support for generating calls through the procedure linkage table where required for a given ExternalSymbol or GlobalAddress callee.

[jrtc27]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1108 ↗

(On Diff #176742)

Do we want to be parsing the @plt for things other than call/tail? PseudoLLA also takes a bare_symbol but @plt isn't valid. Currently we parse bar@plt as a valid bare symbol; however, GNU as will reject it with illegal operands (as I understand it, this is because it doesn't treat @ as part of a valid identifier).

lib/Target/RISCV/RISCVSubtarget.cpp

51 ↗

(On Diff #176742)

This can be inlined in LowerCall, especially once the fno-plt stuff is gone, as it's the only user.

56 ↗

(On Diff #176742)

This seems to be X86-specific in LLVM; do we really need this in RISC-V? Clang's test/CodeGen/noplt.c gives a normal call foo@plt when compiled with riscv64-linux-gnu-gcc -fpic -fno-plt, so I would remove this and the related code.

[lewis-revill]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1108 ↗

(On Diff #176742)

Hmm, probably a good idea. I guess I'd have to add yet another operand type in RISCVInstrInfo. Checking Operands[0] for "call" or "tail" seems a bit hacky to me, but maybe it's a reasonable approach?

lib/Target/RISCV/RISCVSubtarget.cpp

56 ↗

(On Diff #176742)

OK, that makes things a lot simpler for LowerCall then. Is there no case where calls need to be lowered using GOT?

[lewis-revill]

Splitting this patch into MC layer and Codegen.

[lewis-revill]

Split into MC layer (patch D55335) and codegen (this patch).

[lewis-revill]

Removed capability of lowering through GOT since there is no apparent need to do so.

[lewis-revill]

Rebased to use D55560 and with fewer dependencies

[lewis-revill]

Rebased.

[lewis-revill]

Rebased and added testing using -relocation-model=pic in 'calls.ll'. Also added a dso_local callee to 'calls.ll' since this affects whether PLT is used for PIC.

[asb]

LGTM, thanks!

llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp

for (auto &Reg : RegsToPass) {
     Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
     Glue = Chain.getValue(1);
   }
 
   // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
   // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
   // split it and then direct call can be matched by PseudoCALL.
   if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
-    Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT, 0,
-                                        RISCVII::MO_CALL);
+    const GlobalValue *GV = S->getGlobal();
+
+    unsigned OpFlags = RISCVII::MO_CALL;
+    if (!getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV))
+      OpFlags = RISCVII::MO_PLT;
+
+    Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
   } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
-    Callee =
-        DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, RISCVII::MO_CALL);
+    unsigned OpFlags = RISCVII::MO_CALL;
+
+    if (!getTargetMachine().shouldAssumeDSOLocal(*MF.getFunction().getParent(),
+                                                 nullptr))
+      OpFlags = RISCVII::MO_PLT;
+
+    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags);
   }
 
   // The first call operand is the chain and the second is the target address.
   SmallVector<SDValue, 8> Ops;
   Ops.push_back(Chain);
   Ops.push_back(Callee);
 
   // Add argument registers to the end of the list so that they are

llvm/trunk/lib/Target/RISCV/RISCVMCInstLower.cpp

static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
   default:
     llvm_unreachable("Unknown target flag on GV operand");
   case RISCVII::MO_None:
     Kind = RISCVMCExpr::VK_RISCV_None;
     break;
   case RISCVII::MO_CALL:
     Kind = RISCVMCExpr::VK_RISCV_CALL;
     break;
+  case RISCVII::MO_PLT:
+    Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
+    break;
   case RISCVII::MO_LO:
     Kind = RISCVMCExpr::VK_RISCV_LO;
     break;
   case RISCVII::MO_HI:
     Kind = RISCVMCExpr::VK_RISCV_HI;
     break;
   case RISCVII::MO_PCREL_LO:
     Kind = RISCVMCExpr::VK_RISCV_PCREL_LO;

llvm/trunk/lib/Target/RISCV/Utils/RISCVBaseInfo.h

enum {
   InstFormatOther = 17,
 
   InstFormatMask = 31
 };
 
 enum {
   MO_None,
   MO_CALL,
+  MO_PLT,
   MO_LO,
   MO_HI,
   MO_PCREL_LO,
   MO_PCREL_HI,
   MO_GOT_HI,
 };
 } // namespace RISCVII
 

llvm/trunk/test/CodeGen/RISCV/calls.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN: llc -relocation-model=pic -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32I-PIC %s
 
 declare i32 @external_function(i32)
 
 define i32 @test_call_external(i32 %a) nounwind {
 ; RV32I-LABEL: test_call_external:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    call external_function
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32I-PIC-LABEL: test_call_external:
+; RV32I-PIC:       # %bb.0:
+; RV32I-PIC-NEXT:    addi sp, sp, -16
+; RV32I-PIC-NEXT:    sw ra, 12(sp)
+; RV32I-PIC-NEXT:    call external_function@plt
+; RV32I-PIC-NEXT:    lw ra, 12(sp)
+; RV32I-PIC-NEXT:    addi sp, sp, 16
+; RV32I-PIC-NEXT:    ret
   %1 = call i32 @external_function(i32 %a)
   ret i32 %1
 }
 
+declare dso_local i32 @dso_local_function(i32)
+
+define i32 @test_call_dso_local(i32 %a) nounwind {
+; RV32I-LABEL: test_call_dso_local:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp)
+; RV32I-NEXT:    call dso_local_function
+; RV32I-NEXT:    lw ra, 12(sp)
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+;
+; RV32I-PIC-LABEL: test_call_dso_local:
+; RV32I-PIC:       # %bb.0:
+; RV32I-PIC-NEXT:    addi sp, sp, -16
+; RV32I-PIC-NEXT:    sw ra, 12(sp)
+; RV32I-PIC-NEXT:    call dso_local_function
+; RV32I-PIC-NEXT:    lw ra, 12(sp)
+; RV32I-PIC-NEXT:    addi sp, sp, 16
+; RV32I-PIC-NEXT:    ret
+  %1 = call i32 @dso_local_function(i32 %a)
+  ret i32 %1
+}
+
 define i32 @defined_function(i32 %a) nounwind {
 ; RV32I-LABEL: defined_function:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, a0, 1
 ; RV32I-NEXT:    ret
+;
+; RV32I-PIC-LABEL: defined_function:
+; RV32I-PIC:       # %bb.0:
+; RV32I-PIC-NEXT:    addi a0, a0, 1
+; RV32I-PIC-NEXT:    ret
   %1 = add i32 %a, 1
   ret i32 %1
 }
 
 define i32 @test_call_defined(i32 %a) nounwind {
 ; RV32I-LABEL: test_call_defined:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    call defined_function
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32I-PIC-LABEL: test_call_defined:
+; RV32I-PIC:       # %bb.0:
+; RV32I-PIC-NEXT:    addi sp, sp, -16
+; RV32I-PIC-NEXT:    sw ra, 12(sp)
+; RV32I-PIC-NEXT:    call defined_function@plt
+; RV32I-PIC-NEXT:    lw ra, 12(sp)
+; RV32I-PIC-NEXT:    addi sp, sp, 16
+; RV32I-PIC-NEXT:    ret
   %1 = call i32 @defined_function(i32 %a)
   ret i32 %1
 }
 
 define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind {
 ; RV32I-LABEL: test_call_indirect:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    mv a0, a1
 ; RV32I-NEXT:    jalr a2
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32I-PIC-LABEL: test_call_indirect:
+; RV32I-PIC:       # %bb.0:
+; RV32I-PIC-NEXT:    addi sp, sp, -16
+; RV32I-PIC-NEXT:    sw ra, 12(sp)
+; RV32I-PIC-NEXT:    mv a2, a0
+; RV32I-PIC-NEXT:    mv a0, a1
+; RV32I-PIC-NEXT:    jalr a2
+; RV32I-PIC-NEXT:    lw ra, 12(sp)
+; RV32I-PIC-NEXT:    addi sp, sp, 16
+; RV32I-PIC-NEXT:    ret
   %1 = call i32 %a(i32 %b)
   ret i32 %1
 }
 
 ; Ensure that calls to fastcc functions aren't rejected. Such calls may be
 ; introduced when compiling with optimisation.
 
 define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: fastcc_function:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
+;
+; RV32I-PIC-LABEL: fastcc_function:
+; RV32I-PIC:       # %bb.0:
+; RV32I-PIC-NEXT:    add a0, a0, a1
+; RV32I-PIC-NEXT:    ret
  %1 = add i32 %a, %b
  ret i32 %1
 }
 
 define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
 ; RV32I-LABEL: test_call_fastcc:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    sw s0, 8(sp)
 ; RV32I-NEXT:    mv s0, a0
 ; RV32I-NEXT:    call fastcc_function
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32I-PIC-LABEL: test_call_fastcc:
+; RV32I-PIC:       # %bb.0:
+; RV32I-PIC-NEXT:    addi sp, sp, -16
+; RV32I-PIC-NEXT:    sw ra, 12(sp)
+; RV32I-PIC-NEXT:    sw s0, 8(sp)
+; RV32I-PIC-NEXT:    mv s0, a0
+; RV32I-PIC-NEXT:    call fastcc_function@plt
+; RV32I-PIC-NEXT:    mv a0, s0
+; RV32I-PIC-NEXT:    lw s0, 8(sp)
+; RV32I-PIC-NEXT:    lw ra, 12(sp)
+; RV32I-PIC-NEXT:    addi sp, sp, 16
+; RV32I-PIC-NEXT:    ret
   %1 = call fastcc i32 @fastcc_function(i32 %a, i32 %b)
   ret i32 %a
 }
 
 declare i32 @external_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) nounwind
 
 define i32 @test_call_external_many_args(i32 %a) nounwind {
 ; RV32I-LABEL: test_call_external_many_args:

 ; RV32I-NEXT:    mv a6, a0
 ; RV32I-NEXT:    mv a7, a0
 ; RV32I-NEXT:    call external_many_args
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    lw s0, 8(sp)
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32I-PIC-LABEL: test_call_external_many_args:
+; RV32I-PIC:       # %bb.0:
+; RV32I-PIC-NEXT:    addi sp, sp, -16
+; RV32I-PIC-NEXT:    sw ra, 12(sp)
+; RV32I-PIC-NEXT:    sw s0, 8(sp)
+; RV32I-PIC-NEXT:    mv s0, a0
+; RV32I-PIC-NEXT:    sw a0, 4(sp)
+; RV32I-PIC-NEXT:    sw a0, 0(sp)
+; RV32I-PIC-NEXT:    mv a1, a0
+; RV32I-PIC-NEXT:    mv a2, a0
+; RV32I-PIC-NEXT:    mv a3, a0
+; RV32I-PIC-NEXT:    mv a4, a0
+; RV32I-PIC-NEXT:    mv a5, a0
+; RV32I-PIC-NEXT:    mv a6, a0
+; RV32I-PIC-NEXT:    mv a7, a0
+; RV32I-PIC-NEXT:    call external_many_args@plt
+; RV32I-PIC-NEXT:    mv a0, s0
+; RV32I-PIC-NEXT:    lw s0, 8(sp)
+; RV32I-PIC-NEXT:    lw ra, 12(sp)
+; RV32I-PIC-NEXT:    addi sp, sp, 16
+; RV32I-PIC-NEXT:    ret
   %1 = call i32 @external_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
                                     i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
   ret i32 %a
 }
 
 define i32 @defined_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %j) nounwind {
 ; RV32I-LABEL: defined_many_args:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lw a0, 4(sp)
 ; RV32I-NEXT:    addi a0, a0, 1
 ; RV32I-NEXT:    ret
+;
+; RV32I-PIC-LABEL: defined_many_args:
+; RV32I-PIC:       # %bb.0:
+; RV32I-PIC-NEXT:    lw a0, 4(sp)
+; RV32I-PIC-NEXT:    addi a0, a0, 1
+; RV32I-PIC-NEXT:    ret
   %added = add i32 %j, 1
   ret i32 %added
 }
 
 define i32 @test_call_defined_many_args(i32 %a) nounwind {
 ; RV32I-LABEL: test_call_defined_many_args:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp)
 ; RV32I-NEXT:    sw a0, 4(sp)
 ; RV32I-NEXT:    sw a0, 0(sp)
 ; RV32I-NEXT:    mv a1, a0
 ; RV32I-NEXT:    mv a2, a0
 ; RV32I-NEXT:    mv a3, a0
 ; RV32I-NEXT:    mv a4, a0
 ; RV32I-NEXT:    mv a5, a0
 ; RV32I-NEXT:    mv a6, a0
 ; RV32I-NEXT:    mv a7, a0
 ; RV32I-NEXT:    call defined_many_args
 ; RV32I-NEXT:    lw ra, 12(sp)
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret
+;
+; RV32I-PIC-LABEL: test_call_defined_many_args:
+; RV32I-PIC:       # %bb.0:
+; RV32I-PIC-NEXT:    addi sp, sp, -16
+; RV32I-PIC-NEXT:    sw ra, 12(sp)
+; RV32I-PIC-NEXT:    sw a0, 4(sp)
+; RV32I-PIC-NEXT:    sw a0, 0(sp)
+; RV32I-PIC-NEXT:    mv a1, a0
+; RV32I-PIC-NEXT:    mv a2, a0
+; RV32I-PIC-NEXT:    mv a3, a0
+; RV32I-PIC-NEXT:    mv a4, a0
+; RV32I-PIC-NEXT:    mv a5, a0
+; RV32I-PIC-NEXT:    mv a6, a0
+; RV32I-PIC-NEXT:    mv a7, a0
+; RV32I-PIC-NEXT:    call defined_many_args@plt
+; RV32I-PIC-NEXT:    lw ra, 12(sp)
+; RV32I-PIC-NEXT:    addi sp, sp, 16
+; RV32I-PIC-NEXT:    ret
   %1 = call i32 @defined_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
                                    i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
   ret i32 %1
 }