[RISCV] Lower calls through PLT

[lewis-revill]

Summary

This patch adds support for generating calls through the procedure linkage table where required for a given ExternalSymbol or GlobalAddress callee.

[jrtc27]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1108 ↗

(On Diff #176742)

Do we want to be parsing the @plt for things other than call/tail? PseudoLLA also takes a bare_symbol but @plt isn't valid. Currently we parse bar@plt as a valid bare symbol; however, GNU as will reject it with illegal operands (as I understand it, this is because it doesn't treat @ as part of a valid identifier).

lib/Target/RISCV/RISCVSubtarget.cpp

51

This can be inlined in LowerCall, especially once the fno-plt stuff is gone, as it's the only user.

56

This seems to be X86-specific in LLVM; do we really need this in RISC-V? Clang's test/CodeGen/noplt.c gives a normal call foo@plt when compiled with riscv64-linux-gnu-gcc -fpic -fno-plt, so I would remove this and the related code.

[lewis-revill]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1108 ↗

(On Diff #176742)

Hmm, probably a good idea. I guess I'd have to add yet another operand type in RISCVInstrInfo. Checking Operands[0] for "call" or "tail" seems a bit hacky to me, but maybe it's a reasonable approach?

lib/Target/RISCV/RISCVSubtarget.cpp

56

OK, that makes things a lot simpler for LowerCall then. Is there no case where calls need to be lowered using GOT?

[lewis-revill]

Splitting this patch into MC layer and Codegen.

[lewis-revill]

Split into MC layer (patch D55335) and codegen (this patch).

[lewis-revill]

Removed capability of lowering through GOT since there is no apparent need to do so.

[lewis-revill]

Rebased to use D55560 and with fewer dependencies

[lewis-revill]

Rebased.

[lewis-revill]

Rebased and added testing using -relocation-model=pic in 'calls.ll'. Also added a dso_local callee to 'calls.ll' since this affects whether PLT is used for PIC.

[asb]

LGTM, thanks!

lib/Target/RISCV/RISCVISelLowering.cpp

for (auto &Reg : RegsToPass) {
     Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
     Glue = Chain.getValue(1);
   }
 
   // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
   // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
   // split it and then direct call can be matched by PseudoCALL.
   if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
-    Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT, 0, 0);
+    const GlobalValue *GV = S->getGlobal();
+    unsigned OpFlags = Subtarget
+        .classifyFunctionReference(*GV->getParent(), GV);
+
+    Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
+
+    if (OpFlags == RISCVII::MO_GOT_HI) {
+      Callee = DAG.getNode(RISCVISD::WRAPPER_PCREL, DL, PtrVT, Callee);
+      Callee = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Callee,
+                           MachinePointerInfo());
+    }
   } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
-    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, 0);
+    unsigned OpFlags = Subtarget
+        .classifyFunctionReference(*MF.getFunction().getParent(), nullptr);
+
+    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags);
+
+    if (OpFlags == RISCVII::MO_GOT_HI) {
+      Callee = DAG.getNode(RISCVISD::WRAPPER_PCREL, DL, PtrVT, Callee);
+      Callee = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Callee,
+                           MachinePointerInfo());
+    }
   }
 
   // The first call operand is the chain and the second is the target address.
   SmallVector<SDValue, 8> Ops;
   Ops.push_back(Chain);
   Ops.push_back(Callee);
 
   // Add argument registers to the end of the list so that they are

lib/Target/RISCV/RISCVMCInstLower.cpp

case RISCVII::MO_PCREL_LO:
     Kind = RISCVMCExpr::VK_RISCV_PCREL_LO;
     break;
   case RISCVII::MO_PCREL_HI:
     Kind = RISCVMCExpr::VK_RISCV_PCREL_HI;
     break;
   case RISCVII::MO_GOT_HI:
     Kind = RISCVMCExpr::VK_RISCV_GOT_HI;
     break;
+  case RISCVII::MO_PLT:
+    Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
+    break;
   }
 
   const MCExpr *ME =
       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
 
   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
     ME = MCBinaryExpr::createAdd(
         ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);

lib/Target/RISCV/RISCVSubtarget.h

class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool EnableLinkerRelax = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
+  const TargetMachine &TM;
 
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
                                                   bool Is64Bit);
 
 public:
   // Initializes the data members to match that of the specified triple.
public:
   bool hasStdExtA() const { return HasStdExtA; }
   bool hasStdExtF() const { return HasStdExtF; }
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
   bool is64Bit() const { return HasRV64; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
+
+  unsigned classifyFunctionReference(const Module &M,
+                                     const GlobalValue *GV) const;
 };
 } // End llvm namespace
 
 #endif

lib/Target/RISCV/RISCVSubtarget.cpp

RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(StringRef CPU,
   }
   return *this;
 }
 
 RISCVSubtarget::RISCVSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS, const TargetMachine &TM)
     : RISCVGenSubtargetInfo(TT, CPU, FS),
       FrameLowering(initializeSubtargetDependencies(CPU, FS, TT.isArch64Bit())),
-      InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {}
+      InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this), TM(TM) {}
+
+unsigned
+RISCVSubtarget::classifyFunctionReference(const Module &M,
+                                          const GlobalValue *GV) const {
+  if (TM.shouldAssumeDSOLocal(M, GV))
+    return 0u;
+
+  if (M.getRtLibUseGOT())
+    return RISCVII::MO_GOT_HI;
+
+  return RISCVII::MO_PLT;
+}
 No newline at end of file

lib/Target/RISCV/Utils/RISCVBaseInfo.h

 
 enum {
   MO_None,
   MO_LO,
   MO_HI,
   MO_PCREL_LO,
   MO_PCREL_HI,
   MO_GOT_HI,
+  MO_PLT,
 };
 } // namespace RISCVII
 
 // Describes the predecessor/successor bits used in the FENCE instruction.
 namespace RISCVFenceField {
 enum FenceField {
   I = 8,
   O = 4,