[RISCV] Lower calls through PLT

[lewis-revill]

Summary

This patch adds support for generating calls through the procedure linkage table where required for a given ExternalSymbol or GlobalAddress callee.

[jrtc27]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1108

Do we want to be parsing the @plt for things other than call/tail? PseudoLLA also takes a bare_symbol but @plt isn't valid. Currently we parse bar@plt as a valid bare symbol; however, GNU as will reject it with illegal operands (as I understand it, this is because it doesn't treat @ as part of a valid identifier).

lib/Target/RISCV/RISCVSubtarget.cpp

51

This can be inlined in LowerCall, especially once the fno-plt stuff is gone, as it's the only user.

56

This seems to be X86-specific in LLVM; do we really need this in RISC-V? Clang's test/CodeGen/noplt.c gives a normal call foo@plt when compiled with riscv64-linux-gnu-gcc -fpic -fno-plt, so I would remove this and the related code.

[lewis-revill]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1108

Hmm, probably a good idea. I guess I'd have to add yet another operand type in RISCVInstrInfo. Checking Operands[0] for "call" or "tail" seems a bit hacky to me, but maybe it's a reasonable approach?

lib/Target/RISCV/RISCVSubtarget.cpp

56

OK, that makes things a lot simpler for LowerCall then. Is there no case where calls need to be lowered using GOT?

[lewis-revill]

Splitting this patch into MC layer and Codegen.

[lewis-revill]

Split into MC layer (patch D55335) and codegen (this patch).

[lewis-revill]

Removed capability of lowering through GOT since there is no apparent need to do so.

[lewis-revill]

Rebased to use D55560 and with fewer dependencies

[lewis-revill]

Rebased.

[lewis-revill]

Rebased and added testing using -relocation-model=pic in 'calls.ll'. Also added a dso_local callee to 'calls.ll' since this affects whether PLT is used for PIC.

[asb]

LGTM, thanks!

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

public:
 
   bool isBareSymbol() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK;
     // Must be of 'immediate' type but not a constant.
     if (!isImm() || evaluateConstantImm(getImm(), Imm, VK))
       return false;
     return RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm) &&
-           VK == RISCVMCExpr::VK_RISCV_None;
+           (VK == RISCVMCExpr::VK_RISCV_None ||
+            VK == RISCVMCExpr::VK_RISCV_CALL_PLT);
   }
 
   bool isCSRSystemRegister() const { return isSystemRegister(); }
 
   /// Return true if the operand is a valid for the fence instruction e.g.
   /// ('iorw').
   bool isFenceArg() const {
     if (!isImm())
OperandMatchResultTy RISCVAsmParser::parseBareSymbol(OperandVector &Operands) {
 
   if (getLexer().getKind() != AsmToken::Identifier)
     return MatchOperand_NoMatch;
 
   StringRef Identifier;
   if (getParser().parseIdentifier(Identifier))
     return MatchOperand_ParseFail;
 
+  if (Identifier.consume_back("@plt")) {
     MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
     Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
+    Res = RISCVMCExpr::create(Res, RISCVMCExpr::VK_RISCV_CALL_PLT, getContext());
+  } else {
+    MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
+    Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext());
+  }
   Operands.push_back(RISCVOperand::createImm(Res, S, E, isRV64()));
   return MatchOperand_Success;
 }
 
 OperandMatchResultTy RISCVAsmParser::parseJALOffset(OperandVector &Operands) {
   // Parsing jal operands is fiddly due to the `jal foo` and `jal ra, foo`
   // both being acceptable forms. When parsing `jal ra, foo` this function
   // will be called for the `ra` register operand in an attempt to match the

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h

const static MCFixupKindInfo Infos[] = {
       { "fixup_riscv_pcrel_lo12_i", 20,     12,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_pcrel_lo12_s",  0,     32,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_got_hi20",     12,     20,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_jal",          12,     20,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_branch",        0,     32,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_rvc_jump",      2,     11,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_rvc_branch",    0,     16,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_call",          0,     64,  MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_riscv_call_plt",      0,     64,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_relax",         0,      0,  0 }
     };
     static_assert((array_lengthof(Infos)) == RISCV::NumTargetFixupKinds,
                   "Not all fixup kinds added to Infos array");
 
     if (Kind < FirstTargetFixupKind)
       return MCAsmBackend::getFixupKindInfo(Kind);
 

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

case RISCV::fixup_riscv_branch: {
     unsigned Lo4 = (Value >> 1) & 0xf;
     // Inst{31} = Sbit;
     // Inst{30-25} = Mid6;
     // Inst{11-8} = Lo4;
     // Inst{7} = Hi1;
     Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
     return Value;
   }
-  case RISCV::fixup_riscv_call: {
+  case RISCV::fixup_riscv_call:
+  case RISCV::fixup_riscv_call_plt: {
     // Jalr will add UpperImm with the sign-extended 12-bit LowerImm,
     // we need to add 0x800ULL before extract upper bits to reflect the
     // effect of the sign extension.
     uint64_t UpperImm = (Value + 0x800ULL) & 0xfffff000ULL;
     uint64_t LowerImm = Value & 0xfffULL;
     return UpperImm | ((LowerImm << 20) << 32);
   }
   case RISCV::fixup_riscv_rvc_jump: {

lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

unsigned RISCVELFObjectWriter::getRelocType(MCContext &Ctx,
   case RISCV::fixup_riscv_branch:
     return ELF::R_RISCV_BRANCH;
   case RISCV::fixup_riscv_rvc_jump:
     return ELF::R_RISCV_RVC_JUMP;
   case RISCV::fixup_riscv_rvc_branch:
     return ELF::R_RISCV_RVC_BRANCH;
   case RISCV::fixup_riscv_call:
     return ELF::R_RISCV_CALL;
+  case RISCV::fixup_riscv_call_plt:
+    return ELF::R_RISCV_CALL_PLT;
   case RISCV::fixup_riscv_relax:
     return ELF::R_RISCV_RELAX;
   }
 }
 
 std::unique_ptr<MCObjectTargetWriter>
 llvm::createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit) {
   return llvm::make_unique<RISCVELFObjectWriter>(OSABI, Is64Bit);
 }

lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h

enum Fixups {
   // compressed jump instruction
   fixup_riscv_rvc_jump,
   // fixup_riscv_rvc_branch - 8-bit fixup for symbol references in the
   // compressed branch instruction
   fixup_riscv_rvc_branch,
   // fixup_riscv_call - A fixup representing a call attached to the auipc
   // instruction in a pair composed of adjacent auipc+jalr instructions.
   fixup_riscv_call,
+  // fixup_riscv_call_plt - A fixup representing a procedure linkage table call
+  // attached to the auipc instruction in a pair composed of adjacent auipc+jalr
+  // instructions.
+  fixup_riscv_call_plt,
   // fixup_riscv_relax - Used to generate an R_RISCV_RELAX relocation type,
   // which indicates the linker may relax the instruction pair.
   fixup_riscv_relax,
 
   // fixup_riscv_invalid - used as a sentinel and a marker, must be last fixup
   fixup_riscv_invalid,
   NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind
 };
 } // end namespace RISCV
 } // end namespace llvm
 
 #endif

lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
   MCOperand Func = MI.getOperand(0);
   unsigned Ra = (MI.getOpcode() == RISCV::PseudoTAIL) ? RISCV::X6 : RISCV::X1;
   uint32_t Binary;
 
   assert(Func.isExpr() && "Expected expression");
 
   const MCExpr *Expr = Func.getExpr();
 
+  RISCVMCExpr::VariantKind Kind = RISCVMCExpr::VK_RISCV_CALL;
+  if (const RISCVMCExpr *RVExpr = dyn_cast<RISCVMCExpr>(Expr)) {
+    Expr = RVExpr->getSubExpr();
+    Kind = RVExpr->getKind();
+  }
+
   // Create function call expression CallExpr for AUIPC.
   const MCExpr *CallExpr =
-      RISCVMCExpr::create(Expr, RISCVMCExpr::VK_RISCV_CALL, Ctx);
+      RISCVMCExpr::create(Expr, Kind, Ctx);
 
   // Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
   TmpInst = MCInstBuilder(RISCV::AUIPC)
                 .addReg(Ra)
                 .addOperand(MCOperand::createExpr(CallExpr));
   Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
   support::endian::write(OS, Binary, support::little);
 
case RISCVMCExpr::VK_RISCV_PCREL_HI:
       FixupKind = RISCV::fixup_riscv_pcrel_hi20;
       break;
     case RISCVMCExpr::VK_RISCV_GOT_HI:
       FixupKind = RISCV::fixup_riscv_got_hi20;
       break;
     case RISCVMCExpr::VK_RISCV_CALL:
       FixupKind = RISCV::fixup_riscv_call;
       break;
+    case RISCVMCExpr::VK_RISCV_CALL_PLT:
+      FixupKind = RISCV::fixup_riscv_call_plt;
+      break;
     }
   } else if (Kind == MCExpr::SymbolRef &&
              cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
     if (Desc.getOpcode() == RISCV::JAL) {
       FixupKind = RISCV::fixup_riscv_jal;
     } else if (MIFrm == RISCVII::InstFormatB) {
       FixupKind = RISCV::fixup_riscv_branch;
     } else if (MIFrm == RISCVII::InstFormatCJ) {
       FixupKind = RISCV::fixup_riscv_rvc_jump;
     } else if (MIFrm == RISCVII::InstFormatCB) {
       FixupKind = RISCV::fixup_riscv_rvc_branch;
     }
   }
 
   assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
 
   Fixups.push_back(
       MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
   ++MCNumFixups;
 
   if (EnableRelax) {
-    if (FixupKind == RISCV::fixup_riscv_call) {
+    if (FixupKind == RISCV::fixup_riscv_call ||
+        FixupKind == RISCV::fixup_riscv_call_plt) {
       Fixups.push_back(
       MCFixup::create(0, Expr, MCFixupKind(RISCV::fixup_riscv_relax),
                       MI.getLoc()));
       ++MCNumFixups;
     }
   }
 
   return 0;
 }
 
 #include "RISCVGenMCCodeEmitter.inc"

lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h

public:
   enum VariantKind {
     VK_RISCV_None,
     VK_RISCV_LO,
     VK_RISCV_HI,
     VK_RISCV_PCREL_LO,
     VK_RISCV_PCREL_HI,
     VK_RISCV_GOT_HI,
     VK_RISCV_CALL,
+    VK_RISCV_CALL_PLT,
     VK_RISCV_Invalid
   };
 
 private:
   const MCExpr *Expr;
   const VariantKind Kind;
 
   int64_t evaluateAsInt64(int64_t Value) const;

lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp

 #define DEBUG_TYPE "riscvmcexpr"
 
 const RISCVMCExpr *RISCVMCExpr::create(const MCExpr *Expr, VariantKind Kind,
                                        MCContext &Ctx) {
   return new (Ctx) RISCVMCExpr(Expr, Kind);
 }
 
 void RISCVMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
-  bool HasVariant =
-      ((getKind() != VK_RISCV_None) && (getKind() != VK_RISCV_CALL));
+  VariantKind Kind = getKind();
+  bool HasVariant = ((Kind != VK_RISCV_None) && (Kind != VK_RISCV_CALL) &&
+                     (Kind != VK_RISCV_CALL_PLT));
+
   if (HasVariant)
     OS << '%' << getVariantKindName(getKind()) << '(';
   Expr->print(OS, MAI);
   if (HasVariant)
     OS << ')';
+  if (Kind == VK_RISCV_CALL_PLT)
+    OS << "@plt";
 }
 
 bool RISCVMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
                                             const MCAsmLayout *Layout,
                                             const MCFixup *Fixup) const {
   if (!getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup))
     return false;
 
case VK_RISCV_GOT_HI:
     return "got_hi";
   }
 }
 
 bool RISCVMCExpr::evaluateAsConstant(int64_t &Res) const {
   MCValue Value;
 
   if (Kind == VK_RISCV_PCREL_HI || Kind == VK_RISCV_PCREL_LO ||
-      Kind == VK_RISCV_GOT_HI || Kind == VK_RISCV_CALL)
+      Kind == VK_RISCV_GOT_HI || Kind == VK_RISCV_CALL ||
+      Kind == VK_RISCV_CALL_PLT)
     return false;
 
   if (!getSubExpr()->evaluateAsRelocatable(Value, nullptr, nullptr))
     return false;
 
   if (!Value.isAbsolute())
     return false;
 

lib/Target/RISCV/RISCVISelLowering.cpp

for (auto &Reg : RegsToPass) {
     Chain = DAG.getCopyToReg(Chain, DL, Reg.first, Reg.second, Glue);
     Glue = Chain.getValue(1);
   }
 
   // If the callee is a GlobalAddress/ExternalSymbol node, turn it into a
   // TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
   // split it and then direct call can be matched by PseudoCALL.
   if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
-    Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT, 0, 0);
+    const GlobalValue *GV = S->getGlobal();
+    unsigned OpFlags = Subtarget
+        .classifyFunctionReference(*GV->getParent(), GV);
+
+    Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
+
+    if (OpFlags == RISCVII::MO_GOT_HI) {
+      Callee = DAG.getNode(RISCVISD::WRAPPER_PCREL, DL, PtrVT, Callee);
+      Callee = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Callee,
+                           MachinePointerInfo());
+    }
   } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
-    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, 0);
+    unsigned OpFlags = Subtarget
+        .classifyFunctionReference(*MF.getFunction().getParent(), nullptr);
+
+    Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags);
+
+    if (OpFlags == RISCVII::MO_GOT_HI) {
+      Callee = DAG.getNode(RISCVISD::WRAPPER_PCREL, DL, PtrVT, Callee);
+      Callee = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Callee,
+                           MachinePointerInfo());
+    }
   }
 
   // The first call operand is the chain and the second is the target address.
   SmallVector<SDValue, 8> Ops;
   Ops.push_back(Chain);
   Ops.push_back(Callee);
 
   // Add argument registers to the end of the list so that they are

lib/Target/RISCV/RISCVMCInstLower.cpp

case RISCVII::MO_PCREL_LO:
     Kind = RISCVMCExpr::VK_RISCV_PCREL_LO;
     break;
   case RISCVII::MO_PCREL_HI:
     Kind = RISCVMCExpr::VK_RISCV_PCREL_HI;
     break;
   case RISCVII::MO_GOT_HI:
     Kind = RISCVMCExpr::VK_RISCV_GOT_HI;
     break;
+  case RISCVII::MO_PLT:
+    Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
+    break;
   }
 
   const MCExpr *ME =
       MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
 
   if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
     ME = MCBinaryExpr::createAdd(
         ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);

lib/Target/RISCV/RISCVSubtarget.h

class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool EnableLinkerRelax = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
+  const TargetMachine &TM;
 
   /// Initializes using the passed in CPU and feature strings so that we can
   /// use initializer lists for subtarget initialization.
   RISCVSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
                                                   bool Is64Bit);
 
 public:
   // Initializes the data members to match that of the specified triple.
public:
   bool hasStdExtA() const { return HasStdExtA; }
   bool hasStdExtF() const { return HasStdExtF; }
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
   bool is64Bit() const { return HasRV64; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
+
+  unsigned classifyFunctionReference(const Module &M,
+                                     const GlobalValue *GV) const;
 };
 } // End llvm namespace
 
 #endif

lib/Target/RISCV/RISCVSubtarget.cpp

RISCVSubtarget &RISCVSubtarget::initializeSubtargetDependencies(StringRef CPU,
   }
   return *this;
 }
 
 RISCVSubtarget::RISCVSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS, const TargetMachine &TM)
     : RISCVGenSubtargetInfo(TT, CPU, FS),
       FrameLowering(initializeSubtargetDependencies(CPU, FS, TT.isArch64Bit())),
-      InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {}
+      InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this), TM(TM) {}
+
+unsigned
+RISCVSubtarget::classifyFunctionReference(const Module &M,
+                                          const GlobalValue *GV) const {
+  if (TM.shouldAssumeDSOLocal(M, GV))
+    return 0u;
+
+  if (M.getRtLibUseGOT())
+    return RISCVII::MO_GOT_HI;
+
+  return RISCVII::MO_PLT;
+}
 No newline at end of file

lib/Target/RISCV/Utils/RISCVBaseInfo.h

 
 enum {
   MO_None,
   MO_LO,
   MO_HI,
   MO_PCREL_LO,
   MO_PCREL_HI,
   MO_GOT_HI,
+  MO_PLT,
 };
 } // namespace RISCVII
 
 // Describes the predecessor/successor bits used in the FENCE instruction.
 namespace RISCVFenceField {
 enum FenceField {
   I = 8,
   O = 4,

test/MC/RISCV/function-call.s

 # INSTR: jalr  ra
 # FIXUP: fixup A - offset: 0, value: ra, kind: fixup_riscv_call
 
 call mstatus
 # RELOC: R_RISCV_CALL mstatus 0x0
 # INSTR: auipc ra, 0
 # INSTR: jalr  ra
 # FIXUP: fixup A - offset: 0, value: mstatus, kind: fixup_riscv_call
+
+# Ensure that calls to procedure linkage table symbols work.
+
+call foo@plt
+# RELOC: R_RISCV_CALL_PLT foo 0x0
+# INSTR: auipc ra, 0
+# INSTR: jalr  ra
+# FIXUP: fixup A - offset: 0, value: foo@plt, kind: fixup_riscv_call_plt