Page MenuHomePhabricator

[RISCV] Add inline asm constraint A for RISC-V
ClosedPublic

Authored by lewis-revill on Nov 9 2018, 1:21 AM.

Details

Summary

This allows the constraint A to be used in inline asm for RISC-V, which allows an address held in a register to be used.

This patch adds the minimal amount of code required to get operands with the right constraints to compile.

Diff Detail

Repository
rL LLVM

Event Timeline

lewis-revill created this revision.Nov 9 2018, 1:21 AM
jrtc27 requested changes to this revision.Feb 6 2019, 7:00 AM
jrtc27 added inline comments.
test/CodeGen/riscv-inline-asm.c
32 ↗(On Diff #173278)

Should be sideeffect

This revision now requires changes to proceed.Feb 6 2019, 7:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 6 2019, 7:00 AM

Correct test.

Herald added a project: Restricted Project. · View Herald TranscriptFeb 19 2019, 2:55 AM
lewis-revill retitled this revision from [WIP, RISCV] Add inline asm constraint A for RISC-V to [RISCV] Add inline asm constraint A for RISC-V.
asb accepted this revision.Jun 18 2019, 8:21 AM

LGTM, thanks!

lewis-revill edited the summary of this revision. (Show Details)

Rebased prior to commit.

This revision was not accepted when it landed; it landed in state Needs Review.Aug 16 2019, 3:23 AM
This revision was automatically updated to reflect the committed changes.