[RISCV] Add inline asm constraint A for RISC-V

[lewis-revill]

Summary

This allows the constraint A to be used in inline asm for RISC-V, which allows an address held in a register to be used.

This patch adds the minimal amount of code required to get operands with the right constraints to compile.

[jrtc27]

test/CodeGen/riscv-inline-asm.c

32 ↗

(On Diff #173278)

Should be sideeffect

[lewis-revill]

Correct test.

[asb]

LGTM, thanks!

[lewis-revill]

Rebased prior to commit.

cfe/trunk/lib/Basic/Targets/RISCV.cpp

bool RISCVTargetInfo::validateAsmConstraint(
   case 'K':
     // A 5-bit unsigned immediate for CSR access instructions.
     Info.setRequiresImmediate(0, 31);
     return true;
   case 'f':
     // A floating-point register.
     Info.setAllowsRegister();
     return true;
+  case 'A':
+    // An address that is held in a general-purpose register.
+    Info.setAllowsMemory();
+    return true;
   }
 }
 
 void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
                                        MacroBuilder &Builder) const {
   Builder.defineMacro("__ELF__");
   Builder.defineMacro("__riscv");
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;

cfe/trunk/test/CodeGen/riscv-inline-asm.c

 // CHECK-LABEL: define void @test_f()
 // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, float* @f
 // CHECK: call void asm sideeffect "", "f"(float [[FLT_ARG]])
   asm volatile ("" :: "f"(f));
 // CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load double, double* @d
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}