[RISCV] Add inline asm constraints I, J & K for RISC-V

[lewis-revill]

Summary

This allows the constraints I, J & K to be used in inline asm for RISC-V, with the following semantics (equivalent to GCC):

I: Any 12-bit signed immediate.
J: Integer zero only.
K: Any 5-bit unsigned immediate.

See the GCC definitions here: https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html

Note that GCC also implements 'f' for floating point register and 'A' for address-only operand. These are not implemented here because:

1. It appears trivial to implement the floating point register constraint, however since floating point registers are not yet recognised by the calling convention the call to the inline asm node cannot be lowered.

2. I'm not yet certain how to implement an 'address-only' operand and I'd rather get the above constraints done first and add it later.

[asb]

Thanks for the patch Lewis. Could I please request the following changes:

• It would be handy to link to https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html in the patch summary, so people can easily double-check the constraint definitions for themselves
• Could you add tests for values outside of the expected range. AArch64 and X86 do this in test/Sema/inline-asm-validate-{aarch64,x86}.c
• It would be worth expanding riscv-inline-asm.c to provide simple sanity checks for "m" and "r"

[lewis-revill]

Updated to reflect desired changes (and fix an incorrect boundary). I didn't add r & m to riscv-inline-asm.c as I wasn't clear what exactly was desired.

[asb]

This looks good to me, but is blocked on the dependent patch being updated. I added a minor comment on riscv-inline-asm.c

test/CodeGen/riscv-inline-asm.c

1 ↗

(On Diff #174360)

No need to enable +f for the test, as written.

[lewis-revill]

• Rebased and fixed test run line

cfe/trunk/lib/Basic/Targets/RISCV.h

public:
 
   const char *getClobbers() const override { return ""; }
 
   ArrayRef<const char *> getGCCRegNames() const override;
 
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *&Name,
-                             TargetInfo::ConstraintInfo &Info) const override {
-    return false;
-  }
+                             TargetInfo::ConstraintInfo &Info) const override;
 
   bool hasFeature(StringRef Feature) const override;
 
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override;
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {
 public:

cfe/trunk/lib/Basic/Targets/RISCV.cpp

static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
       {{"a2"}, "x12"},  {{"a3"}, "x13"}, {{"a4"}, "x14"},  {{"a5"}, "x15"},
       {{"a6"}, "x16"},  {{"a7"}, "x17"}, {{"s2"}, "x18"},  {{"s3"}, "x19"},
       {{"s4"}, "x20"},  {{"s5"}, "x21"}, {{"s6"}, "x22"},  {{"s7"}, "x23"},
       {{"s8"}, "x24"},  {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
       {{"t3"}, "x28"},  {{"t4"}, "x29"}, {{"t5"}, "x30"},  {{"t6"}, "x31"}};
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool RISCVTargetInfo::validateAsmConstraint(
+    const char *&Name, TargetInfo::ConstraintInfo &Info) const {
+  switch (*Name) {
+  default:
+    return false;
+  case 'I':
+    // A 12-bit signed immediate.
+    Info.setRequiresImmediate(-2048, 2047);
+    return true;
+  case 'J':
+    // Integer zero.
+    Info.setRequiresImmediate(0);
+    return true;
+  case 'K':
+    // A 5-bit unsigned immediate for CSR access instructions.
+    Info.setRequiresImmediate(0, 31);
+    return true;
+  }
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
                                        MacroBuilder &Builder) const {
   Builder.defineMacro("__ELF__");
   Builder.defineMacro("__riscv");
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
   Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
   // TODO: modify when more code models and ABIs are supported.
   Builder.defineMacro("__riscv_cmodel_medlow");