[RISCV] Add implied zero offset load/store alias patterns

[jrtc27]

Summary

Allow load/store instructions with implied zero offset for compatibility with GNU assembler.

[lewis-revill]

lib/Target/RISCV/RISCVInstrInfo.td

538 ↗

(On Diff #183256)

LW should not be guarded by IsRV64.

541 ↗

(On Diff #183256)

LD is missing here.

[lewis-revill]

Some basic tests should probably be included for completeness.

[jrtc27]

Ah, I already did this in my fork, covering all the compressed and floating-point instructions too, with a complete set of tests. Probably easiest if I just post that rather than you working to produce what would turn out to be nearly-identical code?

[apazos]

Yes James, please post your patch and tests. Kito quickly posted this one to unblock me.

[kito-cheng]

@jrtc27 feel free to upload your one, it's just a 5 minute quick patch :P

[jrtc27]

Support all memory instructions; add test coverage

[asb]

Thanks, this looks good to me. Needs a small fixup to apply cleanly to the previous patches in the queue (TODO comments in RISCVInstrInfo{F,D}.td were removed).

[jrtc27]

D50496 in the stack has now landed, so other than the TODO comments having been dropped this is now ready. Alex, are you happy to do that rebasing when you commit this, or would you like me to?

[asb]

In D57141#1404697, @jrtc27 wrote:

D50496 in the stack has now landed, so other than the TODO comments having been dropped this is now ready. Alex, are you happy to do that rebasing when you commit this, or would you like me to?

Committing now - thanks James!

llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td

 def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
 }
 
 def : InstAlias<"sfence.vma",     (SFENCE_VMA      X0, X0)>;
 def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
 
 let EmitPriority = 0 in {
+def : InstAlias<"lb $rd, (${rs1})",
+                (LB  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lh $rd, (${rs1})",
+                (LH  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lw $rd, (${rs1})",
+                (LW  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lbu $rd, (${rs1})",
+                (LBU  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"lhu $rd, (${rs1})",
+                (LHU  GPR:$rd, GPR:$rs1, 0)>;
+
+def : InstAlias<"sb $rs2, (${rs1})",
+                (SB  GPR:$rs2, GPR:$rs1, 0)>;
+def : InstAlias<"sh $rs2, (${rs1})",
+                (SH  GPR:$rs2, GPR:$rs1, 0)>;
+def : InstAlias<"sw $rs2, (${rs1})",
+                (SW  GPR:$rs2, GPR:$rs1, 0)>;
+
 def : InstAlias<"add $rd, $rs1, $imm12",
                 (ADDI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
 def : InstAlias<"and $rd, $rs1, $imm12",
                 (ANDI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
 def : InstAlias<"xor $rd, $rs1, $imm12",
                 (XORI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
 def : InstAlias<"or $rd, $rs1, $imm12",
                 (ORI  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
 def : InstAlias<"sll $rd, $rs1, $shamt",
                 (SLLI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
 def : InstAlias<"srl $rd, $rs1, $shamt",
                 (SRLI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
 def : InstAlias<"sra $rd, $rs1, $shamt",
                 (SRAI  GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
 let Predicates = [IsRV64] in {
+def : InstAlias<"lwu $rd, (${rs1})",
+                (LWU  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"ld $rd, (${rs1})",
+                (LD  GPR:$rd, GPR:$rs1, 0)>;
+def : InstAlias<"sd $rs2, (${rs1})",
+                (SD  GPR:$rs2, GPR:$rs1, 0)>;
+
 def : InstAlias<"addw $rd, $rs1, $imm12",
                 (ADDIW  GPR:$rd, GPR:$rs1, simm12:$imm12)>;
 def : InstAlias<"sllw $rd, $rs1, $shamt",
                 (SLLIW  GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
 def : InstAlias<"srlw $rd, $rs1, $shamt",
                 (SRLIW  GPR:$rd, GPR:$rs1, uimm5:$shamt)>;
 def : InstAlias<"sraw $rd, $rs1, $shamt",
                 (SRAIW  GPR:$rd, GPR:$rs1, uimm5:$shamt)>;

llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td

 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
 def C_UNIMP : RVInst16<(outs), (ins), "c.unimp", "", [], InstFormatOther> {
   let Inst{15-0} = 0;
 }
 
 } // Predicates = [HasStdExtC]
 
 //===----------------------------------------------------------------------===//
+// Assembler Pseudo Instructions
+//===----------------------------------------------------------------------===//
+
+let EmitPriority = 0 in {
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fld $rd, (${rs1})", (C_FLD FPR64C:$rd, GPRC:$rs1, 0)>;
+
+def : InstAlias<"c.lw $rd, (${rs1})", (C_LW GPRC:$rd, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.flw $rd, (${rs1})", (C_FLW FPR32C:$rd, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.ld $rd, (${rs1})", (C_LD GPRC:$rd, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fsd $rs2, (${rs1})", (C_FSD FPR64C:$rs2, GPRC:$rs1, 0)>;
+
+def : InstAlias<"c.sw $rs2, (${rs1})", (C_SW GPRC:$rs2, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.fsw $rs2, (${rs1})", (C_FSW FPR32C:$rs2, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.sd $rs2, (${rs1})", (C_SD GPRC:$rs2, GPRC:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fldsp $rd, (${rs1})", (C_FLDSP FPR64C:$rd, SP:$rs1, 0)>;
+
+def : InstAlias<"c.lwsp $rd, (${rs1})", (C_LWSP GPRC:$rd, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.flwsp $rd, (${rs1})", (C_FLWSP FPR32C:$rd, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.ldsp $rd, (${rs1})", (C_LDSP GPRC:$rd, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtD] in
+def : InstAlias<"c.fsdsp $rs2, (${rs1})", (C_FSDSP FPR64C:$rs2, SP:$rs1, 0)>;
+
+def : InstAlias<"c.swsp $rs2, (${rs1})", (C_SWSP GPRC:$rs2, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, HasStdExtF, IsRV32] in
+def : InstAlias<"c.fswsp $rs2, (${rs1})", (C_FSWSP FPR32C:$rs2, SP:$rs1, 0)>;
+
+let Predicates = [HasStdExtC, IsRV64] in
+def : InstAlias<"c.sdsp $rs2, (${rs1})", (C_SDSP GPRC:$rs2, SP:$rs1, 0)>;
+}
+
+//===----------------------------------------------------------------------===//
 // Compress Instruction tablegen backend.
 //===----------------------------------------------------------------------===//
 
 class CompressPat<dag input, dag output> {
   dag Input  = input;
   dag Output    = output;
   list<Predicate> Predicates = [];
 }

llvm/trunk/lib/Target/RISCV/RISCVInstrInfoD.td

 }
 } // Predicates = [HasStdExtD, IsRV64]
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtD] in {
+def : InstAlias<"fld $rd, (${rs1})",  (FLD FPR64:$rd,  GPR:$rs1, 0), 0>;
+def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
+
 def : InstAlias<"fmv.d $rd, $rs",  (FSGNJ_D  FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 
 // fgt.d/fge.d are recognised by the GNU assembler but the canonical
 // flt.d/fle.d forms will always be printed. Therefore, set a zero weight.
 def : InstAlias<"fgt.d $rd, $rs, $rt",
                 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;

llvm/trunk/lib/Target/RISCV/RISCVInstrInfoF.td

 def           : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>;
 } // Predicates = [HasStdExtF, IsRV64]
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtF] in {
+def : InstAlias<"flw $rd, (${rs1})",  (FLW FPR32:$rd,  GPR:$rs1, 0), 0>;
+def : InstAlias<"fsw $rs2, (${rs1})", (FSW FPR32:$rs2, GPR:$rs1, 0), 0>;
+
 def : InstAlias<"fmv.s $rd, $rs",  (FSGNJ_S  FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
 def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
 def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
 
 // fgt.s/fge.s are recognised by the GNU assembler but the canonical
 // flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
 def : InstAlias<"fgt.s $rd, $rs, $rt",
                 (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;

llvm/trunk/test/MC/RISCV/rv32fc-aliases-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+f -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+f < %s \
+# RUN:     | llvm-objdump -mattr=+c,+f -riscv-no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+
+# CHECK-EXPAND: c.flw fs0, 0(s1)
+c.flw f8, (x9)
+# CHECK-EXPAND: c.fsw fs0, 0(s1)
+c.fsw f8, (x9)
+# CHECK-EXPAND: c.flwsp fs0, 0(sp)
+c.flwsp f8, (x2)
+# CHECK-EXPAND: c.fswsp fs0, 0(sp)
+c.fswsp f8, (x2)

llvm/trunk/test/MC/RISCV/rv32i-aliases-valid.s

 # CHECK-ALIAS: rdinstreth t4
 rdinstreth x29
 # CHECK-INST: csrrs s11, cycleh, zero
 # CHECK-ALIAS: rdcycleh s11
 rdcycleh x27
 # CHECK-INST: csrrs t3, timeh, zero
 # CHECK-ALIAS: rdtimeh t3
 rdtimeh x28
+
+# CHECK-EXPAND: lb a0, 0(a1)
+lb x10, (x11)
+# CHECK-EXPAND: lh a0, 0(a1)
+lh x10, (x11)
+# CHECK-EXPAND: lw a0, 0(a1)
+lw x10, (x11)
+# CHECK-EXPAND: lbu a0, 0(a1)
+lbu x10, (x11)
+# CHECK-EXPAND: lhu a0, 0(a1)
+lhu x10, (x11)
+
+# CHECK-EXPAND: sb a0, 0(a1)
+sb x10, (x11)
+# CHECK-EXPAND: sh a0, 0(a1)
+sh x10, (x11)
+# CHECK-EXPAND: sw a0, 0(a1)
+sw x10, (x11)

llvm/trunk/test/MC/RISCV/rv64c-aliases-valid.s

 # CHECK-EXPAND: addi t4, t4, -947
 # CHECK-EXPAND: c.slli t4, 12
 # CHECK-EXPAND: addi t4, t4, 1511
 # CHECK-EXPAND: c.slli t4, 13
 # CHECK-EXPAND: addi t4, t4, -272
 li t4, 0x123456789abcdef0
 # CHECK-EXPAND: c.li t5, -1
 li t5, 0xFFFFFFFFFFFFFFFF
+
+# CHECK-EXPAND: c.ld s0, 0(s1)
+c.ld x8, (x9)
+# CHECK-EXPAND: c.sd s0, 0(s1)
+c.sd x8, (x9)
+# CHECK-EXPAND: c.ldsp s0, 0(sp)
+c.ldsp x8, (x2)
+# CHECK-EXPAND: c.sdsp s0, 0(sp)
+c.sdsp x8, (x2)

llvm/trunk/test/MC/RISCV/rv64i-aliases-valid.s

 
 # CHECK-INST: srliw a2, a3, 4
 # CHECK-ALIAS: srliw a2, a3, 4
 srlw a2,a3,4
 
 # CHECK-INST: sraiw a2, a3, 4
 # CHECK-ALIAS: sraiw a2, a3, 4
 sraw a2,a3,4
+
+# CHECK-EXPAND: lwu a0, 0(a1)
+lwu x10, (x11)
+# CHECK-EXPAND: ld a0, 0(a1)
+ld x10, (x11)
+# CHECK-EXPAND: sd a0, 0(a1)
+sd x10, (x11)

llvm/trunk/test/MC/RISCV/rvc-aliases-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+c -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+c -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
+# RUN:     | llvm-objdump -riscv-no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \
+# RUN:     | llvm-objdump -riscv-no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+
+# CHECK-EXPAND: c.lw s0, 0(s1)
+c.lw x8, (x9)
+# CHECK-EXPAND: c.sw s0, 0(s1)
+c.sw x8, (x9)
+# CHECK-EXPAND: c.lwsp s0, 0(sp)
+c.lwsp x8, (x2)
+# CHECK-EXPAND: c.swsp s0, 0(sp)
+c.swsp x8, (x2)

llvm/trunk/test/MC/RISCV/rvd-aliases-valid.s

 
 # CHECK-INST: flt.d tp, ft6, ft5
 # CHECK-ALIAS: flt.d tp, ft6, ft5
 fgt.d x4, f5, f6
 # CHECK-INST: fle.d t2, fs1, fs0
 # CHECK-ALIAS: fle.d t2, fs1, fs0
 fge.d x7, f8, f9
 
+# CHECK-INST: fld ft0, 0(a0)
+# CHECK-ALIAS: fld ft0, 0(a0)
+fld f0, (x10)
+# CHECK-INST: fsd ft0, 0(a0)
+# CHECK-ALIAS: fsd ft0, 0(a0)
+fsd f0, (x10)
+
 ##===----------------------------------------------------------------------===##
 ## Aliases which omit the rounding mode.
 ##===----------------------------------------------------------------------===##
 
 # CHECK-INST: fmadd.d fa0, fa1, fa2, fa3, dyn
 # CHECK-ALIAS: fmadd.d fa0, fa1, fa2, fa3{{[[:space:]]}}
 fmadd.d f10, f11, f12, f13
 # CHECK-INST: fmsub.d fa4, fa5, fa6, fa7, dyn

llvm/trunk/test/MC/RISCV/rvdc-aliases-valid.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+d -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+c,+d -riscv-no-aliases \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+d < %s \
+# RUN:     | llvm-objdump -mattr=+c,+d -riscv-no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+d < %s \
+# RUN:     | llvm-objdump -mattr=+c,+d -riscv-no-aliases -d - \
+# RUN:     | FileCheck -check-prefixes=CHECK-EXPAND %s
+
+c.fld f8, (x9)
+# CHECK-EXPAND: c.fsd fs0, 0(s1)
+c.fsd f8, (x9)
+# CHECK-EXPAND: c.fldsp fs0, 0(sp)
+c.fldsp f8, (x2)
+# CHECK-EXPAND: c.fsdsp fs0, 0(sp)
+c.fsdsp f8, (x2)

llvm/trunk/test/MC/RISCV/rvf-aliases-valid.s

 
 # CHECK-INST: fmv.x.w a2, fs7
 # CHECK-ALIAS: fmv.x.w a2, fs7
 fmv.x.s a2, fs7
 # CHECK-INST: fmv.w.x ft1, a6
 # CHECK-ALIAS: fmv.w.x ft1, a6
 fmv.s.x ft1, a6
 
+# CHECK-INST: flw ft0, 0(a0)
+# CHECK-ALIAS: flw ft0, 0(a0)
+flw f0, (x10)
+# CHECK-INST: fsw ft0, 0(a0)
+# CHECK-ALIAS: fsw ft0, 0(a0)
+fsw f0, (x10)
+
 ##===----------------------------------------------------------------------===##
 ## Aliases which omit the rounding mode.
 ##===----------------------------------------------------------------------===##
 
 # CHECK-INST: fmadd.s fa0, fa1, fa2, fa3, dyn
 # CHECK-ALIAS: fmadd.s fa0, fa1, fa2, fa3{{[[:space:]]}}
 fmadd.s f10, f11, f12, f13
 # CHECK-INST: fmsub.s fa4, fa5, fa6, fa7, dyn