[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel.

[courbet]

Summary

The pfm counters are now in the MCSubtargetInfo rather than the
MCSchedModel (PR39165).

This also compresses the pfm counter tables (PR37068).

[courbet]

Sorry for the formatting noise, I'll revert the non-related changes.

[courbet]

Remove formatting noise.

[gchatelet]

include/llvm/MC/MCSchedule.h

195

What would ProcResName be is case of retired instruction for instance?

203

Why do you need both?

lib/MC/MCSchedule.cpp

155

I don't understand the error message.

utils/TableGen/CodeGenSchedule.cpp

786

join string literals and reapply formatting.

889

Same here

1207

Can you explain what the 6 is referring to?

1435

const

1466

join string literals

1957

Can you reformat

utils/TableGen/SubtargetEmitter.cpp

1892–1894

llvm::format would help here

OS << llvm::format("{0}ProcSchedKV, {0}ProcPfmKV, {0}WriteProcResTable, {0}WriteLatencyTable, {0}ReadAdvanceTable, ", Target);

1986–1988

Same here.

[courbet]

@gchatelet a bunch of your comments are on old code touched by unwanted reformatting. I ignored these since I have reverted the formatted changes.

include/llvm/MC/MCSchedule.h

195

the retired counter is a scheduler concept, not tied to proc resources. It would go with CycleCounter and UopsCounter above.

203

For consistency with MCSchedModel (see getValueForCpu() below).

lib/MC/MCSchedule.cpp

155

This is ensuring that the value can be constructed by the linker without running any dynamic initialization.

[courbet]

use "dynamic initialization" instead of "static constructor".

[courbet]

address review comments

[courbet]

Thanks

utils/TableGen/SubtargetEmitter.cpp

1892–1894

I want to remain consistent with the rest of the file. I've reformatted to make it more readable.

[RKSimon]

lib/Target/X86/X86.td

978

Missing btver2 details?

[courbet]

add missing BtVer2PfmCounters to btver2.

lib/Target/X86/X86.td

978

Thanks for the catch.

[andreadb]

I’m not at work today, but I’d like a bit of time to review this patch.

I saw that it has already been accepted. However I am not entirely sure if I like the idea of adding another field to MCSubtargetInfo. I need to think about this.

[courbet]

In D52932#1256560, @andreadb wrote:

I’m not at work today, but I’d like a bit of time to review this patch.

I saw that it has already been accepted. However I am not entirely sure if I like the idea of adding another field to MCSubtargetInfo. I need to think about this.

Sure, take your time.

[andreadb]

Thanks for waiting Clement.

I am now back from holiday, and I finally had time to look at your patch.

What concerns me about this approach is that MCSubtargetInfo describes a processor for the purpose of codegen.
At least for me (I know it may sound a bit philosophical), exposing the knowledge about PFMs to MCSubtargetInfo is not ideal. Ideally, the MCSubtargetInfo interface should be small and "abstract enough" to allow the description of different subprocessors for different targets. Anything perf related, should be described by other modules (i.e. in a separate class; alternatively, perf-related knowledge should be described by scheduling models).

What if instead we make PFM descriptors a customizable property tablegen class SchedMachineModel? Something that defaults to an empty set of descriptors.

On X86, knowledge about PFM counters of a vendor/family could be moved to a separate .td file (similarly to what you already do with lib/Target/X86/X86PfmCounters.td).
When a new model is created, people can either use let expressions to override the PFM set, or - alternatively - derive from a IntelSchedMachineModel class (vic. AMDSchedMachineModel) that sets some common "defaults".
Alternatively, we could introduce the concept of target vendor/processor family, if that helps mapping models to "default sets of" PFM counters.
As long as people are allowed to customize that set (either by using let expressions, or by overriding fiels using a a tablegen derived class), then it should be okay.

Not sure if it makes sense.

The bottom line is: I think we should try to keep the concept of PFMs separate from MCSubtargetInfo as much as possible.
That being said, I don't have a too strong opinion on this; if other devs think that I am wrong on this, then fine. I don't want to block the development on this.

I hope this helps.
Andrea

[courbet]

Hi Andrea, thanks for the comments.

I think there are two independent points that we're discussing here:
1 - Where we're putting the generated table
2 - How we specify the table.

Regarding (1):
The goal of this patch is to move the pfm counters out of the SchedModels (see PR39165), because different CPUs with different PFM counters can use the same sched model (e.g. sandybridge).
That being said, I'm not opposed to moving the table of CPU->MCPfmCountersInfo outside of the MCSubtargetInfo. One possible approach is to create a new PfmEmitter tablegen backend and PfmCounters library. If people think that's reasonable I can do that easily.

Regarding (2), I'm not sure I understand extactly what you're suggesting. Are you suggesting I do something like:

let PfmCounters = HaswellPfmCounters in {
def : HaswellProc<"haswell">;
def : HaswellProc<"core-avx2">; // Legacy alias.
}

Or more like:

// In X86.td:
def HaswellProcessorModel : HaswellProc<"haswell">;
def CoreAvx2ProcessorModel : HaswellProc<"core-avx2">; // Legacy alias.

// In X86PfmCounters.td:
def : ProcPfmCounters {
  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
  let UopsCounter = UopsIssuedPfmCounter;
  let IssueCounters = [
    PfmIssueCounter<"HWPort0", "uops_dispatched_port:port_0">,
    PfmIssueCounter<"HWPort1", "uops_dispatched_port:port_1">,
    PfmIssueCounter<"HWPort2", "uops_dispatched_port:port_2">,
    PfmIssueCounter<"HWPort3", "uops_dispatched_port:port_3">,
    PfmIssueCounter<"HWPort4", "uops_dispatched_port:port_4">,
    PfmIssueCounter<"HWPort5", "uops_dispatched_port:port_5">,
    PfmIssueCounter<"HWPort6", "uops_dispatched_port:port_6">,
    PfmIssueCounter<"HWPort7", "uops_dispatched_port:port_7">
  ];
  let ProcModels = [HaswellProcessorModel, CoreAvx2ProcessorModel]
}

[andreadb]

Thanks for the description Clement,

In D52932#1258740, @courbet wrote:

Hi Andrea, thanks for the comments.

I think there are two independent points that we're discussing here:
1 - Where we're putting the generated table
2 - How we specify the table.

Regarding (1):
The goal of this patch is to move the pfm counters out of the SchedModels (see PR39165), because different CPUs with different PFM counters can use the same sched model (e.g. sandybridge).

Sorry. I didn't realize this patch was trying to fix that issue.
The use case for this change was not very clear to me. I though it was just a simple: "how to inherit a default set of PMCs, so that I didn't have to specify the same set over and over..".

I still think it is a preferrable solution to not touch MCSubtargetInfo. That being said, I don't have a strong opinion; other reviewers are definitely more knowledgeable than me on exegesis..

Andrea

[courbet]

@RKSimon, any opinions ?

[courbet]

ping

[RKSimon]

Sorry for late reply!

It looks like we need to find a way to still embed this information in MCExtraProcessorInfo but allow for different CPUs PFM mappings.

One of the aims for PR39165 was to make it possible for llvm-exegesis to be run on CPUs with declared PFMs but without a model - allowing a report on raw resource usage for an instruction and to help create the model from scratch. @courbet @gchatelet do you think this would still be useful? Is it still an aim of llvm-exegesis to create models from scratch or just report on existing models?

Can you easily attach PFM mappings to the GenericModel/GenericPostRAModel?

[courbet]

In D52932#1270595, @RKSimon wrote:

It looks like we need to find a way to still embed this information in MCExtraProcessorInfo but allow for different CPUs PFM mappings.
Can you easily attach PFM mappings to the GenericModel/GenericPostRAModel?

I don't think an MCExtraProcessorInfo should store information for several CPUs, because MCExtraProcessorInfo is in MCSchedModel, which is selected by CPU, so that would be weird.

Before this change, we were putting the MCPfmCountersInfo inside MCSchedModel, which implicitly meant that there was a 1:1 mapping between them. This change decouples MCPfmCountersInfo from MCSchedModel.
A CPU chooses its SchedModel and PfmCounters independently.

Now the decision we have to make now is whether in TD files (see point (2) in my comment above):

• (A) the CPU should declare its PfmCounters (this is the approach I'm taking here). Because that's very similar to what is done for MCSchedModels, I'm doing the same for PfmCounters, i.e. putting the table of Cpu->PfmCounter inside TargetSubtargetInfo, but that is actually independent from (see point (1) in my response to Andrea's comment above)
• (B) the mapping of CPU->PfmCounter is kept separately (in X86PfmCounters.td).

One of the aims for PR39165 was to make it possible for llvm-exegesis to be run on CPUs with declared PFMs but without a model - allowing a report on raw resource usage for an instruction and to help create the model from scratch. @courbet @gchatelet do you think this would still be useful?
Is it still an aim of llvm-exegesis to create models from scratch or just report on existing models?

@lebedev.ri used llvm-exegesis to produce the bdverX model. At that point there was no SchedModel, so it still seems desirable to do this.

[RKSimon]

I don't think an MCExtraProcessorInfo should store information for several CPUs, because MCExtraProcessorInfo is in MCSchedModel, which is selected by CPU, so that would be weird.

You say that but we have multiple, very different, CPUs referencing the same model - Knights Landing uses the Haswell Model, the PileDriver model is likely to be used for the entire Bulldozer range, Sandy Bridge model is used as the default cpu - if you run llvm-exegesis in any of these cases apart for the 'main' cpu case it will just crash.

Before this change, we were putting the MCPfmCountersInfo inside MCSchedModel, which implicitly meant that there was a 1:1 mapping between them. This change decouples MCPfmCountersInfo from MCSchedModel.
A CPU chooses its SchedModel and PfmCounters independently.

Now the decision we have to make now is whether in TD files (see point (2) in my comment above):

• (A) the CPU should declare its PfmCounters (this is the approach I'm taking here). Because that's very similar to what is done for MCSchedModels, I'm doing the same for PfmCounters, i.e. putting the table of Cpu->PfmCounter inside TargetSubtargetInfo, but that is actually independent from (see point (1) in my response to Andrea's comment above)
• (B) the mapping of CPU->PfmCounter is kept separately (in X86PfmCounters.td).

(C) As the PFMs are only used by llvm-exegesis (and are likely to only every be) the PFM mappings should be moved entirely into llvm-exegesis code.

One of the aims for PR39165 was to make it possible for llvm-exegesis to be run on CPUs with declared PFMs but without a model - allowing a report on raw resource usage for an instruction and to help create the model from scratch. @courbet @gchatelet do you think this would still be useful?
Is it still an aim of llvm-exegesis to create models from scratch or just report on existing models?

@lebedev.ri used llvm-exegesis to produce the bdverX model. At that point there was no SchedModel, so it still seems desirable to do this.

IIRC @lebedev.ri had to create a copy of the btver2 model and then slowly iterate on it until it matched the bdver arch.

[lebedev.ri]

In D52932#1270712, @RKSimon wrote:

@lebedev.ri used llvm-exegesis to produce the bdverX model. At that point there was no SchedModel, so it still seems desirable to do this.

IIRC @lebedev.ri had to create a copy of the btver2 model and then slowly iterate on it

Correct.

until it matched the bdver arch.

[courbet]

In D52932#1270712, @RKSimon wrote:

I don't think an MCExtraProcessorInfo should store information for several CPUs, because MCExtraProcessorInfo is in MCSchedModel, which is selected by CPU, so that would be weird.

You say that but we have multiple, very different, CPUs referencing the same model - Knights Landing uses the Haswell Model, the PileDriver model is likely to be used for the entire Bulldozer range, Sandy Bridge model is used as the default cpu - if you run llvm-exegesis in any of these cases apart for the 'main' cpu case it will just crash.

That's exactly my point: Because we have very different CPUs referencing the same SchedModel, we should not store stuff that's going to vary from CPU to CPU (e.g. PfmCounters) inside the MCSchedModel.

Before this change, we were putting the MCPfmCountersInfo inside MCSchedModel, which implicitly meant that there was a 1:1 mapping between them. This change decouples MCPfmCountersInfo from MCSchedModel.
A CPU chooses its SchedModel and PfmCounters independently.

Now the decision we have to make now is whether in TD files (see point (2) in my comment above):

• (A) the CPU should declare its PfmCounters (this is the approach I'm taking here). Because that's very similar to what is done for MCSchedModels, I'm doing the same for PfmCounters, i.e. putting the table of Cpu->PfmCounter inside TargetSubtargetInfo, but that is actually independent from (see point (1) in my response to Andrea's comment above)
• (B) the mapping of CPU->PfmCounter is kept separately (in X86PfmCounters.td).

(C) As the PFMs are only used by llvm-exegesis (and are likely to only every be) the PFM mappings should be moved entirely into llvm-exegesis code.

This is choice (B) here, plus choice (1) in the comment I mentioned above, quoting myself:

"That being said, I'm not opposed to moving the table of CPU->MCPfmCountersInfo outside of the MCSubtargetInfo. One possible approach is to create a new PfmEmitter tablegen backend and PfmCounters library. If people think that's reasonable I can do that easily."

So it seems we have a plan now :)

One of the aims for PR39165 was to make it possible for llvm-exegesis to be run on CPUs with declared PFMs but without a model - allowing a report on raw resource usage for an instruction and to help create the model from scratch. @courbet @gchatelet do you think this would still be useful?
Is it still an aim of llvm-exegesis to create models from scratch or just report on existing models?

@lebedev.ri used llvm-exegesis to produce the bdverX model. At that point there was no SchedModel, so it still seems desirable to do this.

IIRC @lebedev.ri had to create a copy of the btver2 model and then slowly iterate on it until it matched the bdver arch.

[courbet]

Move pfm counters to ExegesisTarget. There is now a separate Exegesis TableGen backend.

[courbet]

AArch64 is not yet tablegened.

[andreadb]

In D52932#1272557, @courbet wrote:

Move pfm counters to ExegesisTarget. There is now a separate Exegesis TableGen backend.

Thanks Clement!

I really like this approach. Overall, I think it is a much better design than the original one, since it avoid polluting MCSubtargetInfo.

Cheers
-Andrea

[RKSimon]

LGTM - thanks @courbet

[courbet]

Thanks!

[courbet]

rebase

[CarlosAlbertoEnciso]

@courbet: Your commit seems to cause build issues:

http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/838

Thanks

[andreadb]

In D52932#1275505, @CarlosAlbertoEnciso wrote:

@courbet: Your commit seems to cause build issues:

http://lab.llvm.org:8011/builders/clang-x64-windows-msvc/builds/838

Thanks

Simon fixed this issue at r345252
http://llvm.org/viewvc/llvm-project?view=revision&revision=345252

-Andrea

[thakis]

llvm/trunk/lib/Target/X86/CMakeLists.txt

16 ↗

(On Diff #171043)

This list is in alphabetical order. Mind putting this entry in alphabetical order too?

[thakis]

llvm/trunk/lib/Target/X86/CMakeLists.txt

16 ↗

(On Diff #171043)

Also, it looks like X86GenExegesis.inc is only used on llvm/tools/lib/X86. Shouldn't this tablegen call be there?

include/llvm/CodeGen/TargetSubtargetInfo.h

 /// be exposed through a TargetSubtargetInfo-derived class.
 ///
 class TargetSubtargetInfo : public MCSubtargetInfo {
 protected: // Can only create subclasses...
   TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
                       ArrayRef<SubtargetFeatureKV> PF,
                       ArrayRef<SubtargetFeatureKV> PD,
                       const SubtargetInfoKV *ProcSched,
+                      const SubtargetInfoKV *ProcPfm,
                       const MCWriteProcResEntry *WPR,
                       const MCWriteLatencyEntry *WL,
                       const MCReadAdvanceEntry *RA, const InstrStage *IS,
                       const unsigned *OC, const unsigned *FP);
 
 public:
   // AntiDepBreakMode - Type of anti-dependence breaking that should
   // be performed before post-RA scheduling.
public:
   virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
     return false;
   }
 
   /// Returns true if MI is a dependency breaking instruction for the subtarget.
   ///
   /// Similar in behavior to `isZeroIdiom`. However, it knows how to identify
   /// all dependency breaking instructions (i.e. not just zero-idioms).
-  /// 
+  ///
   /// As for `isZeroIdiom`, this method returns a mask of "broken" dependencies.
   /// (See method `isZeroIdiom` for a detailed description of Mask).
   virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
     return isZeroIdiom(MI, Mask);
   }
 
   /// True if the subtarget should run MachineScheduler after aggressive
   /// coalescing.

include/llvm/MC/MCSchedule.h

struct MCExtraProcessorInfo {
   // Actual size of the reorder buffer in hardware.
   unsigned ReorderBufferSize;
   // Number of instructions retired per cycle.
   unsigned MaxRetirePerCycle;
   const MCRegisterFileDesc *RegisterFiles;
   unsigned NumRegisterFiles;
   const MCRegisterCostEntry *RegisterCostTable;
   unsigned NumRegisterCostEntries;
+};
 
-  struct PfmCountersInfo {
-    // An optional name of a performance counter that can be used to measure
-    // cycles.
-    const char *CycleCounter;
+struct MCPfmCountersInfo {
+  const char *const CycleCounter;
 
-    // An optional name of a performance counter that can be used to measure
-    // uops.
-    const char *UopsCounter;
+  const char *const UopsCounter;
 
-    // For each MCProcResourceDesc defined by the processor, an optional list of
-    // names of performance counters that can be used to measure the resource
-    // utilization.
-    const char **IssueCounters;
+  // An IssueCounter specifies how to measure uops issued to specific proc
+  // resources.
+  struct IssueCounter {
+    const char *const Counter;
+    // The name of the ProcResource that this counter measures.
+    const char *const ProcResName;
   };
-  PfmCountersInfo PfmCounters;
+  // An optional list of IssueCounters.
+  const IssueCounter *const IssueCounters;
+  const unsigned NumIssueCounters;
+
+  /// Returns the default initialized pfm counters.
+  static const MCPfmCountersInfo &getDefault() { return Default; }
+  static const MCPfmCountersInfo Default;
 };
 
 /// Machine model for scheduling, bundling, and heuristics.
 ///
 /// The machine model directly provides basic information about the
 /// microarchitecture to the scheduler in the form of properties. It also
 /// optionally refers to scheduler resource tables and itinerary
 /// tables. Scheduler resource tables model the latency and cost for each

include/llvm/MC/MCSubtargetInfo.h

 class MCSubtargetInfo {
   Triple TargetTriple;
   std::string CPU; // CPU being targeted.
   ArrayRef<SubtargetFeatureKV> ProcFeatures;  // Processor feature list
   ArrayRef<SubtargetFeatureKV> ProcDesc;  // Processor descriptions
 
   // Scheduler machine model
   const SubtargetInfoKV *ProcSchedModels;
+  const SubtargetInfoKV *ProcPfmCounters;
   const MCWriteProcResEntry *WriteProcResTable;
   const MCWriteLatencyEntry *WriteLatencyTable;
   const MCReadAdvanceEntry *ReadAdvanceTable;
   const MCSchedModel *CPUSchedModel;
+  const MCPfmCountersInfo *CPUPfmCounters;
 
   const InstrStage *Stages;            // Instruction itinerary stages
   const unsigned *OperandCycles;       // Itinerary operand cycles
   const unsigned *ForwardingPaths;
   FeatureBitset FeatureBits;           // Feature bits for current CPU + FS
 
 public:
   MCSubtargetInfo(const MCSubtargetInfo &) = default;
   MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
                   ArrayRef<SubtargetFeatureKV> PF,
                   ArrayRef<SubtargetFeatureKV> PD,
                   const SubtargetInfoKV *ProcSched,
+                  const SubtargetInfoKV *ProcPfm,
                   const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
                   const MCReadAdvanceEntry *RA, const InstrStage *IS,
                   const unsigned *OC, const unsigned *FP);
   MCSubtargetInfo() = delete;
   MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
   MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete;
   virtual ~MCSubtargetInfo() = default;
 
public:
   bool checkFeatures(StringRef FS) const;
 
   /// Get the machine model of a CPU.
   const MCSchedModel &getSchedModelForCPU(StringRef CPU) const;
 
   /// Get the machine model for this subtarget's CPU.
   const MCSchedModel &getSchedModel() const { return *CPUSchedModel; }
 
+  /// Get the pfm counters of a CPU.
+  const MCPfmCountersInfo &getPfmCountersForCPU(StringRef CPU) const;
+
+  /// Get the pfm counters for this subtarget's CPU.
+  const MCPfmCountersInfo &getPfmCounters() const { return *CPUPfmCounters; }
+
   /// Return an iterator at the first process resource consumed by the given
   /// scheduling class.
   const MCWriteProcResEntry *getWriteProcResBegin(
     const MCSchedClassDesc *SC) const {
     return &WriteProcResTable[SC->WriteProcResIdx];
   }
   const MCWriteProcResEntry *getWriteProcResEnd(
     const MCSchedClassDesc *SC) const {

include/llvm/Target/Target.td

class ComplexDeprecationPredicate<string dep> {
   string ComplexDeprecationPredicate = dep;
 }
 
 //===----------------------------------------------------------------------===//
 // Processor chip sets - These values represent each of the chip sets supported
 // by the scheduler.  Each Processor definition requires corresponding
 // instruction itineraries.
 //
-class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
+class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f,
+                ProcPfmCounters counters = NoProcPfmCounters> {
   // Name - Chip set name.  Used by command line (-mcpu=) to determine the
   // appropriate target chip.
   //
   string Name = n;
 
   // SchedModel - The machine model for scheduling and instruction cost.
   //
   SchedMachineModel SchedModel = NoSchedModel;
 
   // ProcItin - The scheduling information for the target processor.
   //
   ProcessorItineraries ProcItin = pi;
 
   // Features - list of
   list<SubtargetFeature> Features = f;
+
+  ProcPfmCounters PfmCounters = counters;
 }
 
 // ProcessorModel allows subtargets to specify the more general
 // SchedMachineModel instead if a ProcessorItinerary. Subtargets will
 // gradually move to this newer form.
 //
 // Although this class always passes NoItineraries to the Processor
 // class, the SchedMachineModel may still define valid Itineraries.
-class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f>
-  : Processor<n, NoItineraries, f> {
+class ProcessorModel<string n, SchedMachineModel m, list<SubtargetFeature> f,
+                    ProcPfmCounters counters = NoProcPfmCounters>
+  : Processor<n, NoItineraries, f, counters> {
   let SchedModel = m;
 }
 
 //===----------------------------------------------------------------------===//
 // InstrMapping - This class is used to create mapping tables to relate
 // instructions with each other based on the values specified in RowFields,
 // ColFields, KeyCol and ValueCols.
 //

include/llvm/Target/TargetSchedule.td

 // scheduling model.
 class RetireControlUnit<int bufferSize, int retirePerCycle> {
   int ReorderBufferSize = bufferSize;
   int MaxRetirePerCycle = retirePerCycle;
   SchedMachineModel SchedModel = ?;
 }
 
 // Allow the definition of hardware counters.
-class PfmCounter {
-  SchedMachineModel SchedModel = ?;
-}
-
-// Each processor can define how to measure cycles by defining a
-// PfmCycleCounter.
-class PfmCycleCounter<string counter> : PfmCounter {
+class PfmCounter<string counter> {
+  // The name of the counter that measures events.
+  // The name can be "some_counter + some_other_counter", in which case the
+  // measured value is the sum of events on these counters.
   string Counter = counter;
 }
 
-// Each ProcResourceUnits can define how to measure issued uops by defining
-// a PfmIssueCounter.
-class PfmIssueCounter<ProcResourceUnits resource, list<string> counters>
-    : PfmCounter{
-  // The resource units on which uops are issued.
-  ProcResourceUnits Resource = resource;
-  // The list of counters that measure issue events.
-  list<string> Counters = counters;
-}
-
-// Each processor can define how to measure NumMicroOps by defining a
-// PfmUopsCounter.
-class PfmUopsCounter<string counter> : PfmCounter {
-  string Counter = counter;
+// Issue counters can be tied to a ProcResource
+class PfmIssueCounter<string resource_name, string counter>
+    : PfmCounter<counter> {
+  // The name of the ProcResource on which uops are issued. This is used by
+  // llvm-exegesis to compare measurements with values in the SchedModels.
+  // If the CPU has a sched model, this should correspond to the name of a
+  // ProcResource.
+  string ResourceName = resource_name;
+}
+
+def NoPfmCounter : PfmCounter <""> {}
+
+class ProcPfmCounters {
+  // Processors can define how to measure cycles by defining a CycleCounter.
+  PfmCounter CycleCounter = NoPfmCounter;
+  // Processors can define how to measure uops by defining a UopsCounter.
+  PfmCounter UopsCounter = NoPfmCounter;
+  // Processors can define how to measure issued uops by defining IssueCounters.
+  list<PfmIssueCounter> IssueCounters = [];
 }
 
+def NoProcPfmCounters : ProcPfmCounters {}

lib/CodeGen/TargetSubtargetInfo.cpp

 #include "llvm/Support/raw_ostream.h"
 #include <string>
 
 using namespace llvm;
 
 TargetSubtargetInfo::TargetSubtargetInfo(
     const Triple &TT, StringRef CPU, StringRef FS,
     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
-    const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
-    const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
-    const InstrStage *IS, const unsigned *OC, const unsigned *FP)
-    : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) {
-}
+    const SubtargetInfoKV *ProcSched, const SubtargetInfoKV *ProcPfm,
+    const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
+    const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
+    const unsigned *FP)
+    : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, ProcPfm, WPR, WL, RA, IS,
+                      OC, FP) {}
 
 TargetSubtargetInfo::~TargetSubtargetInfo() = default;
 
 bool TargetSubtargetInfo::enableAtomicExpand() const {
   return true;
 }
 
 bool TargetSubtargetInfo::enableIndirectBrExpand() const {

lib/MC/MCSchedule.cpp

 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include <type_traits>
 
 using namespace llvm;
 
 static_assert(std::is_pod<MCSchedModel>::value,
-              "We shouldn't have a static constructor here");
+              "We shouldn't have dynamic initialization here");
 const MCSchedModel MCSchedModel::Default = {DefaultIssueWidth,
                                             DefaultMicroOpBufferSize,
                                             DefaultLoopMicroOpBufferSize,
                                             DefaultLoadLatency,
                                             DefaultHighLatency,
                                             DefaultMispredictPenalty,
                                             false,
                                             true,
MCSchedModel::getReciprocalThroughput(unsigned SchedClass,
   }
   if (Throughput.hasValue())
     return 1.0 / Throughput.getValue();
 
   // If there are no execution resources specified for this class, then assume
   // that it can execute at the maximum default issue width.
   return 1.0 / DefaultIssueWidth;
 }
+
+static_assert(std::is_pod<MCPfmCountersInfo>::value,
+              "We shouldn't have dynamic initialization here");
+const MCPfmCountersInfo MCPfmCountersInfo::Default = {nullptr, nullptr,
+                                                      nullptr};

lib/MC/MCSubtargetInfo.cpp

static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
                                  ArrayRef<SubtargetFeatureKV> ProcDesc,
                                  ArrayRef<SubtargetFeatureKV> ProcFeatures) {
   SubtargetFeatures Features(FS);
   return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
 }
 
 void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
   FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
-  if (!CPU.empty())
+  if (!CPU.empty()) {
     CPUSchedModel = &getSchedModelForCPU(CPU);
-  else
+    CPUPfmCounters = &getPfmCountersForCPU(CPU);
+  } else {
     CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
+    CPUPfmCounters = &MCPfmCountersInfo::getDefault();
+  }
 }
 
 void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
   FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
 }
 
 MCSubtargetInfo::MCSubtargetInfo(
     const Triple &TT, StringRef C, StringRef FS,
     ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
-    const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
-    const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
-    const InstrStage *IS, const unsigned *OC, const unsigned *FP)
+    const SubtargetInfoKV *ProcSched, const SubtargetInfoKV *ProcPfm,
+    const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
+    const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
+    const unsigned *FP)
     : TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
-      ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
-      ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
+      ProcSchedModels(ProcSched), ProcPfmCounters(ProcPfm),
+      WriteProcResTable(WPR), WriteLatencyTable(WL), ReadAdvanceTable(RA),
+      Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
   InitMCProcessorInfo(CPU, FS);
 }
 
 FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
   FeatureBits.flip(FB);
   return FeatureBits;
 }
 
for (std::string F : T.getFeatures()) {
     SubtargetFeatures::ApplyFeatureFlag(Set, F, ProcFeatures);
     if (F[0] == '-')
       F[0] = '+';
     SubtargetFeatures::ApplyFeatureFlag(All, F, ProcFeatures);
   }
   return (FeatureBits & All) == Set;
 }
 
-const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
-  assert(ProcSchedModels && "Processor machine model not available!");
-
-  ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
-
-  assert(std::is_sorted(SchedModels.begin(), SchedModels.end(),
-                    [](const SubtargetInfoKV &LHS, const SubtargetInfoKV &RHS) {
-                      return strcmp(LHS.Key, RHS.Key) < 0;
-                    }) &&
-         "Processor machine model table is not sorted");
+template <typename ValueT, const ValueT &(*GetDefault)()>
+static const ValueT &getValueForCpu(StringRef CPU,
+                                    ArrayRef<SubtargetInfoKV> ProcTs) {
+  assert(std::is_sorted(
+             ProcTs.begin(), ProcTs.end(),
+         "SubtargetInfoKV table is not sorted");
 
   // Find entry
-  auto Found =
-    std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU);
-  if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) {
+  auto Found = std::lower_bound(ProcTs.begin(), ProcTs.end(), CPU);
+  if (Found == ProcTs.end() || StringRef(Found->Key) != CPU) {
     if (CPU != "help") // Don't error if the user asked for help.
       errs() << "'" << CPU
              << "' is not a recognized processor for this target"
              << " (ignoring processor)\n";
-    return MCSchedModel::GetDefaultSchedModel();
-  }
-  assert(Found->Value && "Missing processor SchedModel value");
-  return *(const MCSchedModel *)Found->Value;
+    return GetDefault();
+  }
+  assert(Found->Value && "Missing processor value");
+  return *(const ValueT *)Found->Value;
+
+const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
+  assert(ProcSchedModels && "Processor machine model not available!");
+  return getValueForCpu<MCSchedModel, MCSchedModel::GetDefaultSchedModel>(
+      CPU, ArrayRef<SubtargetInfoKV>(ProcSchedModels, ProcDesc.size()));
+}
+
+const MCPfmCountersInfo &
+MCSubtargetInfo::getPfmCountersForCPU(StringRef CPU) const {
+  assert(ProcPfmCounters && "Processor pfm counters are available!");
+  return getValueForCpu<MCPfmCountersInfo, MCPfmCountersInfo::getDefault>(
+      CPU, ArrayRef<SubtargetInfoKV>(ProcPfmCounters, ProcDesc.size()));
 }
 
 InstrItineraryData
 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
   const MCSchedModel &SchedModel = getSchedModelForCPU(CPU);
   return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
 }
 
 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
   InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
                                   ForwardingPaths);
 }

lib/Target/X86/X86.td

 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "X86RegisterInfo.td"
 include "X86RegisterBanks.td"
 
 //===----------------------------------------------------------------------===//
+// Pfm Counters
+//===----------------------------------------------------------------------===//
+
+include "X86PfmCounters.td"
+
+//===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "X86Schedule.td"
 include "X86InstrInfo.td"
 include "X86SchedPredicates.td"
 
 def X86InstrInfo : InstrInfo;

 def ProcIntelCNL  : SubtargetFeature<"cannonlake", "X86ProcFamily",
                     "IntelCannonlake", "Intel Cannonlake processors">;
 def ProcIntelICL  : SubtargetFeature<"icelake-client", "X86ProcFamily",
                     "IntelIcelakeClient", "Intel Icelake processors">;
 def ProcIntelICX  : SubtargetFeature<"icelake-server", "X86ProcFamily",
                     "IntelIcelakeServer", "Intel Icelake Server processors">;
 
 class Proc<string Name, list<SubtargetFeature> Features>
- : ProcessorModel<Name, GenericModel, Features>;
+ : ProcessorModel<Name, GenericModel, Features, NoProcPfmCounters>;
 
 def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16]>;
 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
 def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16]>;
 def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16]>;
 def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
 

 
 class ProcessorFeatures<list<SubtargetFeature> Inherited,
                         list<SubtargetFeature> NewFeatures> {
   list<SubtargetFeature> Value = !listconcat(Inherited, NewFeatures);
 }
 
 class ProcModel<string Name, SchedMachineModel Model,
                 list<SubtargetFeature> ProcFeatures,
-                list<SubtargetFeature> OtherFeatures> :
-  ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures)>;
+                list<SubtargetFeature> OtherFeatures,
+                ProcPfmCounters counters = NoProcPfmCounters> :
+  ProcessorModel<Name, Model, !listconcat(ProcFeatures, OtherFeatures),
+                 counters>;
 
 def GLMFeatures : ProcessorFeatures<[], [
   FeatureX87,
   FeatureCMOV,
   FeatureMMX,
   FeatureSSE42,
   FeatureFXSR,
   FeatureNOPL,
def SNBFeatures : ProcessorFeatures<[], [
   FeatureSlowIncDec,
   FeatureMacroFusion
 ]>;
 
 class SandyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
                                                SNBFeatures.Value, [
   FeatureSlowUAMem32,
   FeaturePOPCNTFalseDeps
-]>;
+], SandyBridgePfmCounters>;
 def : SandyBridgeProc<"sandybridge">;
 def : SandyBridgeProc<"corei7-avx">; // Legacy alias.
 
 def IVBFeatures : ProcessorFeatures<SNBFeatures.Value, [
   FeatureRDRAND,
   FeatureF16C,
   FeatureFSGSBase
 ]>;
 
 class IvyBridgeProc<string Name> : ProcModel<Name, SandyBridgeModel,
                                              IVBFeatures.Value, [
   FeatureSlowUAMem32,
   FeaturePOPCNTFalseDeps
-]>;
+], SandyBridgePfmCounters>;
 def : IvyBridgeProc<"ivybridge">;
 def : IvyBridgeProc<"core-avx-i">; // Legacy alias.
 
 def HSWFeatures : ProcessorFeatures<IVBFeatures.Value, [
   FeatureAVX2,
   FeatureBMI,
   FeatureBMI2,
   FeatureERMSB,
   FeatureFMA,
   FeatureINVPCID,
   FeatureLZCNT,
   FeatureMOVBE,
   FeatureFastVariableShuffle
 ]>;
 
 class HaswellProc<string Name> : ProcModel<Name, HaswellModel,
                                            HSWFeatures.Value, [
   ProcIntelHSW,
   FeaturePOPCNTFalseDeps,
   FeatureLZCNTFalseDeps
-]>;
+], HaswellPfmCounters>;
 def : HaswellProc<"haswell">;
 def : HaswellProc<"core-avx2">; // Legacy alias.
 
 def BDWFeatures : ProcessorFeatures<HSWFeatures.Value, [
   FeatureADX,
   FeatureRDSEED,
   FeaturePRFCHW
 ]>;
 class BroadwellProc<string Name> : ProcModel<Name, BroadwellModel,
                                              BDWFeatures.Value, [
   ProcIntelBDW,
   FeaturePOPCNTFalseDeps,
   FeatureLZCNTFalseDeps
-]>;
+], BroadwellPfmCounters>;
 def : BroadwellProc<"broadwell">;
 
 def SKLFeatures : ProcessorFeatures<BDWFeatures.Value, [
   FeatureAES,
   FeatureMPX,
   FeatureRTM,
   FeatureXSAVEC,
   FeatureXSAVES,
   FeatureCLFLUSHOPT,
   FeatureFastVectorFSQRT
 ]>;
 
 class SkylakeClientProc<string Name> : ProcModel<Name, SkylakeClientModel,
                                                  SKLFeatures.Value, [
   ProcIntelSKL,
   FeatureHasFastGather,
   FeaturePOPCNTFalseDeps,
   FeatureSGX
-]>;
+], SkylakeClientPfmCounters>;
 def : SkylakeClientProc<"skylake">;
 
 def KNLFeatures : ProcessorFeatures<IVBFeatures.Value, [
   FeatureAVX512,
   FeatureERI,
   FeatureCDI,
   FeaturePFI,
   FeaturePREFETCHWT1,
def SKXFeatures : ProcessorFeatures<SKLFeatures.Value, [
   FeatureCLWB
 ]>;
 
 class SkylakeServerProc<string Name> : ProcModel<Name, SkylakeServerModel,
                                                  SKXFeatures.Value, [
   ProcIntelSKX,
   FeatureHasFastGather,
   FeaturePOPCNTFalseDeps
-]>;
+], SkylakeServerPfmCounters>;
 def : SkylakeServerProc<"skylake-avx512">;
 def : SkylakeServerProc<"skx">; // Legacy alias.
 
 def CNLFeatures : ProcessorFeatures<SKLFeatures.Value, [
   FeatureAVX512,
   FeatureCDI,
   FeatureDQI,
   FeatureBWI,
def : Proc<"btver1", [
   FeatureLZCNT,
   FeaturePOPCNT,
   FeatureSlowSHLD,
   FeatureLAHFSAHF,
   FeatureFast15ByteNOP
 ]>;
 
 // Jaguar
 def : ProcessorModel<"btver2", BtVer2Model, [
   FeatureX87,
   FeatureCMOV,
   FeatureMMX,
   FeatureAVX,
   FeatureFXSR,
   FeatureNOPL,
   FeatureSSE4A,
   Feature64Bit,

 
 def X86 : Target {
   // Information about the instructions...
   let InstructionSet = X86InstrInfo;
   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
   let AllowRegisterRenaming = 1;
 }
-
-//===----------------------------------------------------------------------===//
-// Pfm Counters
-//===----------------------------------------------------------------------===//
-
-include "X86PfmCounters.td"

lib/Target/X86/X86PfmCounters.td

 //===-- X86PfmCounters.td - X86 Hardware Counters ----------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This describes the available hardware counters for various subtargets.
 //
 //===----------------------------------------------------------------------===//
 
-let SchedModel = SandyBridgeModel in {
-def SBCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
-def SBPort0Counter : PfmIssueCounter<SBPort0, ["uops_dispatched_port:port_0"]>;
-def SBPort1Counter : PfmIssueCounter<SBPort1, ["uops_dispatched_port:port_1"]>;
-def SBPort23Counter : PfmIssueCounter<SBPort23,
-                                      ["uops_dispatched_port:port_2",
-                                       "uops_dispatched_port:port_3"]>;
-def SBPort4Counter : PfmIssueCounter<SBPort4, ["uops_dispatched_port:port_4"]>;
-def SBPort5Counter : PfmIssueCounter<SBPort5, ["uops_dispatched_port:port_5"]>;
-def SBUopsCounter  : PfmUopsCounter<"uops_issued:any">;
-}
-
-let SchedModel = HaswellModel in {
-def HWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
-def HWPort0Counter : PfmIssueCounter<HWPort0, ["uops_dispatched_port:port_0"]>;
-def HWPort1Counter : PfmIssueCounter<HWPort1, ["uops_dispatched_port:port_1"]>;
-def HWPort2Counter : PfmIssueCounter<HWPort2, ["uops_dispatched_port:port_2"]>;
-def HWPort3Counter : PfmIssueCounter<HWPort3, ["uops_dispatched_port:port_3"]>;
-def HWPort4Counter : PfmIssueCounter<HWPort4, ["uops_dispatched_port:port_4"]>;
-def HWPort5Counter : PfmIssueCounter<HWPort5, ["uops_dispatched_port:port_5"]>;
-def HWPort6Counter : PfmIssueCounter<HWPort6, ["uops_dispatched_port:port_6"]>;
-def HWPort7Counter : PfmIssueCounter<HWPort7, ["uops_dispatched_port:port_7"]>;
-def HWUopsCounter  : PfmUopsCounter<"uops_issued:any">;
-}
-
-let SchedModel = BroadwellModel in {
-def BWCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
-def BWPort0Counter : PfmIssueCounter<BWPort0, ["uops_executed_port:port_0"]>;
-def BWPort1Counter : PfmIssueCounter<BWPort1, ["uops_executed_port:port_1"]>;
-def BWPort2Counter : PfmIssueCounter<BWPort2, ["uops_executed_port:port_2"]>;
-def BWPort3Counter : PfmIssueCounter<BWPort3, ["uops_executed_port:port_3"]>;
-def BWPort4Counter : PfmIssueCounter<BWPort4, ["uops_executed_port:port_4"]>;
-def BWPort5Counter : PfmIssueCounter<BWPort5, ["uops_executed_port:port_5"]>;
-def BWPort6Counter : PfmIssueCounter<BWPort6, ["uops_executed_port:port_6"]>;
-def BWPort7Counter : PfmIssueCounter<BWPort7, ["uops_executed_port:port_7"]>;
-def BWUopsCounter  : PfmUopsCounter<"uops_issued:any">;
-}
-
-let SchedModel = SkylakeClientModel in {
-def SKLCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
-def SKLPort0Counter : PfmIssueCounter<SKLPort0, ["uops_dispatched_port:port_0"]>;
-def SKLPort1Counter : PfmIssueCounter<SKLPort1, ["uops_dispatched_port:port_1"]>;
-def SKLPort2Counter : PfmIssueCounter<SKLPort2, ["uops_dispatched_port:port_2"]>;
-def SKLPort3Counter : PfmIssueCounter<SKLPort3, ["uops_dispatched_port:port_3"]>;
-def SKLPort4Counter : PfmIssueCounter<SKLPort4, ["uops_dispatched_port:port_4"]>;
-def SKLPort5Counter : PfmIssueCounter<SKLPort5, ["uops_dispatched_port:port_5"]>;
-def SKLPort6Counter : PfmIssueCounter<SKLPort6, ["uops_dispatched_port:port_6"]>;
-def SKLPort7Counter : PfmIssueCounter<SKLPort7, ["uops_dispatched_port:port_7"]>;
-def SKLUopsCounter  : PfmUopsCounter<"uops_issued:any">;
-}
-
-let SchedModel = SkylakeServerModel in {
-def SKXCycleCounter : PfmCycleCounter<"unhalted_core_cycles">;
-def SKXPort0Counter : PfmIssueCounter<SKXPort0, ["uops_dispatched_port:port_0"]>;
-def SKXPort1Counter : PfmIssueCounter<SKXPort1, ["uops_dispatched_port:port_1"]>;
-def SKXPort2Counter : PfmIssueCounter<SKXPort2, ["uops_dispatched_port:port_2"]>;
-def SKXPort3Counter : PfmIssueCounter<SKXPort3, ["uops_dispatched_port:port_3"]>;
-def SKXPort4Counter : PfmIssueCounter<SKXPort4, ["uops_dispatched_port:port_4"]>;
-def SKXPort5Counter : PfmIssueCounter<SKXPort5, ["uops_dispatched_port:port_5"]>;
-def SKXPort6Counter : PfmIssueCounter<SKXPort6, ["uops_dispatched_port:port_6"]>;
-def SKXPort7Counter : PfmIssueCounter<SKXPort7, ["uops_dispatched_port:port_7"]>;
-def SKXUopsCounter  : PfmUopsCounter<"uops_issued:any">;
-}
-
-let SchedModel = BtVer2Model in {
-def JCycleCounter : PfmCycleCounter<"cpu_clk_unhalted">;
-def JUopsCounter  : PfmUopsCounter<"retired_uops">;
-def JFPU0Counter  : PfmIssueCounter<JFPU0, ["dispatched_fpu:pipe0"]>;
-def JFPU1Counter  : PfmIssueCounter<JFPU1, ["dispatched_fpu:pipe1"]>;
+def UnhaltedCoreCyclesPfmCounter : PfmCounter<"unhalted_core_cycles">;
+def UopsIssuedPfmCounter : PfmCounter<"uops_issued:any">;
+
+def SandyBridgePfmCounters : ProcPfmCounters {
+  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
+  let UopsCounter = UopsIssuedPfmCounter;
+  let IssueCounters = [
+    PfmIssueCounter<"SBPort0",  "uops_dispatched_port:port_0">,
+    PfmIssueCounter<"SBPort1",  "uops_dispatched_port:port_1">,
+    PfmIssueCounter<"SBPort23", "uops_dispatched_port:port_2 + uops_dispatched_port:port_3">,
+    PfmIssueCounter<"SBPort4",  "uops_dispatched_port:port_4">,
+    PfmIssueCounter<"SBPort5",  "uops_dispatched_port:port_5">
+  ];
+}
+
+def HaswellPfmCounters : ProcPfmCounters {
+  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
+  let UopsCounter = UopsIssuedPfmCounter;
+  let IssueCounters = [
+    PfmIssueCounter<"HWPort0", "uops_dispatched_port:port_0">,
+    PfmIssueCounter<"HWPort1", "uops_dispatched_port:port_1">,
+    PfmIssueCounter<"HWPort2", "uops_dispatched_port:port_2">,
+    PfmIssueCounter<"HWPort3", "uops_dispatched_port:port_3">,
+    PfmIssueCounter<"HWPort4", "uops_dispatched_port:port_4">,
+    PfmIssueCounter<"HWPort5", "uops_dispatched_port:port_5">,
+    PfmIssueCounter<"HWPort6", "uops_dispatched_port:port_6">,
+    PfmIssueCounter<"HWPort7", "uops_dispatched_port:port_7">
+  ];
+}
+
+def BroadwellPfmCounters : ProcPfmCounters {
+  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
+  let UopsCounter = UopsIssuedPfmCounter;
+  let IssueCounters = [
+    PfmIssueCounter<"BWPort0", "uops_executed_port:port_0">,
+    PfmIssueCounter<"BWPort1", "uops_executed_port:port_1">,
+    PfmIssueCounter<"BWPort2", "uops_executed_port:port_2">,
+    PfmIssueCounter<"BWPort3", "uops_executed_port:port_3">,
+    PfmIssueCounter<"BWPort4", "uops_executed_port:port_4">,
+    PfmIssueCounter<"BWPort5", "uops_executed_port:port_5">,
+    PfmIssueCounter<"BWPort6", "uops_executed_port:port_6">,
+    PfmIssueCounter<"BWPort7", "uops_executed_port:port_7">
+  ];
+}
+
+def SkylakeClientPfmCounters : ProcPfmCounters {
+  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
+  let UopsCounter = UopsIssuedPfmCounter;
+  let IssueCounters = [
+    PfmIssueCounter<"SKLPort0", "uops_dispatched_port:port_0">,
+    PfmIssueCounter<"SKLPort1", "uops_dispatched_port:port_1">,
+    PfmIssueCounter<"SKLPort2", "uops_dispatched_port:port_2">,
+    PfmIssueCounter<"SKLPort3", "uops_dispatched_port:port_3">,
+    PfmIssueCounter<"SKLPort4", "uops_dispatched_port:port_4">,
+    PfmIssueCounter<"SKLPort5", "uops_dispatched_port:port_5">,
+    PfmIssueCounter<"SKLPort6", "uops_dispatched_port:port_6">,
+    PfmIssueCounter<"SKLPort7", "uops_dispatched_port:port_7">
+  ];
+}
+
+def SkylakeServerPfmCounters : ProcPfmCounters {
+  let CycleCounter = UnhaltedCoreCyclesPfmCounter;
+  let UopsCounter = UopsIssuedPfmCounter;
+  let IssueCounters = [
+    PfmIssueCounter<"SKXPort0", "uops_dispatched_port:port_0">,
+    PfmIssueCounter<"SKXPort1", "uops_dispatched_port:port_1">,
+    PfmIssueCounter<"SKXPort2", "uops_dispatched_port:port_2">,
+    PfmIssueCounter<"SKXPort3", "uops_dispatched_port:port_3">,
+    PfmIssueCounter<"SKXPort4", "uops_dispatched_port:port_4">,
+    PfmIssueCounter<"SKXPort5", "uops_dispatched_port:port_5">,
+    PfmIssueCounter<"SKXPort6", "uops_dispatched_port:port_6">,
+    PfmIssueCounter<"SKXPort7", "uops_dispatched_port:port_7">
+  ];
+}
+
+def BtVer2PfmCounters : ProcPfmCounters {
+  let CycleCounter = PfmCounter<"cpu_clk_unhalted">;
+  let UopsCounter = PfmCounter<"retired_uops">;
+  let IssueCounters = [
+    PfmIssueCounter<"JFPU0", "dispatched_fpu:pipe0">,
+    PfmIssueCounter<"JFPU1", "dispatched_fpu:pipe1">
+  ];
 }

tools/llvm-exegesis/lib/Latency.cpp

if (auto CT = generateSelfAliasingCodeTemplate(Instr))
     return CT;
   else
     llvm::consumeError(CT.takeError());
   // No self aliasing, trying to create a dependency through another opcode.
   return generateTwoInstructionPrototype(Instr);
 }
 
 const char *LatencyBenchmarkRunner::getCounterName() const {
-  if (!State.getSubtargetInfo().getSchedModel().hasExtraProcessorInfo())
-    llvm::report_fatal_error("sched model is missing extra processor info!");
-  const char *CounterName = State.getSubtargetInfo()
-                                .getSchedModel()
-                                .getExtraProcessorInfo()
-                                .PfmCounters.CycleCounter;
+  const char *CounterName =
+      State.getSubtargetInfo().getPfmCounters().CycleCounter;
   if (!CounterName)
     llvm::report_fatal_error("sched model does not define a cycle counter");
   return CounterName;
 }
 
 LatencyBenchmarkRunner::~LatencyBenchmarkRunner() = default;
 
 std::vector<BenchmarkMeasure>

tools/llvm-exegesis/lib/Uops.cpp

UopsSnippetGenerator::generateCodeTemplate(unsigned Opcode) const {
   CT.Instructions.push_back(std::move(IT));
   instantiateMemoryOperands(CT.ScratchSpacePointerInReg, CT.Instructions);
   return std::move(CT);
 }
 
 std::vector<BenchmarkMeasure>
 UopsBenchmarkRunner::runMeasurements(const ExecutableFunction &Function,
                                      ScratchSpace &Scratch) const {
-  const auto &SchedModel = State.getSubtargetInfo().getSchedModel();
-
-  const auto RunMeasurement = [&Function,
-                               &Scratch](const char *const Counters) {
+  const auto RunMeasurement = [&Function, &Scratch](const char *const Counter) {
     // We sum counts when there are several counters for a single ProcRes
     // (e.g. P23 on SandyBridge).
     int64_t CounterValue = 0;
     llvm::SmallVector<llvm::StringRef, 2> CounterNames;
-    llvm::StringRef(Counters).split(CounterNames, ',');
-    for (const auto &CounterName : CounterNames) {
+    llvm::StringRef(Counter).split(CounterNames, '+');
+    for (auto CounterName : CounterNames) {
+      CounterName = CounterName.trim();
       pfm::PerfEvent UopPerfEvent(CounterName);
       if (!UopPerfEvent.valid())
         llvm::report_fatal_error(
-            llvm::Twine("invalid perf event ").concat(Counters));
+            llvm::Twine("invalid perf event ").concat(Counter));
       pfm::Counter Counter(UopPerfEvent);
       Scratch.clear();
       Counter.start();
       Function(Scratch.ptr());
       Counter.stop();
       CounterValue += Counter.read();
     }
     return CounterValue;
   };
 
   std::vector<BenchmarkMeasure> Result;
-  const auto &PfmCounters = SchedModel.getExtraProcessorInfo().PfmCounters;
+  const llvm::MCPfmCountersInfo &PCI =
+      State.getSubtargetInfo().getPfmCounters();
   // Uops per port.
-  for (unsigned ProcResIdx = 1;
-       ProcResIdx < SchedModel.getNumProcResourceKinds(); ++ProcResIdx) {
-    const char *const Counters = PfmCounters.IssueCounters[ProcResIdx];
-    if (!Counters)
-      continue;
-    const double CounterValue = RunMeasurement(Counters);
-    Result.push_back(BenchmarkMeasure::Create(
-        SchedModel.getProcResource(ProcResIdx)->Name, CounterValue));
+  for (const auto *IssueCounter = PCI.IssueCounters,
+                  *IssueCounterEnd = PCI.IssueCounters + PCI.NumIssueCounters;
+       IssueCounter != IssueCounterEnd; ++IssueCounter) {
+    const double CounterValue =
+        IssueCounter->Counter ? RunMeasurement(IssueCounter->Counter) : 0.0;
+    Result.push_back(
+        BenchmarkMeasure::Create(IssueCounter->ProcResName, CounterValue));
   }
   // NumMicroOps.
-  if (const char *const UopsCounter = PfmCounters.UopsCounter) {
+  if (const char *const UopsCounter = PCI.UopsCounter) {
     const double CounterValue = RunMeasurement(UopsCounter);
     Result.push_back(BenchmarkMeasure::Create("NumMicroOps", CounterValue));
   }
   return Result;
 }
 
 constexpr const size_t UopsSnippetGenerator::kMinNumDifferentAddresses;
 
 } // namespace exegesis

unittests/CodeGen/MachineInstrTest.cpp

void emitEpilogue(MachineFunction &MF,
                     MachineBasicBlock &MBB) const override {}
   bool hasFP(const MachineFunction &MF) const override { return false; }
 };
 
 class BogusSubtarget : public TargetSubtargetInfo {
 public:
   BogusSubtarget(TargetMachine &TM)
       : TargetSubtargetInfo(Triple(""), "", "", {}, {}, nullptr, nullptr,
-                            nullptr, nullptr, nullptr, nullptr, nullptr),
+                            nullptr, nullptr, nullptr, nullptr, nullptr,
+                            nullptr),
         FL(), TL(TM) {}
   ~BogusSubtarget() override {}
 
   const TargetFrameLowering *getFrameLowering() const override { return &FL; }
 
   const TargetLowering *getTargetLowering() const override { return &TL; }
 
   const TargetInstrInfo *getInstrInfo() const override { return &TII; }

utils/TableGen/CodeGenSchedule.h

struct CodeGenProcModel {
   RecVec ProcResourceDefs;
 
   // List of Register Files.
   std::vector<CodeGenRegisterFile> RegisterFiles;
 
   // Optional Retire Control Unit definition.
   Record *RetireControlUnit;
 
-  // List of PfmCounters.
-  RecVec PfmIssueCounterDefs;
-  Record *PfmCycleCounterDef = nullptr;
-  Record *PfmUopsCounterDef = nullptr;
-
   CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef,
                    Record *IDef) :
     Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef),
     RetireControlUnit(nullptr) {}
 
   bool hasItineraries() const {
     return !ItinsDef->getValueAsListOfDefs("IID").empty();
   }
 
   bool hasInstrSchedModel() const {
     return !WriteResDefs.empty() || !ItinRWDefs.empty();
   }
 
   bool hasExtraProcessorInfo() const {
-    return RetireControlUnit || !RegisterFiles.empty() ||
-        !PfmIssueCounterDefs.empty() ||
-        PfmCycleCounterDef != nullptr ||
-        PfmUopsCounterDef != nullptr;
+    return RetireControlUnit || !RegisterFiles.empty();
   }
 
   unsigned getProcResourceIdx(Record *PRDef) const;
 
   bool isUnsupported(const CodeGenInstruction &Inst) const;
 
 #ifndef NDEBUG
   void dump() const;
class CodeGenSchedModels {
 
   // Map each instruction to its unique SchedClass index considering the
   // combination of it's itinerary class, SchedRW list, and InstRW records.
   using InstClassMapTy = DenseMap<Record*, unsigned>;
   InstClassMapTy InstrClassMap;
 
   std::vector<STIPredicateFunction> STIPredicates;
 
+  // Table of counter name -> counter index.
+  std::map<llvm::StringRef, unsigned> PfmCounterNameTable;
+
 public:
   CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
 
   // iterator access to the scheduling classes.
   using class_iterator = std::vector<CodeGenSchedClass>::iterator;
   using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator;
   class_iterator classes_begin() { return SchedClasses.begin(); }
   const_class_iterator classes_begin() const { return SchedClasses.begin(); }
   class_iterator classes_end() { return SchedClasses.end(); }
   const_class_iterator classes_end() const { return SchedClasses.end(); }
   iterator_range<class_iterator> classes() {
    return make_range(classes_begin(), classes_end());
   }
   iterator_range<const_class_iterator> classes() const {
    return make_range(classes_begin(), classes_end());
   }
   iterator_range<class_iterator> explicit_classes() {
     return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
   }
   iterator_range<const_class_iterator> explicit_classes() const {
     return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
   }
 
+  const std::map<llvm::StringRef, unsigned> &getPfmCounterNameTable() const {
+    return PfmCounterNameTable;
+  }
+
   Record *getModelOrItinDef(Record *ProcDef) const {
     Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
     Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
     if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
       assert(ModelDef->getValueAsBit("NoModel")
              && "Itineraries must be defined within SchedMachineModel");
       return ItinsDef;
     }

utils/TableGen/CodeGenSchedule.cpp

if (Rec->getValueInit("SchedModel")->isComplete()) {
       Record *ModelDef = Rec->getValueAsDef("SchedModel");
       if (&getProcModel(ModelDef) != &ProcModel)
         continue;
     }
     if (AliasDef)
       PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
                       "defined for processor " + ProcModel.ModelName +
                       " Ensure only one SchedAlias exists per RW.");
     AliasDef = AliasRW.TheDef;
   }
   if (AliasDef) {
     expandRWSeqForProc(getSchedRWIdx(AliasDef, IsRead),
                        RWSeq, IsRead,ProcModel);
     return;
   }
   if (!SchedWrite.IsSequence) {
     RWSeq.push_back(RWIdx);
if (!SCIdx) {
         if (!Inst->hasNoSchedulingInfo)
           dbgs() << "No machine model for " << Inst->TheDef->getName() << '\n';
       });
       continue;
     }
     CodeGenSchedClass &SC = getSchedClass(SCIdx);
     if (SC.ProcIndices[0] != 0)
       PrintFatalError(Inst->TheDef->getLoc(), "Instruction's sched class "
                       "must not be subtarget specific.");
 
     IdxVec ProcIndices;
     if (SC.ItinClassDef->getName() != "NoItinerary") {
       ProcIndices.push_back(0);
       dbgs() << "Itinerary for " << InstName << ": "
              << SC.ItinClassDef->getName() << '\n';
     }
     if (!SC.Writes.empty()) {
for (unsigned Idx = 0; Idx != SchedClasses.size(); ++Idx) {
     if (SchedClasses[Idx].ItinClassDef)
       inferFromItinClass(SchedClasses[Idx].ItinClassDef, Idx);
     if (!SchedClasses[Idx].InstRWs.empty())
       inferFromInstRWs(Idx);
     if (!SchedClasses[Idx].Writes.empty()) {
       inferFromRW(SchedClasses[Idx].Writes, SchedClasses[Idx].Reads,
                   Idx, SchedClasses[Idx].ProcIndices);
     }
     assert(SchedClasses.size() < (NumInstrSchedClasses*6) &&
            "too many SchedVariants");
   }
 }
 
 /// Infer classes from per-processor itinerary resources.
 void CodeGenSchedModels::inferFromItinClass(Record *ItinClassDef,
                                             unsigned FromClassIdx) {
   for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
if (AliasProcIdx == 0)
       GenericRW = true;
   }
   for (TransVariant &Variant : Variants) {
     // Don't expand variants if the processor models don't intersect.
     // A zero processor index means any processor.
     SmallVectorImpl<unsigned> &ProcIndices = TransVec[TransIdx].ProcIndices;
     if (ProcIndices[0] && Variant.ProcIdx) {
       unsigned Cnt = std::count(ProcIndices.begin(), ProcIndices.end(),
                                 Variant.ProcIdx);
       if (!Cnt)
         continue;
       if (Cnt > 1) {
         const CodeGenProcModel &PM =
           *(SchedModels.procModelBegin() + Variant.ProcIdx);
         PrintFatalError(Variant.VarOrSeqDef->getLoc(),
                         "Multiple variants defined for processor " +
                         PM.ModelName +
else {
       // Push another copy of the current transition for more variants.
       Variant.TransVecIdx = TransVec.size();
       IntersectingVariants.push_back(Variant);
       TransVec.push_back(TransVec[TransIdx]);
     }
   }
   if (GenericRW && IntersectingVariants.empty()) {
     PrintFatalError(SchedRW.TheDef->getLoc(), "No variant of this type has "
                     "a matching predicate on any processor");
   }
 }
 
 // Push the Reads/Writes selected by this variant onto the PredTransition
 // specified by VInfo.
 void PredTransitions::
 pushVariant(const TransVariant &VInfo, bool IsRead) {
   PredTransition &Trans = TransVec[VInfo.TransVecIdx];
for (Record *RF : RegisterFileDefs) {
     std::vector<int64_t> RegisterCosts = RF->getValueAsListOfInts("RegCosts");
     for (unsigned I = 0, E = RegisterClasses.size(); I < E; ++I) {
       int Cost = RegisterCosts.size() > I ? RegisterCosts[I] : 1;
       CGRF.Costs.emplace_back(RegisterClasses[I], Cost);
     }
   }
 }
 
-// Collect all the RegisterFile definitions available in this target.
+// Collect all the ProcPfmCounters definitions available in this target.
 void CodeGenSchedModels::collectPfmCounters() {
-  for (Record *Def : Records.getAllDerivedDefinitions("PfmIssueCounter")) {
-    CodeGenProcModel &PM = getProcModel(Def->getValueAsDef("SchedModel"));
-    PM.PfmIssueCounterDefs.emplace_back(Def);
-  }
-  for (Record *Def : Records.getAllDerivedDefinitions("PfmCycleCounter")) {
-    CodeGenProcModel &PM = getProcModel(Def->getValueAsDef("SchedModel"));
-    if (PM.PfmCycleCounterDef) {
-      PrintFatalError(Def->getLoc(),
-                      "multiple cycle counters for " +
-                          Def->getValueAsDef("SchedModel")->getName());
-    }
-    PM.PfmCycleCounterDef = Def;
-  }
-  for (Record *Def : Records.getAllDerivedDefinitions("PfmUopsCounter")) {
-    CodeGenProcModel &PM = getProcModel(Def->getValueAsDef("SchedModel"));
-    if (PM.PfmUopsCounterDef) {
-      PrintFatalError(Def->getLoc(),
-                      "multiple uops counters for " +
-                          Def->getValueAsDef("SchedModel")->getName());
-    }
-    PM.PfmUopsCounterDef = Def;
-  }
+  const auto AddPfmCounterName = [this](const Record *PfmCounterDef) {
+    const llvm::StringRef Counter = PfmCounterDef->getValueAsString("Counter");
+    if (!Counter.empty())
+      PfmCounterNameTable.emplace(Counter, 0);
+  };
+  for (Record *Def : Records.getAllDerivedDefinitions("ProcPfmCounters")) {
+    // Check that ResourceNames are unique.
+    llvm::SmallSet<llvm::StringRef, 16> Seen;
+    for (const Record *IssueCounter :
+         Def->getValueAsListOfDefs("IssueCounters")) {
+      const llvm::StringRef ResourceName =
+          IssueCounter->getValueAsString("ResourceName");
+      if (ResourceName.empty())
+        PrintFatalError(IssueCounter->getLoc(), "invalid empty ResourceName");
+      if (!Seen.insert(ResourceName).second)
+        PrintFatalError(IssueCounter->getLoc(),
+                        "duplicate ResourceName " + ResourceName);
+      AddPfmCounterName(IssueCounter);
+    }
+    AddPfmCounterName(Def->getValueAsDef("CycleCounter"));
+    AddPfmCounterName(Def->getValueAsDef("UopsCounter"));
+  }
+  unsigned Index = 0;
+  for (auto &NameAndIndex : PfmCounterNameTable)
+    NameAndIndex.second = Index++;
 }
 
 // Collect and sort WriteRes, ReadAdvance, and ProcResources.
 void CodeGenSchedModels::collectProcResources() {
   ProcResourceDefs = Records.getAllDerivedDefinitions("ProcResourceUnits");
   ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");
 
   // Add any subtarget-specific SchedReadWrites that are directly associated
if (!Complete) {
     errs() << "\n\nIncomplete schedule models found.\n"
       << "- Consider setting 'CompleteModel = 0' while developing new models.\n"
       << "- Pseudo instructions can be marked with 'hasNoSchedulingInfo = 1'.\n"
       << "- Instructions should usually have Sched<[...]> as a superclass, "
          "you may temporarily use an empty list.\n"
       << "- Instructions related to unsupported features can be excluded with "
          "list<Predicate> UnsupportedFeatures = [HasA,..,HasY]; in the "
          "processor model.\n\n";
     PrintFatalError("Incomplete schedule model");
   }
 }
 
 // Collect itinerary class resources for each processor.
 void CodeGenSchedModels::collectItinProcResources(Record *ItinClassDef) {
   for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) {
     const CodeGenProcModel &PM = ProcModels[PIdx];
     // For all ItinRW entries.

utils/TableGen/SubtargetEmitter.cpp

void EmitStageAndOperandCycleData(raw_ostream &OS,
                                       &ProcItinLists);
   void EmitItineraries(raw_ostream &OS,
                        std::vector<std::vector<InstrItinerary>>
                          &ProcItinLists);
   unsigned EmitRegisterFileTables(const CodeGenProcModel &ProcModel,
                                   raw_ostream &OS);
   void EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
                               raw_ostream &OS);
+  void EmitPfmCounters(raw_ostream &OS);
   void EmitProcessorProp(raw_ostream &OS, const Record *R, StringRef Name,
                          char Separator);
   void EmitProcessorResourceSubUnits(const CodeGenProcModel &ProcModel,
                                      raw_ostream &OS);
   void EmitProcessorResources(const CodeGenProcModel &ProcModel,
                               raw_ostream &OS);
   Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
                              const CodeGenProcModel &ProcModel);
for (const CodeGenRegisterFile &RD : ProcModel.RegisterFiles) {
     OS << NumCostEntries << ", " << CostTblIndex << "},\n";
     CostTblIndex += NumCostEntries;
   }
   OS << "};\n";
 
   return CostTblIndex;
 }
 
-static bool EmitPfmIssueCountersTable(const CodeGenProcModel &ProcModel,
-                                      raw_ostream &OS) {
-  unsigned NumCounterDefs = 1 + ProcModel.ProcResourceDefs.size();
-  std::vector<const Record *> CounterDefs(NumCounterDefs);
-  bool HasCounters = false;
-  for (const Record *CounterDef : ProcModel.PfmIssueCounterDefs) {
-    const Record *&CD = CounterDefs[ProcModel.getProcResourceIdx(
-        CounterDef->getValueAsDef("Resource"))];
-    if (CD) {
-      PrintFatalError(CounterDef->getLoc(),
-                      "multiple issue counters for " +
-                          CounterDef->getValueAsDef("Resource")->getName());
-    }
-    CD = CounterDef;
-    HasCounters = true;
-  }
-  if (!HasCounters) {
-    return false;
-  }
-  OS << "\nstatic const char* " << ProcModel.ModelName
-     << "PfmIssueCounters[] = {\n";
-  for (unsigned i = 0; i != NumCounterDefs; ++i) {
-    const Record *CounterDef = CounterDefs[i];
-    if (CounterDef) {
-      const auto PfmCounters = CounterDef->getValueAsListOfStrings("Counters");
-      if (PfmCounters.empty())
-        PrintFatalError(CounterDef->getLoc(), "empty counter list");
-      OS << "  \"" << PfmCounters[0];
-      for (unsigned p = 1, e = PfmCounters.size(); p != e; ++p)
-        OS << ",\" \"" << PfmCounters[p];
-      OS << "\",  // #" << i << " = ";
-      OS << CounterDef->getValueAsDef("Resource")->getName() << "\n";
-    } else {
-      OS << "  nullptr, // #" << i << "\n";
-    }
-  }
-  OS << "};\n";
-  return true;
-}
-
-static void EmitPfmCounters(const CodeGenProcModel &ProcModel,
-                            const bool HasPfmIssueCounters, raw_ostream &OS) {
-  OS << "  {\n";
-  // Emit the cycle counter.
-  if (ProcModel.PfmCycleCounterDef)
-    OS << "    \"" << ProcModel.PfmCycleCounterDef->getValueAsString("Counter")
-       << "\",  // Cycle counter.\n";
-  else
-    OS << "    nullptr,  // No cycle counter.\n";
-
-  // Emit the uops counter.
-  if (ProcModel.PfmUopsCounterDef)
-    OS << "    \"" << ProcModel.PfmUopsCounterDef->getValueAsString("Counter")
-       << "\",  // Uops counter.\n";
-  else
-    OS << "    nullptr,  // No uops counter.\n";
-
-  // Emit a reference to issue counters table.
-  if (HasPfmIssueCounters)
-    OS << "    " << ProcModel.ModelName << "PfmIssueCounters\n";
-  else
-    OS << "    nullptr  // No issue counters.\n";
-  OS << "  }\n";
-}
-
 void SubtargetEmitter::EmitExtraProcessorInfo(const CodeGenProcModel &ProcModel,
                                               raw_ostream &OS) {
   // Generate a table of register file descriptors (one entry per each user
   // defined register file), and a table of register costs.
   unsigned NumCostEntries = EmitRegisterFileTables(ProcModel, OS);
 
-  // Generate a table of ProcRes counter names.
-  const bool HasPfmIssueCounters = EmitPfmIssueCountersTable(ProcModel, OS);
-
   // Now generate a table for the extra processor info.
   OS << "\nstatic const llvm::MCExtraProcessorInfo " << ProcModel.ModelName
      << "ExtraInfo = {\n  ";
 
   // Add information related to the retire control unit.
   EmitRetireControlUnitInfo(ProcModel, OS);
 
   // Add information related to the register files (i.e. where to find register
   // file descriptors and register costs).
   EmitRegisterFileInfo(ProcModel, ProcModel.RegisterFiles.size(),
                        NumCostEntries, OS);
 
-  EmitPfmCounters(ProcModel, HasPfmIssueCounters, OS);
+  OS << "};\n";
+}
+
+static void
+EmitPfmCountersInfo(const Record &Def,
+                    std::map<llvm::StringRef, unsigned> PfmCounterNameTable,
+                    llvm::StringRef Target, unsigned &IssueCountersTableOffset,
+                    raw_ostream &OS) {
+  const auto CycleCounter =
+      Def.getValueAsDef("CycleCounter")->getValueAsString("Counter");
+  const auto UopsCounter =
+      Def.getValueAsDef("UopsCounter")->getValueAsString("Counter");
+  const size_t NumIssueCounters =
+      Def.getValueAsListOfDefs("IssueCounters").size();
+
+  // This is the default, do not emit.
+  if (CycleCounter.empty() && UopsCounter.empty() && NumIssueCounters == 0)
+    return;
+
+  OS << "\nstatic const llvm::MCPfmCountersInfo " << Target << Def.getName()
+     << " = {\n";
+
+  // Cycle Counter.
+  if (CycleCounter.empty())
+    OS << "  nullptr,  // No cycle counter.\n";
+  else
+    OS << "  " << Target << "PfmCounterNames["
+       << PfmCounterNameTable[CycleCounter] << "],  // Cycle counter\n";
+
+  // Uops Counter.
+  if (UopsCounter.empty())
+    OS << "  nullptr,  // No uops counter.\n";
+  else
+    OS << "  " << Target << "PfmCounterNames["
+       << PfmCounterNameTable[UopsCounter] << "],  // Uops counter\n";
+
+  // Issue Counters
+  if (NumIssueCounters == 0)
+    OS << "  nullptr,  // No issue counters.\n  0\n";
+  else
+    OS << "  " << Target << "PfmIssueCounters + " << IssueCountersTableOffset
+       << ", " << NumIssueCounters << " // Issue counters.\n";
 
   OS << "};\n";
+  IssueCountersTableOffset += NumIssueCounters;
+}
+
+void SubtargetEmitter::EmitPfmCounters(raw_ostream &OS) {
+  // Emit the counter name table.
+  const auto &PfmCounterNameTable = SchedModels.getPfmCounterNameTable();
+  OS << "\nstatic const char* " << Target << "PfmCounterNames[] = {\n";
+  for (const auto &NameAndIndex : PfmCounterNameTable)
+    OS << "  \"" << NameAndIndex.first << "\", // " << NameAndIndex.second
+       << "\n";
+  OS << "};\n\n";
+
+  // Emit the IssueCounters table.
+  const RecVec PfmCounterDefs =
+      Records.getAllDerivedDefinitions("ProcPfmCounters");
+  OS << "static const llvm::MCPfmCountersInfo::IssueCounter " << Target
+     << "PfmIssueCounters[] = {\n";
+  for (const Record *Def : PfmCounterDefs) {
+    for (const Record *ICDef : Def->getValueAsListOfDefs("IssueCounters"))
+      OS << "  { " << Target << "PfmCounterNames["
+         << PfmCounterNameTable.find(ICDef->getValueAsString("Counter"))->second
+         << "], \"" << ICDef->getValueAsString("ResourceName") << "\"},\n";
+  }
+
+  OS << "};\n";
+
+  // Now generate the MCPfmCountersInfos.
+  unsigned IssueCountersTableOffset = 0;
+  for (const Record *Def : PfmCounterDefs)
+    EmitPfmCountersInfo(*Def, PfmCounterNameTable, Target,
+                        IssueCountersTableOffset, OS);
+
+  OS << "\n";
 }
 
 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
                                               raw_ostream &OS) {
   EmitProcessorResourceSubUnits(ProcModel, OS);
 
   OS << "\n// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}\n";
   OS << "static const llvm::MCProcResourceDesc " << ProcModel.ModelName
if (PM.hasExtraProcessorInfo())
       OS << "  &" << PM.ModelName << "ExtraInfo,\n";
     else
       OS << "  nullptr // No extra processor descriptor\n";
     OS << "};\n";
   }
 }
 
 //
-// EmitProcessorLookup - generate cpu name to itinerary lookup table.
+// EmitProcessorLookup - generate cpu name to sched model and cpu name to pfm
+//                       counters lookup tables.
 //
 void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
   // Gather and sort processor information
   std::vector<Record*> ProcessorList =
                           Records.getAllDerivedDefinitions("Processor");
   llvm::sort(ProcessorList, LessRecordFieldName());
 
-  // Begin processor table
+  // Begin processor->sched model table
   OS << "\n";
-  OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
-     << "extern const llvm::SubtargetInfoKV "
-     << Target << "ProcSchedKV[] = {\n";
-
+  OS << "// Sorted (by key) array of sched model for CPU subtype.\n"
+     << "extern const llvm::SubtargetInfoKV " << Target
+     << "ProcSchedKV[] = {\n";
   // For each processor
   for (Record *Processor : ProcessorList) {
     StringRef Name = Processor->getValueAsString("Name");
     const std::string &ProcModelName =
       SchedModels.getModelForProc(Processor).ModelName;
 
     // Emit as { "cpu", procinit },
     OS << "  { \"" << Name << "\", (const void *)&" << ProcModelName << " },\n";
   }
+  // End processor->sched model table
+  OS << "};\n";
 
-  // End processor table
+  // Begin processor->sched model table
+  OS << "\n";
+  OS << "// Sorted (by key) array of pfm counters for CPU subtype.\n"
+     << "extern const llvm::SubtargetInfoKV " << Target << "ProcPfmKV[] = {\n";
+  // For each processor
+  for (Record *Processor : ProcessorList) {
+    const Record *Def = Processor->getValueAsDef("PfmCounters");
+    const auto CycleCounter =
+        Def->getValueAsDef("CycleCounter")->getValueAsString("Counter");
+    const auto UopsCounter =
+        Def->getValueAsDef("UopsCounter")->getValueAsString("Counter");
+    const size_t NumIssueCounters =
+        Def->getValueAsListOfDefs("IssueCounters").size();
+
+    // Emit as { "cpu", procinit },
+    OS << "  { \"" << Processor->getValueAsString("Name")
+       << "\", (const void *)&";
+    if (CycleCounter.empty() && UopsCounter.empty() && NumIssueCounters == 0)
+      OS << "MCPfmCountersInfo::getDefault()";
+    else
+      OS << Target << Def->getName();
+    OS << " },\n";
+  }
+  // End processor->sched model table
   OS << "};\n";
 }
 
 //
 // EmitSchedModel - Emits all scheduling model tables, folding common patterns.
 //
 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
   OS << "#ifdef DBGFIELD\n"
      << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
      << "#endif\n"
      << "#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)\n"
      << "#define DBGFIELD(x) x,\n"
      << "#else\n"
      << "#define DBGFIELD(x)\n"
      << "#endif\n";
 
+  EmitPfmCounters(OS);
+
   if (SchedModels.hasItineraries()) {
     std::vector<std::vector<InstrItinerary>> ProcItinLists;
     // Emit the stage data
     EmitStageAndOperandCycleData(OS, ProcItinLists);
     EmitItineraries(OS, ProcItinLists);
   }
   OS << "\n// ===============================================================\n"
      << "// Data tables for the new per-operand machine model.\n";
OS << "unsigned " << ClassName
      << "\n::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI,"
      << " const TargetSchedModel *SchedModel) const {\n";
 
   // Emit the predicate prolog code.
   emitPredicateProlog(Records, OS);
 
   // Emit target predicates.
   emitSchedModelHelpersImpl(OS);
-  
   OS << "} // " << ClassName << "::resolveSchedClass\n\n";
 
   OS << "unsigned " << ClassName
      << "\n::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI,"
      << " unsigned CPUID) const {\n"
      << "  return " << Target << "_MC"
      << "::resolveVariantSchedClassImpl(SchedClass, MI, CPUID);\n"
      << "} // " << ClassName << "::resolveVariantSchedClass\n\n";
void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) {
   OS << "} // end of namespace " << Target << "_MC\n\n";
 
   OS << "struct " << Target
      << "GenMCSubtargetInfo : public MCSubtargetInfo {\n";
   OS << "  " << Target << "GenMCSubtargetInfo(const Triple &TT, \n"
      << "    StringRef CPU, StringRef FS, ArrayRef<SubtargetFeatureKV> PF,\n"
      << "    ArrayRef<SubtargetFeatureKV> PD,\n"
      << "    const SubtargetInfoKV *ProcSched,\n"
+     << "    const SubtargetInfoKV *ProcPfm,\n"
      << "    const MCWriteProcResEntry *WPR,\n"
      << "    const MCWriteLatencyEntry *WL,\n"
      << "    const MCReadAdvanceEntry *RA, const InstrStage *IS,\n"
      << "    const unsigned *OC, const unsigned *FP) :\n"
-     << "      MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched,\n"
+     << "      MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, ProcPfm,\n"
      << "                      WPR, WL, RA, IS, OC, FP) { }\n\n"
      << "  unsigned resolveVariantSchedClass(unsigned SchedClass,\n"
      << "      const MCInst *MI, unsigned CPUID) const override {\n"
      << "    return " << Target << "_MC"
      << "::resolveVariantSchedClassImpl(SchedClass, MI, CPUID); \n";
   OS << "  }\n";
   OS << "};\n";
 }
if (NumFeatures)
     OS << Target << "FeatureKV, ";
   else
     OS << "None, ";
   if (NumProcs)
     OS << Target << "SubTypeKV, ";
   else
     OS << "None, ";
   OS << '\n'; OS.indent(22);
-  OS << Target << "ProcSchedKV, "
-     << Target << "WriteProcResTable, "
-     << Target << "WriteLatencyTable, "
-     << Target << "ReadAdvanceTable, ";
+  OS << Target << "ProcSchedKV, " << Target << "ProcPfmKV, " << Target
+     << "WriteProcResTable, " << Target << "WriteLatencyTable, " << Target
+     << "ReadAdvanceTable, ";
   OS << '\n'; OS.indent(22);
   if (SchedModels.hasItineraries()) {
     OS << Target << "Stages, "
        << Target << "OperandCycles, "
        << Target << "ForwardingPaths";
   } else
     OS << "nullptr, nullptr, nullptr";
   OS << ");\n}\n\n";
#endif
   OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
   OS << "#undef GET_SUBTARGETINFO_CTOR\n\n";
 
   OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n\n";
   OS << "namespace llvm {\n";
   OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
   OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
   OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
+  OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcPfmKV[];\n";
   OS << "extern const llvm::MCWriteProcResEntry "
      << Target << "WriteProcResTable[];\n";
   OS << "extern const llvm::MCWriteLatencyEntry "
      << Target << "WriteLatencyTable[];\n";
   OS << "extern const llvm::MCReadAdvanceEntry "
      << Target << "ReadAdvanceTable[];\n";
 
   if (SchedModels.hasItineraries()) {
if (NumFeatures)
     OS << "makeArrayRef(" << Target << "FeatureKV, " << NumFeatures << "), ";
   else
     OS << "None, ";
   if (NumProcs)
     OS << "makeArrayRef(" << Target << "SubTypeKV, " << NumProcs << "), ";
   else
     OS << "None, ";
   OS << '\n'; OS.indent(24);
-  OS << Target << "ProcSchedKV, "
-     << Target << "WriteProcResTable, "
-     << Target << "WriteLatencyTable, "
-     << Target << "ReadAdvanceTable, ";
+  OS << Target << "ProcSchedKV, " << Target << "ProcPfmKV, " << Target
+     << "WriteProcResTable, " << Target << "WriteLatencyTable, " << Target
+     << "ReadAdvanceTable, ";
   OS << '\n'; OS.indent(24);
   if (SchedModels.hasItineraries()) {
     OS << Target << "Stages, "
        << Target << "OperandCycles, "
        << Target << "ForwardingPaths";
   } else
     OS << "nullptr, nullptr, nullptr";
   OS << ") {}\n\n";