X86, AArch64, ARM: Do not attach debug location to spill/reload instructions

[MatzeB]

Summary

Spill/reload instructions are artificially generated by the compiler and
have no relation to the original source code. So the best thing to do is
not attach any debug location to them (instead of just taking the next
debug location we find on following instructions).

(I stumbled upon this when working on the fast regalloc. At least to me it
felt odd that we do set a debug location on spill/reload instructions...)

[vsk]

As Matthias points out, a spill/reload can't unambiguously be associated with a specific instruction.

Note that passing an empty location means that the instruction is described by the previous .loc directive in the stream (if one is present). I think the pedantic thing to do would be to use the special "line 0" location. However, that might bloat the line table and possibly interfere with the way llvm currently identifies prologues.

I think this is the right approach. LGTM, although a regression test on the ARM side wouldn't hurt :).

[MatzeB]

In D52125#1235612, @vsk wrote:

As Matthias points out, a spill/reload can't unambiguously be associated with a specific instruction.

Note that passing an empty location means that the instruction is described by the previous .loc directive in the stream (if one is present). I think the pedantic thing to do would be to use the special "line 0" location. However, that might bloat the line table and possibly interfere with the way llvm currently identifies prologues.

What would be the difference between a "line 0" location and an empty location? They both sound like "doesn't have a corresponding location in the source" to me...

I think this is the right approach. LGTM, although a regression test on the ARM side wouldn't hurt :).

added an aarch64 test.

[vsk]

In D52125#1251473, @MatzeB wrote:

In D52125#1235612, @vsk wrote:

As Matthias points out, a spill/reload can't unambiguously be associated with a specific instruction.

Note that passing an empty location means that the instruction is described by the previous .loc directive in the stream (if one is present). I think the pedantic thing to do would be to use the special "line 0" location. However, that might bloat the line table and possibly interfere with the way llvm currently identifies prologues.

What would be the difference between a "line 0" location and an empty location? They both sound like "doesn't have a corresponding location in the source" to me...

A "line 0" location is used to describe compiler-generated instructions which nonetheless have meaningful lexical scopes and inlining data. E.g you could attach "line 0" to a conditional move instruction.

An empty location isn't a location at all, so it doesn't have a specific definition. LLVM generally handles instructions without debug locations by presuming that the "last seen" location is unchanged.

I think this is the right approach. LGTM, although a regression test on the ARM side wouldn't hurt :).

added an aarch64 test.

[morehouse]

This change is breaking some symbolization tests on the Android bot: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-android/builds/15630

Please fix or revert.

[MatzeB]

Feel free to revert for now, but are you sure it is actually this commit?

It's hard to say for sure what happenes with the earlier hwasan tests, but the later tests that failed are crashing in GlobalISel related code, which should all run before the code that I changed...

[MatzeB]

+CC dsanders

[eugenis]

It's a bug in HWASan where we symbolize the address of the previous instruction, as usual when going up the stack (call instruction is at function return address - 4), but fault address from the signal handler does not need this adjustment. The previous instruction happens to be a reload (with -O0).

I'll fix it.

I've noticed that your change increases the size of .debug_line with HWASan, -gline-tables-only and -O0 by ~50%. Perhaps this is the worst possible case, because HWASan inserts lots of short cold BBs, something like

if (unlikely(bad_address)) {x0 = addr; brk; unreachable; }

before each memory access, and at -O0 there is often a reload of addr in the cold branch.

This is what the line table looks like:
Contents of the .debug_line section:

CU: /code/llvm-project/compiler-rt/test/hwasan/TestCases/halt-on-error.cc:
File name Line number Starting address View
halt-on-error.cc 9 0
halt-on-error.cc 10 0xa8
halt-on-error.cc 11 0xb4
halt-on-error.cc 11 0xc0
halt-on-error.cc 0 0xec
halt-on-error.cc 11 0xf0
halt-on-error.cc 0 0xf4
halt-on-error.cc 11 0xfc
halt-on-error.cc 12 0x104
halt-on-error.cc 0 0x12c
halt-on-error.cc 12 0x130
halt-on-error.cc 0 0x134
halt-on-error.cc 12 0x138
halt-on-error.cc 12 0x13c
halt-on-error.cc 13 0x140
halt-on-error.cc 14 0x14c
halt-on-error.cc 0 0x174
halt-on-error.cc 14 0x178
halt-on-error.cc 0 0x17c
halt-on-error.cc 14 0x180
halt-on-error.cc 0 0x1bc
halt-on-error.cc 14 0x1c0
halt-on-error.cc 0 0x1c4
halt-on-error.cc 14 0x1c8
halt-on-error.cc 14 0x1d4
halt-on-error.cc 0 0x200
halt-on-error.cc 14 0x204
halt-on-error.cc 0 0x208
halt-on-error.cc 14 0x20c
halt-on-error.cc 14 0x210
halt-on-error.cc 0 0x248
halt-on-error.cc 14 0x24c
halt-on-error.cc 0 0x250
halt-on-error.cc 14 0x254
halt-on-error.cc 14 0x25c
halt-on-error.cc 14 0x268
halt-on-error.cc 0 0x294
halt-on-error.cc 14 0x298
halt-on-error.cc 0 0x29c
halt-on-error.cc 14 0x2a0
halt-on-error.cc 14 0x2a4
halt-on-error.cc 0 0x2dc
halt-on-error.cc 14 0x2e0
halt-on-error.cc 0 0x2e4
halt-on-error.cc 14 0x2e8
halt-on-error.cc 14 0x2f0
halt-on-error.cc 14 0x2f8
halt-on-error.cc 14 0x324

[vsk]

In D52125#1253039, @eugenis wrote:

It's a bug in HWASan where we symbolize the address of the previous instruction, as usual when going up the stack (call instruction is at function return address - 4), but fault address from the signal handler does not need this adjustment. The previous instruction happens to be a reload (with -O0).

I'll fix it.

I've noticed that your change increases the size of .debug_line with HWASan, -gline-tables-only and -O0 by ~50%. Perhaps this is the worst possible case, because HWASan inserts lots of short cold BBs, something like

if (unlikely(bad_address)) {x0 = addr; brk; unreachable; }

before each memory access, and at -O0 there is often a reload of addr in the cold branch.
[snip]

With this patch, the reload doesn't have a location. ISTM that the bug causing line table bloat is that the dwarf generator is emitting 0 locations when it shouldn't be.

[eugenis]

In case someone wants to look at debug info issue:

1.ii40 KBDownload

test case
bin/clang++ -fsanitize=hwaddress --target=aarch64-linux-android -gline-tables-only -O0 1.ii -c

[vsk]

In D52125#1253075, @eugenis wrote:

In case someone wants to look at debug info issue:

1.ii40 KBDownload

test case
bin/clang++ -fsanitize=hwaddress --target=aarch64-linux-android -gline-tables-only -O0 1.ii -c

I can reproduce the issue. I think the unexpected locations come from DwargDebug::beginInstruction:

if (!DL) {
  // We have an unspecified location, which might want to be line 0.

Apparently there's a toggle which can switch off this behavior: -mllvm -use-unknown-locations=Disable.

... and trying again with that option set, the line table bloat is gone.

By default line 0 locations are enabled if the instruction is the first inst in a block, or is after a label. That seems reasonable, but in light of this issue it might be worth revisiting.

[MatzeB]

In D52125#1253119, @vsk wrote:

In D52125#1253075, @eugenis wrote:

In case someone wants to look at debug info issue:

1.ii40 KBDownload

test case
bin/clang++ -fsanitize=hwaddress --target=aarch64-linux-android -gline-tables-only -O0 1.ii -c

I can reproduce the issue. I think the unexpected locations come from DwargDebug::beginInstruction:

if (!DL) {
  // We have an unspecified location, which might want to be line 0.

Apparently there's a toggle which can switch off this behavior: -mllvm -use-unknown-locations=Disable.

... and trying again with that option set, the line table bloat is gone.

By default line 0 locations are enabled if the instruction is the first inst in a block, or is after a label. That seems reasonable, but in light of this issue it might be worth revisiting.

Interesting. I can understand that we don't want debug locs from the previous block to flow over. I guess we could take the next debug loc we can find (in the same basic block) in a case like this.
I'll look into this before attempting to re-commit this...

[vsk]

In D52125#1253161, @MatzeB wrote:

In D52125#1253119, @vsk wrote:

In D52125#1253075, @eugenis wrote:

In case someone wants to look at debug info issue:

1.ii40 KBDownload

test case
bin/clang++ -fsanitize=hwaddress --target=aarch64-linux-android -gline-tables-only -O0 1.ii -c

I can reproduce the issue. I think the unexpected locations come from DwargDebug::beginInstruction:

if (!DL) {
  // We have an unspecified location, which might want to be line 0.

Apparently there's a toggle which can switch off this behavior: -mllvm -use-unknown-locations=Disable.

... and trying again with that option set, the line table bloat is gone.

By default line 0 locations are enabled if the instruction is the first inst in a block, or is after a label. That seems reasonable, but in light of this issue it might be worth revisiting.

Interesting. I can understand that we don't want debug locs from the previous block to flow over. I guess we could take the next debug loc we can find (in the same basic block) in a case like this.
I'll look into this before attempting to re-commit this...

Thanks! That sounds reasonable to me. As an added benefit it doesn't seem likely to break very many tests.

[eugenis]

I've fixed HWASan in r343638.

[MatzeB]

Recommitted as rL343895 now, let's hope it passes the tests this time.

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

void AArch64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 
   llvm_unreachable("unimplemented reg-to-reg copy");
 }
 
 void AArch64InstrInfo::storeRegToStackSlot(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
     bool isKill, int FI, const TargetRegisterClass *RC,
     const TargetRegisterInfo *TRI) const {
-  DebugLoc DL;
-  if (MBBI != MBB.end())
-    DL = MBBI->getDebugLoc();
   MachineFunction &MF = *MBB.getParent();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   unsigned Align = MFI.getObjectAlignment(FI);
 
   MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
   MachineMemOperand *MMO = MF.getMachineMemOperand(
       PtrInfo, MachineMemOperand::MOStore, MFI.getObjectSize(FI), Align);
   unsigned Opc = 0;
void AArch64InstrInfo::storeRegToStackSlot(
   case 16:
     if (AArch64::FPR128RegClass.hasSubClassEq(RC))
       Opc = AArch64::STRQui;
     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
       Opc = AArch64::ST1Twov1d;
       Offset = false;
     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
-      BuildMI(MBB, MBBI, DL, get(AArch64::STPXi))
+      BuildMI(MBB, MBBI, DebugLoc(), get(AArch64::STPXi))
           .addReg(TRI->getSubReg(SrcReg, AArch64::sube64),
                   getKillRegState(isKill))
           .addReg(TRI->getSubReg(SrcReg, AArch64::subo64),
                   getKillRegState(isKill))
           .addFrameIndex(FI)
           .addImm(0)
           .addMemOperand(MMO);
       return;
if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register store without NEON");
       Opc = AArch64::ST1Fourv2d;
       Offset = false;
     }
     break;
   }
   assert(Opc && "Unknown register class");
 
-  const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc))
+  const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
                                      .addReg(SrcReg, getKillRegState(isKill))
                                      .addFrameIndex(FI);
 
   if (Offset)
     MI.addImm(0);
   MI.addMemOperand(MMO);
 }
 
 void AArch64InstrInfo::loadRegFromStackSlot(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
     int FI, const TargetRegisterClass *RC,
     const TargetRegisterInfo *TRI) const {
-  DebugLoc DL;
-  if (MBBI != MBB.end())
-    DL = MBBI->getDebugLoc();
   MachineFunction &MF = *MBB.getParent();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   unsigned Align = MFI.getObjectAlignment(FI);
   MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(MF, FI);
   MachineMemOperand *MMO = MF.getMachineMemOperand(
       PtrInfo, MachineMemOperand::MOLoad, MFI.getObjectSize(FI), Align);
 
   unsigned Opc = 0;
void AArch64InstrInfo::loadRegFromStackSlot(
   case 16:
     if (AArch64::FPR128RegClass.hasSubClassEq(RC))
       Opc = AArch64::LDRQui;
     else if (AArch64::DDRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
       Opc = AArch64::LD1Twov1d;
       Offset = false;
     } else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
-      BuildMI(MBB, MBBI, DL, get(AArch64::LDPXi))
+      BuildMI(MBB, MBBI, DebugLoc(), get(AArch64::LDPXi))
           .addReg(TRI->getSubReg(DestReg, AArch64::sube64),
                   getDefRegState(true))
           .addReg(TRI->getSubReg(DestReg, AArch64::subo64),
                   getDefRegState(true))
           .addFrameIndex(FI)
           .addImm(0)
           .addMemOperand(MMO);
       return;
if (AArch64::QQQQRegClass.hasSubClassEq(RC)) {
       assert(Subtarget.hasNEON() && "Unexpected register load without NEON");
       Opc = AArch64::LD1Fourv2d;
       Offset = false;
     }
     break;
   }
   assert(Opc && "Unknown register class");
 
-  const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc))
+  const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
                                      .addReg(DestReg, getDefRegState(true))
                                      .addFrameIndex(FI);
   if (Offset)
     MI.addImm(0);
   MI.addMemOperand(MMO);
 }
 
 void llvm::emitFrameOffset(MachineBasicBlock &MBB,

llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
   return MIB.addReg(Reg, State, SubIdx);
 }
 
 void ARMBaseInstrInfo::
 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                     unsigned SrcReg, bool isKill, int FI,
                     const TargetRegisterClass *RC,
                     const TargetRegisterInfo *TRI) const {
-  DebugLoc DL;
-  if (I != MBB.end()) DL = I->getDebugLoc();
   MachineFunction &MF = *MBB.getParent();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   unsigned Align = MFI.getObjectAlignment(FI);
 
   MachineMemOperand *MMO = MF.getMachineMemOperand(
       MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
       MFI.getObjectSize(FI), Align);
 
   switch (TRI->getSpillSize(*RC)) {
     case 2:
       if (ARM::HPRRegClass.hasSubClassEq(RC)) {
-        BuildMI(MBB, I, DL, get(ARM::VSTRH))
+        BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
             .addReg(SrcReg, getKillRegState(isKill))
             .addFrameIndex(FI)
             .addImm(0)
             .addMemOperand(MMO)
             .add(predOps(ARMCC::AL));
       } else
         llvm_unreachable("Unknown reg class!");
       break;
     case 4:
       if (ARM::GPRRegClass.hasSubClassEq(RC)) {
-        BuildMI(MBB, I, DL, get(ARM::STRi12))
+        BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
             .addReg(SrcReg, getKillRegState(isKill))
             .addFrameIndex(FI)
             .addImm(0)
             .addMemOperand(MMO)
             .add(predOps(ARMCC::AL));
       } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
-        BuildMI(MBB, I, DL, get(ARM::VSTRS))
+        BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
             .addReg(SrcReg, getKillRegState(isKill))
             .addFrameIndex(FI)
             .addImm(0)
             .addMemOperand(MMO)
             .add(predOps(ARMCC::AL));
       } else
         llvm_unreachable("Unknown reg class!");
       break;
     case 8:
       if (ARM::DPRRegClass.hasSubClassEq(RC)) {
-        BuildMI(MBB, I, DL, get(ARM::VSTRD))
+        BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
             .addReg(SrcReg, getKillRegState(isKill))
             .addFrameIndex(FI)
             .addImm(0)
             .addMemOperand(MMO)
             .add(predOps(ARMCC::AL));
       } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
         if (Subtarget.hasV5TEOps()) {
-          MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
+          MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
           MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
              .add(predOps(ARMCC::AL));
         } else {
           // Fallback to STM instruction, which has existed since the dawn of
           // time.
-          MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STMIA))
+          MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
                                         .addFrameIndex(FI)
                                         .addMemOperand(MMO)
                                         .add(predOps(ARMCC::AL));
           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
         }
       } else
         llvm_unreachable("Unknown reg class!");
       break;
     case 16:
       if (ARM::DPairRegClass.hasSubClassEq(RC)) {
         // Use aligned spills if the stack can be realigned.
         if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
-          BuildMI(MBB, I, DL, get(ARM::VST1q64))
+          BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
               .addFrameIndex(FI)
               .addImm(16)
               .addReg(SrcReg, getKillRegState(isKill))
               .addMemOperand(MMO)
               .add(predOps(ARMCC::AL));
         } else {
-          BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
+          BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
               .addReg(SrcReg, getKillRegState(isKill))
               .addFrameIndex(FI)
               .addMemOperand(MMO)
               .add(predOps(ARMCC::AL));
         }
       } else
         llvm_unreachable("Unknown reg class!");
       break;
     case 24:
       if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
         // Use aligned spills if the stack can be realigned.
         if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
-          BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
+          BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
               .addFrameIndex(FI)
               .addImm(16)
               .addReg(SrcReg, getKillRegState(isKill))
               .addMemOperand(MMO)
               .add(predOps(ARMCC::AL));
         } else {
-          MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
+          MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
+                                            get(ARM::VSTMDIA))
                                         .addFrameIndex(FI)
                                         .add(predOps(ARMCC::AL))
                                         .addMemOperand(MMO);
           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
           AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
         }
       } else
         llvm_unreachable("Unknown reg class!");
       break;
     case 32:
       if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
         if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
           // FIXME: It's possible to only store part of the QQ register if the
           // spilled def has a sub-register index.
-          BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
+          BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
               .addFrameIndex(FI)
               .addImm(16)
               .addReg(SrcReg, getKillRegState(isKill))
               .addMemOperand(MMO)
               .add(predOps(ARMCC::AL));
         } else {
-          MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
+          MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
+                                            get(ARM::VSTMDIA))
                                         .addFrameIndex(FI)
                                         .add(predOps(ARMCC::AL))
                                         .addMemOperand(MMO);
           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
           MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
                 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
         }
       } else
         llvm_unreachable("Unknown reg class!");
       break;
     case 64:
       if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
-        MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
+        MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
                                       .addFrameIndex(FI)
                                       .add(predOps(ARMCC::AL))
                                       .addMemOperand(MMO);
         MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
         MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
         MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
         MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
         MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);

llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   const MachineFunction &MF = *MBB.getParent();
   assert(MF.getFrameInfo().getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) &&
          "Stack slot too small for store");
   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
   bool isAligned =
       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
       RI.canRealignStack(MF);
   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
-  DebugLoc DL = MBB.findDebugLoc(MI);
-  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
+  addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
     .addReg(SrcReg, getKillRegState(isKill));
 }
 
 void X86InstrInfo::storeRegToAddr(
     MachineFunction &MF, unsigned SrcReg, bool isKill,
     SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
     ArrayRef<MachineMemOperand *> MMOs,
     SmallVectorImpl<MachineInstr *> &NewMIs) const {
void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                         const TargetRegisterClass *RC,
                                         const TargetRegisterInfo *TRI) const {
   const MachineFunction &MF = *MBB.getParent();
   unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16);
   bool isAligned =
       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
       RI.canRealignStack(MF);
   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
-  DebugLoc DL = MBB.findDebugLoc(MI);
-  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
+  addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
 }
 
 void X86InstrInfo::loadRegFromAddr(
     MachineFunction &MF, unsigned DestReg,
     SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC,
     ArrayRef<MachineMemOperand *> MMOs,
     SmallVectorImpl<MachineInstr *> &NewMIs) const {
   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();

llvm/trunk/test/CodeGen/AArch64/spill-debuginfo.mir

+# RUN: llc -o - %s -run-pass=regallocfast | FileCheck %s
+--- |
+  target triple = "aarch64--"
+
+  !0 = !DIFile(filename: "test.ll", directory: "/")
+  !1 = distinct !DICompileUnit(file: !0, language: DW_LANG_C)
+  !2 = distinct !DISubprogram(name: "test")
+  !3 = !DILocation(line: 17, scope: !2)
+  !4 = !DILocation(line: 42, scope: !2)
+
+  define void @func() {
+    unreachable
+  }
+...
+---
+# CHECK-LABEL: name: func
+name: func
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $x0
+    ; CHECK: LDRXui killed $x0
+    ; Should find a spill here, but it should not have a debug-location.
+    ; CHECK-NOT: STRXui {{.*}}debug-location
+    ; CHECK: BLR
+    ; Should find a reload here, but it should not have a debug-location.
+    ; CHECK-NOT: LDRXui {{.*}}debug-location
+    ; CHECK: STRXui {{.*}}, killed $x0
+    %0 : gpr64 = LDRXui $x0, 0, debug-location !3
+    ; an instruction with regmask should force us to spill %0
+    BLR undef $x0, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $x0, debug-location !3
+    STRXui %0, $x0, 0, debug-location !4

llvm/trunk/test/DebugInfo/X86/fission-ranges.ll

 ; section and that the compile unit has a DW_AT_rnglists_base attribute.
 ; The table should contain at least one rangelist with at least 2 individual ranges.
 
 ; V5RNGLISTS:      .debug_info contents:
 ; V5RNGLISTS:      DW_TAG_compile_unit
 ; V5RNGLISTS-NOT:  DW_TAG
 ; V5RNGLISTS:      DW_AT_rnglists_base [DW_FORM_sec_offset]  (0x0000000c)
 ; V5RNGLISTS:      .debug_rnglists contents:
-; V5RNGLISTS-NEXT: 0x00000000: range list header: length = 0x00000014, version = 0x0005,
+; V5RNGLISTS-NEXT: 0x00000000: range list header: length = 0x00000015, version = 0x0005,
 ; V5RNGLISTS-SAME: addr_size = 0x08, seg_size = 0x00, offset_entry_count = 0x00000000
 ; V5RNGLISTS-NEXT: ranges:
 ; V5RNGLISTS-NEXT: 0x0000000c: [DW_RLE_offset_pair]:
 ; V5RNGLISTS-NEXT: 0x0000000f: [DW_RLE_offset_pair]:
 ; V5RNGLISTS:      0x{{[0-9a-f]+}}: [DW_RLE_end_of_list]
 
 ; From the code:
 

llvm/trunk/test/DebugInfo/X86/parameters.ll

 ; }
 
 ; CHECK: debug_info contents
 ; The parameter is accessed indirectly (with a zero offset) from the second
 ; register parameter. RDI is consumed by 'sret'.
 ; CHECK: DW_TAG_subprogram
 ; CHECK: DW_AT_name{{.*}} = "func"
 ; CHECK: DW_TAG_formal_parameter
-; CHECK: DW_AT_location {{.*}} (DW_OP_breg4 RSI+0, DW_OP_deref)
+; CHECK: DW_AT_location {{.*}}
+; CHECK-NEXT: DW_OP_breg4 RSI+0, DW_OP_deref
 ; CHECK-NOT: DW_TAG
 ; CHECK: DW_AT_name{{.*}} = "f"
 
 ; CHECK: DW_TAG_subprogram
 ; CHECK: DW_AT_name{{.*}} = "func2"
 ; CHECK: DW_TAG_formal_parameter
 ; CHECK: DW_AT_location{{.*}}(DW_OP_fbreg +23)
 ; CHECK: DW_TAG_formal_parameter