[LoongArch] Use empty debug location for register spill/reload

[benshi001]

Summary

Spill/reload instructions are automatically generated by the compiler
and have no relation to the original source code. So it would be better
to not attach any debug location to them. The X86/AArch64/ARM/Thumb
backends all follow this way.

[benshi001]

Please check X86/ARM 's loadRegFromStackSlot and storeRegToStackSlot, they all use empty DebugLoc() instead of MachineBasicBlock::iterator::getDebugLoc().

[jacquesguan]

I think this revision is not NFC, it does change the behavior of debug information.

[xen0n]

Looks good at first glance but would it be better to have some test coverage (if feasible)?

[benshi001]

In D148304#4267356, @xen0n wrote:

Looks good at first glance but would it be better to have some test coverage (if feasible)?

It is not easy to compose a proper test case for that, for example,

int foo;
int as(int a) {
        foo += a;
        return foo;
}

Build it with clang a.c -O0 -g --target=loongarch32, the difference is as following

[benshi001]

We can see a .loc is eliminated by my patch. It is not good to test my patch with CHECK-NOT: .loc ***. We have to commit the test in another patch and then we can see the difference. But is it worthy to do so? This is just a tiny change.

[xen0n]

In D148304#4270645, @benshi001 wrote:

We can see a .loc is eliminated by my patch. It is not good to test my patch with CHECK-NOT: .loc ***. We have to commit the test in another patch and then we can see the difference. But is it worthy to do so? This is just a tiny change.

Fine with me then, it's not one of those non-trivial changes that would benefit very much from test coverage anyway. I said "if feasible" in my original comment too ;-)

[SixWeining]

X86, AArch64 and ARM made similar change in D52125 to make hwasan test pass.

llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp

void LoongArchInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
       .addReg(SrcReg, getKillRegState(KillSrc));
 }
 
 void LoongArchInstrInfo::storeRegToStackSlot(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register SrcReg,
     bool IsKill, int FI, const TargetRegisterClass *RC,
     const TargetRegisterInfo *TRI, Register VReg) const {
-  DebugLoc DL;
-  if (I != MBB.end())
-    DL = I->getDebugLoc();
   MachineFunction *MF = MBB.getParent();
   MachineFrameInfo &MFI = MF->getFrameInfo();
 
   unsigned Opcode;
   if (LoongArch::GPRRegClass.hasSubClassEq(RC))
     Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
                  ? LoongArch::ST_W
                  : LoongArch::ST_D;
   else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
     Opcode = LoongArch::FST_S;
   else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
     Opcode = LoongArch::FST_D;
   else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
     Opcode = LoongArch::PseudoST_CFR;
   else
     llvm_unreachable("Can't store this register to stack slot");
 
   MachineMemOperand *MMO = MF->getMachineMemOperand(
       MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
       MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
 
-  BuildMI(MBB, I, DL, get(Opcode))
+  BuildMI(MBB, I, DebugLoc(), get(Opcode))
       .addReg(SrcReg, getKillRegState(IsKill))
       .addFrameIndex(FI)
       .addImm(0)
       .addMemOperand(MMO);
 }
 
 void LoongArchInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                               MachineBasicBlock::iterator I,
                                               Register DstReg, int FI,
                                               const TargetRegisterClass *RC,
                                               const TargetRegisterInfo *TRI,
                                               Register VReg) const {
-  DebugLoc DL;
-  if (I != MBB.end())
-    DL = I->getDebugLoc();
   MachineFunction *MF = MBB.getParent();
   MachineFrameInfo &MFI = MF->getFrameInfo();
 
   unsigned Opcode;
   if (LoongArch::GPRRegClass.hasSubClassEq(RC))
     Opcode = TRI->getRegSizeInBits(LoongArch::GPRRegClass) == 32
                  ? LoongArch::LD_W
                  : LoongArch::LD_D;
   else if (LoongArch::FPR32RegClass.hasSubClassEq(RC))
     Opcode = LoongArch::FLD_S;
   else if (LoongArch::FPR64RegClass.hasSubClassEq(RC))
     Opcode = LoongArch::FLD_D;
   else if (LoongArch::CFRRegClass.hasSubClassEq(RC))
     Opcode = LoongArch::PseudoLD_CFR;
   else
     llvm_unreachable("Can't load this register from stack slot");
 
   MachineMemOperand *MMO = MF->getMachineMemOperand(
       MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
       MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
 
-  BuildMI(MBB, I, DL, get(Opcode), DstReg)
+  BuildMI(MBB, I, DebugLoc(), get(Opcode), DstReg)
       .addFrameIndex(FI)
       .addImm(0)
       .addMemOperand(MMO);
 }
 
 void LoongArchInstrInfo::movImm(MachineBasicBlock &MBB,
                                 MachineBasicBlock::iterator MBBI,
                                 const DebugLoc &DL, Register DstReg,