[LiveDebugValues] Track transferring variable's value from one register to another

[NikolaPrica]

Summary

During the execution of long functions or functions that have a lot of inlined code could come to the situation where variable's value could be transferred from one register to another. Also some variables values could be moved from subreg to reg by the ABI, like on the figure 1. In that situation we have variable's value in two registers. First location could be lost at some moment but second location will probably be used at some point and we could use that location to get this variable's value. This patch adds support for tracking such second location. The transfer is recognized only if destination register is callee saved register.

renamable $s4_64 = SLL64_32 renamable $s2, implicit killed $s2_64 
...                                                                                                
%s4_64<def> = or64 %s2_64<kill>, %zero_64                                
--------------------------------------------------------------------------------
Figure 1: Transferring register values from s2 to s4 with killing s2

Since I do not have small test example I will insert here part of MachineInstruction stream that I have been working on:

BB#3: derived from LLVM BB %if.end4
Live Ins: %GP_64 %S0_64 %S1_64 %S3_64 %S4_64 %S5_64 %S7_64
Predecessors according to CFG: BB#1 BB#2
    ...
    DBG_VALUE %S1_64, %noreg, !"tid", <!606>; line no:81
    %S6_64<def> = SLL64_32 %S1, %S1_64<imp-use,kill>; dbg:singlefunction.c:141:6 <-- copy like instruction
    ...
    %A0_64<def> = OR64 %S0_64, %ZERO_64; dbg:singlefunction.c:141:6
    %A1_64<def> = OR64 %S6_64, %ZERO_64; dbg:singlefunction.c:141:6 <- tid is indeed second argument of the following function call
    JALR64Pseudo %T9_64, <regmask ... %S1_64 %S2_64 %S3_64 %S4_64 %S5_64 %S6_64 %S7_64>, ... ; dbg:singlefunction.c:141:6
      * %A2_64<def> = OR64 %S7_64, %ZERO_64; dbg:singlefunction.c:141:6
    %S1_64<def> = OR64 %V0_64, %ZERO_64; dbg:singlefunction.c:141:6
    DBG_VALUE %S6_64, %noreg, !"tid", <!606>; line no:81  <-- This DBG_VALUE is feature of this patch
    DBG_VALUE %S1_64, %noreg, !"child_oid_cur", <!606>; line no:134
    %V0<def> = LW %FP_64, 8292; mem:LD4[%cur_local_err](tbaa=!616)(dereferenceable) dbg:singlefunction.c:144:6
    DBG_VALUE %V0, %noreg, !"cur_local_err", <!606>; line no:87
    BEQ %V0, %ZERO, <BB#6>, %AT<imp-def>; dbg:singlefunction.c:144:6
      * NOP; dbg:singlefunction.c:144:6
Successors according to CFG: BB#6 BB#4

[aprantl]

That's an interesting idea, thanks! The first thought that came to my mind is: why not implement this functionality in DbgValueHistoryCalculator or DwarfDebug::buildLocationList(), or much earlier in LiveDebugVariables? I suppose that by doing it in LiveDebugValues there is a faint chance that we might be able to propagate a backup DBG_VALUE beyond basic block boundaries, but I'm not convinced that that is worth it. I we can I would prefer to keep the mandate of LiveDebugValues well-defined, i.e.: perform cross-basic-block propagation. IIUC, this patch is doing something that is strictly local, so I would feel better about it in a context that also does only local scan of one basic block, like buildLocationList().

What do you think?

[sdardis]

Some comments on the MIPS part of this patch inlined.

I believe we should extend the tablegen class Instruction to record if this instruction is a possible copy instruction, that we can just use TableGen to portions of the work.

include/llvm/CodeGen/TargetInstrInfo.h

825–826 ↗

(On Diff #136748)

Nit: spellings. spcific -> specific, extra space after from, and othere -> another.

lib/CodeGen/LiveDebugValues.cpp

450

basci -> basic.

477

Space after the '//'

478

Sentence is a bit garbled.

650

incosiste -> inconsistent.

lib/Target/Mips/MipsSEInstrInfo.cpp

184 ↗

(On Diff #136748)

Nit on the implementation here. Rather than recognising large amounts of instructions with a switch statement, instead extend the TableGen class Instruction in include/llvm/Target/Target.td to include the field, 'isPossibleCopy' like we have for isReturn, .. etc. Some other files would need to be touched as well to account for this new field.

The the generic interface can check that bit before dispatching to the target to handle cases such as MIPS' usage of OR. Other targets would probably just return true.

217–218 ↗

(On Diff #136748)

Nit: this is incorrect. On MIPS64, a value that is smaller than 32 bits will be type legalized to i32 and assigned to the GPR32 register class, so copies of those values will use OR.

Instead test that the second operand is Mips::ZERO or Mips::ZERO_64 for those two 'or' cases if they're joined together. (Most uses of Subtarget.isGP64bit() are checking the wrong thing.)

[sdardis]

lib/Target/Mips/Mips16InstrInfo.cpp

102 ↗

(On Diff #136748)

Missing Move32R16.

lib/Target/Mips/MipsSEInstrInfo.cpp

184 ↗

(On Diff #136748)

Not a copy instruction.

185 ↗

(On Diff #136748)

Not a copy instruction.

188–202 ↗

(On Diff #136748)

Missing the microMIPS versions of these instructions (except the ones are microMIPS).

203 ↗

(On Diff #136748)

Missing CFCMSA.

204 ↗

(On Diff #136748)

Missing the microMIPS versions of this and the next instruction.

215 ↗

(On Diff #136748)

Missing the microMIPS version of this instruction.

[NikolaPrica]

@sdardis @aprantl Thank you for your comments!

The first thought that came to my mind is: why not implement this functionality in DbgValueHistoryCalculator or DwarfDebug::buildLocationList(), or much earlier in LiveDebugVariables? I suppose that by doing it in LiveDebugValues there is a faint chance that we might be able to propagate a backup DBG_VALUE beyond basic block boundaries, but I'm not convinced that that is worth it.

It wouldn't work completely in DbgValueHistoryCalculator or DwarfDebug::buildLocationList() since newly added backup DBG_VALUE location would be inserted only in block where copy/move occurs. Such new DBG_VALUE could be also propagated to successive blocks as it is been done now in LiveDebugValues.

If we can I would prefer to keep the mandate of LiveDebugValues well-defined, i.e.: perform cross-basic-block propagation. IIUC, this patch is doing something that is strictly local, so I would feel better about it in a context that also does only local scan of one basic block, like buildLocationList().

I have an idea that could make this on local scan of one basic block. My original taught was to keep first location as long as it could be kept in case that backup location is some register that is clobbered by the reg mask, but if backup location could survive up to the end of basic block it could be propagated instead of original location? In that way scan would be performed only locally.

I will need some more time to look into LiveDebugVariables pass and see whether this could be done there.

[NikolaPrica]

@aprantl > I've checked LiveDebugVariables pass and there is already such functionality but it performs only in blocks where DBG_VALUE is definded but copy instructions could occur in some further block. Maybe I should try to follow debuged value register location accros multiple blocks here and see whether it is copied to some other virtual register location?

lib/Target/Mips/MipsSEInstrInfo.cpp

184 ↗

(On Diff #136748)

@sdardis > I've came across a lot of situations of using this instructions that seemed to be copy like instruction. As I followed movement from register to register and usage of such registers it looked to me that same variable is used. Is your concern that bits from 32-63 will be undefined when transferring value from 32bit reg to 64 reg or that this new 64bit value won't be used properly as it is differently represented or both? As I've seen it is used over functions parameter that is later used as another functions parameter. For example I had following situation:

DBG_VALUE %S1_64, %noreg, !"tid", <!606>; line no:81 <- "tid" has int32 type
%S6_64<def> = SLL64_32 %S1, %S1_64<imp-use,kill>; dbg:singlefunction.c:141:6
...
%A1_64<def> = OR64 %S6_64, %ZERO_64; dbg:singlefunction.c:141:6 <- tid is indeed second argument of the following function call
JALR64Pseudo %T9_64, <regmask ... %S1_64 %S2_64 %S3_64 %S4_64 %S5_64 %S6_64 %S7_64>, ... ; dbg:singlefunction.c:141:6

"tid" is defined in last instruction call as "i32 signext %tid" in function argument list. It is propagated in other function calls in same way.

If we can't consider this as copy/move like instruction, do you think that such situations should be modelled earlier in instruction selection phase?

[aprantl]

@aprantl > I've checked LiveDebugVariables pass and there is already such functionality but it performs only in blocks where DBG_VALUE is definded but copy instructions could occur in some further block. Maybe I should try to follow debuged value register location accros multiple blocks here and see whether it is copied to some other virtual register location?

What "here" are you referring to? LiveDebugVariables should be strictly doing basic-block-local analysis. LiveDebugValues should be the only pass doing cross-bb data flow analysis. If you insist that the cross-bb part is important then the cross-bb part must be done in LiveDebugValues. I don't think that you will have a lot of situations where value is in the same register on all paths to a subsequent basic block where the variable isn't also described by a fresh DBG_VALUE. Have you collected any data that shows that supporting this would be worthwhile?

[sdardis]

lib/Target/Mips/MipsSEInstrInfo.cpp

184 ↗

(On Diff #136748)

It's a sort of a move.

%S6_64<def> = SLL64_32 %S1, %S1_64<imp-use,kill>; dbg:singlefunction.c:141:6

This is a def of $s6 with the value of $s1 sign-extended from bit 31.

Instructions which define 32 bit results on MIPS64 almost always sign-extend their result to the wider register size. Although the MIPS64 backend in LLVM has 32bit registers and 64bit registers, that's an implementation detail as MIPS doesn't have sub-register addressing.

The N64 and N32 ABIs require that values smaller that i32s are promoted to i32s, and that i32s are sign-extended to i64s.

SLL64_32 is a quirk of the MIPS64 backend implementation in that it is an instruction that operates on 32 bit gprs and produces a 64bit gpr result.

So, I suppose you could consider SLL64_32 a move as such.

185 ↗

(On Diff #136748)

You can ignore this comment given my new one above.

[NikolaPrica]

What "here" are you referring to?

Oh, sorry. I meant in LiveDebugVariables.

I don't think that you will have a lot of situations where value is in the same register on all paths to a subsequent basic block where the variable isn't also described by a fresh DBG_VALUE.

Yes. I agree with you. If that would be the case then the problem would be elsewhere. I will update patch then.

Have you collected any data that shows that supporting this would be worthwhile?

I have some examples but their MIR seems to big. I've also managed to produce test case for X86 but the example seems to big. In this cases idea of tracking copies/moves of variables register locations could work on basic block level. I will attach them just as an example. Would it be fine to produce MIR from smaller example and alter it so it could cover all code?

mips32test.c2 KBDownload

mips64andx86test.c3 KBDownload

testingCommands993 BDownload

[aprantl]

In D44016#1035849, @NikolaPrica wrote:

What "here" are you referring to?

Oh, sorry. I meant in LiveDebugVariables.

Okay. LiveDebugVariables definitely should not attempt to do anything non-local. That's LiveDebugValues' job.

I don't think that you will have a lot of situations where value is in the same register on all paths to a subsequent basic block where the variable isn't also described by a fresh DBG_VALUE.

Yes. I agree with you. If that would be the case then the problem would be elsewhere. I will update patch then.

Have you collected any data that shows that supporting this would be worthwhile?

I have some examples but their MIR seems to big. I've also managed to produce test case for X86 but the example seems to big. In this cases idea of tracking copies/moves of variables register locations could work on basic block level. I will attach them just as an example.

Sorry I should have been more specific, too :-) I meant, have you collected any data that the *cross-bb propagation* would be beneficial. I totally believe that the local part is worthwhile!

Would it be fine to produce MIR from smaller example and alter it so it could cover all code?

Sure! Yes, a smaller, handcrafted test is likely easier to understand and update than a large example generated from source.

• adrian

mips32test.c2 KBDownload

mips64andx86test.c3 KBDownload

testingCommands993 BDownload

[NikolaPrica]

I've changed patch to perform locally now by restricting copy instructions recognition to ones that copy to callee saved registers.
I've also added test for mips64 that I've managed to find without making any changes to MIR. Also I've extended this functionality for recognizing some of X86 and ARM instructions (I've marked some of instructions in copyPhysReg TII method). I suppose that this could be extended even more by labeling other instructions as isMoveReg but I'm not familiar with other architectures.

[NikolaPrica]

Updated test to recognize metadata id number.

[sdardis]

Some small nits inlined, I've mostly looked at the non debug related parts. A lot of my comments are the MIPS .td parts can be summarized as: where possible, modify the underlying *_DESC or MXC1 classes where possible rather than wrapping the definition of the instruction with a 'isRegMove = 1'. There are some cases where it can't be done as the instruction description class is shared multiple other instructions which are not moves.

Can you also provide some additional tests, e.g. tracking floating point values, and integer/floating point tests for X86 and ARM?

include/llvm/MC/MCInstrDesc.h

251 ↗

(On Diff #139112)

Return true if the instruction is a register to register move.

lib/CodeGen/LiveDebugValues.cpp

546

If it is a copy instruction, return true along with @SrcReg

548

an instruction

555

Extra space between the which and we.

556

This sentence fragment is unclear.

568

if @MI is a register copy instruction that copies a previously tracked value

lib/Target/ARM/ARMInstrInfo.td

3355 ↗

(On Diff #139112)

From looking further down this .td file, it appears the coding style would put the 'isMoveReg = 1' as an additional part of the let clause for this instruction.

lib/Target/Mips/MicroMipsDSPInstrInfo.td

528 ↗

(On Diff #138969)

Modify WRDSP_MM_DESC rather than adding a '{ let isMoveReg = 1; } to the definition here.

lib/Target/Mips/MicroMipsInstrInfo.td

634–638 ↗

(On Diff #139112)

Modify the MoveFromHILOMM, MoveMM16, MovePMM16 classes rather than wrapping the instruction definitions in an isMoveReg = 1 scope.

lib/Target/Mips/Mips64InstrInfo.td

294–301 ↗

(On Diff #139112)

Modify the MoveToLOHI class instead of wrapping isMoveReg = 1 scope here.

lib/Target/Mips/MipsDSPInstrInfo.td

1167–1170 ↗

(On Diff #139112)

Modify the M(F|T)(HI|LO)_DESC classes instead.

1226–1228 ↗

(On Diff #139112)

Modify the (RD|WR)DSP_DESC classes instead.

lib/Target/Mips/MipsInstrFPU.td

478–512 ↗

(On Diff #139112)

Modify the M(F|T)C1_FT class instead.

lib/Target/Mips/MipsMSAInstrInfo.td

2886 ↗

(On Diff #139112)

Modify the CFCMSA_DESC class as well.

2940 ↗

(On Diff #139112)

Modify the CTCMSA_DESC class instead.

3292 ↗

(On Diff #139112)

Modify the MOVE_V_DESC class instead.

lib/Target/Mips/MipsSEInstrInfo.cpp

183 ↗

(On Diff #139112)

Simplify the implementation here by switching over the opcode, and in the default case, directly returning the value of TargetInstrInfo::isCopyInstr(MI).

Add a comment stating we check for the common cases of 'or', as it's MIPS' preferred move instruction for GPRs but we have to check the operands to ensure that is the case. Other move instructions for MIPS are directly identifiable.

test/DebugInfo/MIR/Mips/live-debug-value-reg-copy.mir

1 ↗

(On Diff #139112)

Can you also add a test case of floating point values?

3 ↗

(On Diff #139112)

transferning -> transferring

4 ↗

(On Diff #139112)

Missing the rest of the sentence.

[aprantl]

lib/CodeGen/LiveDebugValues.cpp

245

can you rename this to makeTransferDebugPair or perhaps make this into a constructor of TransferDebugPair?

[NikolaPrica]

I've added test case for MIPS integer/float point values and tests for tracking integer values for X86 and ARM. Because it is hard to find a small real example I produced test cases by manually altering the machine IR but I'm not quite sure about producing test case for floating points for X86 and ARM. Basically what I've done is add 'isMoveReg = 1' to the instructions that are mentioned in TargetInstrInfo::copyPhysReg. Maybe someone else who is more familiar with ARM/X86 could assist or take over if everything else is fine?

[NikolaPrica]

Ping.

[aprantl]

I'm afraid this is getting too broad in scope for me to comfortably review this. In order to make progress on this, would it be possible to split out the addition of isMoveReg to a separate patch get that reviewed by developers familiar with the backends? Once that is in, we should be able to move ahead with the debug info part quickly.

[NikolaPrica]

Sure. I will do so. Do you think that it would be better to provide 3 different patches for X86/ARM/MIPS separately or should I post it all in one?

[aprantl]

I'm not sure. I think it's important to reach consensus first that the new attribute is the right way forward. So one large patch may be better initially.

[NikolaPrica]

Splited patch in two revisions -> https://reviews.llvm.org/D45204

[NikolaPrica]

Updated patch to match TII isCopyInstr instruction.

[aprantl]

lib/CodeGen/LiveDebugValues.cpp

380

we usually spell this \p Transfers

390

please clang-format the patch

548

typo

test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir

6

below

8

Since you are only checking one variable, you could reduce the test case quite a bit by stripping out all debug info for the other variables.

21

... such as this.

[NikolaPrica]

Ping.

[NikolaPrica]

@aprantl do you have any more concerns or is this ready for commit?

[aprantl]

lib/CodeGen/LiveDebugValues.cpp

243

Just double-checking: 0 is always an invalid register number?

381

These two lines sound confusing :-)
Are we inserting or not?

382

\p OldVarID for consistency?

383

Isn't it the other way round: when NewReg is non-zero it is the new location?

570

It would be even better if this comment would explain *why* we want to recognize them.

734

You could define an enum for improved readability:

enum : bool {
  dontTransferChanges = false;
  transferChanges = true;
};

820

I *think* that this block is equivalent to:
TFI->determineCalleeSaves(MF, CalleeSavedRegs, RegScavenger());

test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir

25

Can you strip out all the unnecessary metadata? I don't think we need the !tbaa stuff or the !dbg locations on most of the instructions.

[aprantl]

Thanks, this is looking pretty good now. I just have a few more small details, mostly to make it easier to read and understand what's going on.

[NikolaPrica]

I thought that comments were submitted along with patch.

lib/CodeGen/LiveDebugValues.cpp

243

Yes. In printReg function there is :

if (!Reg)
  OS << "$noreg";

At this stage only valid physical registers should come into consideration. Also it is impossible to forward 0 from transferRegisterCopy since we have check if (!isCalleSavedReg(DestReg)) there.

820

determineCalleeSaves requires pointer as third argument. Is this solution with make_unique better?

[NikolaPrica]

Ping.

[aprantl]

lib/CodeGen/LiveDebugValues.cpp

385

Actually, it is weird to have a function called make... that doesn't return anything. Should we call it insertTransferDebugPair instead?

774–777

Ugh. This is now really confusing: We are both calling the transfer function of the data flow analysis transfer, and the action of moving a value from one place to another a transfer.

I think we should either rename Transfers to Moves or transfer... to process...

test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir

91

do you really need all these different DILocations?

[aprantl]

I think we're almost there now!

[NikolaPrica]

renamed makeTransferDebugPair -> insertTransferDebugPair
renamed transfer -> process
removed unnecessary DILocation metadata from tests

[aprantl]

Thanks!

[NikolaPrica]

Thank you for review!

lib/CodeGen/LiveDebugValues.cpp

 #include "llvm/CodeGen/MachineMemOperand.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetLowering.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
+#include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/Config/llvm-config.h"
 #include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Module.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/Casting.h"

 
 namespace {
 
 class LiveDebugValues : public MachineFunctionPass {
 private:
   const TargetRegisterInfo *TRI;
   const TargetInstrInfo *TII;
   const TargetFrameLowering *TFI;
+  BitVector CalleeSavedRegs;
   LexicalScopes LS;
 
   /// Keeps track of lexical scopes associated with a user value's source
   /// location.
   class UserValueScopes {
     DebugLoc DL;
     LexicalScopes &LS;
     SmallPtrSet<const MachineBasicBlock *, 4> LBlocks;
bool operator<(const VarLoc &Other) const {
         return Loc.Hash < Other.Loc.Hash;
       return Var < Other.Var;
     }
   };
 
   using VarLocMap = UniqueVector<VarLoc>;
   using VarLocSet = SparseBitVector<>;
   using VarLocInMBB = SmallDenseMap<const MachineBasicBlock *, VarLocSet>;
-  struct SpillDebugPair {
-    MachineInstr *SpillInst;
+  struct TransferDebugPair {
+    MachineInstr *TransferInst;
     MachineInstr *DebugInst;
   };
-  using SpillMap = SmallVector<SpillDebugPair, 4>;
+  using TransferMap = SmallVector<TransferDebugPair, 4>;
 
   /// This holds the working set of currently open ranges. For fast
   /// access, this is done both as a set of VarLocIDs, and a map of
   /// DebugVariable to recent VarLocID. Note that a DBG_VALUE ends all
   /// previous open ranges for the same variable.
   class OpenRangesSet {
     VarLocSet VarLocs;
     SmallDenseMap<DebugVariableBase, unsigned, 8> Vars;
bool empty() const {
       assert(Vars.empty() == VarLocs.empty() && "open ranges are inconsistent");
       return VarLocs.empty();
     }
   };
 
   bool isSpillInstruction(const MachineInstr &MI, MachineFunction *MF,
                           unsigned &Reg);
   int extractSpillBaseRegAndOffset(const MachineInstr &MI, unsigned &Reg);
+  void insertTransferDebugPair(MachineInstr &MI, OpenRangesSet &OpenRanges,
+                               TransferMap &Transfers, VarLocMap &VarLocIDs,
+                               unsigned OldVarID, unsigned NewReg = 0);
 
   void transferDebugValue(const MachineInstr &MI, OpenRangesSet &OpenRanges,
                           VarLocMap &VarLocIDs);
   void transferSpillInst(MachineInstr &MI, OpenRangesSet &OpenRanges,
-                         VarLocMap &VarLocIDs, SpillMap &Spills);
+                         VarLocMap &VarLocIDs, TransferMap &Transfers);
+  void transferRegisterCopy(MachineInstr &MI, OpenRangesSet &OpenRanges,
+                            VarLocMap &VarLocIDs, TransferMap &Transfers);
   void transferRegisterDef(MachineInstr &MI, OpenRangesSet &OpenRanges,
                            const VarLocMap &VarLocIDs);
   bool transferTerminatorInst(MachineInstr &MI, OpenRangesSet &OpenRanges,
                               VarLocInMBB &OutLocs, const VarLocMap &VarLocIDs);
-  bool transfer(MachineInstr &MI, OpenRangesSet &OpenRanges,
-                VarLocInMBB &OutLocs, VarLocMap &VarLocIDs, SpillMap &Spills,
-                bool transferSpills);
+  bool process(MachineInstr &MI, OpenRangesSet &OpenRanges,
+               VarLocInMBB &OutLocs, VarLocMap &VarLocIDs,
+               TransferMap &Transfers, bool transferChanges);
 
   bool join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs, VarLocInMBB &InLocs,
             const VarLocMap &VarLocIDs,
             SmallPtrSet<const MachineBasicBlock *, 16> &Visited);
 
   bool ExtendRanges(MachineFunction &MF);
 
 public:
void LiveDebugValues::transferDebugValue(const MachineInstr &MI,
   // TODO: Currently handles DBG_VALUE which has only reg as location.
   if (isDbgValueDescribedByReg(MI)) {
     VarLoc VL(MI, LS);
     unsigned ID = VarLocIDs.insert(VL);
     OpenRanges.insert(ID, VL.Var);
   }
 }
 
+/// Create new TransferDebugPair and insert it in \p Transfers. The VarLoc
+/// with \p OldVarID should be deleted form \p OpenRanges and replaced with
+/// new VarLoc. If \p NewReg is different than default zero value then the
+/// new location will be register location created by the copy like instruction,
+/// otherwise it is variable's location on the stack.
+void LiveDebugValues::insertTransferDebugPair(
+    MachineInstr &MI, OpenRangesSet &OpenRanges, TransferMap &Transfers,
+    VarLocMap &VarLocIDs, unsigned OldVarID, unsigned NewReg) {
+  const MachineInstr *DMI = &VarLocIDs[OldVarID].MI;
+  MachineFunction *MF = MI.getParent()->getParent();
+  MachineInstr *NewDMI;
+  if (NewReg) {
+    // Create a DBG_VALUE instruction to describe the Var in its new
+    // register location.
+    NewDMI = BuildMI(*MF, DMI->getDebugLoc(), DMI->getDesc(),
+                     DMI->isIndirectDebugValue(), NewReg,
+                     DMI->getDebugVariable(), DMI->getDebugExpression());
+    if (DMI->isIndirectDebugValue())
+      NewDMI->getOperand(1).setImm(DMI->getOperand(1).getImm());
+    LLVM_DEBUG(dbgs() << "Creating DBG_VALUE inst for register copy: ";
+               NewDMI->print(dbgs(), false, false, false, TII));
+  } else {
+    // Create a DBG_VALUE instruction to describe the Var in its spilled
+    // location.
+    unsigned SpillBase;
+    int SpillOffset = extractSpillBaseRegAndOffset(MI, SpillBase);
+    auto *SpillExpr = DIExpression::prepend(DMI->getDebugExpression(),
+                                            DIExpression::NoDeref, SpillOffset);
+    NewDMI = BuildMI(*MF, DMI->getDebugLoc(), DMI->getDesc(), true, SpillBase,
+                     DMI->getDebugVariable(), SpillExpr);
+    LLVM_DEBUG(dbgs() << "Creating DBG_VALUE inst for spill: ";
+               NewDMI->print(dbgs(), false, false, false, TII));
+  }
+
+  // The newly created DBG_VALUE instruction NewDMI must be inserted after
+  // MI. Keep track of the pairing.
+  TransferDebugPair MIP = {&MI, NewDMI};
+  Transfers.push_back(MIP);
+
+  // End all previous ranges of Var.
+  OpenRanges.erase(VarLocIDs[OldVarID].Var);
+
+  // Add the VarLoc to OpenRanges.
+  VarLoc VL(*NewDMI, LS);
+  unsigned LocID = VarLocIDs.insert(VL);
+  OpenRanges.insert(LocID, VL.Var);
+}
+
 /// A definition of a register may mark the end of a range.
 void LiveDebugValues::transferRegisterDef(MachineInstr &MI,
                                           OpenRangesSet &OpenRanges,
                                           const VarLocMap &VarLocIDs) {
   MachineFunction *MF = MI.getMF();
   const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
   unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
   SparseBitVector<> KillSet;
   for (const MachineOperand &MO : MI.operands()) {
     // Determine whether the operand is a register def.  Assume that call
     // instructions never clobber SP, because some backends (e.g., AArch64)
     // never list SP in the regmask.
     if (MO.isReg() && MO.isDef() && MO.getReg() &&
         TRI->isPhysicalRegister(MO.getReg()) &&
         !(MI.isCall() && MO.getReg() == SP)) {
       // Remove ranges of all aliased registers.
       for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI)
         for (unsigned ID : OpenRanges.getVarLocs())
           if (VarLocIDs[ID].isDescribedByReg() == *RAI)
             KillSet.set(ID);
     } else if (MO.isRegMask()) {
       // Remove ranges of all clobbered registers. Register masks don't usually
       // list SP as preserved.  While the debug info may be off for an
       // instruction or two around callee-cleanup calls, transferring the
       // DEBUG_VALUE across the call is still a better user experience.
       for (unsigned ID : OpenRanges.getVarLocs()) {
         unsigned Reg = VarLocIDs[ID].isDescribedByReg();
         if (Reg && Reg != SP && MO.clobbersPhysReg(Reg))
           KillSet.set(ID);
       }
     }

 bool LiveDebugValues::isSpillInstruction(const MachineInstr &MI,
                                          MachineFunction *MF, unsigned &Reg) {
   const MachineFrameInfo &FrameInfo = MF->getFrameInfo();
   int FI;
   const MachineMemOperand *MMO;
 
   // TODO: Handle multiple stores folded into one. 
   if (!MI.hasOneMemOperand())
     return false;
 
   // To identify a spill instruction, use the same criteria as in AsmPrinter.
   if (!((TII->isStoreToStackSlotPostFE(MI, FI) ||
          TII->hasStoreToStackSlot(MI, MMO, FI)) &&
         FrameInfo.isSpillSlotObjectIndex(FI)))
     return false;
 
   auto isKilledReg = [&](const MachineOperand MO, unsigned &Reg) {
     if (!MO.isReg() || !MO.isUse()) {
for (const MachineOperand &MO : MI.operands()) {
     }
   }
   // Return false if we didn't find spilled register.
   return false;
 }
 
 /// A spilled register may indicate that we have to end the current range of
 /// a variable and create a new one for the spill location.
-/// We don't want to insert any instructions in transfer(), so we just create
-/// the DBG_VALUE witout inserting it and keep track of it in @Spills.
+/// We don't want to insert any instructions in process(), so we just create
+/// the DBG_VALUE without inserting it and keep track of it in \p Transfers.
 /// It will be inserted into the BB when we're done iterating over the
 /// instructions.
 void LiveDebugValues::transferSpillInst(MachineInstr &MI,
                                         OpenRangesSet &OpenRanges,
                                         VarLocMap &VarLocIDs,
-                                        SpillMap &Spills) {
+                                        TransferMap &Transfers) {
   unsigned Reg;
   MachineFunction *MF = MI.getMF();
   if (!isSpillInstruction(MI, MF, Reg))
     return;
 
   // Check if the register is the location of a debug value.
   for (unsigned ID : OpenRanges.getVarLocs()) {
     if (VarLocIDs[ID].isDescribedByReg() == Reg) {
       LLVM_DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '('
                         << VarLocIDs[ID].Var.getVar()->getName() << ")\n");
+      insertTransferDebugPair(MI, OpenRanges, Transfers, VarLocIDs, ID);
+      return;
+    }
+  }
+}
 
-      // Create a DBG_VALUE instruction to describe the Var in its spilled
-      // location, but don't insert it yet to avoid invalidating the
-      // iterator in our caller.
-      unsigned SpillBase;
-      int SpillOffset = extractSpillBaseRegAndOffset(MI, SpillBase);
-      const MachineInstr *DMI = &VarLocIDs[ID].MI;
-      auto *SpillExpr = DIExpression::prepend(
-          DMI->getDebugExpression(), DIExpression::NoDeref, SpillOffset);
-      MachineInstr *SpDMI =
-          BuildMI(*MF, DMI->getDebugLoc(), DMI->getDesc(), true, SpillBase,
-                  DMI->getDebugVariable(), SpillExpr);
-      LLVM_DEBUG(dbgs() << "Creating DBG_VALUE inst for spill: ";
-                 SpDMI->print(dbgs(), false, TII));
+/// If \p MI is a register copy instruction, that copies a previously tracked
+/// value from one register to another register that is callee saved, we
+/// create new DBG_VALUE instruction  described with copy destination register.
+void LiveDebugValues::transferRegisterCopy(MachineInstr &MI,
+                                           OpenRangesSet &OpenRanges,
+                                           VarLocMap &VarLocIDs,
+                                           TransferMap &Transfers) {
+  const MachineOperand *SrcRegOp, *DestRegOp;
 
-      // The newly created DBG_VALUE instruction SpDMI must be inserted after
-      // MI. Keep track of the pairing.
-      SpillDebugPair MIP = {&MI, SpDMI};
-      Spills.push_back(MIP);
+  if (!TII->isCopyInstr(MI, SrcRegOp, DestRegOp) || !SrcRegOp->isKill() ||
+      !DestRegOp->isDef())
+    return;
 
-      // End all previous ranges of Var.
-      OpenRanges.erase(VarLocIDs[ID].Var);
+  auto isCalleSavedReg = [&](unsigned Reg) {
+    for (MCRegAliasIterator RAI(Reg, TRI, true); RAI.isValid(); ++RAI)
+      if (CalleeSavedRegs.test(*RAI))
+        return true;
+    return false;
+  };
 
-      // Add the VarLoc to OpenRanges.
-      VarLoc VL(*SpDMI, LS);
-      unsigned SpillLocID = VarLocIDs.insert(VL);
-      OpenRanges.insert(SpillLocID, VL.Var);
+  unsigned SrcReg = SrcRegOp->getReg();
+  unsigned DestReg = DestRegOp->getReg();
+
+  // We want to recognize instructions where destination register is callee
+  // saved register. If register that could be clobbered by the call is
+  // included, there would be a great chance that it is going to be clobbered
+  // soon. It is more likely that previous register location, which is callee
+  // saved, is going to stay unclobbered longer, even if it is killed.
+  if (!isCalleSavedReg(DestReg))
+    return;
+
+  for (unsigned ID : OpenRanges.getVarLocs()) {
+    if (VarLocIDs[ID].isDescribedByReg() == SrcReg) {
+      insertTransferDebugPair(MI, OpenRanges, Transfers, VarLocIDs, ID,
+                              DestReg);
       return;
     }
   }
 }
 
 /// Terminate all open ranges at the end of the current basic block.
 bool LiveDebugValues::transferTerminatorInst(MachineInstr &MI,
                                              OpenRangesSet &OpenRanges,
bool LiveDebugValues::transferTerminatorInst(MachineInstr &MI,
   });
   VarLocSet &VLS = OutLocs[CurMBB];
   Changed = VLS |= OpenRanges.getVarLocs();
   OpenRanges.clear();
   return Changed;
 }
 
 /// This routine creates OpenRanges and OutLocs.
-bool LiveDebugValues::transfer(MachineInstr &MI, OpenRangesSet &OpenRanges,
-                               VarLocInMBB &OutLocs, VarLocMap &VarLocIDs,
-                               SpillMap &Spills, bool transferSpills) {
+bool LiveDebugValues::process(MachineInstr &MI, OpenRangesSet &OpenRanges,
+                              TransferMap &Transfers, bool transferChanges) {
   bool Changed = false;
   transferDebugValue(MI, OpenRanges, VarLocIDs);
   transferRegisterDef(MI, OpenRanges, VarLocIDs);
-  if (transferSpills)
-    transferSpillInst(MI, OpenRanges, VarLocIDs, Spills);
+  if (transferChanges) {
+    transferRegisterCopy(MI, OpenRanges, VarLocIDs, Transfers);
+    transferSpillInst(MI, OpenRanges, VarLocIDs, Transfers);
+  }
   Changed = transferTerminatorInst(MI, OpenRanges, OutLocs, VarLocIDs);
   return Changed;
 }
 
 /// This routine joins the analysis results of all incoming edges in @MBB by
 /// inserting a new DBG_VALUE instruction at the start of the @MBB - if the same
 /// source variable in all the predecessors of @MBB reside in the same location.
 bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs,
for (auto p : MBB.predecessors()) {
     // the blocks in reverse post-order any unvisited block can
     // be considered to not remove any incoming values.
     if (!Visited.count(p))
       continue;
     auto OL = OutLocs.find(p);
     // Join is null in case of empty OutLocs from any of the pred.
     if (OL == OutLocs.end())
       return false;
 
     // Just copy over the Out locs to incoming locs for the first visited
     // predecessor, and for all other predecessors join the Out locs.
     if (!NumVisited)
       InLocsT = OL->second;
     else
       InLocsT &= OL->second;
     NumVisited++;
   }
bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs,
   VarLocSet &ILS = InLocs[&MBB];
 
   // Insert DBG_VALUE instructions, if not already inserted.
   VarLocSet Diff = InLocsT;
   Diff.intersectWithComplement(ILS);
   for (auto ID : Diff) {
     // This VarLoc is not found in InLocs i.e. it is not yet inserted. So, a
     // new range is started for the var from the mbb's beginning by inserting
-    // a new DBG_VALUE. transfer() will end this range however appropriate.
+    // a new DBG_VALUE. process() will end this range however appropriate.
     const VarLoc &DiffIt = VarLocIDs[ID];
     const MachineInstr *DMI = &DiffIt.MI;
     MachineInstr *MI =
         BuildMI(MBB, MBB.instr_begin(), DMI->getDebugLoc(), DMI->getDesc(),
                 DMI->isIndirectDebugValue(), DMI->getOperand(0).getReg(),
                 DMI->getDebugVariable(), DMI->getDebugExpression());
     if (DMI->isIndirectDebugValue())
       MI->getOperand(1).setImm(DMI->getOperand(1).getImm());
bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
   bool Changed = false;
   bool OLChanged = false;
   bool MBBJoined = false;
 
   VarLocMap VarLocIDs;      // Map VarLoc<>unique ID for use in bitvectors.
   OpenRangesSet OpenRanges; // Ranges that are open until end of bb.
   VarLocInMBB OutLocs;      // Ranges that exist beyond bb.
   VarLocInMBB InLocs;       // Ranges that are incoming after joining.
-  SpillMap Spills;          // DBG_VALUEs associated with spills.
+  TransferMap Transfers;    // DBG_VALUEs associated with spills.
 
   DenseMap<unsigned int, MachineBasicBlock *> OrderToBB;
   DenseMap<MachineBasicBlock *, unsigned int> BBToOrder;
   std::priority_queue<unsigned int, std::vector<unsigned int>,
                       std::greater<unsigned int>>
       Worklist;
   std::priority_queue<unsigned int, std::vector<unsigned int>,
                       std::greater<unsigned int>>
       Pending;
 
+  enum : bool { dontTransferChanges = false, transferChanges = true };
+
   // Initialize every mbb with OutLocs.
   // We are not looking at any spill instructions during the initial pass
   // over the BBs. The LiveDebugVariables pass has already created DBG_VALUE
   // instructions for spills of registers that are known to be user variables
   // within the BB in which the spill occurs.
   for (auto &MBB : MF)
     for (auto &MI : MBB)
-      transfer(MI, OpenRanges, OutLocs, VarLocIDs, Spills,
-               /*transferSpills=*/false);
+      process(MI, OpenRanges, OutLocs, VarLocIDs, Transfers,
+              dontTransferChanges);
 
   LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,
                               "OutLocs after initialization", dbgs()));
 
   ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
   unsigned int RPONumber = 0;
   for (auto RI = RPOT.begin(), RE = RPOT.end(); RI != RE; ++RI) {
     OrderToBB[RPONumber] = *RI;
     BBToOrder[*RI] = RPONumber;
     Worklist.push(RPONumber);
     ++RPONumber;
   }
   // This is a standard "union of predecessor outs" dataflow problem.
-  // To solve it, we perform join() and transfer() using the two worklist method
+  // To solve it, we perform join() and process() using the two worklist method
   // until the ranges converge.
   // Ranges have converged when both worklists are empty.
   SmallPtrSet<const MachineBasicBlock *, 16> Visited;
   while (!Worklist.empty() || !Pending.empty()) {
     // We track what is on the pending worklist to avoid inserting the same
     // thing twice.  We could avoid this with a custom priority queue, but this
     // is probably not worth it.
     SmallPtrSet<MachineBasicBlock *, 16> OnPending;
     LLVM_DEBUG(dbgs() << "Processing Worklist\n");
     while (!Worklist.empty()) {
       MachineBasicBlock *MBB = OrderToBB[Worklist.top()];
       Worklist.pop();
       MBBJoined = join(*MBB, OutLocs, InLocs, VarLocIDs, Visited);
       Visited.insert(MBB);
       if (MBBJoined) {
         MBBJoined = false;
         Changed = true;
         // Now that we have started to extend ranges across BBs we need to
         // examine spill instructions to see whether they spill registers that
         // correspond to user variables.
         for (auto &MI : *MBB)
-          OLChanged |= transfer(MI, OpenRanges, OutLocs, VarLocIDs, Spills,
-                                /*transferSpills=*/true);
+          OLChanged |= process(MI, OpenRanges, OutLocs, VarLocIDs, Transfers,
+                               transferChanges);
 
         // Add any DBG_VALUE instructions necessitated by spills.
-        for (auto &SP : Spills)
-          MBB->insertAfter(MachineBasicBlock::iterator(*SP.SpillInst),
-                           SP.DebugInst);
-        Spills.clear();
+        for (auto &TR : Transfers)
+          MBB->insertAfter(MachineBasicBlock::iterator(*TR.TransferInst),
+                           TR.DebugInst);
+        Transfers.clear();
 
         LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,
                                     "OutLocs after propagating", dbgs()));
         LLVM_DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs,
                                     "InLocs after propagating", dbgs()));
 
         if (OLChanged) {
           OLChanged = false;
bool LiveDebugValues::runOnMachineFunction(MachineFunction &MF) {
   // Skip functions from NoDebug compilation units.
   if (MF.getFunction().getSubprogram()->getUnit()->getEmissionKind() ==
       DICompileUnit::NoDebug)
     return false;
 
   TRI = MF.getSubtarget().getRegisterInfo();
   TII = MF.getSubtarget().getInstrInfo();
   TFI = MF.getSubtarget().getFrameLowering();
+  TFI->determineCalleeSaves(MF, CalleeSavedRegs,
+                            make_unique<RegScavenger>().get());
   LS.initialize(MF);
 
   bool Changed = ExtendRanges(MF);
   return Changed;
 }

test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir

+# RUN: llc -run-pass=livedebugvalues %s -o - | FileCheck %s
+#
+# This test tests tracking variables value transferring from one register to another.
+# This example is altered additionally in order to test transferring from one float register
+# to another. The altered instructions are labeled below.
+#
+# CHECK: ![[ARG1:.*]] = !DILocalVariable(name: "arg1"
+# CHECK: DBG_VALUE debug-use $r4, debug-use $noreg, ![[ARG1]], !DIExpression(), debug-location
+# CHECK: $r5 = MOVr killed $r4, 14, $noreg, $noreg, debug-location
+# CHECK-NEXT: DBG_VALUE debug-use $r5, debug-use $noreg, ![[ARG1]], !DIExpression(), debug-location
+--- |
+  ; ModuleID = 'live-debug-values-reg-copy.ll'
+  source_filename = "live-debug-values-reg-copy.c"
+  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+  target triple = "armv4t--"
+  
+  define dso_local arm_aapcscc i32 @foo(i32 %arg1) local_unnamed_addr !dbg !8 {
+  entry:
+    call void @llvm.dbg.value(metadata i32 %arg1, metadata !13, metadata !DIExpression()), !dbg !16
+    %cmp = icmp sgt i32 %arg1, 10, !dbg !16
+    br i1 %cmp, label %if.end, label %if.else, !dbg !16
+  
+  if.else:                                          ; preds = %entry
+    %add5 = add nsw i32 %arg1, 10, !dbg !16
+    call void @llvm.dbg.value(metadata i32 %add5, metadata !13, metadata !DIExpression()), !dbg !16
+    %call6 = tail call arm_aapcscc i32 @externFunc2(i32 %add5), !dbg !16
+    %call8 = tail call arm_aapcscc i32 @externFunc(i32 %add5), !dbg !16
+    ret i32 %call6, !dbg !16
+  
+  if.end:                                           ; preds = %entry
+    %call = tail call arm_aapcscc i32 @externFunc(i32 %arg1), !dbg !16
+    ret i32 1, !dbg !16
+  }
+  
+  declare dso_local arm_aapcscc i32 @externFunc(i32) local_unnamed_addr
+  
+  declare dso_local arm_aapcscc i32 @externFunc2(i32) local_unnamed_addr
+  
+  ; Function Attrs: nounwind readnone speculatable
+  declare void @llvm.dbg.value(metadata, metadata, metadata) #0
+  
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #1
+  
+  attributes #0 = { nounwind readnone speculatable }
+  attributes #1 = { nounwind }
+  
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!3, !4, !5, !6}
+  !llvm.ident = !{!7}
+  
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 7.0.0 ", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+  !1 = !DIFile(filename: "live-debug-values-reg-copy.c", directory: "/")
+  !2 = !{}
+  !3 = !{i32 2, !"Dwarf Version", i32 4}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = !{i32 1, !"wchar_size", i32 4}
+  !6 = !{i32 1, !"min_enum_size", i32 4}
+  !7 = !{!"clang version 7.0.0"}
+  !8 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 4, type: !9, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !12)
+  !9 = !DISubroutineType(types: !10)
+  !10 = !{!11, !11}
+  !11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+  !12 = !{!13}
+  !13 = !DILocalVariable(name: "arg1", arg: 1, scope: !8, file: !1, line: 4, type: !11)
+  !16 = !DILocation(line: 4, column: 13, scope: !8)
+
+...
+---
+name:            foo
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: false
+registers:       
+liveins:         
+  - { reg: '$r0', virtual-reg: '' }
+frameInfo:       
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       16
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      
+stack:           
+  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4, 
+      stack-id: 0, callee-saved-register: '$lr', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4, 
+      stack-id: 0, callee-saved-register: '$r11', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4, 
+      stack-id: 0, callee-saved-register: '$r5', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4, 
+      stack-id: 0, callee-saved-register: '$r4', callee-saved-restored: true, 
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:       
+body:             |
+  bb.0.entry:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+  
+    $sp = frame-setup STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r11, killed $lr
+    frame-setup CFI_INSTRUCTION def_cfa_offset 16
+    frame-setup CFI_INSTRUCTION offset $lr, -4
+    frame-setup CFI_INSTRUCTION offset $r11, -8
+    frame-setup CFI_INSTRUCTION offset $r5, -12
+    frame-setup CFI_INSTRUCTION offset $r4, -16
+    DBG_VALUE debug-use $r0, debug-use $noreg, !13, !DIExpression(), debug-location !16
+    DBG_VALUE debug-use $r0, debug-use $noreg, !13, !DIExpression(), debug-location !16
+    CMPri renamable $r0, 10, 14, $noreg, implicit-def $cpsr, debug-location !16
+    Bcc %bb.2, 13, killed $cpsr, debug-location !16
+  
+  bb.1.if.end:
+    BL @externFunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def dead $r0, debug-location !16
+    $r0 = MOVi 1, 14, $noreg, $noreg, debug-location !16
+    $sp = LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r11, def $lr, debug-location !16
+    BX_RET 14, $noreg, implicit killed $r0, debug-location !16
+  
+  bb.2.if.else:
+    renamable $r4 = ADDri killed renamable $r0, 10, 14, $noreg, $noreg, debug-location !16
+    DBG_VALUE debug-use $r4, debug-use $noreg, !13, !DIExpression(), debug-location !16
+    $r0 = MOVr $r4, 14, $noreg, $noreg, debug-location !16
+    BL @externFunc2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0, debug-location !16
+    $r5 = MOVr killed $r0, 14, $noreg, $noreg, debug-location !16
+    $r0 = MOVr $r4, 14, $noreg, $noreg, debug-location !16
+    BL @externFunc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def dead $r0, debug-location !16
+    $r0 = MOVr killed $r5, 14, $noreg, $noreg, debug-location !16
+    ; Instruction below is added in order to test moving variable's value from one register to another.
+    $r5 = MOVr killed $r4, 14, $noreg, $noreg, debug-location !16
+    $sp = LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r11, def $lr, debug-location !16
+    BX_RET 14, $noreg, implicit killed $r0, debug-location !16
+
+...

test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir

+# RUN: llc -run-pass=livedebugvalues %s -o - | FileCheck %s
+#
+# This test tests tracking variables value transferring from one register to another.
+# This example is altered additionally in order to test transferring from one float register
+# to another. The altered instructions are labeled below.
+#
+# CHECK: ![[ARG1:.*]] = !DILocalVariable(name: "arg1"
+# CHECK: ![[ARG2:.*]] = !DILocalVariable(name: "arg2"
+# CHECK: DBG_VALUE debug-use $s0_64, debug-use $noreg, ![[ARG2]], !DIExpression(), debug-location
+# CHECK: $s1_64 = OR64 killed $s0_64, $zero_64, debug-location
+# CHECK-NEXT: DBG_VALUE debug-use $s1_64, debug-use $noreg, ![[ARG2]], !DIExpression(), debug-location
+# CHECK: DBG_VALUE debug-use $f24, debug-use $noreg, ![[ARG1]], !DIExpression(), debug-location
+# CHECK: $f26 = FMOV_S killed $f24, debug-location
+# CHECK-NEXT: DBG_VALUE debug-use $f26, debug-use $noreg, ![[ARG1]], !DIExpression(), debug-location
+
+--- |
+  ; ModuleID = 'live-debug-values-reg-copy.ll'
+  source_filename = "live-debug-values-reg-copy.c"
+  target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
+  target triple = "mips64-octeon-linux"
+
+  define float @foo(float %arg1, i32 signext %arg2) local_unnamed_addr !dbg !8 {
+  entry:
+    call void @llvm.dbg.value(metadata float %arg1, metadata !14, metadata !DIExpression()), !dbg !19
+    call void @llvm.dbg.value(metadata i32 %arg2, metadata !15, metadata !DIExpression()), !dbg !19
+    %conv = fpext float %arg1 to double, !dbg !19
+    %cmp = fcmp ogt double %conv, 1.012310e+01, !dbg !19
+    br i1 %cmp, label %if.then, label %if.else, !dbg !19
+
+  if.then:                                          ; preds = %entry
+    %call = tail call float @externFunc(float %arg1), !dbg !19
+    %call5 = tail call i32 @externFunc3(i32 signext %arg2), !dbg !19
+    %conv6 = sitofp i32 %call5 to float, !dbg !19
+    %add7 = fadd float %conv6, 0x3FF522D0E0000000, !dbg !19
+    br label %if.end, !dbg !19
+
+  if.else:                                          ; preds = %entry
+    %add8 = fadd float %arg1, 1.000000e+01, !dbg !19
+    call void @llvm.dbg.value(metadata float %add8, metadata !14, metadata !DIExpression()), !dbg !19
+    %call9 = tail call float @externFunc2(float %add8), !dbg !19
+    %call10 = tail call i32 @externFunc4(i32 signext %arg2), !dbg !19
+    %conv11 = sitofp i32 %call10 to float, !dbg !19
+    %add12 = fadd float %call9, %conv11, !dbg !19
+    %call14 = tail call float @externFunc(float %add8), !dbg !19
+    br label %if.end
+
+  if.end:                                           ; preds = %if.else, %if.then
+    %local.0 = phi float [ %add7, %if.then ], [ %add12, %if.else ]
+    ret float %local.0, !dbg !19
+  }
+
+  declare float @externFunc(float) local_unnamed_addr
+
+  declare i32 @externFunc3(i32 signext) local_unnamed_addr
+
+  declare float @externFunc2(float) local_unnamed_addr
+
+  declare i32 @externFunc4(i32 signext) local_unnamed_addr
+
+  ; Function Attrs: nounwind readnone speculatable
+  declare void @llvm.dbg.value(metadata, metadata, metadata) #0
+
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #1
+
+  attributes #0 = { nounwind readnone speculatable }
+  attributes #1 = { nounwind }
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!3, !4, !5, !6}
+  !llvm.ident = !{!7}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 7.0.0 ", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+  !1 = !DIFile(filename: "live-debug-values-reg-copy.c", directory: "/")
+  !2 = !{}
+  !3 = !{i32 2, !"Dwarf Version", i32 4}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = !{i32 1, !"wchar_size", i32 4}
+  !6 = !{i32 7, !"PIC Level", i32 2}
+  !7 = !{!"clang version 7.0.0 "}
+  !8 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 6, type: !9, isLocal: false, isDefinition: true, scopeLine: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !13)
+  !9 = !DISubroutineType(types: !10)
+  !10 = !{!11, !11, !12}
+  !11 = !DIBasicType(name: "float", size: 32, encoding: DW_ATE_float)
+  !12 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+  !13 = !{!14, !15}
+  !14 = !DILocalVariable(name: "arg1", arg: 1, scope: !8, file: !1, line: 6, type: !11)
+  !15 = !DILocalVariable(name: "arg2", arg: 2, scope: !8, file: !1, line: 6, type: !12)
+  !19 = !DILocation(line: 6, column: 17, scope: !8)
+
+...
+---
+name:            foo
+alignment:       3
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: false
+registers:
+liveins:
+  - { reg: '$f12', virtual-reg: '' }
+  - { reg: '$a1_64', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       32
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8,
+      stack-id: 0, callee-saved-register: '$d25_64', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
+      stack-id: 0, callee-saved-register: '$d24_64', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 2, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8,
+      stack-id: 0, callee-saved-register: '$ra_64', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 3, name: '', type: spill-slot, offset: -32, size: 8, alignment: 8,
+      stack-id: 0, callee-saved-register: '$s0_64', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+  - id:              0
+    value:           'double 1.012310e+01'
+    alignment:       8
+    isTargetSpecific: false
+  - id:              1
+    value:           'float 1.000000e+01'
+    alignment:       4
+    isTargetSpecific: false
+  - id:              2
+    value:           float 0x3FF522D0E0000000
+    alignment:       4
+    isTargetSpecific: false
+body:             |
+  bb.0.entry:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+
+    $sp_64 = DADDiu $sp_64, -32
+    CFI_INSTRUCTION def_cfa_offset 32
+    SDC164 killed $d25_64, $sp_64, 24 :: (store 8 into %stack.0)
+    SDC164 killed $d24_64, $sp_64, 16 :: (store 8 into %stack.1)
+    SD killed $ra_64, $sp_64, 8 :: (store 8 into %stack.2)
+    SD killed $s0_64, $sp_64, 0 :: (store 8 into %stack.3)
+    CFI_INSTRUCTION offset $d26_64, -8
+    CFI_INSTRUCTION offset $d25_64, -4
+    CFI_INSTRUCTION offset $d25_64, -16
+    CFI_INSTRUCTION offset $d24_64, -12
+    CFI_INSTRUCTION offset $ra_64, -24
+    CFI_INSTRUCTION offset $s0_64, -32
+    DBG_VALUE debug-use $f12, debug-use $noreg, !14, !DIExpression(), debug-location !19
+    DBG_VALUE debug-use $a1_64, debug-use $noreg, !15, !DIExpression(), debug-location !19
+    DBG_VALUE debug-use $s0, debug-use $noreg, !15, !DIExpression(), debug-location !19
+    DBG_VALUE debug-use $s0_64, debug-use $noreg, !15, !DIExpression(), debug-location !19
+    DBG_VALUE debug-use $f12, debug-use $noreg, !14, !DIExpression(), debug-location !19
+    renamable $d0_64 = CVT_D64_S renamable $f12, debug-location !19
+    renamable $at_64 = LUi64 target-flags(mips-highest) %const.0
+    renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-higher) %const.0
+    renamable $at_64 = DSLL killed renamable $at_64, 16
+    renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-abs-hi) %const.0
+    renamable $at_64 = DSLL killed renamable $at_64, 16
+    renamable $d1_64 = LDC164 killed renamable $at_64, target-flags(mips-abs-lo) %const.0, debug-location !19 :: (load 8 from constant-pool)
+    FCMP_D64 killed renamable $d0_64, killed renamable $d1_64, 7, implicit-def $fcc0, debug-location !19
+    BC1T killed $fcc0, %bb.2, implicit-def $at, debug-location !19 {
+      $s0_64 = OR64 $a1_64, $zero_64
+    }
+
+  bb.1.if.then:
+    successors: %bb.3(0x80000000)
+
+    JAL @externFunc, csr_n64, implicit-def dead $ra, implicit $f12, implicit-def $sp, implicit-def dead $f0, debug-location !19 {
+      NOP debug-location !19
+    }
+    JAL @externFunc3, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0, debug-location !19 {
+      renamable $a0_64 = SLL64_32 renamable $s0, implicit $s0_64, debug-location !19
+    }
+    $f0 = MTC1 killed $v0, debug-location !19
+    $f0 = CVT_S_W killed $f0, debug-location !19
+    ; This instruction is inserted additionally in order to test moving from one register to another
+    $s1_64 = OR64 killed $s0_64, $zero_64, debug-location !19
+    renamable $at_64 = LUi64 target-flags(mips-highest) %const.2
+    renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-higher) %const.2
+    renamable $at_64 = DSLL killed renamable $at_64, 16
+    renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-abs-hi) %const.2
+    renamable $at_64 = DSLL killed renamable $at_64, 16
+    renamable $f1 = LWC1 killed renamable $at_64, target-flags(mips-abs-lo) %const.2, debug-location !19 :: (load 4 from constant-pool)
+    J %bb.3, implicit-def dead $at, debug-location !19 {
+      renamable $f0 = FADD_S killed renamable $f0, killed renamable $f1, debug-location !19
+    }
+
+  bb.2.if.else:
+    successors: %bb.3(0x80000000)
+
+    renamable $at_64 = LUi64 target-flags(mips-highest) %const.1
+    renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-higher) %const.1
+    renamable $at_64 = DSLL killed renamable $at_64, 16
+    renamable $at_64 = DADDiu killed renamable $at_64, target-flags(mips-abs-hi) %const.1
+    renamable $at_64 = DSLL killed renamable $at_64, 16
+    renamable $f0 = LWC1 killed renamable $at_64, target-flags(mips-abs-lo) %const.1, debug-location !19 :: (load 4 from constant-pool)
+    renamable $f24 = FADD_S killed renamable $f12, killed renamable $f0, debug-location !19
+    DBG_VALUE debug-use $f24, debug-use $noreg, !14, !DIExpression(), debug-location !19
+    JAL @externFunc2, csr_n64, implicit-def dead $ra, implicit $f12, implicit-def $sp, implicit-def $f0, debug-location !19 {
+      $f12 = FMOV_S $f24, debug-location !19
+    }
+    $f25 = FMOV_S $f0, debug-location !19
+    JAL @externFunc4, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit-def $sp, implicit-def $v0, debug-location !19 {
+      renamable $a0_64 = SLL64_32 renamable $s0, implicit killed $s0_64, debug-location !19
+    }
+    $s0 = OR $v0, $zero, debug-location !19
+    JAL @externFunc, csr_n64, implicit-def dead $ra, implicit $f12, implicit-def $sp, implicit-def dead $f0, debug-location !19 {
+      $f12 = FMOV_S $f24, debug-location !19
+    }
+    $f0 = MTC1 killed $s0, debug-location !19
+    $f0 = CVT_S_W killed $f0, debug-location !19
+    renamable $f0 = FADD_S renamable $f25, killed renamable $f0, debug-location !19
+    ; This instruction is inserted additionally in order to test moving variable's value from one float register to another.
+    $f26 = FMOV_S killed $f24, debug-location !19
+
+  bb.3.if.end:
+    $s0_64 = LD $sp_64, 0, debug-location !19 :: (load 8 from %stack.3)
+    $ra_64 = LD $sp_64, 8, debug-location !19 :: (load 8 from %stack.2)
+    $d24_64 = LDC164 $sp_64, 16, debug-location !19 :: (load 8 from %stack.1)
+    $d25_64 = LDC164 $sp_64, 24, debug-location !19 :: (load 8 from %stack.0)
+    PseudoReturn64 undef $ra_64, implicit $f0, debug-location !19 {
+      $sp_64 = DADDiu $sp_64, 32
+    }
+
+...

test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir

+# RUN: llc -run-pass=livedebugvalues %s -o - | FileCheck %s
+#
+# This test tests tracking variables value transferring from one register to another.
+# This example is altered additionally in order to test transferring from one float register
+# to another. The altered instructions are labeled below.
+#
+# CHECK: ![[ARG1:.*]] = !DILocalVariable(name: "arg1"
+# CHECK: DBG_VALUE debug-use $ebx, debug-use $noreg, ![[ARG1]], !DIExpression(), debug-location
+# CHECK: $r12d = MOV32rr killed $ebx, implicit-def $r12
+# CHECK-NEXT: DBG_VALUE debug-use $r12d, debug-use $noreg, ![[ARG1]], !DIExpression(), debug-location
+--- |
+  ; ModuleID = 'live-debug-values-reg-copy.ll'
+  source_filename = "live-debug-values-reg-copy.c"
+  target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+  target triple = "x86_64-unknown-linux-gnu"
+
+  define dso_local i32 @foo(i32 %arg1) local_unnamed_addr !dbg !7 {
+  entry:
+    %local1 = alloca i32, align 4
+    call void @llvm.dbg.value(metadata i32 %arg1, metadata !12, metadata !DIExpression()), !dbg !15
+    %0 = bitcast i32* %local1 to i8*, !dbg !15
+    call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull %0), !dbg !15
+    call void @init(i32* nonnull %local1), !dbg !15
+    %1 = load i32, i32* %local1, align 4, !dbg !15, !tbaa !20
+    %add = add nsw i32 %1, %arg1, !dbg !15
+    %call = call i32 @coeficient(i32 %add), !dbg !15
+    %cmp = icmp sgt i32 %call, 32, !dbg !15
+    br i1 %cmp, label %if.then, label %if.else, !dbg !15
+
+  if.then:                                          ; preds = %entry
+    %call1 = call i32 @externFunc(i32 %arg1), !dbg !15
+    %2 = load i32, i32* %local1, align 4, !dbg !15, !tbaa !20
+    %add2 = add nsw i32 %2, %call1, !dbg !15
+    br label %if.end, !dbg !15
+
+  if.else:                                          ; preds = %entry
+    %call3 = call i32 @externFunc2(i32 %arg1), !dbg !15
+    %3 = load i32, i32* %local1, align 4, !dbg !15, !tbaa !20
+    %add4 = add nsw i32 %3, %call3, !dbg !15
+    br label %if.end
+
+  if.end:                                           ; preds = %if.else, %if.then
+    %storemerge = phi i32 [ %add4, %if.else ], [ %add2, %if.then ]
+    %4 = bitcast i32* %local1 to i8*
+    %mul = shl nsw i32 %arg1, 2, !dbg !15
+    %add5 = add nsw i32 %storemerge, %mul, !dbg !15
+    %mul6 = mul nsw i32 %add5, %call, !dbg !15
+    call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull %4), !dbg !15
+    ret i32 %mul6, !dbg !15
+  }
+
+  ; Function Attrs: argmemonly nounwind
+  declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #0
+
+  declare dso_local void @init(i32*) local_unnamed_addr
+
+  declare dso_local i32 @coeficient(i32) local_unnamed_addr
+
+  declare dso_local i32 @externFunc(i32) local_unnamed_addr
+
+  declare dso_local i32 @externFunc2(i32) local_unnamed_addr
+
+  ; Function Attrs: argmemonly nounwind
+  declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #0
+
+  ; Function Attrs: nounwind readnone speculatable
+  declare void @llvm.dbg.value(metadata, metadata, metadata) #1
+
+  ; Function Attrs: nounwind
+  declare void @llvm.stackprotector(i8*, i8**) #2
+
+  attributes #0 = { argmemonly nounwind }
+  attributes #1 = { nounwind readnone speculatable }
+  attributes #2 = { nounwind }
+
+  !llvm.dbg.cu = !{!0}
+  !llvm.module.flags = !{!3, !4, !5}
+  !llvm.ident = !{!6}
+
+  !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "clang version 7.0.0 ", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
+  !1 = !DIFile(filename: "live-debug-values-reg-copy.c", directory: "/")
+  !2 = !{}
+  !3 = !{i32 2, !"Dwarf Version", i32 4}
+  !4 = !{i32 2, !"Debug Info Version", i32 3}
+  !5 = !{i32 1, !"wchar_size", i32 4}
+  !6 = !{!"clang version 7.0.0 "}
+  !7 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 6, type: !8, isLocal: false, isDefinition: true, scopeLine: 6, flags: DIFlagPrototyped, isOptimized: true, unit: !0, retainedNodes: !11)
+  !8 = !DISubroutineType(types: !9)
+  !9 = !{!10, !10}
+  !10 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+  !11 = !{!12}
+  !12 = !DILocalVariable(name: "arg1", arg: 1, scope: !7, file: !1, line: 6, type: !10)
+  !15 = !DILocation(line: 6, column: 13, scope: !7)
+  !20 = !{!21, !21, i64 0}
+  !21 = !{!"int", !22, i64 0}
+  !22 = !{!"omnipotent char", !23, i64 0}
+  !23 = !{!"Simple C/C++ TBAA"}
+
+...
+---
+name:            foo
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+tracksRegLiveness: true
+registers:
+liveins:
+  - { reg: '$edi', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       24
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:
+  - { id: 0, type: spill-slot, offset: -24, size: 8, alignment: 8, stack-id: 0,
+      callee-saved-register: '$rbx', callee-saved-restored: true }
+  - { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 16, stack-id: 0,
+      callee-saved-register: '$rbp', callee-saved-restored: true }
+stack:
+  - { id: 0, name: local1, type: default, offset: -28, size: 4, alignment: 4,
+      stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+constants:
+body:             |
+  bb.0.entry:
+    successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    liveins: $edi, $rbp, $rbx
+
+    frame-setup PUSH64r killed $rbp, implicit-def $rsp, implicit $rsp
+    CFI_INSTRUCTION def_cfa_offset 16
+    frame-setup PUSH64r killed $rbx, implicit-def $rsp, implicit $rsp
+    CFI_INSTRUCTION def_cfa_offset 24
+    frame-setup PUSH64r undef $rax, implicit-def $rsp, implicit $rsp
+    CFI_INSTRUCTION def_cfa_offset 32
+    CFI_INSTRUCTION offset $rbx, -24
+    CFI_INSTRUCTION offset $rbp, -16
+    DBG_VALUE debug-use $edi, debug-use $noreg, !12, !DIExpression(), debug-location !15
+    $ebx = MOV32rr $edi, implicit-def $rbx
+    DBG_VALUE debug-use $ebx, debug-use $noreg, !12, !DIExpression(), debug-location !15
+    renamable $rdi = LEA64r $rsp, 1, $noreg, 4, $noreg
+    CALL64pcrel32 @init, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit-def $rsp, implicit-def $ssp, debug-location !15
+    renamable $edi = MOV32rm $rsp, 1, $noreg, 4, $noreg :: (dereferenceable load 4 from %ir.local1, !tbaa !20)
+    renamable $edi = ADD32rr killed renamable $edi, renamable $ebx, implicit-def dead $eflags, debug-location !15
+    CALL64pcrel32 @coeficient, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !15
+    $ebp = MOV32rr $eax, debug-location !15
+    $edi = MOV32rr $ebx, debug-location !15
+    CMP32ri8 renamable $ebp, 33, implicit-def $eflags, debug-location !15
+    JL_1 %bb.2, implicit killed $eflags, debug-location !15
+
+  bb.1.if.then:
+    successors: %bb.3(0x80000000)
+    liveins: $ebp, $edi
+
+    CALL64pcrel32 @externFunc, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !15
+    JMP_1 %bb.3
+
+  bb.2.if.else:
+    successors: %bb.3(0x80000000)
+    liveins: $ebp, $edi
+
+    CALL64pcrel32 @externFunc2, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !15
+
+  bb.3.if.end:
+    liveins: $ebp, $ebx, $eax
+    ; Instruction below is added in order to test moving variable's value from one register to another.
+    $r12d = MOV32rr killed $ebx, implicit-def $r12
+    renamable $eax = KILL $eax, implicit-def $rax
+    renamable $eax = ADD32rm renamable $eax, $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, implicit killed $rax, implicit-def $rax :: (dereferenceable load 4 from %ir.local1, !tbaa !20)
+    renamable $eax = LEA64_32r killed renamable $rax, 4, killed renamable $r12, 0, $noreg, debug-location !15
+    renamable $eax = IMUL32rr killed renamable $eax, killed renamable $ebp, implicit-def dead $eflags, debug-location !15
+    $rsp = frame-destroy ADD64ri8 $rsp, 8, implicit-def dead $eflags, debug-location !15
+    $rbx = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !15
+    $rbp = frame-destroy POP64r implicit-def $rsp, implicit $rsp, debug-location !15
+    RETQ $eax, debug-location !15
+
+...