[LiveDebugValues] Track transferring variable's value from one register to another

[NikolaPrica]

Summary

During the execution of long functions or functions that have a lot of inlined code could come to the situation where variable's value could be transferred from one register to another. Also some variables values could be moved from subreg to reg by the ABI, like on the figure 1. In that situation we have variable's value in two registers. First location could be lost at some moment but second location will probably be used at some point and we could use that location to get this variable's value. This patch adds support for tracking such second location. The transfer is recognized only if destination register is callee saved register.

renamable $s4_64 = SLL64_32 renamable $s2, implicit killed $s2_64 
...                                                                                                
%s4_64<def> = or64 %s2_64<kill>, %zero_64                                
--------------------------------------------------------------------------------
Figure 1: Transferring register values from s2 to s4 with killing s2

Since I do not have small test example I will insert here part of MachineInstruction stream that I have been working on:

BB#3: derived from LLVM BB %if.end4
Live Ins: %GP_64 %S0_64 %S1_64 %S3_64 %S4_64 %S5_64 %S7_64
Predecessors according to CFG: BB#1 BB#2
    ...
    DBG_VALUE %S1_64, %noreg, !"tid", <!606>; line no:81
    %S6_64<def> = SLL64_32 %S1, %S1_64<imp-use,kill>; dbg:singlefunction.c:141:6 <-- copy like instruction
    ...
    %A0_64<def> = OR64 %S0_64, %ZERO_64; dbg:singlefunction.c:141:6
    %A1_64<def> = OR64 %S6_64, %ZERO_64; dbg:singlefunction.c:141:6 <- tid is indeed second argument of the following function call
    JALR64Pseudo %T9_64, <regmask ... %S1_64 %S2_64 %S3_64 %S4_64 %S5_64 %S6_64 %S7_64>, ... ; dbg:singlefunction.c:141:6
      * %A2_64<def> = OR64 %S7_64, %ZERO_64; dbg:singlefunction.c:141:6
    %S1_64<def> = OR64 %V0_64, %ZERO_64; dbg:singlefunction.c:141:6
    DBG_VALUE %S6_64, %noreg, !"tid", <!606>; line no:81  <-- This DBG_VALUE is feature of this patch
    DBG_VALUE %S1_64, %noreg, !"child_oid_cur", <!606>; line no:134
    %V0<def> = LW %FP_64, 8292; mem:LD4[%cur_local_err](tbaa=!616)(dereferenceable) dbg:singlefunction.c:144:6
    DBG_VALUE %V0, %noreg, !"cur_local_err", <!606>; line no:87
    BEQ %V0, %ZERO, <BB#6>, %AT<imp-def>; dbg:singlefunction.c:144:6
      * NOP; dbg:singlefunction.c:144:6
Successors according to CFG: BB#6 BB#4

[aprantl]

That's an interesting idea, thanks! The first thought that came to my mind is: why not implement this functionality in DbgValueHistoryCalculator or DwarfDebug::buildLocationList(), or much earlier in LiveDebugVariables? I suppose that by doing it in LiveDebugValues there is a faint chance that we might be able to propagate a backup DBG_VALUE beyond basic block boundaries, but I'm not convinced that that is worth it. I we can I would prefer to keep the mandate of LiveDebugValues well-defined, i.e.: perform cross-basic-block propagation. IIUC, this patch is doing something that is strictly local, so I would feel better about it in a context that also does only local scan of one basic block, like buildLocationList().

What do you think?

[sdardis]

Some comments on the MIPS part of this patch inlined.

I believe we should extend the tablegen class Instruction to record if this instruction is a possible copy instruction, that we can just use TableGen to portions of the work.

include/llvm/CodeGen/TargetInstrInfo.h

825–826

Nit: spellings. spcific -> specific, extra space after from, and othere -> another.

lib/CodeGen/LiveDebugValues.cpp

442

basci -> basic.

477

Space after the '//'

478

Sentence is a bit garbled.

658

incosiste -> inconsistent.

lib/Target/Mips/MipsSEInstrInfo.cpp

184

Nit on the implementation here. Rather than recognising large amounts of instructions with a switch statement, instead extend the TableGen class Instruction in include/llvm/Target/Target.td to include the field, 'isPossibleCopy' like we have for isReturn, .. etc. Some other files would need to be touched as well to account for this new field.

The the generic interface can check that bit before dispatching to the target to handle cases such as MIPS' usage of OR. Other targets would probably just return true.

217–218

Nit: this is incorrect. On MIPS64, a value that is smaller than 32 bits will be type legalized to i32 and assigned to the GPR32 register class, so copies of those values will use OR.

Instead test that the second operand is Mips::ZERO or Mips::ZERO_64 for those two 'or' cases if they're joined together. (Most uses of Subtarget.isGP64bit() are checking the wrong thing.)

[sdardis]

lib/Target/Mips/Mips16InstrInfo.cpp

102

Missing Move32R16.

lib/Target/Mips/MipsSEInstrInfo.cpp

184

Not a copy instruction.

185

Not a copy instruction.

188–202

Missing the microMIPS versions of these instructions (except the ones are microMIPS).

203

Missing CFCMSA.

204

Missing the microMIPS versions of this and the next instruction.

215

Missing the microMIPS version of this instruction.

[NikolaPrica]

@sdardis @aprantl Thank you for your comments!

The first thought that came to my mind is: why not implement this functionality in DbgValueHistoryCalculator or DwarfDebug::buildLocationList(), or much earlier in LiveDebugVariables? I suppose that by doing it in LiveDebugValues there is a faint chance that we might be able to propagate a backup DBG_VALUE beyond basic block boundaries, but I'm not convinced that that is worth it.

It wouldn't work completely in DbgValueHistoryCalculator or DwarfDebug::buildLocationList() since newly added backup DBG_VALUE location would be inserted only in block where copy/move occurs. Such new DBG_VALUE could be also propagated to successive blocks as it is been done now in LiveDebugValues.

If we can I would prefer to keep the mandate of LiveDebugValues well-defined, i.e.: perform cross-basic-block propagation. IIUC, this patch is doing something that is strictly local, so I would feel better about it in a context that also does only local scan of one basic block, like buildLocationList().

I have an idea that could make this on local scan of one basic block. My original taught was to keep first location as long as it could be kept in case that backup location is some register that is clobbered by the reg mask, but if backup location could survive up to the end of basic block it could be propagated instead of original location? In that way scan would be performed only locally.

I will need some more time to look into LiveDebugVariables pass and see whether this could be done there.

[NikolaPrica]

@aprantl > I've checked LiveDebugVariables pass and there is already such functionality but it performs only in blocks where DBG_VALUE is definded but copy instructions could occur in some further block. Maybe I should try to follow debuged value register location accros multiple blocks here and see whether it is copied to some other virtual register location?

lib/Target/Mips/MipsSEInstrInfo.cpp

184

@sdardis > I've came across a lot of situations of using this instructions that seemed to be copy like instruction. As I followed movement from register to register and usage of such registers it looked to me that same variable is used. Is your concern that bits from 32-63 will be undefined when transferring value from 32bit reg to 64 reg or that this new 64bit value won't be used properly as it is differently represented or both? As I've seen it is used over functions parameter that is later used as another functions parameter. For example I had following situation:

DBG_VALUE %S1_64, %noreg, !"tid", <!606>; line no:81 <- "tid" has int32 type
%S6_64<def> = SLL64_32 %S1, %S1_64<imp-use,kill>; dbg:singlefunction.c:141:6
...
%A1_64<def> = OR64 %S6_64, %ZERO_64; dbg:singlefunction.c:141:6 <- tid is indeed second argument of the following function call
JALR64Pseudo %T9_64, <regmask ... %S1_64 %S2_64 %S3_64 %S4_64 %S5_64 %S6_64 %S7_64>, ... ; dbg:singlefunction.c:141:6

"tid" is defined in last instruction call as "i32 signext %tid" in function argument list. It is propagated in other function calls in same way.

If we can't consider this as copy/move like instruction, do you think that such situations should be modelled earlier in instruction selection phase?

[aprantl]

@aprantl > I've checked LiveDebugVariables pass and there is already such functionality but it performs only in blocks where DBG_VALUE is definded but copy instructions could occur in some further block. Maybe I should try to follow debuged value register location accros multiple blocks here and see whether it is copied to some other virtual register location?

What "here" are you referring to? LiveDebugVariables should be strictly doing basic-block-local analysis. LiveDebugValues should be the only pass doing cross-bb data flow analysis. If you insist that the cross-bb part is important then the cross-bb part must be done in LiveDebugValues. I don't think that you will have a lot of situations where value is in the same register on all paths to a subsequent basic block where the variable isn't also described by a fresh DBG_VALUE. Have you collected any data that shows that supporting this would be worthwhile?

[sdardis]

lib/Target/Mips/MipsSEInstrInfo.cpp

184

It's a sort of a move.

%S6_64<def> = SLL64_32 %S1, %S1_64<imp-use,kill>; dbg:singlefunction.c:141:6

This is a def of $s6 with the value of $s1 sign-extended from bit 31.

Instructions which define 32 bit results on MIPS64 almost always sign-extend their result to the wider register size. Although the MIPS64 backend in LLVM has 32bit registers and 64bit registers, that's an implementation detail as MIPS doesn't have sub-register addressing.

The N64 and N32 ABIs require that values smaller that i32s are promoted to i32s, and that i32s are sign-extended to i64s.

SLL64_32 is a quirk of the MIPS64 backend implementation in that it is an instruction that operates on 32 bit gprs and produces a 64bit gpr result.

So, I suppose you could consider SLL64_32 a move as such.

185

You can ignore this comment given my new one above.

[NikolaPrica]

What "here" are you referring to?

Oh, sorry. I meant in LiveDebugVariables.

I don't think that you will have a lot of situations where value is in the same register on all paths to a subsequent basic block where the variable isn't also described by a fresh DBG_VALUE.

Yes. I agree with you. If that would be the case then the problem would be elsewhere. I will update patch then.

Have you collected any data that shows that supporting this would be worthwhile?

I have some examples but their MIR seems to big. I've also managed to produce test case for X86 but the example seems to big. In this cases idea of tracking copies/moves of variables register locations could work on basic block level. I will attach them just as an example. Would it be fine to produce MIR from smaller example and alter it so it could cover all code?

mips32test.c2 KBDownload

mips64andx86test.c3 KBDownload

testingCommands993 BDownload

[aprantl]

In D44016#1035849, @NikolaPrica wrote:

What "here" are you referring to?

Oh, sorry. I meant in LiveDebugVariables.

Okay. LiveDebugVariables definitely should not attempt to do anything non-local. That's LiveDebugValues' job.

I don't think that you will have a lot of situations where value is in the same register on all paths to a subsequent basic block where the variable isn't also described by a fresh DBG_VALUE.

Yes. I agree with you. If that would be the case then the problem would be elsewhere. I will update patch then.

Have you collected any data that shows that supporting this would be worthwhile?

I have some examples but their MIR seems to big. I've also managed to produce test case for X86 but the example seems to big. In this cases idea of tracking copies/moves of variables register locations could work on basic block level. I will attach them just as an example.

Sorry I should have been more specific, too :-) I meant, have you collected any data that the *cross-bb propagation* would be beneficial. I totally believe that the local part is worthwhile!

Would it be fine to produce MIR from smaller example and alter it so it could cover all code?

Sure! Yes, a smaller, handcrafted test is likely easier to understand and update than a large example generated from source.

• adrian

mips32test.c2 KBDownload

mips64andx86test.c3 KBDownload

testingCommands993 BDownload

[NikolaPrica]

I've changed patch to perform locally now by restricting copy instructions recognition to ones that copy to callee saved registers.
I've also added test for mips64 that I've managed to find without making any changes to MIR. Also I've extended this functionality for recognizing some of X86 and ARM instructions (I've marked some of instructions in copyPhysReg TII method). I suppose that this could be extended even more by labeling other instructions as isMoveReg but I'm not familiar with other architectures.

[NikolaPrica]

Updated test to recognize metadata id number.

[sdardis]

Some small nits inlined, I've mostly looked at the non debug related parts. A lot of my comments are the MIPS .td parts can be summarized as: where possible, modify the underlying *_DESC or MXC1 classes where possible rather than wrapping the definition of the instruction with a 'isRegMove = 1'. There are some cases where it can't be done as the instruction description class is shared multiple other instructions which are not moves.

Can you also provide some additional tests, e.g. tracking floating point values, and integer/floating point tests for X86 and ARM?

include/llvm/MC/MCInstrDesc.h

251 ↗

(On Diff #139112)

Return true if the instruction is a register to register move.

lib/CodeGen/LiveDebugValues.cpp

569

If it is a copy instruction, return true along with @SrcReg

571

an instruction

597

Extra space between the which and we.

598

This sentence fragment is unclear.

610

if @MI is a register copy instruction that copies a previously tracked value

lib/Target/ARM/ARMInstrInfo.td

3355 ↗

(On Diff #139112)

From looking further down this .td file, it appears the coding style would put the 'isMoveReg = 1' as an additional part of the let clause for this instruction.

lib/Target/Mips/MicroMipsDSPInstrInfo.td

528 ↗

(On Diff #138969)

Modify WRDSP_MM_DESC rather than adding a '{ let isMoveReg = 1; } to the definition here.

lib/Target/Mips/MicroMipsInstrInfo.td

634–638 ↗

(On Diff #139112)

Modify the MoveFromHILOMM, MoveMM16, MovePMM16 classes rather than wrapping the instruction definitions in an isMoveReg = 1 scope.

lib/Target/Mips/Mips64InstrInfo.td

294–301 ↗

(On Diff #139112)

Modify the MoveToLOHI class instead of wrapping isMoveReg = 1 scope here.

lib/Target/Mips/MipsDSPInstrInfo.td

1167–1170 ↗

(On Diff #139112)

Modify the M(F|T)(HI|LO)_DESC classes instead.

1226–1228 ↗

(On Diff #139112)

Modify the (RD|WR)DSP_DESC classes instead.

lib/Target/Mips/MipsInstrFPU.td

478–512 ↗

(On Diff #139112)

Modify the M(F|T)C1_FT class instead.

lib/Target/Mips/MipsMSAInstrInfo.td

2886 ↗

(On Diff #139112)

Modify the CFCMSA_DESC class as well.

2940 ↗

(On Diff #139112)

Modify the CTCMSA_DESC class instead.

3292 ↗

(On Diff #139112)

Modify the MOVE_V_DESC class instead.

lib/Target/Mips/MipsSEInstrInfo.cpp

183

Simplify the implementation here by switching over the opcode, and in the default case, directly returning the value of TargetInstrInfo::isCopyInstr(MI).

Add a comment stating we check for the common cases of 'or', as it's MIPS' preferred move instruction for GPRs but we have to check the operands to ensure that is the case. Other move instructions for MIPS are directly identifiable.

test/DebugInfo/MIR/Mips/live-debug-value-reg-copy.mir

1 ↗

(On Diff #139112)

Can you also add a test case of floating point values?

3 ↗

(On Diff #139112)

transferning -> transferring

4 ↗

(On Diff #139112)

Missing the rest of the sentence.

[aprantl]

lib/CodeGen/LiveDebugValues.cpp

267

can you rename this to makeTransferDebugPair or perhaps make this into a constructor of TransferDebugPair?

[NikolaPrica]

I've added test case for MIPS integer/float point values and tests for tracking integer values for X86 and ARM. Because it is hard to find a small real example I produced test cases by manually altering the machine IR but I'm not quite sure about producing test case for floating points for X86 and ARM. Basically what I've done is add 'isMoveReg = 1' to the instructions that are mentioned in TargetInstrInfo::copyPhysReg. Maybe someone else who is more familiar with ARM/X86 could assist or take over if everything else is fine?

[NikolaPrica]

Ping.

[aprantl]

I'm afraid this is getting too broad in scope for me to comfortably review this. In order to make progress on this, would it be possible to split out the addition of isMoveReg to a separate patch get that reviewed by developers familiar with the backends? Once that is in, we should be able to move ahead with the debug info part quickly.

[NikolaPrica]

Sure. I will do so. Do you think that it would be better to provide 3 different patches for X86/ARM/MIPS separately or should I post it all in one?

[aprantl]

I'm not sure. I think it's important to reach consensus first that the new attribute is the right way forward. So one large patch may be better initially.

[NikolaPrica]

Splited patch in two revisions -> https://reviews.llvm.org/D45204

[NikolaPrica]

Updated patch to match TII isCopyInstr instruction.

[aprantl]

lib/CodeGen/LiveDebugValues.cpp

417

we usually spell this \p Transfers

427

please clang-format the patch

569

typo

test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir

5 ↗

(On Diff #150358)

below

7 ↗

(On Diff #150358)

Since you are only checking one variable, you could reduce the test case quite a bit by stripping out all debug info for the other variables.

20 ↗

(On Diff #150358)

... such as this.

[NikolaPrica]

Ping.

[NikolaPrica]

@aprantl do you have any more concerns or is this ready for commit?

[aprantl]

lib/CodeGen/LiveDebugValues.cpp

268

Just double-checking: 0 is always an invalid register number?

418

These two lines sound confusing :-)
Are we inserting or not?

419

\p OldVarID for consistency?

420

Isn't it the other way round: when NewReg is non-zero it is the new location?

612

It would be even better if this comment would explain *why* we want to recognize them.

824

You could define an enum for improved readability:

enum : bool {
  dontTransferChanges = false;
  transferChanges = true;
};

911

I *think* that this block is equivalent to:
TFI->determineCalleeSaves(MF, CalleeSavedRegs, RegScavenger());

test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir

24 ↗

(On Diff #150483)

Can you strip out all the unnecessary metadata? I don't think we need the !tbaa stuff or the !dbg locations on most of the instructions.

[aprantl]

Thanks, this is looking pretty good now. I just have a few more small details, mostly to make it easier to read and understand what's going on.

[NikolaPrica]

I thought that comments were submitted along with patch.

lib/CodeGen/LiveDebugValues.cpp

268

Yes. In printReg function there is :

if (!Reg)
  OS << "$noreg";

At this stage only valid physical registers should come into consideration. Also it is impossible to forward 0 from transferRegisterCopy since we have check if (!isCalleSavedReg(DestReg)) there.

911

determineCalleeSaves requires pointer as third argument. Is this solution with make_unique better?

[NikolaPrica]

Ping.

[aprantl]

lib/CodeGen/LiveDebugValues.cpp

422

Actually, it is weird to have a function called make... that doesn't return anything. Should we call it insertTransferDebugPair instead?

865–868

Ugh. This is now really confusing: We are both calling the transfer function of the data flow analysis transfer, and the action of moving a value from one place to another a transfer.

I think we should either rename Transfers to Moves or transfer... to process...

test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir

90 ↗

(On Diff #152309)

do you really need all these different DILocations?

[aprantl]

I think we're almost there now!

[NikolaPrica]

renamed makeTransferDebugPair -> insertTransferDebugPair
renamed transfer -> process
removed unnecessary DILocation metadata from tests

[aprantl]

Thanks!

[NikolaPrica]

Thank you for review!

include/llvm/CodeGen/TargetInstrInfo.h

public:
   /// large registers. See for example the ARM target.
   virtual void copyPhysReg(MachineBasicBlock &MBB,
                            MachineBasicBlock::iterator MI, const DebugLoc &DL,
                            unsigned DestReg, unsigned SrcReg,
                            bool KillSrc) const {
     llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!");
   }
 
+  /// If the spcific machine instruction is a instruction that moves/copies
+  /// value from  one register to othere register return true.
+  virtual bool isCopyInstruction(MachineInstr &MI) const { return false; }
+
   /// Store the specified register of the given register class to the specified
   /// stack frame index. The store instruction is to be added to the given
   /// machine basic block before the specified machine instruction. If isKill
   /// is true, the register operand is the last use and must be marked kill.
   virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    unsigned SrcReg, bool isKill, int FrameIndex,
                                    const TargetRegisterClass *RC,

lib/CodeGen/LiveDebugValues.cpp

struct DebugVariable : public DebugVariableBase {
     }
   };
 
   /// A pair of debug variable and value location.
   struct VarLoc {
     const DebugVariable Var;
     const MachineInstr &MI; ///< Only used for cloning a new DBG_VALUE.
     mutable UserValueScopes UVS;
-    enum { InvalidKind = 0, RegisterKind } Kind = InvalidKind;
+    mutable enum { InvalidKind = 0, RegisterKind, BackupKind }
+            Kind = InvalidKind;
 
     /// The value location. Stored separately to avoid repeatedly
     /// extracting it from MI.
     union {
       uint64_t RegNo;
       uint64_t Hash;
     } Loc;
 
     VarLoc(const MachineInstr &MI, LexicalScopes &LS)
         : Var(MI.getDebugVariable(), MI.getDebugLoc()->getInlinedAt()), MI(MI),
           UVS(MI.getDebugLoc(), LS) {
       static_assert((sizeof(Loc) == sizeof(uint64_t)),
                     "hash does not cover all members of Loc");
       assert(MI.isDebugValue() && "not a DBG_VALUE");
       assert(MI.getNumOperands() == 4 && "malformed DBG_VALUE");
       if (int RegNo = isDbgValueDescribedByReg(MI)) {
         Kind = RegisterKind;
         Loc.RegNo = RegNo;
       }
     }
 
     /// If this variable is described by a register, return it,
     /// otherwise return 0.
     unsigned isDescribedByReg() const {
-      if (Kind == RegisterKind)
+      if (Kind == RegisterKind || Kind == BackupKind)
         return Loc.RegNo;
       return 0;
     }
 
+    bool isBackupKind() const { return Kind == BackupKind; }
+
+    void setRegisterKind() const { Kind = RegisterKind; }
+
+    void setBackupKind() { Kind = BackupKind; }
+
     /// Determine whether the lexical scope of this value's debug location
     /// dominates MBB.
     bool dominates(MachineBasicBlock &MBB) const { return UVS.dominates(&MBB); }
 
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
     LLVM_DUMP_METHOD void dump() const { MI.dump(); }
 #endif
 
     bool operator==(const VarLoc &Other) const {
       return Var == Other.Var && Loc.Hash == Other.Loc.Hash;
     }
 
     /// This operator guarantees that VarLocs are sorted by Variable first.
     bool operator<(const VarLoc &Other) const {
-      if (Var == Other.Var)
+      if (Var == Other.Var) {
+        if (Kind == Other.Kind)
           return Loc.Hash < Other.Loc.Hash;
+        return Kind < Other.Kind;
+      }
       return Var < Other.Var;
     }
   };
 
   using VarLocMap = UniqueVector<VarLoc>;
+  using RegBackupMap = SmallDenseMap<unsigned, unsigned>;
   using VarLocSet = SparseBitVector<>;
   using VarLocInMBB = SmallDenseMap<const MachineBasicBlock *, VarLocSet>;
-  struct SpillDebugPair {
-    MachineInstr *SpillInst;
+  struct TransferDebugPair {
+    MachineInstr *TransferInst;
     MachineInstr *DebugInst;
   };
-  using SpillMap = SmallVector<SpillDebugPair, 4>;
+  using TransferMap = SmallVector<TransferDebugPair, 4>;
 
   /// This holds the working set of currently open ranges. For fast
   /// access, this is done both as a set of VarLocIDs, and a map of
   /// DebugVariable to recent VarLocID. Note that a DBG_VALUE ends all
   /// previous open ranges for the same variable.
   class OpenRangesSet {
     VarLocSet VarLocs;
     SmallDenseMap<DebugVariableBase, unsigned, 8> Vars;
+    SmallDenseMap<DebugVariableBase, unsigned, 8> BackupVars;
 
   public:
     const VarLocSet &getVarLocs() const { return VarLocs; }
 
     /// Terminate all open ranges for Var by removing it from the set.
-    void erase(DebugVariable Var) {
-      auto It = Vars.find(Var);
-      if (It != Vars.end()) {
+    void erase(const VarLoc &VL) {
+      auto *EraseFrom = VL.isBackupKind() ? &BackupVars : &Vars;
+      auto It = EraseFrom->find(VL.Var);
+      if (It != EraseFrom->end()) {
         unsigned ID = It->second;
         VarLocs.reset(ID);
-        Vars.erase(It);
+        EraseFrom->erase(It);
       }
     }
 
     /// Terminate all open ranges listed in \c KillSet by removing
     /// them from the set.
     void erase(const VarLocSet &KillSet, const VarLocMap &VarLocIDs) {
       VarLocs.intersectWithComplement(KillSet);
-      for (unsigned ID : KillSet)
-        Vars.erase(VarLocIDs[ID].Var);
+      for (unsigned ID : KillSet) {
+        const VarLoc *VL = &VarLocIDs[ID];
+        auto *EraseFrom = VL->isBackupKind() ? &BackupVars : &Vars;
+        EraseFrom->erase(VL->Var);
+      }
     }
 
     /// Insert a new range into the set.
-    void insert(unsigned VarLocID, DebugVariableBase Var) {
+    void insert(unsigned VarLocID,const VarLoc &VL) {
+      auto *InsertInto = VL.isBackupKind() ? &BackupVars : &Vars;
        VarLocs.set(VarLocID);
+      InsertInto->insert({VL.Var, VarLocID});
+    }
+
+    void moveToVars(unsigned VarLocID, DebugVariable Var) {
+      BackupVars.erase(Var);
       Vars.insert({Var, VarLocID});
     }
 
     /// Empty the set.
     void clear() {
       VarLocs.clear();
       Vars.clear();
+      BackupVars.clear();
     }
 
     /// Return whether the set is empty or not.
     bool empty() const {
-      assert(Vars.empty() == VarLocs.empty() && "open ranges are inconsistent");
+      assert((Vars.empty() && BackupVars.empty()) == VarLocs.empty() &&
+             "open ranges are inconsistent");
       return VarLocs.empty();
     }
+
+    bool test(unsigned Idx) { return VarLocs.test(Idx); }
   };
 
   bool isSpillInstruction(const MachineInstr &MI, MachineFunction *MF,
                           unsigned &Reg);
+  bool isCopyInstruction(MachineInstr &MI, unsigned &SrcReg,
+                         unsigned &DefReg);
   int extractSpillBaseRegAndOffset(const MachineInstr &MI, unsigned &Reg);
 
+  void transferBackups(const MachineBasicBlock *MBB, VarLocInMBB &InLocs,
+                       OpenRangesSet &OpenRanges, const VarLocMap &VarLocIDs);
   void transferDebugValue(const MachineInstr &MI, OpenRangesSet &OpenRanges,
                           VarLocMap &VarLocIDs);
   void transferSpillInst(MachineInstr &MI, OpenRangesSet &OpenRanges,
-                         VarLocMap &VarLocIDs, SpillMap &Spills);
+                         VarLocMap &VarLocIDs, TransferMap &Transfers);
   void transferRegisterDef(MachineInstr &MI, OpenRangesSet &OpenRanges,
-                           const VarLocMap &VarLocIDs);
+                           const VarLocMap &VarLocIDs,
+                           RegBackupMap &RegBackup,
+                           TransferMap &Transfers);
+  void transferRegisterCopy(MachineInstr &MI, OpenRangesSet &OpenRanges,
+                            VarLocMap &VarLocIDs, RegBackupMap &RegBackup);
   bool transferTerminatorInst(MachineInstr &MI, OpenRangesSet &OpenRanges,
                               VarLocInMBB &OutLocs, const VarLocMap &VarLocIDs);
   bool transfer(MachineInstr &MI, OpenRangesSet &OpenRanges,
-                VarLocInMBB &OutLocs, VarLocMap &VarLocIDs, SpillMap &Spills,
-                bool transferSpills);
+                VarLocInMBB &OutLocs, VarLocMap &VarLocIDs, TransferMap &Transfers,
+                RegBackupMap &RegBackup, bool transferChanges);
 
   bool join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs, VarLocInMBB &InLocs,
             const VarLocMap &VarLocIDs,
             SmallPtrSet<const MachineBasicBlock *, 16> &Visited);
 
   bool ExtendRanges(MachineFunction &MF);
 
 public:
void LiveDebugValues::printVarLocInMBB(const MachineFunction &MF,
   Out << '\n' << msg << '\n';
   for (const MachineBasicBlock &BB : MF) {
     const auto &L = V.lookup(&BB);
     Out << "MBB: " << BB.getName() << ":\n";
     for (unsigned VLL : L) {
       const VarLoc &VL = VarLocIDs[VLL];
       Out << " Var: " << VL.Var.getVar()->getName();
       Out << " MI: ";
-      VL.dump();
+      VL.MI.print(Out, false, false, false, TII);
     }
   }
   Out << "\n";
 }
 #endif
 
 /// Given a spill instruction, extract the register and offset used to
 /// address the spill location in a target independent way.
 int LiveDebugValues::extractSpillBaseRegAndOffset(const MachineInstr &MI,
                                                   unsigned &Reg) {
   assert(MI.hasOneMemOperand() && 
          "Spill instruction does not have exactly one memory operand?");
   auto MMOI = MI.memoperands_begin();
   const PseudoSourceValue *PVal = (*MMOI)->getPseudoValue();
   assert(PVal->kind() == PseudoSourceValue::FixedStack &&
          "Inconsistent memory operand in spill instruction");
   int FI = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
   const MachineBasicBlock *MBB = MI.getParent();
   return TFI->getFrameIndexReference(*MBB->getParent(), FI, Reg);
 }
 
+/// Transfer backup locations into OpenRanges set so we could use them
+/// in the following iteration of MBB.
+void LiveDebugValues::transferBackups(const MachineBasicBlock *MBB,
+                                      VarLocInMBB &InLocs,
+                                      OpenRangesSet &OpenRanges,
+                                      const VarLocMap &VarLocIDs) {
+  for (unsigned ID: InLocs[MBB])
+    if (VarLocIDs[ID].isBackupKind())
+       OpenRanges.insert(ID, VarLocIDs[ID]);
+}
+
 /// End all previous ranges related to @MI and start a new range from @MI
 /// if it is a DBG_VALUE instr.
 void LiveDebugValues::transferDebugValue(const MachineInstr &MI,
                                          OpenRangesSet &OpenRanges,
                                          VarLocMap &VarLocIDs) {
   if (!MI.isDebugValue())
     return;
   const DILocalVariable *Var = MI.getDebugVariable();
   const DILocation *DebugLoc = MI.getDebugLoc();
   const DILocation *InlinedAt = DebugLoc->getInlinedAt();
   assert(Var->isValidLocationForIntrinsic(DebugLoc) &&
          "Expected inlined-at fields to agree");
 
   // End all previous ranges of Var.
   DebugVariable V(Var, InlinedAt);
-  OpenRanges.erase(V);
+  VarLoc VL(MI, LS);
+  OpenRanges.erase(VL);
 
   // Add the VarLoc to OpenRanges from this DBG_VALUE.
   // TODO: Currently handles DBG_VALUE which has only reg as location.
   if (isDbgValueDescribedByReg(MI)) {
-    VarLoc VL(MI, LS);
     unsigned ID = VarLocIDs.insert(VL);
-    OpenRanges.insert(ID, VL.Var);
+    OpenRanges.insert(ID, VL);
   }
 }
 
 /// A definition of a register may mark the end of a range.
 void LiveDebugValues::transferRegisterDef(MachineInstr &MI,
                                           OpenRangesSet &OpenRanges,
-                                          const VarLocMap &VarLocIDs) {
+                                          const VarLocMap &VarLocIDs,
+                                          RegBackupMap &RegBackup,
+                                          TransferMap &Transfers) {
   MachineFunction *MF = MI.getMF();
   const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
   unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
   SparseBitVector<> KillSet;
+  unsigned ReplacementID = 0;
   for (const MachineOperand &MO : MI.operands()) {
     // Determine whether the operand is a register def.  Assume that call
     // instructions never clobber SP, because some backends (e.g., AArch64)
     // never list SP in the regmask.
     if (MO.isReg() && MO.isDef() && MO.getReg() &&
         TRI->isPhysicalRegister(MO.getReg()) &&
         !(MI.isCall() && MO.getReg() == SP)) {
       // Remove ranges of all aliased registers.
       for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI)
         for (unsigned ID : OpenRanges.getVarLocs())
-          if (VarLocIDs[ID].isDescribedByReg() == *RAI)
+          if (VarLocIDs[ID].isDescribedByReg() == *RAI) {
+            auto BackupIDs = RegBackup.find(ID);
+            // Save replacement's ID if this value is saved in another
+            // register and that register is live and not cloberred in
+            // current basci block iteration.
+            if (BackupIDs != RegBackup.end() &&
+                OpenRanges.test(BackupIDs->second))
+              ReplacementID = BackupIDs->second;
             KillSet.set(ID);
+          }
     } else if (MO.isRegMask()) {
       // Remove ranges of all clobbered registers. Register masks don't usually
       // list SP as preserved.  While the debug info may be off for an
       // instruction or two around callee-cleanup calls, transferring the
       // DEBUG_VALUE across the call is still a better user experience.
       for (unsigned ID : OpenRanges.getVarLocs()) {
         unsigned Reg = VarLocIDs[ID].isDescribedByReg();
         if (Reg && Reg != SP && MO.clobbersPhysReg(Reg))
           KillSet.set(ID);
       }
     }
   }
   OpenRanges.erase(KillSet, VarLocIDs);
+  if (ReplacementID) {
+    const MachineInstr *DMI = &VarLocIDs[ReplacementID].MI;
+    MachineInstr *NewDMI =
+        BuildMI(*MF, DMI->getDebugLoc(), DMI->getDesc(),
+                DMI->isIndirectDebugValue(), DMI->getOperand(0).getReg(),
+                DMI->getDebugVariable(), DMI->getDebugExpression());
+    if (DMI->isIndirectDebugValue())
+        NewDMI->getOperand(1).setImm(DMI->getOperand(1).getImm());
+    DEBUG(dbgs() << "Creating DBG_VALUE inst from backup: ";
+          NewDMI->print(dbgs(), false, false, false, TII));
+
+    // The newly created DBG_VALUE instruction NewDMI must be inserted after
+    // MI. Keep track of the pairing.
+    TransferDebugPair MIP = {&MI, NewDMI};
+    Transfers.push_back(MIP);
+
+    //We don't remove this ReplacementID from OpenRanges set since it needs
+    //to stay there butn now it is as real register location.
+    VarLocIDs[ReplacementID].setRegisterKind();
+    OpenRanges.moveToVars(ReplacementID, VarLocIDs[ReplacementID].Var);
+  }
+
 }
 
 /// Decide if @MI is a spill instruction and return true if it is. We use 2
 /// criteria to make this decision:
 /// - Is this instruction a store to a spill slot?
 /// - Is there a register operand that is both used and killed?
 /// TODO: Store optimization can fold spills into other stores (including
 /// other spills). We do not handle this yet (more than one memory operand).
bool LiveDebugValues::isSpillInstruction(const MachineInstr &MI,
   }
   // Return false if we didn't find spilled register.
   return false;
 }
 
 /// A spilled register may indicate that we have to end the current range of
 /// a variable and create a new one for the spill location.
 /// We don't want to insert any instructions in transfer(), so we just create
-/// the DBG_VALUE witout inserting it and keep track of it in @Spills.
+/// the DBG_VALUE witout inserting it and keep track of it in @Transfers.
 /// It will be inserted into the BB when we're done iterating over the
 /// instructions.
 void LiveDebugValues::transferSpillInst(MachineInstr &MI,
                                         OpenRangesSet &OpenRanges,
                                         VarLocMap &VarLocIDs,
-                                        SpillMap &Spills) {
+                                        TransferMap &Transfers) {
   unsigned Reg;
   MachineFunction *MF = MI.getMF();
   if (!isSpillInstruction(MI, MF, Reg))
     return;
 
   // Check if the register is the location of a debug value.
   for (unsigned ID : OpenRanges.getVarLocs()) {
     if (VarLocIDs[ID].isDescribedByReg() == Reg) {
       DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '('
                    << VarLocIDs[ID].Var.getVar()->getName() << ")\n");
 
       // Create a DBG_VALUE instruction to describe the Var in its spilled
       // location, but don't insert it yet to avoid invalidating the
       // iterator in our caller.
       unsigned SpillBase;
       int SpillOffset = extractSpillBaseRegAndOffset(MI, SpillBase);
       const MachineInstr *DMI = &VarLocIDs[ID].MI;
       auto *SpillExpr = DIExpression::prepend(
           DMI->getDebugExpression(), DIExpression::NoDeref, SpillOffset);
       MachineInstr *SpDMI =
           BuildMI(*MF, DMI->getDebugLoc(), DMI->getDesc(), true, SpillBase,
                   DMI->getDebugVariable(), SpillExpr);
       DEBUG(dbgs() << "Creating DBG_VALUE inst for spill: ";
-            SpDMI->print(dbgs(), false, TII));
+            SpDMI->print(dbgs(), false, false, false, TII));
 
       // The newly created DBG_VALUE instruction SpDMI must be inserted after
       // MI. Keep track of the pairing.
-      SpillDebugPair MIP = {&MI, SpDMI};
-      Spills.push_back(MIP);
+      TransferDebugPair MIP = {&MI, SpDMI};
+      Transfers.push_back(MIP);
 
       // End all previous ranges of Var.
-      OpenRanges.erase(VarLocIDs[ID].Var);
+      OpenRanges.erase(VarLocIDs[ID]);
 
       // Add the VarLoc to OpenRanges.
       VarLoc VL(*SpDMI, LS);
       unsigned SpillLocID = VarLocIDs.insert(VL);
-      OpenRanges.insert(SpillLocID, VL.Var);
+      OpenRanges.insert(SpillLocID, VL);
+      return;
+    }
+  }
+}
+
+/// Check whether @MI is instruction that copies value forme one register
+/// to another one. If it is copy instruction return true along with @SrcReg
+/// and newly definded location register @DefReg. We are only looking for
+/// instruction in wich source registers is killed after copy instruction.
+bool LiveDebugValues::isCopyInstruction(MachineInstr &MI, unsigned &SrcReg,
+                                        unsigned &DefReg) {
+  MachineFunction *MF = MI.getParent()->getParent();
+  const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
+  unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
+  if (!TII->isCopyInstruction(MI))
+    return false;
+
+  for (const MachineOperand &MO : MI.operands()) {
+    if (MO.isReg() && MO.getReg() && TRI->isPhysicalRegister(MO.getReg()) &&
+        !(MI.isCall() && MO.getReg() == SP)) {
+      if (MO.isDef())
+        DefReg = MO.getReg();
+      else if (MO.isKill())
+        SrcReg = MO.getReg();
+    }
+  }
+  // We just want to recognize instructions after which  we have both killed
+  // end definded register register.
+  if (!DefReg || !SrcReg)
+    return false;
+  return true;
+}
+
+/// If @MI is register copy instruction that copies previously tracked value
+/// from one register to another we create new backup DBG_VALEU instruction
+/// described with copy destination register. This newley created instruction
+/// is added to VarLocIDs and to OpenRanges in case that first DBG_VALUE's
+/// register gets clobbered.
+void LiveDebugValues::transferRegisterCopy(MachineInstr &MI,
+                                           OpenRangesSet &OpenRanges,
+                                           VarLocMap &VarLocIDs,
+                                           RegBackupMap &RegBackup) {
+  unsigned Reg = 0;
+  unsigned DefReg = 0;
+  if(!isCopyInstruction(MI, Reg, DefReg))
+      return;
+  for (unsigned ID : OpenRanges.getVarLocs()) {
+    if (VarLocIDs[ID].isDescribedByReg() == Reg) {
+      auto BackupIDs = RegBackup.find(ID);
+      if (BackupIDs == RegBackup.end()) {
+        const MachineInstr *DMI = &VarLocIDs[ID].MI;
+        MachineFunction *MF = MI.getParent()->getParent();
+        MachineInstr *NewDMI =
+            BuildMI(*MF, DMI->getDebugLoc(), DMI->getDesc(),
+            DMI->isIndirectDebugValue(), DefReg,
+            DMI->getDebugVariable(), DMI->getDebugExpression());
+        if (DMI->isIndirectDebugValue())
+          NewDMI->getOperand(1).setImm(DMI->getOperand(1).getImm());
+        DEBUG(dbgs() << "Creating backup DBG_VALUE inst for register copy: ";
+              NewDMI->print(dbgs(), false, false, false, TII));
+
+        // Add the VarLoc to OpenRanges.
+        VarLoc VL(*NewDMI, LS);
+        VL.setBackupKind();
+        unsigned LocID = VarLocIDs.insert(VL);
+        OpenRanges.insert(LocID, VL);
+        // Make pair of origianl value ID and its new backup ID.
+        RegBackup[ID] = LocID;
+      } else if (VarLocIDs[BackupIDs->second].isDescribedByReg() != DefReg) {
+         // We came up incosiste register copy. This register has already
+         // been copied in some of previous blocks and it was copied to
+         // different location than current MI is trying to copy to.
+         // For now we just untrack such copy.
+         RegBackup.erase(ID);
+      } else {
+        // This DBG_VALUE is already in RegBackup and its backup register is
+        // same as it is in current MI. We are adding this backup location
+        // to OpenRanges.
+        unsigned BackupID = BackupIDs->second;
+        OpenRanges.insert(BackupID, VarLocIDs[BackupID]);
+      }
        return;
      }
    }
 }
 
 /// Terminate all open ranges at the end of the current basic block.
 bool LiveDebugValues::transferTerminatorInst(MachineInstr &MI,
                                              OpenRangesSet &OpenRanges,
                                              VarLocInMBB &OutLocs,
                                              const VarLocMap &VarLocIDs) {
   bool Changed = false;
   const MachineBasicBlock *CurMBB = MI.getParent();
   if (!(MI.isTerminator() || (&MI == &CurMBB->back())))
     return false;
 
   if (OpenRanges.empty())
     return false;
 
   DEBUG(for (unsigned ID : OpenRanges.getVarLocs()) {
           // Copy OpenRanges to OutLocs, if not already present.
-          dbgs() << "Add to OutLocs: "; VarLocIDs[ID].dump();
+          dbgs() << "Add to OutLocs: ";
+          VarLocIDs[ID].MI.print(dbgs(), false, false, false, TII);
         });
   VarLocSet &VLS = OutLocs[CurMBB];
   Changed = VLS |= OpenRanges.getVarLocs();
   OpenRanges.clear();
   return Changed;
 }
 
 /// This routine creates OpenRanges and OutLocs.
 bool LiveDebugValues::transfer(MachineInstr &MI, OpenRangesSet &OpenRanges,
                                VarLocInMBB &OutLocs, VarLocMap &VarLocIDs,
-                               SpillMap &Spills, bool transferSpills) {
+                               TransferMap &Transfers, RegBackupMap &RegBackup,
+                               bool transferChanges) {
   bool Changed = false;
   transferDebugValue(MI, OpenRanges, VarLocIDs);
-  transferRegisterDef(MI, OpenRanges, VarLocIDs);
-  if (transferSpills)
-    transferSpillInst(MI, OpenRanges, VarLocIDs, Spills);
+  transferRegisterDef(MI, OpenRanges, VarLocIDs, RegBackup, Transfers);
+  if (transferChanges) {
+    transferRegisterCopy(MI, OpenRanges, VarLocIDs, RegBackup);
+    transferSpillInst(MI, OpenRanges, VarLocIDs, Transfers);
+  }
   Changed = transferTerminatorInst(MI, OpenRanges, OutLocs, VarLocIDs);
   return Changed;
 }
 
 /// This routine joins the analysis results of all incoming edges in @MBB by
 /// inserting a new DBG_VALUE instruction at the start of the @MBB - if the same
 /// source variable in all the predecessors of @MBB reside in the same location.
 bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs,
bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs,
   VarLocSet Diff = InLocsT;
   Diff.intersectWithComplement(ILS);
   for (auto ID : Diff) {
     // This VarLoc is not found in InLocs i.e. it is not yet inserted. So, a
     // new range is started for the var from the mbb's beginning by inserting
     // a new DBG_VALUE. transfer() will end this range however appropriate.
     const VarLoc &DiffIt = VarLocIDs[ID];
     const MachineInstr *DMI = &DiffIt.MI;
+    if (!DiffIt.isBackupKind()) {
       MachineInstr *MI =
           BuildMI(MBB, MBB.instr_begin(), DMI->getDebugLoc(), DMI->getDesc(),
                   DMI->isIndirectDebugValue(), DMI->getOperand(0).getReg(),
                   DMI->getDebugVariable(), DMI->getDebugExpression());
       if (DMI->isIndirectDebugValue())
         MI->getOperand(1).setImm(DMI->getOperand(1).getImm());
       DEBUG(dbgs() << "Inserted: "; MI->dump(););
+    }
     ILS.set(ID);
     ++NumInserted;
     Changed = true;
   }
   return Changed;
 }
 
 /// Calculate the liveness information for the given machine function and
 /// extend ranges across basic blocks.
 bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
   DEBUG(dbgs() << "\nDebug Range Extension\n");
 
   bool Changed = false;
   bool OLChanged = false;
   bool MBBJoined = false;
 
   VarLocMap VarLocIDs;      // Map VarLoc<>unique ID for use in bitvectors.
   OpenRangesSet OpenRanges; // Ranges that are open until end of bb.
   VarLocInMBB OutLocs;      // Ranges that exist beyond bb.
   VarLocInMBB InLocs;       // Ranges that are incoming after joining.
-  SpillMap Spills;          // DBG_VALUEs associated with spills.
+  TransferMap Transfers;    // DBG_VALUEs associated with spills.
+  RegBackupMap RegBackup;   // Map that perserves backup IDs for VarLocIds
 
   DenseMap<unsigned int, MachineBasicBlock *> OrderToBB;
   DenseMap<MachineBasicBlock *, unsigned int> BBToOrder;
   std::priority_queue<unsigned int, std::vector<unsigned int>,
                       std::greater<unsigned int>>
       Worklist;
   std::priority_queue<unsigned int, std::vector<unsigned int>,
                       std::greater<unsigned int>>
       Pending;
 
   // Initialize every mbb with OutLocs.
   // We are not looking at any spill instructions during the initial pass
   // over the BBs. The LiveDebugVariables pass has already created DBG_VALUE
   // instructions for spills of registers that are known to be user variables
   // within the BB in which the spill occurs.
   for (auto &MBB : MF)
     for (auto &MI : MBB)
-      transfer(MI, OpenRanges, OutLocs, VarLocIDs, Spills,
-               /*transferSpills=*/false);
+      transfer(MI, OpenRanges, OutLocs, VarLocIDs, Transfers, RegBackup,
+               /*transferChanges=*/false);
 
   DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, "OutLocs after initialization",
                          dbgs()));
 
   ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
   unsigned int RPONumber = 0;
   for (auto RI = RPOT.begin(), RE = RPOT.end(); RI != RE; ++RI) {
     OrderToBB[RPONumber] = *RI;
while (!Worklist.empty()) {
       MBBJoined = join(*MBB, OutLocs, InLocs, VarLocIDs, Visited);
       Visited.insert(MBB);
       if (MBBJoined) {
         MBBJoined = false;
         Changed = true;
         // Now that we have started to extend ranges across BBs we need to
         // examine spill instructions to see whether they spill registers that
         // correspond to user variables.
+        transferBackups(MBB, InLocs, OpenRanges, VarLocIDs);
         for (auto &MI : *MBB)
-          OLChanged |= transfer(MI, OpenRanges, OutLocs, VarLocIDs, Spills,
-                                /*transferSpills=*/true);
+          OLChanged |= transfer(MI, OpenRanges, OutLocs, VarLocIDs, Transfers,
+                                RegBackup, /*transferChanges=*/true);
 
         // Add any DBG_VALUE instructions necessitated by spills.
-        for (auto &SP : Spills)
-          MBB->insertAfter(MachineBasicBlock::iterator(*SP.SpillInst),
-                           SP.DebugInst);
-        Spills.clear();
+        for (auto &TR : Transfers)
+          MBB->insertAfter(MachineBasicBlock::iterator(*TR.TransferInst),
+                           TR.DebugInst);
+        Transfers.clear();
 
         DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,
                                "OutLocs after propagating", dbgs()));
         DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs,
                                "InLocs after propagating", dbgs()));
 
         if (OLChanged) {
           OLChanged = false;
if (MF.getFunction().getSubprogram()->getUnit()->getEmissionKind() ==
     return false;
 
   TRI = MF.getSubtarget().getRegisterInfo();
   TII = MF.getSubtarget().getInstrInfo();
   TFI = MF.getSubtarget().getFrameLowering();
   LS.initialize(MF);
 
   bool Changed = ExtendRanges(MF);
   return Changed;
 }

lib/Target/Mips/Mips16InstrInfo.h

public:
   /// any side effects other than storing to the stack slot.
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
 
   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
                    bool KillSrc) const override;
 
+  bool isCopyInstruction(MachineInstr &MI) const override;
+
   void storeRegToStack(MachineBasicBlock &MBB,
                        MachineBasicBlock::iterator MBBI,
                        unsigned SrcReg, bool isKill, int FrameIndex,
                        const TargetRegisterClass *RC,
                        const TargetRegisterInfo *TRI,
                        int64_t Offset) const override;
 
   void loadRegFromStack(MachineBasicBlock &MBB,

lib/Target/Mips/Mips16InstrInfo.cpp

void Mips16InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 
   if (DestReg)
     MIB.addReg(DestReg, RegState::Define);
 
   if (SrcReg)
     MIB.addReg(SrcReg, getKillRegState(KillSrc));
 }
 
+bool Mips16InstrInfo::isCopyInstruction(MachineInstr &MI) const {
+  switch (MI.getOpcode()) {
+  case Mips::MoveR3216:
+  case Mips::Mfhi16:
+  case Mips::Mflo16:
+    return true;
+  default:
+    return false;
+  }
+
+}
+
 void Mips16InstrInfo::storeRegToStack(MachineBasicBlock &MBB,
                                       MachineBasicBlock::iterator I,
                                       unsigned SrcReg, bool isKill, int FI,
                                       const TargetRegisterClass *RC,
                                       const TargetRegisterInfo *TRI,
                                       int64_t Offset) const {
   DebugLoc DL;
   if (I != MBB.end()) DL = I->getDebugLoc();

lib/Target/Mips/MipsSEInstrInfo.h

public:
   /// any side effects other than storing to the stack slot.
   unsigned isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
 
   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
                    bool KillSrc) const override;
 
+  bool isCopyInstruction(MachineInstr &MI) const override;
+
   void storeRegToStack(MachineBasicBlock &MBB,
                        MachineBasicBlock::iterator MI,
                        unsigned SrcReg, bool isKill, int FrameIndex,
                        const TargetRegisterClass *RC,
                        const TargetRegisterInfo *TRI,
                        int64_t Offset) const override;
 
   void loadRegFromStack(MachineBasicBlock &MBB,

lib/Target/Mips/MipsSEInstrInfo.cpp

void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
 
   if (SrcReg)
     MIB.addReg(SrcReg, getKillRegState(KillSrc));
 
   if (ZeroReg)
     MIB.addReg(ZeroReg);
 }
 
+bool MipsSEInstrInfo::isCopyInstruction(MachineInstr &MI) const {
+  switch (MI.getOpcode()) {
+  case Mips::SLL64_32:
+  case Mips::SLL64_64:
+  case Mips::MOVE16_MM:
+  case Mips::CFC1:
+  case Mips::MFC1:
+  case Mips::MFHI16_MM:
+  case Mips::MFHI:
+  case Mips::MFLO16_MM:
+  case Mips::MFLO:
+  case Mips::MFHI_DSP:
+  case Mips::MFLO_DSP:
+  case Mips::RDDSP:
+  case Mips::CTC1:
+  case Mips::MTC1:
+  case Mips::MTHI:
+  case Mips::MTLO:
+  case Mips::MTHI_DSP:
+  case Mips::MTLO_DSP:
+  case Mips::WRDSP:
+  case Mips::CTCMSA:
+  case Mips::FMOV_S:
+  case Mips::FMOV_D32:
+  case Mips::FMOV_D64:
+  case Mips::MFHI64:
+  case Mips::MFLO64:
+  case Mips::DMFC1:
+  case Mips::MTHI64:
+  case Mips::MTLO64:
+  case Mips::DMTC1:
+  case Mips::MOVE_V:
+    return true;
+  case Mips::OR:
+  case Mips::OR64:
+    if (MI.getOperand(2).getReg() ==
+        (Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO))
+      return true;
+  default:
+    return false;
+  }
+}
+
 void MipsSEInstrInfo::
 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                 unsigned SrcReg, bool isKill, int FI,
                 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
                 int64_t Offset) const {
   DebugLoc DL;
   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);