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Differential D41447

[AArch64][SVE] Asm: Negative tests for predicated ADD/SUB register constraints
ClosedPublic

Authored by sdesmalen on Dec 20 2017, 6:40 AM.

Details

Reviewers
rengolin
mcrosier
evandro
fhahn
echristo
Commits
rGba5fd775adf5: [AArch64][SVE] Asm: Negative tests for predicated ADD/SUB register constraints
rL322265: [AArch64][SVE] Asm: Negative tests for predicated ADD/SUB register constraints
Summary

Patch [3/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.

Diff Detail

Event Timeline

sdesmalen created this revision.Dec 20 2017, 6:40 AM
Herald added subscribers: kristof.beyls, tschuett, javed.absar, aemerson. · View Herald TranscriptDec 20 2017, 6:40 AM
sdesmalen added parent revisions: D41443: [AArch64][SVE] Asm: Add predicated ADD/SUB instructions, D41445: [AArch64][AsmParser] Add isScalarReg() and repurpose isReg(), D41446: [TableGen][AsmMatcherEmitter] Generate assembler checks for tied operands.Dec 20 2017, 6:41 AM
fhahn accepted this revision.Jan 2 2018, 3:42 AM

LGTM

This revision is now accepted and ready to land.Jan 2 2018, 3:42 AM
fhahn added inline comments.Jan 2 2018, 3:46 AM
test/MC/AArch64/SVE/sub-diagnostics.s
57

nit: I think it would be slightly clearer if the grouping was like this:

// Source and Destination Registers must match

sub z25.b, p4/m, z26.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sub z25.b, p4/m, z26.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

.....

sub z2.d, p5/m, z3.d, z11.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sub z2.d, p5/m, z3.d, z11.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------
rengolin accepted this revision.Jan 3 2018, 5:23 AM

Same comment as @fhahn :)

sdesmalen updated this revision to Diff 128534.Jan 3 2018, 9:40 AM

Improved formatting of negative tests for predicated add/sub.

sdesmalen marked an inline comment as done.Jan 3 2018, 9:40 AM
sdesmalen closed this revision.Jan 11 2018, 2:03 AM

Revision Contents

PathSize
test/
MC/
AArch64/
SVE/
24 lines
24 lines

Diff 127711

test/MC/AArch64/SVE/add-diagnostics.s

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
// CHECK-NEXT: add z29.d, p7/a, z29.d, z8.d // CHECK-NEXT: add z29.d, p7/a, z29.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Missing predicate suffix // Missing predicate suffix
add z29.d, p7, z29.d, z8.d add z29.d, p7, z29.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: add z29.d, p7, z29.d, z8.d // CHECK-NEXT: add z29.d, p7, z29.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Source and Destination Registers must match
add z19.b, p4/m, z20.b, z13.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: add z19.b, p4/m, z20.b, z13.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Source and Destination Registers must match
add z9.h, p3/m, z10.h, z28.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: add z9.h, p3/m, z10.h, z28.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Source and Destination Registers must match
add z5.s, p3/m, z6.s, z18.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: add z5.s, p3/m, z6.s, z18.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Source and Destination Registers must match
add z9.d, p4/m, z10.d, z7.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: add z9.d, p4/m, z10.d, z7.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file

test/MC/AArch64/SVE/sub-diagnostics.s

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
// CHECK-NEXT: sub z29.d, p7/a, z29.d, z8.d // CHECK-NEXT: sub z29.d, p7/a, z29.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Missing predicate suffix // Missing predicate suffix
sub z29.d, p7, z29.d, z8.d sub z29.d, p7, z29.d, z8.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
// CHECK-NEXT: sub z29.d, p7, z29.d, z8.d // CHECK-NEXT: sub z29.d, p7, z29.d, z8.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Source and Destination Registers must match
fhahnUnsubmitted
Done
ReplyInline Actions

nit: I think it would be slightly clearer if the grouping was like this:

// Source and Destination Registers must match

sub z25.b, p4/m, z26.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sub z25.b, p4/m, z26.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

.....

sub z2.d, p5/m, z3.d, z11.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sub z2.d, p5/m, z3.d, z11.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------
fhahn: nit: I think it would be slightly clearer if the grouping was like this: ``` // Source and…
sub z25.b, p4/m, z26.b, z2.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sub z25.b, p4/m, z26.b, z2.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Source and Destination Registers must match
sub z29.h, p6/m, z30.h, z20.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sub z29.h, p6/m, z30.h, z20.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Source and Destination Registers must match
sub z14.s, p2/m, z15.s, z21.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sub z14.s, p2/m, z15.s, z21.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// Source and Destination Registers must match
sub z2.d, p5/m, z3.d, z11.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
// CHECK-NEXT: sub z2.d, p5/m, z3.d, z11.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
No newline at end of file