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[AArch64][SVE] Asm: Negative tests for predicated ADD/SUB register constraints

Description

[AArch64][SVE] Asm: Negative tests for predicated ADD/SUB register constraints

Summary: Patch [3/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.

Reviewers: rengolin, mcrosier, evandro, fhahn, echristo

Reviewed By: rengolin, fhahn

Subscribers: aemerson, javed.absar, tschuett, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D41447

Details

Committed
s.desmalenJan 11 2018, 2:02 AM
Reviewer
rengolin
Differential Revision
D41447: [AArch64][SVE] Asm: Negative tests for predicated ADD/SUB register constraints
Parents
rL322264: Fix thread race between SectionPiece's OutputOff and Live members
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