Check that emitted instructions meet their predicates on all targets except ARM, Mips, and X86.

[dsanders]

Summary

• ARM is omitted from this patch because this check appears to expose bugs in this target.
• Mips is omitted from this patch because this check either detects bugs or deliberate emission of instructions that don't satisfy their predicates. One deliberate use is the SYNC instruction where the version with an operand is correctly defined as requiring MIPS32 while the version without an operand is defined as an alias of 'SYNC 0' and requires MIPS2.
• X86 is omitted from this patch because it doesn't use the tablegen-erated MCCodeEmitter infrastructure.

Patches for ARM and Mips will follow.

Depends on D25617

[dsanders]

lib/Target/AMDGPU/VOP1Instructions.td

539

@tstellarAMD: Hi Tom, I'm not sure if this line is correct or not. I've included it because a recent change (r284031) left a '?' in this field and that causes problems in tablegen. Is there a correct predicate to use here?

utils/TableGen/CodeEmitterGen.cpp

332

I've just noticed I've forgotten something. I intended for the body of this generated function to be guarded with '#ifndef NDEBUG' so that it isn't checked on release builds. I'll post an updated patch soon

[jmolloy]

This is a great idea, thanks for working on this!

My biggest concern is that there's very little information printed out for a developer to take action on. We absolutely need to have at least the instruction that failed verification printed, and ideally the expected and actual feature sets.

James

lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

175

lowerCamelCase

utils/TableGen/AsmMatcherEmitter.cpp

1417

Whitespace change

utils/TableGen/CodeEmitterGen.cpp

347

This absolutely needs to print out the offending instruction, and ideally the required features although as they're encoded in a bitset that's probably quite difficult.

[• tstellarAMD]

lib/Target/AMDGPU/VOP1Instructions.td

539

I think this needs to be isVI.

[dsanders]

Thanks for the quick feedback.

lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

175

I agree it should be a lower case first letter. The reason it isn't is because the generated function is shared with the AsmMatcher and that one isn't a member function. I'll fix this.

lib/Target/AMDGPU/VOP1Instructions.td

539

Thanks, I'll update the patch.

utils/TableGen/CodeEmitterGen.cpp

347

I agree, so far I've been re-running the failing command under lldb, printing Inst.getOpcode() and then looking that up in the generated AsmMatcher but that's a bit long winded.

In the worst case I can generate a table but I'll see if I can re-use existing information first.

[dsanders]

• Correct the AMDGPU predicate
• Report instruction that showed the problem and the feature predicate(s) that were not satisfied
• The other minor changes (whitespace and naming convention)

[dsanders]

Marked comments as done

[dsanders]

ping

[dsanders]

ping..

@jmolloy: Do you have any comments on the latest version if the patch? If not, would you be willing to LGTM it (as well as D25614 and D25617) so I can commit? Thanks

[foad]

Sorry for commenting on such an old patch but I am wondering why was verifyInstructionPredicates implemented inside of MCCodeEmitter? In practice this seem to mean that llc -filetype=obj gets this checking but llc -filetype=asm (the default, as used by almost all lit codegen tests) does not. Would it be possible to move verifyInstructionPredicates somewhere a bit more generic so that both paths can get this checking?

[dsanders]

In D25618#3135224, @foad wrote:

Sorry for commenting on such an old patch but I am wondering why was verifyInstructionPredicates implemented inside of MCCodeEmitter? In practice this seem to mean that llc -filetype=obj gets this checking but llc -filetype=asm (the default, as used by almost all lit codegen tests) does not. Would it be possible to move verifyInstructionPredicates somewhere a bit more generic so that both paths can get this checking?

I wouldn't rely on this recollection much but IIRC I didn't find a place where the final MCInsts were known and the code hadn't already diverged into asm/obj paths. I think the last pass before the paths diverged sometimes emitted different MCInst's down each path too

If we can do it somewhere where it affects both then that'd be great.

[foad]

In D25618#3135577, @dsanders wrote:

In D25618#3135224, @foad wrote:

Sorry for commenting on such an old patch but I am wondering why was verifyInstructionPredicates implemented inside of MCCodeEmitter? In practice this seem to mean that llc -filetype=obj gets this checking but llc -filetype=asm (the default, as used by almost all lit codegen tests) does not. Would it be possible to move verifyInstructionPredicates somewhere a bit more generic so that both paths can get this checking?

I wouldn't rely on this recollection much but IIRC I didn't find a place where the final MCInsts were known and the code hadn't already diverged into asm/obj paths. I think the last pass before the paths diverged sometimes emitted different MCInst's down each path too

If we can do it somewhere where it affects both then that'd be great.

Here's a demonstration that it *can* work, by making <Target>MCCodeEmitter::verifyInstructionPredicates static and calling into it from <Target>InstPrinter. But that doesn't seem very clean. I'd prefer to find a more neutral place to put verifyInstructionPredicates, but I'm not too familiar with the various classes that TableGen creates,

https://github.com/jayfoad/llvm-project/commits/verify-predicates (top three commits)

lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

unsigned fixMulHigh(const MCInst &MI, unsigned EncodedValue,
                       const MCSubtargetInfo &STI) const;
 
   template<int hasRs, int hasRt2> unsigned
   fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,
                         const MCSubtargetInfo &STI) const;
 
   unsigned fixOneOperandFPComparison(const MCInst &MI, unsigned EncodedValue,
                                      const MCSubtargetInfo &STI) const;
+
+private:
+  uint64_t ComputeAvailableFeatures(const FeatureBitset &FB) const;
+  void verifyInstructionPredicates(const MCInst &MI,
+                                   uint64_t AvailableFeatures) const;
 };
 
 } // end anonymous namespace
 
 MCCodeEmitter *llvm::createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
                                                 const MCRegisterInfo &MRI,
                                                 MCContext &Ctx) {
   return new AArch64MCCodeEmitter(MCII, Ctx);
unsigned AArch64MCCodeEmitter::fixMOVZ(const MCInst &MI, unsigned EncodedValue,
 
 
   return EncodedValue & ~(1u << 30);
 }
 
 void AArch64MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                              SmallVectorImpl<MCFixup> &Fixups,
                                              const MCSubtargetInfo &STI) const {
+  verifyInstructionPredicates(MI,
+                              ComputeAvailableFeatures(STI.getFeatureBits()));
+
   if (MI.getOpcode() == AArch64::TLSDESCCALL) {
     // This is a directive which applies an R_AARCH64_TLSDESC_CALL to the
     // following (BLR) instruction. It doesn't emit any code itself so it
     // doesn't go through the normal TableGenerated channels.
     MCFixupKind Fixup = MCFixupKind(AArch64::fixup_aarch64_tlsdesc_call);
     Fixups.push_back(MCFixup::create(0, MI.getOperand(0).getExpr(), Fixup));
     return;
   }

 unsigned AArch64MCCodeEmitter::fixOneOperandFPComparison(
     const MCInst &MI, unsigned EncodedValue, const MCSubtargetInfo &STI) const {
   // The Rm field of FCMP and friends is unused - it should be assembled
   // as 0, but is ignored by the processor.
   EncodedValue &= ~(0x1f << 16);
   return EncodedValue;
 }
 
+#define ENABLE_INSTR_PREDICATE_VERIFIER
 #include "AArch64GenMCCodeEmitter.inc"

lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.h

 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/Support/raw_ostream.h"
 
 namespace llvm {
 
 class MCInst;
 class MCOperand;
 class MCSubtargetInfo;
+class FeatureBitset;
 
 class AMDGPUMCCodeEmitter : public MCCodeEmitter {
   virtual void anchor();
 public:
 
   uint64_t getBinaryCodeForInstr(const MCInst &MI,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
 
   virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                                      SmallVectorImpl<MCFixup> &Fixups,
                                      const MCSubtargetInfo &STI) const {
     return 0;
   }
 
   virtual unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
                                      SmallVectorImpl<MCFixup> &Fixups,
                                      const MCSubtargetInfo &STI) const {
     return 0;
   }
+
+protected:
+  uint64_t ComputeAvailableFeatures(const FeatureBitset &FB) const;
+  void verifyInstructionPredicates(const MCInst &MI,
+                                   uint64_t AvailableFeatures) const;
 };
 
 } // End namespace llvm
 
 #endif

lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp

MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII,
                                              const MCRegisterInfo &MRI,
                                              MCContext &Ctx) {
   return new R600MCCodeEmitter(MCII, MRI);
 }
 
 void R600MCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
+  verifyInstructionPredicates(MI,
+                              ComputeAvailableFeatures(STI.getFeatureBits()));
+
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   if (MI.getOpcode() == AMDGPU::RETURN ||
     MI.getOpcode() == AMDGPU::FETCH_CLAUSE ||
     MI.getOpcode() == AMDGPU::ALU_CLAUSE ||
     MI.getOpcode() == AMDGPU::BUNDLE ||
     MI.getOpcode() == AMDGPU::KILL) {
     return;
   } else if (IS_VTX(Desc)) {
if (MO.isExpr()) {
     Fixups.push_back(MCFixup::create(offset, MO.getExpr(), FK_SecRel_4, MI.getLoc()));
     return 0;
   }
 
   assert(MO.isImm());
   return MO.getImm();
 }
 
+#define ENABLE_INSTR_PREDICATE_VERIFIER
 #include "AMDGPUGenMCCodeEmitter.inc"

lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp

uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO,
   assert(OpSize == 8);
 
   return getLit64Encoding(static_cast<uint64_t>(Imm), STI);
 }
 
 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const {
+  verifyInstructionPredicates(MI,
+                              ComputeAvailableFeatures(STI.getFeatureBits()));
 
   uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   unsigned bytes = Desc.getSize();
 
   for (unsigned i = 0; i < bytes; i++) {
     OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
   }

lib/Target/AMDGPU/VOP1Instructions.td

 // Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
 // indexing mode. vdst can't be treated as a def for codegen purposes,
 // and an implicit use and def of the super register should be added.
 def V_MOV_B32_indirect : VPseudoInstSI<(outs),
   (ins getVALUDstForVT<i32>.ret:$vdst, getVOPSrc0ForVT<i32>.ret:$src0)>,
   PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,
                                         getVOPSrc0ForVT<i32>.ret:$src0)> {
   let VOP1 = 1;
+  let SubtargetPredicate = isGCN;
 }
 
 let Predicates = [isVI] in {
 
 def : Pat <
   (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask,
                       imm:$bound_ctrl),
   (V_MOV_B32_dpp $src, (as_i32imm $dpp_ctrl), (as_i32imm $row_mask),
                        (as_i32imm $bank_mask), (as_i1imm $bound_ctrl))
 >;
 
 } // End Predicates = [isVI]

lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp

public:
 
   uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op,
                             SmallVectorImpl<MCFixup> &Fixups,
                             const MCSubtargetInfo &STI) const;
 
   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override;
+
+private:
+  uint64_t ComputeAvailableFeatures(const FeatureBitset &FB) const;
+  void verifyInstructionPredicates(const MCInst &MI,
+                                   uint64_t AvailableFeatures) const;
 };
 }
 
 MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII,
                                             const MCRegisterInfo &MRI,
                                             MCContext &Ctx) {
   return new BPFMCCodeEmitter(MRI, true);
 }

 static uint8_t SwapBits(uint8_t Val)
 {
   return (Val & 0x0F) << 4 | (Val & 0xF0) >> 4;
 }
 
 void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                          SmallVectorImpl<MCFixup> &Fixups,
                                          const MCSubtargetInfo &STI) const {
+  verifyInstructionPredicates(MI,
+                              ComputeAvailableFeatures(STI.getFeatureBits()));
+
   unsigned Opcode = MI.getOpcode();
   support::endian::Writer<support::little> LE(OS);
   support::endian::Writer<support::big> BE(OS);
 
   if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
     uint64_t Value = getBinaryCodeForInstr(MI, Fixups, STI);
     LE.write<uint8_t>(Value >> 56);
     if (IsLittleEndian)
uint64_t BPFMCCodeEmitter::getMemoryOpValue(const MCInst &MI, unsigned Op,
   Encoding = MRI.getEncodingValue(Op1.getReg());
   Encoding <<= 16;
   MCOperand Op2 = MI.getOperand(2);
   assert(Op2.isImm() && "Second operand is not immediate.");
   Encoding |= Op2.getImm() & 0xffff;
   return Encoding;
 }
 
+#define ENABLE_INSTR_PREDICATE_VERIFIER
 #include "BPFGenMCCodeEmitter.inc"

lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.h

public:
   uint64_t getBinaryCodeForInstr(MCInst const &MI,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  MCSubtargetInfo const &STI) const;
 
   /// \brief Return binary encoding of operand.
   unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
                              SmallVectorImpl<MCFixup> &Fixups,
                              MCSubtargetInfo const &STI) const;
+
+private:
+  uint64_t ComputeAvailableFeatures(const FeatureBitset &FB) const;
+  void verifyInstructionPredicates(const MCInst &MI,
+                                   uint64_t AvailableFeatures) const;
 }; // class HexagonMCCodeEmitter
 
 } // namespace llvm
 
 #endif /* HEXAGONMCCODEEMITTER_H */

lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp

void HexagonMCCodeEmitter::encodeInstruction(MCInst const &MI, raw_ostream &OS,
   DEBUG(dbgs() << "Encoding bundle\n";);
   *Addend = 0;
   *Extended = false;
   *CurrentBundle = &MI;
   size_t Instruction = 0;
   size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
   for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
     MCInst &HMI = const_cast<MCInst &>(*I.getInst());
+    verifyInstructionPredicates(HMI,
+                                ComputeAvailableFeatures(STI.getFeatureBits()));
+
     EncodeSingleInstruction(HMI, OS, Fixups, STI,
                             parseBits(Instruction, Last, HMB, HMI),
                             Instruction);
     *Extended = HexagonMCInstrInfo::isImmext(HMI);
     *Addend += HEXAGON_INSTR_SIZE;
     ++Instruction;
   }
   return;

 }
 
 MCCodeEmitter *llvm::createHexagonMCCodeEmitter(MCInstrInfo const &MII,
                                                 MCRegisterInfo const &MRI,
                                                 MCContext &MCT) {
   return new HexagonMCCodeEmitter(MII, MCT);
 }
 
+#define ENABLE_INSTR_PREDICATE_VERIFIER
 #include "HexagonGenMCCodeEmitter.inc"

lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp

public:
   // getBinaryCodeForInstr - TableGen'erated function for getting the
   // binary encoding for an instruction.
   uint64_t getBinaryCodeForInstr(const MCInst &MI,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override {
+    verifyInstructionPredicates(MI,
+                                ComputeAvailableFeatures(STI.getFeatureBits()));
+
     unsigned Opcode = MI.getOpcode();
     const MCInstrDesc &Desc = MCII.get(Opcode);
 
     uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
 
     // Output the constant in big/little endian byte order.
     unsigned Size = Desc.getSize();
     switch (Size) {
case 8:
       }
       break;
     default:
       llvm_unreachable ("Invalid instruction size");
     }
     
     ++MCNumEmitted;  // Keep track of the # of mi's emitted.
   }
-  
+private:
+  uint64_t ComputeAvailableFeatures(const FeatureBitset &FB) const;
+  void verifyInstructionPredicates(const MCInst &MI,
+                                   uint64_t AvailableFeatures) const;
 };
   
 } // end anonymous namespace
 
 MCCodeEmitter *llvm::createPPCMCCodeEmitter(const MCInstrInfo &MCII,
                                             const MCRegisterInfo &MRI,
                                             MCContext &Ctx) {
   return new PPCMCCodeEmitter(MCII, Ctx);
getMachineOpValue(const MCInst &MI, const MCOperand &MO,
   }
   
   assert(MO.isImm() &&
          "Relocation required in an instruction that we cannot encode!");
   return MO.getImm();
 }
 
 
+
+#define ENABLE_INSTR_PREDICATE_VERIFIER
 #include "PPCGenMCCodeEmitter.inc"

lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp

unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo,
                              const MCSubtargetInfo &STI) const;
   unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo,
                                       SmallVectorImpl<MCFixup> &Fixups,
                                       const MCSubtargetInfo &STI) const;
   unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
                                        SmallVectorImpl<MCFixup> &Fixups,
                                        const MCSubtargetInfo &STI) const;
 
+private:
+  uint64_t ComputeAvailableFeatures(const FeatureBitset &FB) const;
+  void verifyInstructionPredicates(const MCInst &MI,
+                                   uint64_t AvailableFeatures) const;
 };
 } // end anonymous namespace
 
 MCCodeEmitter *llvm::createSparcMCCodeEmitter(const MCInstrInfo &MCII,
                                               const MCRegisterInfo &MRI,
                                               MCContext &Ctx) {
   return new SparcMCCodeEmitter(Ctx);
 }
 
 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
+  verifyInstructionPredicates(MI,
+                              ComputeAvailableFeatures(STI.getFeatureBits()));
+
   unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI);
 
   if (Ctx.getAsmInfo()->isLittleEndian()) {
     // Output the bits in little-endian byte order.
     support::endian::Writer<support::little>(OS).write<uint32_t>(Bits);
   } else {
     // Output the bits in big-endian byte order.
     support::endian::Writer<support::big>(OS).write<uint32_t>(Bits);
getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo,
   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
                                    (MCFixupKind)Sparc::fixup_sparc_br16_2));
   Fixups.push_back(MCFixup::create(0, MO.getExpr(),
                                    (MCFixupKind)Sparc::fixup_sparc_br16_14));
 
   return 0;
 }
 
-
-
+#define ENABLE_INSTR_PREDICATE_VERIFIER
 #include "SparcGenMCCodeEmitter.inc"

lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp

return getPCRelEncoding(MI, OpNum, Fixups,
                             SystemZ::FK_390_PC16DBL, 2, true);
   }
   uint64_t getPC32DBLTLSEncoding(const MCInst &MI, unsigned OpNum,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const {
     return getPCRelEncoding(MI, OpNum, Fixups,
                             SystemZ::FK_390_PC32DBL, 2, true);
   }
+
+private:
+  uint64_t ComputeAvailableFeatures(const FeatureBitset &FB) const;
+  void verifyInstructionPredicates(const MCInst &MI,
+                                   uint64_t AvailableFeatures) const;
 };
 } // end anonymous namespace
 
 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
                                                 const MCRegisterInfo &MRI,
                                                 MCContext &Ctx) {
   return new SystemZMCCodeEmitter(MCII, Ctx);
 }
 
 void SystemZMCCodeEmitter::
 encodeInstruction(const MCInst &MI, raw_ostream &OS,
                   SmallVectorImpl<MCFixup> &Fixups,
                   const MCSubtargetInfo &STI) const {
+  verifyInstructionPredicates(MI,
+                              ComputeAvailableFeatures(STI.getFeatureBits()));
+
   uint64_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
   unsigned Size = MCII.get(MI.getOpcode()).getSize();
   // Big-endian insertion of Size bytes.
   unsigned ShiftValue = (Size * 8) - 8;
   for (unsigned I = 0; I != Size; ++I) {
     OS << uint8_t(Bits >> ShiftValue);
     ShiftValue -= 8;
   }
SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
   if (AllowTLS && OpNum + 1 < MI.getNumOperands()) {
     const MCOperand &MOTLS = MI.getOperand(OpNum + 1);
     Fixups.push_back(MCFixup::create(0, MOTLS.getExpr(),
                                      (MCFixupKind)SystemZ::FK_390_TLS_CALL));
   }
   return 0;
 }
 
+#define ENABLE_INSTR_PREDICATE_VERIFIER
 #include "SystemZGenMCCodeEmitter.inc"

utils/TableGen/AsmMatcherEmitter.cpp

for (const auto &OCM : OpClassMask) {
       OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
                                                            OpMask));
     }
   }
 }
 
 void AsmMatcherInfo::buildInfo() {
   // Build information about all of the AssemblerPredicates.
+
   const auto &SubtargetFeaturePairs = SubtargetFeatureInfo::getAll(Records);
   SubtargetFeatures.insert(SubtargetFeaturePairs.begin(),
                            SubtargetFeaturePairs.end());
   for (const auto &Pair : SubtargetFeatures)
     DEBUG(Pair.second.dump());
   assert(SubtargetFeatures.size() <= 64 && "Too many subtarget features!");
 
   bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
static void emitMatchRegisterAltName(CodeGenTarget &Target, Record *AsmParser,
   OS << "static unsigned MatchRegisterAltName(StringRef Name) {\n";
 
   StringMatcher("Name", Matches, OS).Emit();
 
   OS << "  return 0;\n";
   OS << "}\n\n";
 }
 
-static const char *getMinimalRequiredFeaturesType(const AsmMatcherInfo &Info) {
-  uint64_t MaxIndex = Info.SubtargetFeatures.size();
-  if (MaxIndex > 0)
-    MaxIndex--;
-  return getMinimalTypeForRange(1ULL << MaxIndex);
-}
-
-/// emitSubtargetFeatureFlagEnumeration - Emit the subtarget feature flag
-/// definitions.
-static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info,
-                                                raw_ostream &OS) {
-  OS << "// Flags for subtarget features that participate in "
-     << "instruction matching.\n";
-  OS << "enum SubtargetFeatureFlag : " << getMinimalRequiredFeaturesType(Info)
-     << " {\n";
-  for (const auto &SF : Info.SubtargetFeatures) {
-    const SubtargetFeatureInfo &SFI = SF.second;
-    OS << "  " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
-  }
-  OS << "  Feature_None = 0\n";
-  OS << "};\n\n";
-}
-
 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
   // Get the set of diagnostic types from all of the operand classes.
   std::set<StringRef> Types;
   for (const auto &OpClassEntry : Info.AsmOperandClasses) {
     if (!OpClassEntry.second->DiagnosticType.empty())
       Types.insert(OpClassEntry.second->DiagnosticType);
   }
static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
   unsigned MaxMask = 0;
   for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
     MaxMask |= OMI.OperandMask;
   }
 
   // Emit the static custom operand parsing table;
   OS << "namespace {\n";
   OS << "  struct OperandMatchEntry {\n";
-  OS << "    " << getMinimalRequiredFeaturesType(Info)
+  OS << "    " << getMinimalTypeForEnumBitfield(Info.SubtargetFeatures.size())
                << " RequiredFeatures;\n";
   OS << "    " << getMinimalTypeForRange(MaxMnemonicIndex)
                << " Mnemonic;\n";
   OS << "    " << getMinimalTypeForRange(std::distance(
                       Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
   OS << "    " << getMinimalTypeForRange(MaxMask)
                << " OperandMask;\n\n";
   OS << "    StringRef getMnemonic() const {\n";
#endif // NDEBUG
   OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
   emitOperandDiagnosticTypes(Info, OS);
   OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
 
   OS << "\n#ifdef GET_REGISTER_MATCHER\n";
   OS << "#undef GET_REGISTER_MATCHER\n\n";
 
   // Emit the subtarget feature enumeration.
-  emitSubtargetFeatureFlagEnumeration(Info, OS);
+  SubtargetFeatureInfo::emitSubtargetFeatureFlagEnumeration(
+      Info.SubtargetFeatures, OS);
 
   // Emit the function to match a register name to number.
   // This should be omitted for Mips target
   if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
     emitMatchRegisterName(Target, AsmParser, OS);
 
   if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterAltName"))
     emitMatchRegisterAltName(Target, AsmParser, OS);
#endif // NDEBUG
   // following the mnemonic.
   OS << "namespace {\n";
   OS << "  struct MatchEntry {\n";
   OS << "    " << getMinimalTypeForRange(MaxMnemonicIndex)
                << " Mnemonic;\n";
   OS << "    uint16_t Opcode;\n";
   OS << "    " << getMinimalTypeForRange(Info.Matchables.size())
                << " ConvertFn;\n";
-  OS << "    " << getMinimalRequiredFeaturesType(Info)
+  OS << "    " << getMinimalTypeForEnumBitfield(Info.SubtargetFeatures.size())
                << " RequiredFeatures;\n";
   OS << "    " << getMinimalTypeForRange(
                       std::distance(Info.Classes.begin(), Info.Classes.end()))
      << " Classes[" << MaxNumOperands << "];\n";
   OS << "    StringRef getMnemonic() const {\n";
   OS << "      return StringRef(MnemonicTable + Mnemonic + 1,\n";
   OS << "                       MnemonicTable[Mnemonic]);\n";
   OS << "    }\n";

utils/TableGen/CodeEmitterGen.cpp

 //===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // CodeEmitterGen uses the descriptions of instructions and their fields to
 // construct an automated code emitter: a function that, given a MachineInstr,
 // returns the (currently, 32-bit unsigned) value of the instruction.
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeGenTarget.h"
+#include "SubtargetFeatureInfo.h"
+#include "Types.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
 #include <map>
 #include <string>
 #include <vector>
 using namespace llvm;
void CodeEmitterGen::run(raw_ostream &o) {
   o << "  default:\n"
     << "    std::string msg;\n"
     << "    raw_string_ostream Msg(msg);\n"
     << "    Msg << \"Not supported instr: \" << MI;\n"
     << "    report_fatal_error(Msg.str());\n"
     << "  }\n"
     << "  return Value;\n"
     << "}\n\n";
+
+  const auto &All = SubtargetFeatureInfo::getAll(Records);
+  std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
+  SubtargetFeatures.insert(All.begin(), All.end());
+
+  o << "#ifdef ENABLE_INSTR_PREDICATE_VERIFIER\n"
+       "#undef ENABLE_INSTR_PREDICATE_VERIFIER\n";
+
+  // Emit the subtarget feature enumeration.
+  SubtargetFeatureInfo::emitSubtargetFeatureFlagEnumeration(SubtargetFeatures,
+                                                            o);
+
+  // Emit the available features compute function.
+  SubtargetFeatureInfo::emitComputeAvailableFeatures(
+      Target.getName(), "MCCodeEmitter", SubtargetFeatures, o);
+
+  // Emit the predicate verifier.
+  o << "void " << Target.getName()
+    << "MCCodeEmitter::verifyInstructionPredicates(\n"
+    << "    const MCInst &Inst, uint64_t AvailableFeatures) const {\n"
+    << "  static uint64_t RequiredFeatures[] = {\n";
+  unsigned InstIdx = 0;
+  for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
+    o << "    ";
+    for (Record *Predicate : Inst->TheDef->getValueAsListOfDefs("Predicates")) {
+      const auto &I = SubtargetFeatures.find(Predicate);
+      if (I != SubtargetFeatures.end())
+        o << I->second.getEnumName() << " | ";
+    }
+    o << "0, // " << Inst->TheDef->getName() << " = " << InstIdx << "\n";
+    InstIdx++;
+  }
+  o << "  };\n";
+  o << "  assert(Inst.getOpcode() < " << InstIdx << ");\n";
+  o << "  assert((AvailableFeatures & RequiredFeatures[Inst.getOpcode()])\n"
+    << "             == RequiredFeatures[Inst.getOpcode()] &&\n"
+    << "         \"Attempting to emit an instruction that doesn't satisfy the required\"\n"
+    << "         \"features\");\n";
+  o << "}\n";
+  o << "#endif\n";
 }
 
 } // End anonymous namespace
 
 namespace llvm {
 
 void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) {
   emitSourceFileHeader("Machine Code Emitter", OS);
   CodeEmitterGen(RK).run(OS);
 }
 
 } // End llvm namespace

utils/TableGen/SubtargetFeatureInfo.h

 //===- SubtargetFeatureInfo.h - Helpers for subtarget features ------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_UTIL_TABLEGEN_SUBTARGETFEATUREINFO_H
 #define LLVM_UTIL_TABLEGEN_SUBTARGETFEATUREINFO_H
 
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 
 #include <map>
+#include <string>
+#include <vector>
 
 namespace llvm {
 class Record;
 class RecordKeeper;
 
 /// Helper class for storing information on a subtarget feature which
 /// participates in instruction matching.
 struct SubtargetFeatureInfo {
   /// \brief The predicate record for this feature.
   Record *TheDef;
 
   /// \brief An unique index assigned to represent this feature.
   uint64_t Index;
 
   SubtargetFeatureInfo(Record *D, uint64_t Idx) : TheDef(D), Index(Idx) {}
 
   /// \brief The name of the enumerated constant identifying this feature.
   std::string getEnumName() const { return "Feature_" + TheDef->getName(); }
 
   void dump() const;
   static std::vector<std::pair<Record *, SubtargetFeatureInfo>>
   getAll(const RecordKeeper &Records);
 
+  /// Emit the subtarget feature flag definitions.
+  static void emitSubtargetFeatureFlagEnumeration(
+      std::map<Record *, SubtargetFeatureInfo, LessRecordByID>
+          &SubtargetFeatures,
+      raw_ostream &OS);
+
   /// Emit the function to compute the list of available features given a
   /// subtarget.
   static void emitComputeAvailableFeatures(
       std::string TargetName, std::string ClassName,
       std::map<Record *, SubtargetFeatureInfo, LessRecordByID>
           &SubtargetFeatures,
       raw_ostream &OS);
 };
 } // end namespace llvm
 
 #endif // LLVM_UTIL_TABLEGEN_SUBTARGETFEATUREINFO_H

utils/TableGen/SubtargetFeatureInfo.cpp

 //===- SubtargetFeatureInfo.cpp - Helpers for subtarget features ----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "SubtargetFeatureInfo.h"
 
+#include "Types.h"
 #include "llvm/TableGen/Record.h"
 
 #include <map>
 
 using namespace llvm;
 
 void SubtargetFeatureInfo::dump() const {
   errs() << getEnumName() << " " << Index << "\n";
if (Pred->getName().empty())
       PrintFatalError(Pred->getLoc(), "Predicate has no name!");
 
     SubtargetFeatures.emplace_back(
         Pred, SubtargetFeatureInfo(Pred, SubtargetFeatures.size()));
   }
   return SubtargetFeatures;
 }
 
+void SubtargetFeatureInfo::emitSubtargetFeatureFlagEnumeration(
+    std::map<Record *, SubtargetFeatureInfo, LessRecordByID> &SubtargetFeatures,
+    raw_ostream &OS) {
+  OS << "// Flags for subtarget features that participate in "
+     << "instruction matching.\n";
+  OS << "enum SubtargetFeatureFlag : "
+     << getMinimalTypeForEnumBitfield(SubtargetFeatures.size()) << " {\n";
+  for (const auto &SF : SubtargetFeatures) {
+    const SubtargetFeatureInfo &SFI = SF.second;
+    OS << "  " << SFI.getEnumName() << " = (1ULL << " << SFI.Index << "),\n";
+  }
+  OS << "  Feature_None = 0\n";
+  OS << "};\n\n";
+}
+
 void SubtargetFeatureInfo::emitComputeAvailableFeatures(
     std::string TargetName, std::string ClassName,
     std::map<Record *, SubtargetFeatureInfo, LessRecordByID> &SubtargetFeatures,
     raw_ostream &OS) {
   OS << "uint64_t " << TargetName << ClassName << "::\n"
      << "ComputeAvailableFeatures(const FeatureBitset& FB) const {\n";
   OS << "  uint64_t Features = 0;\n";
   for (const auto &SF : SubtargetFeatures) {

utils/TableGen/Types.h

 
 #include <cstdint>
 
 namespace llvm {
 /// Returns the smallest unsigned integer type that can hold the given range.
 /// MaxSize indicates the largest size of integer to consider (in bits) and only
 /// supports values of at least 32.
 const char *getMinimalTypeForRange(uint64_t Range, unsigned MaxSize = 64);
+
+/// Returns the smallest unsigned integer type that can hold the given bitfield.
+const char *getMinimalTypeForEnumBitfield(uint64_t Size);
 }
 
 #endif

utils/TableGen/Types.cpp

const char *llvm::getMinimalTypeForRange(uint64_t Range, unsigned MaxSize) {
   } else
     assert(Range < 0xFFFFFFFFULL && "Enum too large");
   if (Range > 0xFFFF)
     return "uint32_t";
   if (Range > 0xFF)
     return "uint16_t";
   return "uint8_t";
 }
+
+const char *llvm::getMinimalTypeForEnumBitfield(uint64_t Size) {
+  uint64_t MaxIndex = Size;
+  if (MaxIndex > 0)
+    MaxIndex--;
+  return getMinimalTypeForRange(1ULL << MaxIndex);
+}