[mips] Check that emitted instructions meet their predicates on Mips

[dsanders]

Summary

The following tests fail when this patch is applied.
Failing Tests (26):

LLVM :: CodeGen/Mips/cconv/callee-saved-float.ll
LLVM :: CodeGen/Mips/micromips-atomic1.ll
LLVM :: CodeGen/Mips/tailcall/tailcall-wrong-isa.ll
LLVM :: MC/Mips/cprestore-noreorder.s
LLVM :: MC/Mips/cprestore-reorder.s
LLVM :: MC/Mips/elf_eflags_mips16.s
LLVM :: MC/Mips/expansion-jal-sym-pic.s
LLVM :: MC/Mips/expr1.s
LLVM :: MC/Mips/micromips-16-bit-instructions.s
LLVM :: MC/Mips/micromips-alu-instructions.s
LLVM :: MC/Mips/micromips-branch-fixup.s
LLVM :: MC/Mips/micromips-branch-instructions.s
LLVM :: MC/Mips/micromips-control-instructions.s
LLVM :: MC/Mips/micromips-dsp/valid-micromips32r3.s
LLVM :: MC/Mips/micromips-el-fixup-data.s
LLVM :: MC/Mips/micromips-expansions.s
LLVM :: MC/Mips/micromips-fpu-instructions.s
LLVM :: MC/Mips/micromips-jump-instructions.s
LLVM :: MC/Mips/micromips-jump26.s
LLVM :: MC/Mips/micromips-tailr.s
LLVM :: MC/Mips/micromips/valid.s
LLVM :: MC/Mips/micromips32r6/valid.s
LLVM :: MC/Mips/mips2/valid.s
LLVM :: MC/Mips/mips3/valid.s
LLVM :: MC/Mips/mips4/valid.s
LLVM :: MC/Mips/mips5/valid.s

Some look like bugs but others look like they are deliberate (e.g.
SYNC is using a loophole to implement the MIPS-II version as an
alias of the MIPS32 version).

Depends on D25618

[dsanders]

llvm-commits has been deliberately left off of this since it's not intended for commit. I'm going to reference it from a bug report

[sdardis]

Thanks, started looking at this on Friday.

[sdardis]

Filed https://llvm.org/bugs/show_bug.cgi?id=30714 .

[dsanders]

In D25622#571447, @sdardis wrote:

Filed https://llvm.org/bugs/show_bug.cgi?id=30714 .

Thanks. I'm currently waiting for a bugzilla account for this email address.

[sdardis]

Looking at this again and with trunk, I'm seeing two failing tests with a small change inlined:

Failing Tests (2):

LLVM :: MC/Mips/expansion-jal-sym-pic.s
LLVM :: MC/Mips/micromips32r6/valid.s

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

189–190

This is in the wrong place. It should be:

259

Here. Moving this here means that we translate the instructions to the correct form, then verify it.

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h

 #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H
 
 #include "llvm/MC/MCCodeEmitter.h"
 #include "llvm/Support/DataTypes.h"
 
 using namespace llvm;
 
 namespace llvm {
+class FeatureBitset;
 class MCContext;
 class MCExpr;
 class MCInst;
 class MCInstrInfo;
 class MCFixup;
 class MCOperand;
 class MCSubtargetInfo;
 class raw_ostream;
public:
 
   unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo,
                                   SmallVectorImpl<MCFixup> &Fixups,
                                   const MCSubtargetInfo &STI) const;
 
   unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo,
                                     SmallVectorImpl<MCFixup> &Fixups,
                                     const MCSubtargetInfo &STI) const;
-  private:
+
   void LowerCompactBranch(MCInst& Inst) const;
+  uint64_t ComputeAvailableFeatures(const FeatureBitset &FB) const;
+  void verifyInstructionPredicates(const MCInst &MI,
+                                   uint64_t AvailableFeatures) const;
 }; // class MipsMCCodeEmitter
 } // namespace llvm.
 
 #endif

lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp

 
 /// encodeInstruction - Emit the instruction.
 /// Size the instruction with Desc.getSize().
 void MipsMCCodeEmitter::
 encodeInstruction(const MCInst &MI, raw_ostream &OS,
                   SmallVectorImpl<MCFixup> &Fixups,
                   const MCSubtargetInfo &STI) const
 {
+  verifyInstructionPredicates(MI,
+                              ComputeAvailableFeatures(STI.getFeatureBits()));
 
   // Non-pseudo instructions that get changed for direct object
   // only based on operand values.
   // If this list of instructions get much longer we will move
   // the check to a function call. Until then, this is more efficient.
   MCInst TmpInst = MI;
   switch (MI.getOpcode()) {
   // If shift amount is >= 32 it the inst needs to be lowered further
if (NewOpcode != -1) {
       if (Fixups.size() > N)
         Fixups.pop_back();
 
       Opcode = NewOpcode;
       TmpInst.setOpcode (NewOpcode);
       Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
     }
   }
 
   const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
 
   // Get byte count of instruction
   unsigned Size = Desc.getSize();
   if (!Size)
     llvm_unreachable("Desc.getSize() returns 0");
 
   EmitInstruction(Binary, Size, STI, OS);
MipsMCCodeEmitter::getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo,
   const MCOperand &MO = MI.getOperand(OpNo);
   assert(MO.isImm() && "getSimm23Lsl2Encoding expects only an immediate");
   // The immediate is encoded as 'immediate >> 2'.
   unsigned Res = static_cast<unsigned>(MO.getImm());
   assert((Res & 3) == 0);
   return Res >> 2;
 }
 
+#define ENABLE_INSTR_PREDICATE_VERIFIER
 #include "MipsGenMCCodeEmitter.inc"