[arm] Check that emitted instructions meet their predicates on ARM

[dsanders]

Summary

The following tests fail after this patch:

LLVM :: CodeGen/ARM/debug-segmented-stacks.ll
LLVM :: CodeGen/ARM/segmented-stacks-dynamic.ll
LLVM :: CodeGen/ARM/segmented-stacks.ll
LLVM :: MC/ARM/directive-arch-armv4.s
LLVM :: MC/ARM/mul-v4.s

Depends on D25618

[dsanders]

llvm-commits has been deliberately left off of this since it's not intended for commit. I'm going to reference it from a bug report

lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

for (unsigned i = 0; i != Size; ++i) {
       unsigned Shift = IsLittleEndian ? i * 8 : (Size - 1 - i) * 8;
       EmitByte((Val >> Shift) & 0xff, OS);
     }
   }
 
   void encodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
                          const MCSubtargetInfo &STI) const override;
+
+private:
+  uint64_t ComputeAvailableFeatures(const FeatureBitset &FB) const;
+  void verifyInstructionPredicates(const MCInst &MI,
+                                   uint64_t AvailableFeatures) const;
 };
 
 } // end anonymous namespace
 
 MCCodeEmitter *llvm::createARMLEMCCodeEmitter(const MCInstrInfo &MCII,
                                               const MCRegisterInfo &MRI,
                                               MCContext &Ctx) {
   return new ARMMCCodeEmitter(MCII, Ctx, true);
getShiftRight64Imm(const MCInst &MI, unsigned Op,
                    const MCSubtargetInfo &STI) const {
   return 64 - MI.getOperand(Op).getImm();
 }
 
 void ARMMCCodeEmitter::
 encodeInstruction(const MCInst &MI, raw_ostream &OS,
                   SmallVectorImpl<MCFixup> &Fixups,
                   const MCSubtargetInfo &STI) const {
+  verifyInstructionPredicates(MI,
+                              ComputeAvailableFeatures(STI.getFeatureBits()));
+
   // Pseudo instructions don't get encoded.
   const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
   uint64_t TSFlags = Desc.TSFlags;
   if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
     return;
 
   int Size;
   if (Desc.getSize() == 2 || Desc.getSize() == 4)
     Size = Desc.getSize();
   else
     llvm_unreachable("Unexpected instruction size!");
 
   uint32_t Binary = getBinaryCodeForInstr(MI, Fixups, STI);
   // Thumb 32-bit wide instructions need to emit the high order halfword
   // first.
   if (isThumb(STI) && Size == 4) {
     EmitConstant(Binary >> 16, 2, OS);
     EmitConstant(Binary & 0xffff, 2, OS);
   } else
     EmitConstant(Binary, Size, OS);
   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
 }
 
+#define ENABLE_INSTR_PREDICATE_VERIFIER
 #include "ARMGenMCCodeEmitter.inc"