Assuming the ADD is nsw then it may be sign-extended to merge with a SHL op in a similar fold to the existing (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) fold.
This is most useful for helping to expose address math for X86, but has also touched several aarch64 test cases as well - I think they are benign but would like some confirmation.
@craig.topper RISCV uses isDesirableToCommuteWithShift to prevent creating shifted adds with larger offsets - should this be extended to peek through ext nodes as well? If so I'll need to add suitable test coverage. IIRC there's implicit extension on RISCV targets that I'm not very familiar with.
Do we need to consider the possibility of overflow when c1 << c2?