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Differential D159147

[DAGCombiner] Combine trunc (splat_vector x) -> splat_vector (trunc x)
ClosedPublic

Authored by luke on Aug 29 2023, 4:44 PM.

Details

Reviewers
craig.topper
reames
RKSimon
Commits
rG3a4ad45a2c5e: [DAGCombiner] Combine trunc (splat_vector x) -> splat_vector (trunc x)
Summary

From the discussion in https://reviews.llvm.org/D158853, moving the truncate
into the splat helps more splatted scalar operands get selected on RISC-V, and
also avoids the need for splat_vector_parts on RV32.

Diff Detail

Event Timeline

luke created this revision.Aug 29 2023, 4:44 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 29 2023, 4:44 PM
Herald added subscribers: asb, sunshaoce, pmatos and 22 others. · View Herald Transcript
luke requested review of this revision.Aug 29 2023, 4:44 PM
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RKSimon accepted this revision.Aug 30 2023, 5:54 AM

LGTM

This revision is now accepted and ready to land.Aug 30 2023, 5:54 AM
This revision was landed with ongoing or failed builds.Aug 30 2023, 7:23 AM
Closed by commit rG3a4ad45a2c5e: [DAGCombiner] Combine trunc (splat_vector x) -> splat_vector (trunc x) (authored by luke). · Explain Why
This revision was automatically updated to reflect the committed changes.
luke added a commit: rG3a4ad45a2c5e: [DAGCombiner] Combine trunc (splat_vector x) -> splat_vector (trunc x).

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
10 lines
test/
CodeGen/
RISCV/
rvv/
58 lines
138 lines
80 lines

Diff 554522

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 14,454 Lines • ▼ Show 20 Lines if (N0.getOpcode() == ISD::BUILD_VECTOR && !LegalOperations &&
SmallVector<SDValue, 8> TruncOps; SmallVector<SDValue, 8> TruncOps;
for (const SDValue &Op : N0->op_values()) { for (const SDValue &Op : N0->op_values()) {
SDValue TruncOp = DAG.getNode(ISD::TRUNCATE, DL, SVT, Op); SDValue TruncOp = DAG.getNode(ISD::TRUNCATE, DL, SVT, Op);
TruncOps.push_back(TruncOp); TruncOps.push_back(TruncOp);
} }
return DAG.getBuildVector(VT, DL, TruncOps); return DAG.getBuildVector(VT, DL, TruncOps);
} }
// trunc (splat_vector x) -> splat_vector (trunc x)
if (N0.getOpcode() == ISD::SPLAT_VECTOR &&
(!LegalTypes || TLI.isTypeLegal(VT.getScalarType())) &&
(!LegalOperations || TLI.isOperationLegal(ISD::SPLAT_VECTOR, VT))) {
SDLoc DL(N);
EVT SVT = VT.getScalarType();
return DAG.getSplatVector(
VT, DL, DAG.getNode(ISD::TRUNCATE, DL, SVT, N0->getOperand(0)));
}
// Fold a series of buildvector, bitcast, and truncate if possible. // Fold a series of buildvector, bitcast, and truncate if possible.
// For example fold // For example fold
// (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to
// (2xi32 (buildvector x, y)). // (2xi32 (buildvector x, y)).
if (Level == AfterLegalizeVectorOps && VT.isVector() && if (Level == AfterLegalizeVectorOps && VT.isVector() &&
N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() &&
N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
N0.getOperand(0).hasOneUse()) { N0.getOperand(0).hasOneUse()) {
▲ Show 20 Lines • Show All 13,168 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \ ; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV32 %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \ ; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
; RUN: -verify-machineinstrs < %s | FileCheck -check-prefixes=CHECK,RV64 %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i32> @vnsrl_wx_i64_nxv1i32(<vscale x 1 x i64> %va, i64 %b) { define <vscale x 1 x i32> @vnsrl_wx_i64_nxv1i32(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vnsrl_wx_i64_nxv1i32: ; CHECK-LABEL: vnsrl_wx_i64_nxv1i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wx v8, v8, a0 ; CHECK-NEXT: vnsrl.wx v8, v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
▲ Show 20 Lines • Show All 615 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64> %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = lshr <vscale x 8 x i64> %va, %vb %x = lshr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32> %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y ret <vscale x 8 x i32> %y
} }
define <vscale x 1 x i16> @vnsrl_wx_i64_nxv1i16(<vscale x 1 x i32> %va, i64 %b) { define <vscale x 1 x i16> @vnsrl_wx_i64_nxv1i16(<vscale x 1 x i32> %va, i64 %b) {
; RV32-LABEL: vnsrl_wx_i64_nxv1i16: ; CHECK-LABEL: vnsrl_wx_i64_nxv1i16:
; RV32: # %bb.0: ; CHECK: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; RV32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vnsrl.wx v8, v8, a0
; RV32-NEXT: sw a1, 12(sp) ; CHECK-NEXT: ret
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vnsrl.wi v9, v9, 0
; RV32-NEXT: vsrl.vv v8, v8, v9
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vnsrl_wx_i64_nxv1i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; RV64-NEXT: vnsrl.wx v8, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%vb = trunc <vscale x 1 x i64> %splat to <vscale x 1 x i32> %vb = trunc <vscale x 1 x i64> %splat to <vscale x 1 x i32>
%x = lshr <vscale x 1 x i32> %va, %vb %x = lshr <vscale x 1 x i32> %va, %vb
%y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i16> %y = trunc <vscale x 1 x i32> %x to <vscale x 1 x i16>
ret <vscale x 1 x i16> %y ret <vscale x 1 x i16> %y
} }
define <vscale x 1 x i8> @vnsrl_wx_i64_nxv1i8(<vscale x 1 x i16> %va, i64 %b) { define <vscale x 1 x i8> @vnsrl_wx_i64_nxv1i8(<vscale x 1 x i16> %va, i64 %b) {
; RV32-LABEL: vnsrl_wx_i64_nxv1i8: ; CHECK-LABEL: vnsrl_wx_i64_nxv1i8:
; RV32: # %bb.0: ; CHECK: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vnsrl.wx v8, v8, a0
; RV32-NEXT: sw a1, 12(sp) ; CHECK-NEXT: ret
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; RV32-NEXT: vlse64.v v9, (a0), zero
; RV32-NEXT: vnsrl.wi v9, v9, 0
; RV32-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; RV32-NEXT: vnsrl.wi v9, v9, 0
; RV32-NEXT: vsrl.vv v8, v8, v9
; RV32-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; RV32-NEXT: vnsrl.wi v8, v8, 0
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64-LABEL: vnsrl_wx_i64_nxv1i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV64-NEXT: vnsrl.wx v8, v8, a0
; RV64-NEXT: ret
%head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%vb = trunc <vscale x 1 x i64> %splat to <vscale x 1 x i16> %vb = trunc <vscale x 1 x i64> %splat to <vscale x 1 x i16>
%x = lshr <vscale x 1 x i16> %va, %vb %x = lshr <vscale x 1 x i16> %va, %vb
%y = trunc <vscale x 1 x i16> %x to <vscale x 1 x i8> %y = trunc <vscale x 1 x i16> %x to <vscale x 1 x i8>
ret <vscale x 1 x i8> %y ret <vscale x 1 x i8> %y
} }

llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV32 ; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,CHECK-RV64 ; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB32 ; RUN: llc -mtriple=riscv32 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB,CHECK-ZVBB64 ; RUN: llc -mtriple=riscv64 -mattr=+v,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVBB
; ============================================================================== ; ==============================================================================
; i32 -> i64 ; i32 -> i64
; ============================================================================== ; ==============================================================================
define <vscale x 2 x i64> @vwsll_vv_nxv2i64_sext(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) { define <vscale x 2 x i64> @vwsll_vv_nxv2i64_sext(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
; CHECK-LABEL: vwsll_vv_nxv2i64_sext: ; CHECK-LABEL: vwsll_vv_nxv2i64_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
▲ Show 20 Lines • Show All 268 Lines • ▼ Show 20 Lines
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32> %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
%y = zext <vscale x 4 x i16> %b to <vscale x 4 x i32> %y = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>
%z = shl <vscale x 4 x i32> %x, %y %z = shl <vscale x 4 x i32> %x, %y
ret <vscale x 4 x i32> %z ret <vscale x 4 x i32> %z
} }
define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b) { define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b) {
; CHECK-RV32-LABEL: vwsll_vx_i64_nxv4i32: ; CHECK-LABEL: vwsll_vx_i64_nxv4i32:
; CHECK-RV32: # %bb.0: ; CHECK: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16 ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-RV32-NEXT: sw a1, 12(sp) ; CHECK-NEXT: vsll.vx v8, v10, a0
; CHECK-RV32-NEXT: sw a0, 8(sp) ; CHECK-NEXT: ret
; CHECK-RV32-NEXT: addi a0, sp, 8 ;
; CHECK-RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv4i32:
; CHECK-RV32-NEXT: vlse64.v v12, (a0), zero ; CHECK-ZVBB: # %bb.0:
; CHECK-RV32-NEXT: vzext.vf2 v10, v8 ; CHECK-ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-RV32-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0
; CHECK-RV32-NEXT: vsll.vv v8, v10, v8 ; CHECK-ZVBB-NEXT: vmv2r.v v8, v10
; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-ZVBB-NEXT: ret
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vwsll_vx_i64_nxv4i32:
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v12, a0
; CHECK-RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-RV64-NEXT: vzext.vf2 v10, v8
; CHECK-RV64-NEXT: vnsrl.wi v8, v12, 0
; CHECK-RV64-NEXT: vsll.vv v8, v10, v8
; CHECK-RV64-NEXT: ret
;
; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv4i32:
; CHECK-ZVBB32: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16
; CHECK-ZVBB32-NEXT: sw a1, 12(sp)
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v12, (a0), zero
; CHECK-ZVBB32-NEXT: vzext.vf2 v10, v8
; CHECK-ZVBB32-NEXT: vnsrl.wi v8, v12, 0
; CHECK-ZVBB32-NEXT: vsll.vv v8, v10, v8
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv4i32:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-ZVBB64-NEXT: vwsll.vx v10, v8, a0
; CHECK-ZVBB64-NEXT: vmv2r.v v8, v10
; CHECK-ZVBB64-NEXT: ret
%head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32> %x = zext <vscale x 4 x i16> %a to <vscale x 4 x i32>
%y = trunc <vscale x 4 x i64> %splat to <vscale x 4 x i32> %y = trunc <vscale x 4 x i64> %splat to <vscale x 4 x i32>
%z = shl <vscale x 4 x i32> %x, %y %z = shl <vscale x 4 x i32> %x, %y
ret <vscale x 4 x i32> %z ret <vscale x 4 x i32> %z
} }
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; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16> %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
%y = zext <vscale x 8 x i8> %b to <vscale x 8 x i16> %y = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>
%z = shl <vscale x 8 x i16> %x, %y %z = shl <vscale x 8 x i16> %x, %y
ret <vscale x 8 x i16> %z ret <vscale x 8 x i16> %z
} }
define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b) { define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b) {
; CHECK-RV32-LABEL: vwsll_vx_i64_nxv8i16: ; CHECK-LABEL: vwsll_vx_i64_nxv8i16:
; CHECK-RV32: # %bb.0: ; CHECK: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16 ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-RV32-NEXT: sw a1, 12(sp) ; CHECK-NEXT: vsll.vx v8, v10, a0
; CHECK-RV32-NEXT: sw a0, 8(sp) ; CHECK-NEXT: ret
; CHECK-RV32-NEXT: addi a0, sp, 8 ;
; CHECK-RV32-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-ZVBB-LABEL: vwsll_vx_i64_nxv8i16:
; CHECK-RV32-NEXT: vlse64.v v16, (a0), zero ; CHECK-ZVBB: # %bb.0:
; CHECK-RV32-NEXT: vzext.vf2 v10, v8 ; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0
; CHECK-RV32-NEXT: vnsrl.wi v12, v16, 0 ; CHECK-ZVBB-NEXT: vmv2r.v v8, v10
; CHECK-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; CHECK-ZVBB-NEXT: ret
; CHECK-RV32-NEXT: vnsrl.wi v8, v12, 0
; CHECK-RV32-NEXT: vsll.vv v8, v10, v8
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vwsll_vx_i64_nxv8i16:
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v16, a0
; CHECK-RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-RV64-NEXT: vzext.vf2 v10, v8
; CHECK-RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-RV64-NEXT: vnsrl.wi v12, v16, 0
; CHECK-RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-RV64-NEXT: vnsrl.wi v8, v12, 0
; CHECK-RV64-NEXT: vsll.vv v8, v10, v8
; CHECK-RV64-NEXT: ret
;
; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv8i16:
; CHECK-ZVBB32: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16
; CHECK-ZVBB32-NEXT: sw a1, 12(sp)
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v16, (a0), zero
; CHECK-ZVBB32-NEXT: vzext.vf2 v10, v8
; CHECK-ZVBB32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-ZVBB32-NEXT: vnsrl.wi v12, v16, 0
; CHECK-ZVBB32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-ZVBB32-NEXT: vnsrl.wi v8, v12, 0
; CHECK-ZVBB32-NEXT: vsll.vv v8, v10, v8
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret
;
; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv8i16:
; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-ZVBB64-NEXT: vwsll.vx v10, v8, a0
; CHECK-ZVBB64-NEXT: vmv2r.v v8, v10
; CHECK-ZVBB64-NEXT: ret
%head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 8 x i32> zeroinitializer
%x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16> %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
%y = trunc <vscale x 8 x i64> %splat to <vscale x 8 x i16> %y = trunc <vscale x 8 x i64> %splat to <vscale x 8 x i16>
%z = shl <vscale x 8 x i16> %x, %y %z = shl <vscale x 8 x i16> %x, %y
ret <vscale x 8 x i16> %z ret <vscale x 8 x i16> %z
} }
define <vscale x 8 x i16> @vwsll_vx_i32_nxv8i16(<vscale x 8 x i8> %a, i32 %b) { define <vscale x 8 x i16> @vwsll_vx_i32_nxv8i16(<vscale x 8 x i8> %a, i32 %b) {
; CHECK-LABEL: vwsll_vx_i32_nxv8i16: ; CHECK-LABEL: vwsll_vx_i32_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vsll.vx v8, v10, a0
; CHECK-NEXT: vsll.vv v8, v10, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv8i16: ; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv8i16:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-ZVBB-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0 ; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0
; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: vmv2r.v v8, v10
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
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llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll

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%y = zext <vscale x 4 x i16> %b to <vscale x 4 x i32> %y = zext <vscale x 4 x i16> %b to <vscale x 4 x i32>
%z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m, i32 %vl) %z = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m, i32 %vl)
ret <vscale x 4 x i32> %z ret <vscale x 4 x i32> %z
} }
define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %vl) { define <vscale x 4 x i32> @vwsll_vx_i64_nxv4i32(<vscale x 4 x i16> %a, i64 %b, <vscale x 4 x i1> %m, i32 zeroext %vl) {
; CHECK-RV32-LABEL: vwsll_vx_i64_nxv4i32: ; CHECK-RV32-LABEL: vwsll_vx_i64_nxv4i32:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a1, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-RV32-NEXT: vlse64.v v12, (a0), zero
; CHECK-RV32-NEXT: vzext.vf2 v10, v8 ; CHECK-RV32-NEXT: vzext.vf2 v10, v8
; CHECK-RV32-NEXT: vnsrl.wi v8, v12, 0
; CHECK-RV32-NEXT: vsetvli zero, a2, e32, m2, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a2, e32, m2, ta, ma
; CHECK-RV32-NEXT: vsll.vv v8, v10, v8, v0.t ; CHECK-RV32-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vwsll_vx_i64_nxv4i32: ; CHECK-RV64-LABEL: vwsll_vx_i64_nxv4i32:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetvli a2, zero, e64, m4, ta, ma ; CHECK-RV64-NEXT: vsetvli a2, zero, e32, m2, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v12, a0
; CHECK-RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-RV64-NEXT: vzext.vf2 v10, v8 ; CHECK-RV64-NEXT: vzext.vf2 v10, v8
; CHECK-RV64-NEXT: vnsrl.wi v8, v12, 0
; CHECK-RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; CHECK-RV64-NEXT: vsll.vv v8, v10, v8, v0.t ; CHECK-RV64-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv4i32: ; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv4i32:
; CHECK-ZVBB32: # %bb.0: ; CHECK-ZVBB32: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16 ; CHECK-ZVBB32-NEXT: vsetvli zero, a2, e16, m1, ta, ma
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-ZVBB32-NEXT: vwsll.vx v10, v8, a0, v0.t
; CHECK-ZVBB32-NEXT: sw a1, 12(sp) ; CHECK-ZVBB32-NEXT: vmv2r.v v8, v10
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v12, (a0), zero
; CHECK-ZVBB32-NEXT: vzext.vf2 v10, v8
; CHECK-ZVBB32-NEXT: vnsrl.wi v8, v12, 0
; CHECK-ZVBB32-NEXT: vsetvli zero, a2, e32, m2, ta, ma
; CHECK-ZVBB32-NEXT: vsll.vv v8, v10, v8, v0.t
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret ; CHECK-ZVBB32-NEXT: ret
; ;
; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv4i32: ; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv4i32:
; CHECK-ZVBB64: # %bb.0: ; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-ZVBB64-NEXT: vsetvli zero, a1, e16, m1, ta, ma
; CHECK-ZVBB64-NEXT: vwsll.vx v10, v8, a0, v0.t ; CHECK-ZVBB64-NEXT: vwsll.vx v10, v8, a0, v0.t
; CHECK-ZVBB64-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB64-NEXT: vmv2r.v v8, v10
; CHECK-ZVBB64-NEXT: ret ; CHECK-ZVBB64-NEXT: ret
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%y = zext <vscale x 8 x i8> %b to <vscale x 8 x i16> %y = zext <vscale x 8 x i8> %b to <vscale x 8 x i16>
%z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m, i32 %vl) %z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m, i32 %vl)
ret <vscale x 8 x i16> %z ret <vscale x 8 x i16> %z
} }
define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %vl) { define <vscale x 8 x i16> @vwsll_vx_i64_nxv8i16(<vscale x 8 x i8> %a, i64 %b, <vscale x 8 x i1> %m, i32 zeroext %vl) {
; CHECK-RV32-LABEL: vwsll_vx_i64_nxv8i16: ; CHECK-RV32-LABEL: vwsll_vx_i64_nxv8i16:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: addi sp, sp, -16
; CHECK-RV32-NEXT: .cfi_def_cfa_offset 16
; CHECK-RV32-NEXT: sw a1, 12(sp)
; CHECK-RV32-NEXT: sw a0, 8(sp)
; CHECK-RV32-NEXT: addi a0, sp, 8
; CHECK-RV32-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-RV32-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (a0), zero
; CHECK-RV32-NEXT: vzext.vf2 v10, v8 ; CHECK-RV32-NEXT: vzext.vf2 v10, v8
; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-RV32-NEXT: vnsrl.wi v12, v16, 0
; CHECK-RV32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-RV32-NEXT: vnsrl.wi v8, v12, 0
; CHECK-RV32-NEXT: vsetvli zero, a2, e16, m2, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a2, e16, m2, ta, ma
; CHECK-RV32-NEXT: vsll.vv v8, v10, v8, v0.t ; CHECK-RV32-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vwsll_vx_i64_nxv8i16: ; CHECK-RV64-LABEL: vwsll_vx_i64_nxv8i16:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli a2, zero, e16, m2, ta, ma
; CHECK-RV64-NEXT: vmv.v.x v16, a0
; CHECK-RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-RV64-NEXT: vzext.vf2 v10, v8 ; CHECK-RV64-NEXT: vzext.vf2 v10, v8
; CHECK-RV64-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-RV64-NEXT: vnsrl.wi v12, v16, 0
; CHECK-RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-RV64-NEXT: vnsrl.wi v8, v12, 0
; CHECK-RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a1, e16, m2, ta, ma
; CHECK-RV64-NEXT: vsll.vv v8, v10, v8, v0.t ; CHECK-RV64-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv8i16: ; CHECK-ZVBB32-LABEL: vwsll_vx_i64_nxv8i16:
; CHECK-ZVBB32: # %bb.0: ; CHECK-ZVBB32: # %bb.0:
; CHECK-ZVBB32-NEXT: addi sp, sp, -16 ; CHECK-ZVBB32-NEXT: vsetvli zero, a2, e8, m1, ta, ma
; CHECK-ZVBB32-NEXT: .cfi_def_cfa_offset 16 ; CHECK-ZVBB32-NEXT: vwsll.vx v10, v8, a0, v0.t
; CHECK-ZVBB32-NEXT: sw a1, 12(sp) ; CHECK-ZVBB32-NEXT: vmv2r.v v8, v10
; CHECK-ZVBB32-NEXT: sw a0, 8(sp)
; CHECK-ZVBB32-NEXT: addi a0, sp, 8
; CHECK-ZVBB32-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-ZVBB32-NEXT: vlse64.v v16, (a0), zero
; CHECK-ZVBB32-NEXT: vzext.vf2 v10, v8
; CHECK-ZVBB32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-ZVBB32-NEXT: vnsrl.wi v12, v16, 0
; CHECK-ZVBB32-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-ZVBB32-NEXT: vnsrl.wi v8, v12, 0
; CHECK-ZVBB32-NEXT: vsetvli zero, a2, e16, m2, ta, ma
; CHECK-ZVBB32-NEXT: vsll.vv v8, v10, v8, v0.t
; CHECK-ZVBB32-NEXT: addi sp, sp, 16
; CHECK-ZVBB32-NEXT: ret ; CHECK-ZVBB32-NEXT: ret
; ;
; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv8i16: ; CHECK-ZVBB64-LABEL: vwsll_vx_i64_nxv8i16:
; CHECK-ZVBB64: # %bb.0: ; CHECK-ZVBB64: # %bb.0:
; CHECK-ZVBB64-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-ZVBB64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-ZVBB64-NEXT: vwsll.vx v10, v8, a0, v0.t ; CHECK-ZVBB64-NEXT: vwsll.vx v10, v8, a0, v0.t
; CHECK-ZVBB64-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB64-NEXT: vmv2r.v v8, v10
; CHECK-ZVBB64-NEXT: ret ; CHECK-ZVBB64-NEXT: ret
%head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0 %head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 8 x i32> zeroinitializer
%x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16> %x = zext <vscale x 8 x i8> %a to <vscale x 8 x i16>
%y = trunc <vscale x 8 x i64> %splat to <vscale x 8 x i16> %y = trunc <vscale x 8 x i64> %splat to <vscale x 8 x i16>
%z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m, i32 %vl) %z = call <vscale x 8 x i16> @llvm.vp.shl.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m, i32 %vl)
ret <vscale x 8 x i16> %z ret <vscale x 8 x i16> %z
} }
define <vscale x 8 x i16> @vwsll_vx_i32_nxv8i16(<vscale x 8 x i8> %a, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %vl) { define <vscale x 8 x i16> @vwsll_vx_i32_nxv8i16(<vscale x 8 x i8> %a, i32 %b, <vscale x 8 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vwsll_vx_i32_nxv8i16: ; CHECK-LABEL: vwsll_vx_i32_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a2, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vzext.vf2 v10, v8 ; CHECK-NEXT: vzext.vf2 v10, v8
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
; CHECK-NEXT: vsll.vv v8, v10, v8, v0.t ; CHECK-NEXT: vsll.vx v8, v10, a0, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv8i16: ; CHECK-ZVBB-LABEL: vwsll_vx_i32_nxv8i16:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-ZVBB-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0, v0.t ; CHECK-ZVBB-NEXT: vwsll.vx v10, v8, a0, v0.t
; CHECK-ZVBB-NEXT: vmv2r.v v8, v10 ; CHECK-ZVBB-NEXT: vmv2r.v v8, v10
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
▲ Show 20 Lines • Show All 101 Lines • Show Last 20 Lines