[mlir][vector] Rename vector reductions: `maxf` → `maximumf`, `minf` → `minimumf`

[unterumarmung]

Summary

This patch is part of a larger initiative aimed at fixing floating-point max and min operations in MLIR: https://discourse.llvm.org/t/rfc-fix-floating-point-max-and-min-operations-in-mlir/72671.

Here, we are addressing task 2.1 from the plan, which involves renaming the vector reductions to align with the semantics of the corresponding LLVM intrinsics.

[mravishankar]

I think this is dependent on https://github.com/llvm/llvm-project/commit/dad9de0ae5360b18c890985d212bec266bf8c122. We've been carrying a revert of this commit for a while now cause it triggers an unsupported path in the CUDA backend for architectures earlier than Ampere. Would be too much to carry a chain of reverts. We should either make the lowering added in that commit opt-in/opt-out or wait for the issue in NVPTX backend to get fixed before moving forward here. I am sorry for delaying planned work, but this is having a downstream impact.

[jpienaar]

@tra for visibility

[unterumarmung]

In D158618#4610404, @mravishankar wrote:

I think this is dependent on https://github.com/llvm/llvm-project/commit/dad9de0ae5360b18c890985d212bec266bf8c122. We've been carrying a revert of this commit for a while now cause it triggers an unsupported path in the CUDA backend for architectures earlier than Ampere. Would be too much to carry a chain of reverts. We should either make the lowering added in that commit opt-in/opt-out or wait for the issue in NVPTX backend to get fixed before moving forward here. I am sorry for delaying planned work, but this is having a downstream impact.

Hi there, @mravishankar!

Both @dcaballe and I completely understand your concerns. After discussing it, we've come to the decision not to revert the commit you mentioned upstream. Instead, we're going to push forward with the RFC as planned. Our main focus will be on tasks 2.1, 2.3, and 2.4, giving them the highest priority. This way, we can proceed with the commit in place and also address the NVPTX backend issue.

Regarding the patch, I want to highlight that I haven't completely removed support for minf and maxf. The reason behind this decision is that there are other operations reliant on the CombiningKind, and I'm being cautious not to inadvertently disrupt anything. That being said, I'm planning to easily reintroduce minf and maxf with the new semantics that have been present in LLVM for a longer duration. These intrinsics should be compatible with the older backends. To achieve this, I intend to implement both tasks 2.3 and 2.4 in the upcoming patch together.

Hope this clarifies the plan moving forward!

[dcaballe]

Just to provide a bit more context, we are trying to attack the NVPTX issue from two fronts: 1) @tra is looking into https://reviews.llvm.org/D158053 as a promising way to fix the issue quickly, 2) We are starting the min/max work from point 2.1 (and not 1.1) so that we can quickly introduce the minnum/maxnum variants that will provide an alternative lowering that is supported by NVPTX. Once those variants are in place, we can temporarily lower to them while the NVPTX issue is fixed, if that hasn't happened before. Does it sound reasonable?

[tra]

In D158618#4610429, @jpienaar wrote:

@tra for visibility

BTW, NVPTX is not the only back-end which can't handle fminimum/fmaximum. Only some LLVM back-ends can currently lower fminimum/fmaximum IR instructions. Many just fail. E.g. ppc64: https://godbolt.org/z/8qb3Yxd9Y

https://reviews.llvm.org/D158238 should bring generic lowering for fminimum/fmaximum which can be used to provide fall-back implementation for the targets that don't support NaN-propagating min/max, but we'll likely need more changes to plumb it in on relevant targets (e.g. NVPTX for pre-sm80 GPUs).

It may be useful to provide some sort of escape hatch option to avoid generating fminimum/fmaximum, if this is intended to target platforms other than x86, aarch64,risc-v and nvptx.

[mravishankar]

In D158618#4610486, @unterumarmung wrote:

In D158618#4610404, @mravishankar wrote:

I think this is dependent on https://github.com/llvm/llvm-project/commit/dad9de0ae5360b18c890985d212bec266bf8c122. We've been carrying a revert of this commit for a while now cause it triggers an unsupported path in the CUDA backend for architectures earlier than Ampere. Would be too much to carry a chain of reverts. We should either make the lowering added in that commit opt-in/opt-out or wait for the issue in NVPTX backend to get fixed before moving forward here. I am sorry for delaying planned work, but this is having a downstream impact.

Hi there, @mravishankar!

Both @dcaballe and I completely understand your concerns. After discussing it, we've come to the decision not to revert the commit you mentioned upstream. Instead, we're going to push forward with the RFC as planned. Our main focus will be on tasks 2.1, 2.3, and 2.4, giving them the highest priority. This way, we can proceed with the commit in place and also address the NVPTX backend issue.

Regarding the patch, I want to highlight that I haven't completely removed support for minf and maxf. The reason behind this decision is that there are other operations reliant on the CombiningKind, and I'm being cautious not to inadvertently disrupt anything. That being said, I'm planning to easily reintroduce minf and maxf with the new semantics that have been present in LLVM for a longer duration. These intrinsics should be compatible with the older backends. To achieve this, I intend to implement both tasks 2.3 and 2.4 in the upcoming patch together.

Hope this clarifies the plan moving forward!

Well, that doesnt address currently broken users downstream. Looks like the issue is not limited to NVPTX backend alone. Given that there are several end-to-end flows where these are used there needs to be a way to opt out of these transformations till all the backends can handle this lowering. As it stands I dont see an easy way to do it, and that should be a blocker moving forward. Please provide some guidance for what downstream users should do to avoid hitting compilation errors with this change.

[dcaballe]

Please provide some guidance for what downstream users should do to avoid hitting compilation errors with this change.

When 2.3 and 2.4 points are implemented, we'll be able to temporarily lower to the non-NaN propagating minnum/maxnum variants for those backends without support for the NaN propagating ones.
Perhaps we can wait to land this patch until 2.3 and 2.4 are implemented and land everything in one shot.

[unterumarmung]

Add default clause to the switch MaskedReductionOpConversion because there is no masked intrinsics for maximumf/minumumf vector reductions that match the needed semantics

[dcaballe]

mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp

899

We also need a workaround for this before landing or https://github.com/llvm/llvm-project/issues/64940 to be fixed. Masked reductions are common to be generate. We could generate a vector select that sets the masked-out elements of the input to the identity value, and then use the unmasked version of the intrinsics.

[unterumarmung]

mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp

899

I agree.
I suggest to implement it in a separate patch, so we do not overcomplicate this one, and then merge all 3 patches at the same time.
I'll look into creating the workaround with the unmasked intrinsic and selecting the needed values. Could you please share a pseudocode of the possible lowering or some existing examples from the codebase? I'd help out a lot. Thanks.

[unterumarmung]

mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp

899

It'd*

[unterumarmung]

@mravishankar @dcaballe Could you please re-review the PR?

[mravishankar]

In D158618#4617754, @unterumarmung wrote:

@mravishankar @dcaballe Could you please re-review the PR?

Could one of you give me a stack of patches I could cherry-pick to make sure we can drop the revert we've been carrying. I dont have any material concern here, but I am trying to not have a sequence of reverts/partial reverts to carry downstream.... If there are a stack of patches that can make the revert go away, I am happy with these changes.

[unterumarmung]

In D158618#4622965, @mravishankar wrote:

In D158618#4617754, @unterumarmung wrote:

@mravishankar @dcaballe Could you please re-review the PR?

Could one of you give me a stack of patches I could cherry-pick to make sure we can drop the revert we've been carrying. I dont have any material concern here, but I am trying to not have a sequence of reverts/partial reverts to carry downstream.... If there are a stack of patches that can make the revert go away, I am happy with these changes.

I'm sorry for the delay
Here is the stack with all the three patches: https://github.com/unterumarmung/llvm-project/commits/vector-reduction-changes
I've rebased it to the current main and run tests locally - seems fine

[mravishankar]

In D158618#4629231, @unterumarmung wrote:

In D158618#4622965, @mravishankar wrote:

In D158618#4617754, @unterumarmung wrote:

@mravishankar @dcaballe Could you please re-review the PR?

Could one of you give me a stack of patches I could cherry-pick to make sure we can drop the revert we've been carrying. I dont have any material concern here, but I am trying to not have a sequence of reverts/partial reverts to carry downstream.... If there are a stack of patches that can make the revert go away, I am happy with these changes.

I'm sorry for the delay
Here is the stack with all the three patches: https://github.com/unterumarmung/llvm-project/commits/vector-reduction-changes
I've rebased it to the current main and run tests locally - seems fine

Thanks! I created a draft PR in IREE (downstream) here https://github.com/openxla/iree/pull/14888 with the top three commits of that branch. If everything passes, then feel free to land this change (I am going to be out on vacation soon, so please co-ordinate with @dcaballe ).

mlir/include/mlir/Dialect/Vector/IR/VectorOps.td

 def COMBINING_KIND_MINSI : I32BitEnumAttrCaseBit<"MINSI", 3, "minsi">;
 def COMBINING_KIND_MINF : I32BitEnumAttrCaseBit<"MINF", 4, "minf">;
 def COMBINING_KIND_MAXUI : I32BitEnumAttrCaseBit<"MAXUI", 5, "maxui">;
 def COMBINING_KIND_MAXSI : I32BitEnumAttrCaseBit<"MAXSI", 6, "maxsi">;
 def COMBINING_KIND_MAXF : I32BitEnumAttrCaseBit<"MAXF", 7, "maxf">;
 def COMBINING_KIND_AND : I32BitEnumAttrCaseBit<"AND", 8, "and">;
 def COMBINING_KIND_OR  : I32BitEnumAttrCaseBit<"OR", 9, "or">;
 def COMBINING_KIND_XOR : I32BitEnumAttrCaseBit<"XOR", 10, "xor">;
+def COMBINING_KIND_MINIMUMF : I32BitEnumAttrCaseBit<"MINIMUMF", 11, "minimumf">;
+def COMBINING_KIND_MAXIMUMF : I32BitEnumAttrCaseBit<"MAXIMUMF", 12, "maximumf">;
 
 def CombiningKind : I32BitEnumAttr<
     "CombiningKind",
     "Kind of combining function for contractions and reductions",
     [COMBINING_KIND_ADD, COMBINING_KIND_MUL, COMBINING_KIND_MINUI,
      COMBINING_KIND_MINSI, COMBINING_KIND_MINF, COMBINING_KIND_MAXUI,
      COMBINING_KIND_MAXSI, COMBINING_KIND_MAXF, COMBINING_KIND_AND,
-     COMBINING_KIND_OR, COMBINING_KIND_XOR]> {
+     COMBINING_KIND_OR, COMBINING_KIND_XOR,
+     COMBINING_KIND_MAXIMUMF, COMBINING_KIND_MINIMUMF]> {
   let cppNamespace = "::mlir::vector";
   let genSpecializedAttr = 0;
 }
 
 /// An attribute that specifies the combining function for `vector.contract`,
 /// and `vector.reduction`.
 def Vector_CombiningKindAttr : EnumAttr<Vector_Dialect, CombiningKind, "kind"> {
   let assemblyFormat = "`<` $value `>`";

mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp

matchAndRewrite(vector::ReductionOp reductionOp, OpAdaptor adaptor,
     if (kind == vector::CombiningKind::ADD) {
       result = lowerReductionWithStartValue<LLVM::vector_reduce_fadd,
                                             ReductionNeutralZero>(
           rewriter, loc, llvmType, operand, acc, reassociateFPReductions);
     } else if (kind == vector::CombiningKind::MUL) {
       result = lowerReductionWithStartValue<LLVM::vector_reduce_fmul,
                                             ReductionNeutralFPOne>(
           rewriter, loc, llvmType, operand, acc, reassociateFPReductions);
-    } else if (kind == vector::CombiningKind::MINF) {
+    } else if (kind == vector::CombiningKind::MINIMUMF) {
       result =
           createFPReductionComparisonOpLowering<LLVM::vector_reduce_fminimum>(
               rewriter, loc, llvmType, operand, acc);
-    } else if (kind == vector::CombiningKind::MAXF) {
+    } else if (kind == vector::CombiningKind::MAXIMUMF) {
       result =
           createFPReductionComparisonOpLowering<LLVM::vector_reduce_fmaximum>(
               rewriter, loc, llvmType, operand, acc);
     } else
       return failure();
 
     rewriter.replaceOp(reductionOp, result);
     return success();
case vector::CombiningKind::MINF:
       break;
     case vector::CombiningKind::MAXF:
       // FIXME: MLIR's 'minf' and LLVM's 'vector_reduce_fmin' do not handle
       // NaNs/-0.0/+0.0 in the same way.
       result = lowerReductionWithStartValue<LLVM::VPReduceFMaxOp,
                                             ReductionNeutralFPMin>(
           rewriter, loc, llvmType, operand, acc, maskOp.getMask());
       break;
+    default:
+      return rewriter.notifyMatchFailure(
+          maskOp,
+          "lowering to LLVM is not implemented for this masked operation");
     }
 
     // Replace `vector.mask` operation altogether.
     rewriter.replaceOp(maskOp, result);
     return success();
   }
 };
 

mlir/lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp

 
 #define INT_OR_FLOAT_CASE(kind, fop)                                           \
   case vector::CombiningKind::kind:                                            \
     result = rewriter.create<fop>(loc, resultType, result, next);              \
     break
 
         INT_AND_FLOAT_CASE(ADD, IAddOp, FAddOp);
         INT_AND_FLOAT_CASE(MUL, IMulOp, FMulOp);
-
+        INT_OR_FLOAT_CASE(MAXIMUMF, SPIRVFMaxOp);
+        INT_OR_FLOAT_CASE(MINIMUMF, SPIRVFMinOp);
         INT_OR_FLOAT_CASE(MAXF, SPIRVFMaxOp);
         INT_OR_FLOAT_CASE(MINF, SPIRVFMinOp);
         INT_OR_FLOAT_CASE(MINUI, SPIRVUMinOp);
         INT_OR_FLOAT_CASE(MINSI, SPIRVSMinOp);
         INT_OR_FLOAT_CASE(MAXUI, SPIRVUMaxOp);
         INT_OR_FLOAT_CASE(MAXSI, SPIRVSMaxOp);
 
       case vector::CombiningKind::AND:

mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp

mlir::linalg::getCombinerOpKind(Operation *combinerOp) {
   if (!combinerOp)
     return std::nullopt;
   return llvm::TypeSwitch<Operation *, std::optional<CombiningKind>>(combinerOp)
       .Case<arith::AddIOp, arith::AddFOp>(
           [&](auto op) { return CombiningKind::ADD; })
       .Case<arith::AndIOp>([&](auto op) { return CombiningKind::AND; })
       .Case<arith::MaxSIOp>([&](auto op) { return CombiningKind::MAXSI; })
       .Case<arith::MaxUIOp>([&](auto op) { return CombiningKind::MAXUI; })
-      .Case<arith::MaxFOp>([&](auto op) { return CombiningKind::MAXF; })
+      .Case<arith::MaxFOp>([&](auto op) { return CombiningKind::MAXIMUMF; })
       .Case<arith::MinSIOp>([&](auto op) { return CombiningKind::MINSI; })
       .Case<arith::MinUIOp>([&](auto op) { return CombiningKind::MINUI; })
-      .Case<arith::MinFOp>([&](auto op) { return CombiningKind::MINF; })
+      .Case<arith::MinFOp>([&](auto op) { return CombiningKind::MINIMUMF; })
       .Case<arith::MulIOp, arith::MulFOp>(
           [&](auto op) { return CombiningKind::MUL; })
       .Case<arith::OrIOp>([&](auto op) { return CombiningKind::OR; })
       .Case<arith::XOrIOp>([&](auto op) { return CombiningKind::XOR; })
       .Default([&](auto op) { return std::nullopt; });
 }
 
 /// Check whether `outputOperand` is a reduction with a single combiner
bool isCastOfBlockArgument(Operation *op) {
   return isa<CastOpInterface>(op) && op->getNumOperands() == 1 &&
          isa<BlockArgument>(op->getOperand(0));
 }
 
 bool isSupportedPoolKind(vector::CombiningKind kind) {
   switch (kind) {
   case vector::CombiningKind::ADD:
   case vector::CombiningKind::MAXF:
+  case vector::CombiningKind::MAXIMUMF:
   case vector::CombiningKind::MAXSI:
   case vector::CombiningKind::MAXUI:
   case vector::CombiningKind::MINF:
+  case vector::CombiningKind::MINIMUMF:
   case vector::CombiningKind::MINSI:
   case vector::CombiningKind::MINUI:
     return true;
   default:
     return false;
   }
 }
 

mlir/lib/Dialect/Vector/IR/VectorOps.cpp

static bool isSupportedCombiningKind(CombiningKind combiningKind,
   case CombiningKind::MAXUI:
   case CombiningKind::MAXSI:
   case CombiningKind::AND:
   case CombiningKind::OR:
   case CombiningKind::XOR:
     return elementType.isIntOrIndex();
   case CombiningKind::MINF:
   case CombiningKind::MAXF:
+  case CombiningKind::MINIMUMF:
+  case CombiningKind::MAXIMUMF:
     return llvm::isa<FloatType>(elementType);
   }
   return false;
 }
 
 AffineMap mlir::vector::getTransferMinorIdentityMap(ShapedType shapedType,
                                                     VectorType vectorType) {
   int64_t elementVectorRank = 0;
case arith::AtomicRMWKind::addi:
     return builder.create<vector::ReductionOp>(vector.getLoc(),
                                                CombiningKind::ADD, vector);
   case arith::AtomicRMWKind::mulf:
   case arith::AtomicRMWKind::muli:
     return builder.create<vector::ReductionOp>(vector.getLoc(),
                                                CombiningKind::MUL, vector);
   case arith::AtomicRMWKind::minf:
     return builder.create<vector::ReductionOp>(vector.getLoc(),
-                                               CombiningKind::MINF, vector);
+                                               CombiningKind::MINIMUMF, vector);
   case arith::AtomicRMWKind::mins:
     return builder.create<vector::ReductionOp>(vector.getLoc(),
                                                CombiningKind::MINSI, vector);
   case arith::AtomicRMWKind::minu:
     return builder.create<vector::ReductionOp>(vector.getLoc(),
                                                CombiningKind::MINUI, vector);
   case arith::AtomicRMWKind::maxf:
     return builder.create<vector::ReductionOp>(vector.getLoc(),
-                                               CombiningKind::MAXF, vector);
+                                               CombiningKind::MAXIMUMF, vector);
   case arith::AtomicRMWKind::maxs:
     return builder.create<vector::ReductionOp>(vector.getLoc(),
                                                CombiningKind::MAXSI, vector);
   case arith::AtomicRMWKind::maxu:
     return builder.create<vector::ReductionOp>(vector.getLoc(),
                                                CombiningKind::MAXUI, vector);
   case arith::AtomicRMWKind::andi:
     return builder.create<vector::ReductionOp>(vector.getLoc(),
case CombiningKind::ADD:
     else
       llvm_unreachable("invalid value types for ADD reduction");
     break;
   case CombiningKind::AND:
     assert(t1.isIntOrIndex() && tAcc.isIntOrIndex() && "expected int values");
     result = b.createOrFold<arith::AndIOp>(loc, v1, acc);
     break;
   case CombiningKind::MAXF:
+  case CombiningKind::MAXIMUMF:
     assert(llvm::isa<FloatType>(t1) && llvm::isa<FloatType>(tAcc) &&
            "expected float values");
     result = b.createOrFold<arith::MaxFOp>(loc, v1, acc);
     break;
   case CombiningKind::MINF:
+  case CombiningKind::MINIMUMF:
     assert(llvm::isa<FloatType>(t1) && llvm::isa<FloatType>(tAcc) &&
            "expected float values");
     result = b.createOrFold<arith::MinFOp>(loc, v1, acc);
     break;
   case CombiningKind::MAXSI:
     assert(t1.isIntOrIndex() && tAcc.isIntOrIndex() && "expected int values");
     result = b.createOrFold<arith::MaxSIOp>(loc, v1, acc);
     break;

mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp

 static std::optional<Value>
 createContractArithOp(Location loc, Value x, Value y, Value acc,
                       vector::CombiningKind kind, PatternRewriter &rewriter,
                       bool isInt, Value mask = Value()) {
   using vector::CombiningKind;
   Value mul;
 
   if (isInt) {
-    if (kind == CombiningKind::MINF || kind == CombiningKind::MAXF)
+    if (kind == CombiningKind::MINF || kind == CombiningKind::MAXF ||
+        kind == CombiningKind::MINIMUMF || kind == CombiningKind::MAXIMUMF)
       // Only valid for floating point types.
       return std::nullopt;
     mul = rewriter.create<arith::MulIOp>(loc, x, y);
   } else {
     // Float case.
     if (kind == CombiningKind::AND || kind == CombiningKind::MINUI ||
         kind == CombiningKind::MINSI || kind == CombiningKind::MAXUI ||
         kind == CombiningKind::MAXSI || kind == CombiningKind::OR ||

mlir/lib/Dialect/Vector/Transforms/LowerVectorScan.cpp

case CombiningKind::AND:
     break;
   case CombiningKind::OR:
     combinedResult = rewriter.create<arith::OrIOp>(loc, x, y);
     break;
   case CombiningKind::XOR:
     combinedResult = rewriter.create<arith::XOrIOp>(loc, x, y);
     break;
   case CombiningKind::MINF:
+  case CombiningKind::MINIMUMF:
     combinedResult = rewriter.create<arith::MinFOp>(loc, x, y);
     break;
   case CombiningKind::MAXF:
+  case CombiningKind::MAXIMUMF:
     combinedResult = rewriter.create<arith::MaxFOp>(loc, x, y);
     break;
   }
   return combinedResult;
 }
 
 /// This function checks to see if the vector combining kind
 /// is consistent with the integer or float element type.
 static bool isValidKind(bool isInt, vector::CombiningKind kind) {
   using vector::CombiningKind;
   enum class KindType { FLOAT, INT, INVALID };
   KindType type{KindType::INVALID};
   switch (kind) {
   case CombiningKind::MINF:
+  case CombiningKind::MINIMUMF:
   case CombiningKind::MAXF:
+  case CombiningKind::MAXIMUMF:
     type = KindType::FLOAT;
     break;
   case CombiningKind::MINUI:
   case CombiningKind::MINSI:
   case CombiningKind::MAXUI:
   case CombiningKind::MAXSI:
   case CombiningKind::AND:
   case CombiningKind::OR:

mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir

 // CHECK-LABEL: @reduce_mul_acc_i32(
 //  CHECK-SAME: %[[A:.*]]: vector<16xi32>, %[[ACC:.*]]: i32)
 //       CHECK: %[[R:.*]] = "llvm.intr.vector.reduce.mul"(%[[A]])
 //       CHECK: %[[V:.*]] = llvm.mul %[[ACC]], %[[R]]
 //       CHECK: return %[[V]] : i32
 
 // -----
 
-func.func @reduce_fmax_f32(%arg0: vector<16xf32>, %arg1: f32) -> f32 {
-  %0 = vector.reduction <maxf>, %arg0, %arg1 : vector<16xf32> into f32
+func.func @reduce_fmaximum_f32(%arg0: vector<16xf32>, %arg1: f32) -> f32 {
+  %0 = vector.reduction <maximumf>, %arg0, %arg1 : vector<16xf32> into f32
   return %0 : f32
 }
-// CHECK-LABEL: @reduce_fmax_f32(
+// CHECK-LABEL: @reduce_fmaximum_f32(
 // CHECK-SAME: %[[A:.*]]: vector<16xf32>, %[[B:.*]]: f32)
 //      CHECK: %[[V:.*]] = llvm.intr.vector.reduce.fmaximum(%[[A]]) : (vector<16xf32>) -> f32
 //      CHECK: %[[R:.*]] = llvm.intr.maximum(%[[V]], %[[B]]) : (f32, f32) -> f32
 //      CHECK: return %[[R]] : f32
 
 // -----
 
-func.func @reduce_fmin_f32(%arg0: vector<16xf32>, %arg1: f32) -> f32 {
-  %0 = vector.reduction <minf>, %arg0, %arg1 : vector<16xf32> into f32
+func.func @reduce_fminimum_f32(%arg0: vector<16xf32>, %arg1: f32) -> f32 {
+  %0 = vector.reduction <minimumf>, %arg0, %arg1 : vector<16xf32> into f32
   return %0 : f32
 }
-// CHECK-LABEL: @reduce_fmin_f32(
+// CHECK-LABEL: @reduce_fminimum_f32(
 // CHECK-SAME: %[[A:.*]]: vector<16xf32>, %[[B:.*]]: f32)
 //      CHECK: %[[V:.*]] = llvm.intr.vector.reduce.fminimum(%[[A]]) : (vector<16xf32>) -> f32
 //      CHECK: %[[R:.*]] = llvm.intr.minimum(%[[V]], %[[B]]) : (f32, f32) -> f32
 //      CHECK: return %[[R]] : f32
 
 // -----
 
 func.func @reduce_minui_i32(%arg0: vector<16xi32>) -> i32 {

mlir/test/Conversion/VectorToSPIRV/vector-to-spirv.mlir

 
 // CHECK-LABEL: @cl_fma_size1_vector
 //       CHECK:   spirv.CL.fma %{{.+}} : f32
 func.func @cl_fma_size1_vector(%a: vector<1xf32>, %b: vector<1xf32>, %c: vector<1xf32>) -> vector<1xf32> {
   %0 = vector.fma %a, %b, %c: vector<1xf32>
   return %0 : vector<1xf32>
 }
 
-// CHECK-LABEL: func @cl_reduction_maxf
+// CHECK-LABEL: func @cl_reduction_maximumf
 //  CHECK-SAME: (%[[V:.+]]: vector<3xf32>, %[[S:.+]]: f32)
 //       CHECK:   %[[S0:.+]] = spirv.CompositeExtract %[[V]][0 : i32] : vector<3xf32>
 //       CHECK:   %[[S1:.+]] = spirv.CompositeExtract %[[V]][1 : i32] : vector<3xf32>
 //       CHECK:   %[[S2:.+]] = spirv.CompositeExtract %[[V]][2 : i32] : vector<3xf32>
 //       CHECK:   %[[MAX0:.+]] = spirv.CL.fmax %[[S0]], %[[S1]]
 //       CHECK:   %[[MAX1:.+]] = spirv.CL.fmax %[[MAX0]], %[[S2]]
 //       CHECK:   %[[MAX2:.+]] = spirv.CL.fmax %[[MAX1]], %[[S]]
 //       CHECK:   return %[[MAX2]]
-func.func @cl_reduction_maxf(%v : vector<3xf32>, %s: f32) -> f32 {
-  %reduce = vector.reduction <maxf>, %v, %s : vector<3xf32> into f32
+func.func @cl_reduction_maximumf(%v : vector<3xf32>, %s: f32) -> f32 {
+  %reduce = vector.reduction <maximumf>, %v, %s : vector<3xf32> into f32
   return %reduce : f32
 }
 
-// CHECK-LABEL: func @cl_reduction_minf
+// CHECK-LABEL: func @cl_reduction_minimumf
 //  CHECK-SAME: (%[[V:.+]]: vector<3xf32>, %[[S:.+]]: f32)
 //       CHECK:   %[[S0:.+]] = spirv.CompositeExtract %[[V]][0 : i32] : vector<3xf32>
 //       CHECK:   %[[S1:.+]] = spirv.CompositeExtract %[[V]][1 : i32] : vector<3xf32>
 //       CHECK:   %[[S2:.+]] = spirv.CompositeExtract %[[V]][2 : i32] : vector<3xf32>
 //       CHECK:   %[[MIN0:.+]] = spirv.CL.fmin %[[S0]], %[[S1]]
 //       CHECK:   %[[MIN1:.+]] = spirv.CL.fmin %[[MIN0]], %[[S2]]
 //       CHECK:   %[[MIN2:.+]] = spirv.CL.fmin %[[MIN1]], %[[S]]
 //       CHECK:   return %[[MIN2]]
-func.func @cl_reduction_minf(%v : vector<3xf32>, %s: f32) -> f32 {
-  %reduce = vector.reduction <minf>, %v, %s : vector<3xf32> into f32
+func.func @cl_reduction_minimumf(%v : vector<3xf32>, %s: f32) -> f32 {
+  %reduce = vector.reduction <minimumf>, %v, %s : vector<3xf32> into f32
   return %reduce : f32
 }
 
 // CHECK-LABEL: func @cl_reduction_maxsi
 //  CHECK-SAME: (%[[V:.+]]: vector<3xi32>, %[[S:.+]]: i32)
 //       CHECK:   %[[S0:.+]] = spirv.CompositeExtract %[[V]][0 : i32] : vector<3xi32>
 //       CHECK:   %[[S1:.+]] = spirv.CompositeExtract %[[V]][1 : i32] : vector<3xi32>
 //       CHECK:   %[[S2:.+]] = spirv.CompositeExtract %[[V]][2 : i32] : vector<3xi32>

 //       CHECK:   return %[[MUL2]]
 func.func @reduction_mul(%v : vector<3xf32>, %s: f32) -> f32 {
   %reduce = vector.reduction <mul>, %v, %s : vector<3xf32> into f32
   return %reduce : f32
 }
 
 // -----
 
-// CHECK-LABEL: func @reduction_maxf
+// CHECK-LABEL: func @reduction_maximumf
 //  CHECK-SAME: (%[[V:.+]]: vector<3xf32>, %[[S:.+]]: f32)
 //       CHECK:   %[[S0:.+]] = spirv.CompositeExtract %[[V]][0 : i32] : vector<3xf32>
 //       CHECK:   %[[S1:.+]] = spirv.CompositeExtract %[[V]][1 : i32] : vector<3xf32>
 //       CHECK:   %[[S2:.+]] = spirv.CompositeExtract %[[V]][2 : i32] : vector<3xf32>
 //       CHECK:   %[[MAX0:.+]] = spirv.GL.FMax %[[S0]], %[[S1]]
 //       CHECK:   %[[MAX1:.+]] = spirv.GL.FMax %[[MAX0]], %[[S2]]
 //       CHECK:   %[[MAX2:.+]] = spirv.GL.FMax %[[MAX1]], %[[S]]
 //       CHECK:   return %[[MAX2]]
-func.func @reduction_maxf(%v : vector<3xf32>, %s: f32) -> f32 {
-  %reduce = vector.reduction <maxf>, %v, %s : vector<3xf32> into f32
+func.func @reduction_maximumf(%v : vector<3xf32>, %s: f32) -> f32 {
+  %reduce = vector.reduction <maximumf>, %v, %s : vector<3xf32> into f32
   return %reduce : f32
 }
 
 // -----
 
-// CHECK-LABEL: func @reduction_minf
+// CHECK-LABEL: func @reduction_minimumf
 //  CHECK-SAME: (%[[V:.+]]: vector<3xf32>, %[[S:.+]]: f32)
 //       CHECK:   %[[S0:.+]] = spirv.CompositeExtract %[[V]][0 : i32] : vector<3xf32>
 //       CHECK:   %[[S1:.+]] = spirv.CompositeExtract %[[V]][1 : i32] : vector<3xf32>
 //       CHECK:   %[[S2:.+]] = spirv.CompositeExtract %[[V]][2 : i32] : vector<3xf32>
 //       CHECK:   %[[MIN0:.+]] = spirv.GL.FMin %[[S0]], %[[S1]]
 //       CHECK:   %[[MIN1:.+]] = spirv.GL.FMin %[[MIN0]], %[[S2]]
 //       CHECK:   %[[MIN2:.+]] = spirv.GL.FMin %[[MIN1]], %[[S]]
 //       CHECK:   return %[[MIN2]]
-func.func @reduction_minf(%v : vector<3xf32>, %s: f32) -> f32 {
-  %reduce = vector.reduction <minf>, %v, %s : vector<3xf32> into f32
+func.func @reduction_minimumf(%v : vector<3xf32>, %s: f32) -> f32 {
+  %reduce = vector.reduction <minimumf>, %v, %s : vector<3xf32> into f32
   return %reduce : f32
 }
 
 // -----
 
 // CHECK-LABEL: func @reduction_maxsi
 //  CHECK-SAME: (%[[V:.+]]: vector<3xi32>, %[[S:.+]]: i32)
 //       CHECK:   %[[S0:.+]] = spirv.CompositeExtract %[[V]][0 : i32] : vector<3xi32>

mlir/test/Dialect/Affine/SuperVectorize/vectorize_reduction.mlir

 // CHECK-LABEL: @vecdim_reduction_minf
 // CHECK:       affine.for %{{.*}} = 0 to 256 {
 // CHECK:         %[[vmax:.*]] = arith.constant dense<0x7F800000> : vector<128xf32>
 // CHECK:         %[[vred:.*]] = affine.for %{{.*}} = 0 to 512 step 128 iter_args(%[[red_iter:.*]] = %[[vmax]]) -> (vector<128xf32>) {
 // CHECK:           %[[ld:.*]] = vector.transfer_read %{{.*}} : memref<256x512xf32>, vector<128xf32>
 // CHECK:           %[[min:.*]] = arith.minf %[[red_iter]], %[[ld]] : vector<128xf32>
 // CHECK:           affine.yield %[[min]] : vector<128xf32>
 // CHECK:         }
-// CHECK:         %[[final_min:.*]] = vector.reduction <minf>, %[[vred:.*]] : vector<128xf32> into f32
+// CHECK:         %[[final_min:.*]] = vector.reduction <minimumf>, %[[vred:.*]] : vector<128xf32> into f32
 // CHECK:         affine.store %[[final_min]], %{{.*}} : memref<256xf32>
 // CHECK:       }
 
 // -----
 
 func.func @vecdim_reduction_maxf(%in: memref<256x512xf32>, %out: memref<256xf32>) {
  %cst = arith.constant 0xFF800000 : f32
  affine.for %i = 0 to 256 {

 // CHECK-LABEL: @vecdim_reduction_maxf
 // CHECK:       affine.for %{{.*}} = 0 to 256 {
 // CHECK:         %[[vmin:.*]] = arith.constant dense<0xFF800000> : vector<128xf32>
 // CHECK:         %[[vred:.*]] = affine.for %{{.*}} = 0 to 512 step 128 iter_args(%[[red_iter:.*]] = %[[vmin]]) -> (vector<128xf32>) {
 // CHECK:           %[[ld:.*]] = vector.transfer_read %{{.*}} : memref<256x512xf32>, vector<128xf32>
 // CHECK:           %[[max:.*]] = arith.maxf %[[red_iter]], %[[ld]] : vector<128xf32>
 // CHECK:           affine.yield %[[max]] : vector<128xf32>
 // CHECK:         }
-// CHECK:         %[[final_max:.*]] = vector.reduction <maxf>, %[[vred:.*]] : vector<128xf32> into f32
+// CHECK:         %[[final_max:.*]] = vector.reduction <maximumf>, %[[vred:.*]] : vector<128xf32> into f32
 // CHECK:         affine.store %[[final_max]], %{{.*}} : memref<256xf32>
 // CHECK:       }
 
 // -----
 
 func.func @vecdim_reduction_minsi(%in: memref<256x512xi32>, %out: memref<256xi32>) {
  %cst = arith.constant 2147483647 : i32
  affine.for %i = 0 to 256 {

mlir/test/Dialect/Linalg/vectorization.mlir

 }
 
 // -----
 
 // CHECK-LABEL:   func @red_max_2d(
 func.func @red_max_2d(%arg0: tensor<4x4xf32>) -> tensor<4xf32> {
   // CHECK: %[[CMINF:.+]] = arith.constant dense<-3.402820e+38> : vector<4xf32>
   // CHECK: tensor.empty() : tensor<4xf32>
-  // CHECK: vector.multi_reduction <maxf>, {{.*}}, %[[CMINF]] [1] : vector<4x4xf32> to vector<4xf32>
+  // CHECK: vector.multi_reduction <maximumf>, {{.*}}, %[[CMINF]] [1] : vector<4x4xf32> to vector<4xf32>
   // CHECK: vector.transfer_write {{.*}} : vector<4xf32>, tensor<4xf32>
   %ident = arith.constant -3.40282e+38 : f32
   %init = tensor.empty() : tensor<4xf32>
   %fill = linalg.fill ins(%ident : f32) outs(%init : tensor<4xf32>) -> tensor<4xf32>
   %red = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
                                           affine_map<(d0, d1) -> (d0)>],
                          iterator_types = ["parallel", "reduction"]}
                          ins(%arg0 : tensor<4x4xf32>) outs(%fill : tensor<4xf32>) {

 
 // -----
 
 // CHECK-LABEL:   func @red_min_2d(
 func.func @red_min_2d(%arg0: tensor<4x4xf32>) -> tensor<4xf32> {
   // CHECK: %[[CMAXF:.+]] = arith.constant dense<3.402820e+38> : vector<4xf32>
   // CHECK: tensor.empty() : tensor<4xf32>
   // CHECK: vector.transfer_read {{.*}} : tensor<4x4xf32>, vector<4x4xf32>
-  // CHECK: vector.multi_reduction <minf>, {{.*}}, %[[CMAXF]] [1] : vector<4x4xf32> to vector<4xf32>
+  // CHECK: vector.multi_reduction <minimumf>, {{.*}}, %[[CMAXF]] [1] : vector<4x4xf32> to vector<4xf32>
   // CHECK: vector.transfer_write {{.*}} : vector<4xf32>, tensor<4xf32>
   %maxf32 = arith.constant 3.40282e+38 : f32
   %init = tensor.empty() : tensor<4xf32>
   %fill = linalg.fill ins(%maxf32 : f32) outs(%init : tensor<4xf32>) -> tensor<4xf32>
   %red = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
                                           affine_map<(d0, d1) -> (d0)>],
                          iterator_types = ["parallel", "reduction"]}
                          ins(%arg0 : tensor<4x4xf32>) outs(%fill : tensor<4xf32>) {

mlir/test/Dialect/Vector/canonicalize.mlir

 //       CHECK: vector.reduction
 func.func @dont_reduce_one_element_vector(%a : vector<4xf32>) -> f32 {
   %s = vector.reduction <add>, %a : vector<4xf32> into f32
   return %s : f32
 }
 
 // -----
 
-// CHECK-LABEL: func @reduce_one_element_vector_maxf
+// CHECK-LABEL: func @reduce_one_element_vector_maximumf
 //  CHECK-SAME: (%[[V:.+]]: vector<1xf32>, %[[B:.+]]: f32)
 //       CHECK:   %[[A:.+]] = vector.extract %[[V]][0] : vector<1xf32>
 //       CHECK:   %[[S:.+]] = arith.maxf %[[A]], %[[B]] : f32
 //       CHECK:   return %[[S]]
-func.func @reduce_one_element_vector_maxf(%a : vector<1xf32>, %b: f32) -> f32 {
-  %s = vector.reduction <maxf>, %a, %b : vector<1xf32> into f32
+func.func @reduce_one_element_vector_maximumf(%a : vector<1xf32>, %b: f32) -> f32 {
+  %s = vector.reduction <maximumf>, %a, %b : vector<1xf32> into f32
   return %s : f32
 }
 
 // -----
 
 // CHECK-LABEL: func @bitcast(
 //  CHECK-SAME:               %[[ARG:.*]]: vector<4x8xf32>) -> vector<4x16xi16> {
 //       CHECK: vector.bitcast %[[ARG:.*]] : vector<4x8xf32> to vector<4x16xi16>

mlir/test/Dialect/Vector/ops.mlir

func.func @reduce_fp(%arg0: vector<16xf32>, %arg1: f32) -> f32 {
   // CHECK:    vector.reduction <add>, %{{.*}}, %{{.*}} : vector<16xf32> into f32
   vector.reduction <add>, %arg0, %arg1 : vector<16xf32> into f32
   // CHECK:    vector.reduction <mul>, %{{.*}} : vector<16xf32> into f32
   vector.reduction <mul>, %arg0 : vector<16xf32> into f32
   // CHECK:    vector.reduction <mul>, %{{.*}}, %{{.*}} : vector<16xf32> into f32
   vector.reduction <mul>, %arg0, %arg1 : vector<16xf32> into f32
   // CHECK:    vector.reduction <minf>, %{{.*}} : vector<16xf32> into f32
   vector.reduction <minf>, %arg0 : vector<16xf32> into f32
-  // CHECK:    %[[X:.*]] = vector.reduction <maxf>, %{{.*}} : vector<16xf32> into f32
+  // CHECK:    %[[X0:.*]] = vector.reduction <maxf>, %{{.*}} : vector<16xf32> into f32
   %0 = vector.reduction <maxf>, %arg0 : vector<16xf32> into f32
-  // CHECK:    return %[[X]] : f32
+  // CHECK:    vector.reduction <minimumf>, %{{.*}} : vector<16xf32> into f32
+  vector.reduction <minimumf>, %arg0 : vector<16xf32> into f32
+  // CHECK:    %[[X1:.*]] = vector.reduction <maximumf>, %{{.*}} : vector<16xf32> into f32
+  %1 = vector.reduction <maximumf>, %arg0 : vector<16xf32> into f32
+  // CHECK:    return %[[X0]] : f32
   return %0 : f32
 }
 
 // CHECK-LABEL: @reduce_int
 func.func @reduce_int(%arg0: vector<16xi32>) -> i32 {
   // CHECK:    vector.reduction <add>, %{{.*}} : vector<16xi32> into i32
   vector.reduction <add>, %arg0 : vector<16xi32> into i32
   // CHECK:    vector.reduction <mul>, %{{.*}} : vector<16xi32> into i32

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f32-reassoc.mlir

func.func @entry() {
   // Various vector reductions. Not full functional unit tests, but
   // a simple integration test to see if the code runs end-to-end.
   %0 = vector.reduction <add>, %v2 : vector<64xf32> into f32
   vector.print %0 : f32
   // CHECK: 67
   %1 = vector.reduction <mul>, %v2 : vector<64xf32> into f32
   vector.print %1 : f32
   // CHECK: 6
-  %2 = vector.reduction <minf>, %v2 : vector<64xf32> into f32
+  %2 = vector.reduction <minimumf>, %v2 : vector<64xf32> into f32
   vector.print %2 : f32
   // CHECK: 1
-  %3 = vector.reduction <maxf>, %v2 : vector<64xf32> into f32
+  %3 = vector.reduction <maximumf>, %v2 : vector<64xf32> into f32
   vector.print %3 : f32
   // CHECK: 3
 
   return
 }

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f32.mlir

func.func @entry() {
   // Various vector reductions. Not full functional unit tests, but
   // a simple integration test to see if the code runs end-to-end.
   %0 = vector.reduction <add>, %v9 : vector<10xf32> into f32
   vector.print %0 : f32
   // CHECK: -7.75
   %1 = vector.reduction <mul>, %v9 : vector<10xf32> into f32
   vector.print %1 : f32
   // CHECK: -5760
-  %2 = vector.reduction <minf>, %v9 : vector<10xf32> into f32
+  %2 = vector.reduction <minimumf>, %v9 : vector<10xf32> into f32
   vector.print %2 : f32
   // CHECK: -16
-  %3 = vector.reduction <maxf>, %v9 : vector<10xf32> into f32
+  %3 = vector.reduction <maximumf>, %v9 : vector<10xf32> into f32
   vector.print %3 : f32
   // CHECK: 5
 
   return
 }

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f64-reassoc.mlir

func.func @entry() {
   // Various vector reductions. Not full functional unit tests, but
   // a simple integration test to see if the code runs end-to-end.
   %0 = vector.reduction <add>, %v2 : vector<64xf64> into f64
   vector.print %0 : f64
   // CHECK: 67
   %1 = vector.reduction <mul>, %v2 : vector<64xf64> into f64
   vector.print %1 : f64
   // CHECK: 6
-  %2 = vector.reduction <minf>, %v2 : vector<64xf64> into f64
+  %2 = vector.reduction <minimumf>, %v2 : vector<64xf64> into f64
   vector.print %2 : f64
   // CHECK: 1
-  %3 = vector.reduction <maxf>, %v2 : vector<64xf64> into f64
+  %3 = vector.reduction <maximumf>, %v2 : vector<64xf64> into f64
   vector.print %3 : f64
   // CHECK: 3
 
   return
 }

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f64.mlir

func.func @entry() {
   // Various vector reductions. Not full functional unit tests, but
   // a simple integration test to see if the code runs end-to-end.
   %0 = vector.reduction <add>, %v9 : vector<10xf64> into f64
   vector.print %0 : f64
   // CHECK: -7.75
   %1 = vector.reduction <mul>, %v9 : vector<10xf64> into f64
   vector.print %1 : f64
   // CHECK: -5760
-  %2 = vector.reduction <minf>, %v9 : vector<10xf64> into f64
+  %2 = vector.reduction <minimumf>, %v9 : vector<10xf64> into f64
   vector.print %2 : f64
   // CHECK: -16
-  %3 = vector.reduction <maxf>, %v9 : vector<10xf64> into f64
+  %3 = vector.reduction <maximumf>, %v9 : vector<10xf64> into f64
   vector.print %3 : f64
   // CHECK: 5
 
   return
 }