[AMDGPU] Add DAG ISel support for preloaded kernel arguments

[kerbowa]

Summary

This patch adds the DAG isel changes for kernel argument preloading.
These changes are not usable with older firmware but subsequent patches
in the series will make the codegen backwards compatible. This patch
should only be submitted alongside that subsequent patch.

Preloading here begins from the start of the kernel arguments until the
amount of arguments indicated by the CL flag
amdgpu-kernarg-preload-count.

Aggregates and arguments passed by-ref are not supported.

Special care for the alignment of the kernarg segment is needed as well
as consideration of the alignment of addressable SGPR tuples when we
cannot directly use misaligned large tuples that the arguments are
loaded to.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp

63

Probably should but I don't even know if this is part of debug printing anywhere, I don't know the last time I saw this

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

449

Can you move this to hasKernargPreload helper or something? Probably should make it a full subtarget feature on its own

llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp

261–263 ↗

(On Diff #552593)

Can you separate all the formatting changes out?

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

5003 ↗

(On Diff #552593)

Check the subtarget for the limit

5003–5004 ↗

(On Diff #552593)

Is the interaction with .amdhsa_user_sgpr_count checked?

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

1949–1955 ↗

(On Diff #552593)

Can you split the assembler / MC bits into a separate patch?

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

927–929

Needs some temporary variables

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

2247

I do not understand this metadata system, you know directly from the IR arguments the register layout

2257

unchecked dyn_caast

llvm/test/MC/AMDGPU/hsa-v4.s

113 ↗

(On Diff #552593)

Need some tests with the limit exceeded diagnostic and interactions with amdhsa_user_sgpr_count

[kerbowa]

Factor out MC changes, cleanup, add nop padding.

[kerbowa]

Rebase with non-metadata based kernarg preload tracking.

[kerbowa]

Fixup feature checks.

[kerbowa]

Limit preloading to gfx940.

[arsenm]

Also should do the globalisel equivalent

llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h

158

Why is it a map? Isn't this just an array?

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

209

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

833–839

Shouldn't need this, there are already nop emission utilities?

845

emitValueToAlignment?

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

2247

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

246

This can return ArrayRef?

267

Typo Kerarg

llvm/test/CodeGen/AMDGPU/preload-kernargs.ll

22

should be able to use a directive to avoid spamming this

[kerbowa]

Rebase, address comments.

llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h

158

We would at least need an offset stored somewhere since we shouldn't assume preloads will always start at the first kernel argument.

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

845

I'm not sure how relevant the alignment is here actually. What matters is that we are emitting exactly 256 bytes.

[bcahoon]

Looks good to me. I also tried some additional tests and they also worked as expected.

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

2319

Always

[kerbowa]

Fix case where aligned register class was not a trivially lowerable copy.

[bcahoon]

Changes LGTM. Thanks!

llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h

 //==- AMDGPUArgumentrUsageInfo.h - Function Arg Usage Info -------*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUARGUMENTUSAGEINFO_H
 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUARGUMENTUSAGEINFO_H
 
+#include "llvm/ADT/DenseMap.h"
 #include "llvm/CodeGen/Register.h"
 #include "llvm/Pass.h"
 
 namespace llvm {
 
 class Function;
 class LLT;
 class raw_ostream;
private:
 
   // Bitmask to locate argument within the register.
   unsigned Mask;
 
   bool IsStack : 1;
   bool IsSet : 1;
 
 public:
-  constexpr ArgDescriptor(unsigned Val = 0, unsigned Mask = ~0u,
-                bool IsStack = false, bool IsSet = false)
+  ArgDescriptor(unsigned Val = 0, unsigned Mask = ~0u, bool IsStack = false,
+                bool IsSet = false)
       : Reg(Val), Mask(Mask), IsStack(IsStack), IsSet(IsSet) {}
 
-  static constexpr ArgDescriptor createRegister(Register Reg,
-                                                unsigned Mask = ~0u) {
+  static ArgDescriptor createRegister(Register Reg, unsigned Mask = ~0u) {
     return ArgDescriptor(Reg, Mask, false, true);
   }
 
-  static constexpr ArgDescriptor createStack(unsigned Offset,
-                                             unsigned Mask = ~0u) {
+  static ArgDescriptor createStack(unsigned Offset, unsigned Mask = ~0u) {
     return ArgDescriptor(Offset, Mask, true, true);
   }
 
-  static constexpr ArgDescriptor createArg(const ArgDescriptor &Arg,
-                                           unsigned Mask) {
+  static ArgDescriptor createArg(const ArgDescriptor &Arg, unsigned Mask) {
     return ArgDescriptor(Arg.Reg, Mask, Arg.IsStack, Arg.IsSet);
   }
 
   bool isSet() const {
     return IsSet;
   }
 
   explicit operator bool() const {
public:
   void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const;
 };
 
 inline raw_ostream &operator<<(raw_ostream &OS, const ArgDescriptor &Arg) {
   Arg.print(OS);
   return OS;
 }
 
+struct KernArgPreloadDescriptor : public ArgDescriptor {
+  KernArgPreloadDescriptor() {}
+  SmallVector<MCRegister> Regs;
+};
+
 struct AMDGPUFunctionArgInfo {
   enum PreloadedValue {
     // SGPRS:
     PRIVATE_SEGMENT_BUFFER = 0,
     DISPATCH_PTR        =  1,
     QUEUE_PTR           =  2,
     KERNARG_SEGMENT_PTR =  3,
     DISPATCH_ID         =  4,
struct AMDGPUFunctionArgInfo {
   ArgDescriptor ImplicitBufferPtr;
 
   // VGPRs inputs. For entry functions these are either v0, v1 and v2 or packed
   // into v0, 10 bits per dimension if packed-tid is set.
   ArgDescriptor WorkItemIDX;
   ArgDescriptor WorkItemIDY;
   ArgDescriptor WorkItemIDZ;
 
+  // Map the index of preloaded kernel arguments to its descriptor.
+  SmallDenseMap<int, KernArgPreloadDescriptor> PreloadKernArgs{};
+
   std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
   getPreloadedValue(PreloadedValue Value) const;
 
-  static constexpr AMDGPUFunctionArgInfo fixedABILayout();
+  static AMDGPUFunctionArgInfo fixedABILayout();
 };
 
 class AMDGPUArgumentUsageInfo : public ImmutablePass {
 private:
   DenseMap<const Function *, AMDGPUFunctionArgInfo> ArgInfoMap;
 
 public:
   static char ID;

llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp

bool AMDGPUArgumentUsageInfo::doInitialization(Module &M) {
   return false;
 }
 
 bool AMDGPUArgumentUsageInfo::doFinalization(Module &M) {
   ArgInfoMap.clear();
   return false;
 }
 
+// TODO: Print preload kernargs?
 void AMDGPUArgumentUsageInfo::print(raw_ostream &OS, const Module *M) const {
   for (const auto &FI : ArgInfoMap) {
     OS << "Arguments for " << FI.first->getName() << '\n'
        << "  PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
        << "  DispatchPtr: " << FI.second.DispatchPtr
        << "  QueuePtr: " << FI.second.QueuePtr
        << "  KernargSegmentPtr: " << FI.second.KernargSegmentPtr
        << "  DispatchID: " << FI.second.DispatchID
return std::tuple(WorkItemIDY ? &WorkItemIDY : nullptr,
                       &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
   case AMDGPUFunctionArgInfo::WORKITEM_ID_Z:
     return std::tuple(WorkItemIDZ ? &WorkItemIDZ : nullptr,
                       &AMDGPU::VGPR_32RegClass, LLT::scalar(32));
   }
   llvm_unreachable("unexpected preloaded value type");
 }
 
-constexpr AMDGPUFunctionArgInfo AMDGPUFunctionArgInfo::fixedABILayout() {
+AMDGPUFunctionArgInfo AMDGPUFunctionArgInfo::fixedABILayout() {
   AMDGPUFunctionArgInfo AI;
   AI.PrivateSegmentBuffer
     = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3);
   AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5);
   AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7);
 
   // Do not pass kernarg segment pointer, only pass increment version in its
   // place.

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

if (STM.isMesaKernel(F) &&
        F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
     amd_kernel_code_t KernelCode;
     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
   }
 
   if (STM.isAmdHsaOS())
     HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo);
+
+  if (MFI.getNumKernargPreloadedSGPRs() > 0) {
+    assert(AMDGPU::hasKernargPreload(STM));
+    getTargetStreamer()->EmitKernargPreloadHeader(*getGlobalSTI());
+  }
 }
 
 void AMDGPUAsmPrinter::emitFunctionBodyEnd() {
   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
   if (!MFI.isEntryFunction())
     return;
 
   if (TM.getTargetTriple().getOS() != Triple::AMDHSA)
uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
   return KernelCodeProperties;
 }
 
 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
     const MachineFunction &MF,
     const SIProgramInfo &PI) const {
   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
   const Function &F = MF.getFunction();
+  const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
 
   amdhsa::kernel_descriptor_t KernelDescriptor;
   memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
 
   assert(isUInt<32>(PI.ScratchSize));
   assert(isUInt<32>(PI.getComputePGMRSrc1()));
   assert(isUInt<32>(PI.getComputePGMRSrc2()));
 
   KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
   KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
 
   Align MaxKernArgAlign;
   KernelDescriptor.kernarg_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
 
   KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1();
   KernelDescriptor.compute_pgm_rsrc2 = PI.getComputePGMRSrc2();
   KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
 
   assert(STM.hasGFX90AInsts() || CurrentProgramInfo.ComputePGMRSrc3GFX90A == 0);
   if (STM.hasGFX90AInsts())
     KernelDescriptor.compute_pgm_rsrc3 =
       CurrentProgramInfo.ComputePGMRSrc3GFX90A;
 
+  if (AMDGPU::hasKernargPreload(STM))
+    KernelDescriptor.kernarg_preload =
+        static_cast<uint16_t>(Info->getNumKernargPreloadedSGPRs());
+
   return KernelDescriptor;
 }
 
 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   // Init target streamer lazily on the first function so that previous passes
   // can set metadata.
   if (!IsTargetStreamerInitialized)
     initTargetStreamer(*MF.getFunction().getParent());

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

 const AMDGPUSubtarget &AMDGPUSubtarget::get(const TargetMachine &TM, const Function &F) {
   if (TM.getTargetTriple().getArch() == Triple::amdgcn)
     return static_cast<const AMDGPUSubtarget&>(TM.getSubtarget<GCNSubtarget>(F));
   else
     return static_cast<const AMDGPUSubtarget&>(TM.getSubtarget<R600Subtarget>(F));
 }
 
 GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(const Function &F,
-                                           const GCNSubtarget &ST) {
+                                           const GCNSubtarget &ST)
+    : ST(ST) {
   const CallingConv::ID CC = F.getCallingConv();
   const bool IsKernel =
       CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL;
   // FIXME: Should have analysis or something rather than attribute to detect
   // calls.
   const bool HasCalls = F.hasFnAttribute("amdgpu-calls");
   // FIXME: This attribute is a hack, we just need an analysis on the function
   // to look for allocas.
GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(const Function &F,
   // detecting calls or stack objects that may require it before argument
   // lowering.
   if (ST.hasFlatAddressSpace() && AMDGPU::isEntryFunctionCC(CC) &&
       (IsAmdHsaOrMesa || ST.enableFlatScratch()) &&
       (HasCalls || HasStackObjects || ST.enableFlatScratch()) &&
       !ST.flatScratchIsArchitected()) {
     FlatScratchInit = true;
   }
-}
 
-unsigned GCNUserSGPRUsageInfo::getNumUsedUserSGPRs() const {
-  unsigned NumUserSGPRs = 0;
   if (hasImplicitBufferPtr())
-    NumUserSGPRs += getNumUserSGPRForField(ImplicitBufferPtrID);
+    NumUsedUserSGPRs += getNumUserSGPRForField(ImplicitBufferPtrID);
 
   if (hasPrivateSegmentBuffer())
-    NumUserSGPRs += getNumUserSGPRForField(PrivateSegmentBufferID);
+    NumUsedUserSGPRs += getNumUserSGPRForField(PrivateSegmentBufferID);
 
   if (hasDispatchPtr())
-    NumUserSGPRs += getNumUserSGPRForField(DispatchPtrID);
+    NumUsedUserSGPRs += getNumUserSGPRForField(DispatchPtrID);
 
   if (hasQueuePtr())
-    NumUserSGPRs += getNumUserSGPRForField(QueuePtrID);
+    NumUsedUserSGPRs += getNumUserSGPRForField(QueuePtrID);
 
   if (hasKernargSegmentPtr())
-    NumUserSGPRs += getNumUserSGPRForField(KernargSegmentPtrID);
+    NumUsedUserSGPRs += getNumUserSGPRForField(KernargSegmentPtrID);
 
   if (hasDispatchID())
-    NumUserSGPRs += getNumUserSGPRForField(DispatchIdID);
+    NumUsedUserSGPRs += getNumUserSGPRForField(DispatchIdID);
 
   if (hasFlatScratchInit())
-    NumUserSGPRs += getNumUserSGPRForField(FlatScratchInitID);
+    NumUsedUserSGPRs += getNumUserSGPRForField(FlatScratchInitID);
+}
+
+void GCNUserSGPRUsageInfo::allocKernargPreloadSGPRs(unsigned NumSGPRs) {
+  assert(NumKernargPreloadSGPRs + NumSGPRs <= AMDGPU::getMaxNumUserSGPRs(ST));
+  NumKernargPreloadSGPRs += NumSGPRs;
+  NumUsedUserSGPRs += NumSGPRs;
+}
 
-  return NumUserSGPRs;
+unsigned GCNUserSGPRUsageInfo::getNumFreeUserSGPRs() {
+  return AMDGPU::getMaxNumUserSGPRs(ST) - NumUsedUserSGPRs;
 }

llvm/lib/Target/AMDGPU/GCNSubtarget.h

bool requiresNopBeforeDeallocVGPRs() const {
     // Currently all targets that support the dealloc VGPRs message also require
     // the nop.
     return true;
   }
 };
 
 class GCNUserSGPRUsageInfo {
 public:
-  unsigned getNumUsedUserSGPRs() const;
-
   bool hasImplicitBufferPtr() const { return ImplicitBufferPtr; }
 
   bool hasPrivateSegmentBuffer() const { return PrivateSegmentBuffer; }
 
   bool hasDispatchPtr() const { return DispatchPtr; }
 
   bool hasQueuePtr() const { return QueuePtr; }
 
   bool hasKernargSegmentPtr() const { return KernargSegmentPtr; }
 
   bool hasDispatchID() const { return DispatchID; }
 
   bool hasFlatScratchInit() const { return FlatScratchInit; }
 
+  unsigned getNumKernargPreloadSGPRs() const { return NumKernargPreloadSGPRs; }
+
+  unsigned getNumUsedUserSGPRs() const { return NumUsedUserSGPRs; }
+
+  unsigned getNumFreeUserSGPRs();
+
+  void allocKernargPreloadSGPRs(unsigned NumSGPRs);
+
   enum UserSGPRID : unsigned {
     ImplicitBufferPtrID = 0,
     PrivateSegmentBufferID = 1,
     DispatchPtrID = 2,
     QueuePtrID = 3,
     KernargSegmentPtrID = 4,
     DispatchIdID = 5,
     FlatScratchInitID = 6,
case PrivateSegmentSizeID:
       return 1;
     }
     llvm_unreachable("Unknown UserSGPRID.");
   }
 
   GCNUserSGPRUsageInfo(const Function &F, const GCNSubtarget &ST);
 
 private:
+  const GCNSubtarget &ST;
+
   // Private memory buffer
   // Compute directly in sgpr[0:1]
   // Other shaders indirect 64-bits at sgpr[0:1]
   bool ImplicitBufferPtr = false;
 
   bool PrivateSegmentBuffer = false;
 
   bool DispatchPtr = false;
 
   bool QueuePtr = false;
 
   bool KernargSegmentPtr = false;
 
   bool DispatchID = false;
 
   bool FlatScratchInit = false;
+
+  unsigned NumKernargPreloadSGPRs = 0;
+
+  unsigned NumUsedUserSGPRs = 0;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_AMDGPU_GCNSUBTARGET_H

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h

public:
   /// \returns True on success, false on failure.
   virtual bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) {
     return true;
   }
 
   /// \returns True on success, false on failure.
   virtual bool EmitCodeEnd(const MCSubtargetInfo &STI) { return true; }
 
+  /// \returns True on success, false on failure.
+  virtual bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI) {
+    return true;
+  }
+
   virtual void EmitAmdhsaKernelDescriptor(
       const MCSubtargetInfo &STI, StringRef KernelName,
       const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
       uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
       unsigned CodeObjectVersion){};
 
   static StringRef getArchNameFromElfMach(unsigned ElfMach);
   static unsigned getElfMach(StringRef GPU);
public:
   bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
 
   /// \returns True on success, false on failure.
   bool EmitCodeEnd(const MCSubtargetInfo &STI) override;
 
+  /// \returns True on success, false on failure.
+  bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI) override;
+
   void EmitAmdhsaKernelDescriptor(
       const MCSubtargetInfo &STI, StringRef KernelName,
       const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
       uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
       unsigned CodeObjectVersion) override;
 };
 
 class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer {
public:
   bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
 
   /// \returns True on success, false on failure.
   bool EmitCodeEnd(const MCSubtargetInfo &STI) override;
 
+  /// \returns True on success, false on failure.
+  bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI) override;
+
   void EmitAmdhsaKernelDescriptor(
       const MCSubtargetInfo &STI, StringRef KernelName,
       const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
       uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
       unsigned CodeObjectVersion) override;
 };
 
 }
 #endif

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA,
            [&](MCELFStreamer &OS) {
              OS.emitLabel(DescBegin);
              OS.emitBytes(HSAMetadataString);
              OS.emitLabel(DescEnd);
            });
   return true;
 }
 
+bool AMDGPUTargetAsmStreamer::EmitKernargPreloadHeader(
+    const MCSubtargetInfo &STI) {
+  for (int i = 0; i < 64; ++i) {
+    OS << "\ts_nop 0\n";
+  }
+  return true;
+}
+
+bool AMDGPUTargetELFStreamer::EmitKernargPreloadHeader(
+    const MCSubtargetInfo &STI) {
+  const uint32_t Encoded_s_nop = 0xbf800000;
+  MCStreamer &OS = getStreamer();
+  for (int i = 0; i < 64; ++i) {
+    OS.emitInt32(Encoded_s_nop);
+  }
+  return true;
+}
+
 bool AMDGPUTargetELFStreamer::EmitCodeEnd(const MCSubtargetInfo &STI) {
   const uint32_t Encoded_s_code_end = 0xbf9f0000;
   const uint32_t Encoded_s_nop = 0xbf800000;
   uint32_t Encoded_pad = Encoded_s_code_end;
 
   // Instruction cache line size in bytes.
   const unsigned Log2CacheLineSize = AMDGPU::isGFX11Plus(STI) ? 7 : 6;
   const unsigned CacheLineSize = 1u << Log2CacheLineSize;
Streamer.emitValue(MCBinaryExpr::createSub(
           KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
       MCSymbolRefExpr::create(
           KernelDescriptorSymbol, MCSymbolRefExpr::VK_None, Context),
       Context),
       sizeof(KernelDescriptor.kernel_code_entry_byte_offset));
   for (uint8_t Res : KernelDescriptor.reserved1)
     Streamer.emitInt8(Res);
   Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc3);
   Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc1);
   Streamer.emitInt32(KernelDescriptor.compute_pgm_rsrc2);
   Streamer.emitInt16(KernelDescriptor.kernel_code_properties);
   Streamer.emitInt16(KernelDescriptor.kernarg_preload);
   for (uint8_t Res : KernelDescriptor.reserved3)
     Streamer.emitInt8(Res);
 }

llvm/lib/Target/AMDGPU/SIISelLowering.h

bool requiresUniformRegister(MachineFunction &MF,
                                const Value *V) const override;
   Align getPrefLoopAlignment(MachineLoop *ML) const override;
 
   void allocateHSAUserSGPRs(CCState &CCInfo,
                             MachineFunction &MF,
                             const SIRegisterInfo &TRI,
                             SIMachineFunctionInfo &Info) const;
 
+  void allocatePreloadKernArgSGPRs(CCState &CCInfo,
+                                   SmallVectorImpl<CCValAssign> &ArgLocs,
+                                   const SmallVectorImpl<ISD::InputArg> &Ins,
+                                   MachineFunction &MF,
+                                   const SIRegisterInfo &TRI,
+                                   SIMachineFunctionInfo &Info) const;
+
+  void allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF,
+                           const SIRegisterInfo &TRI,
+                           SIMachineFunctionInfo &Info) const;
+
   void allocateSystemSGPRs(CCState &CCInfo,
                            MachineFunction &MF,
                            SIMachineFunctionInfo &Info,
                            CallingConv::ID CallConv,
                            bool IsShader) const;
 
   void allocateSpecialEntryInputVGPRs(CCState &CCInfo,
                                       MachineFunction &MF,

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

void SITargetLowering::allocateHSAUserSGPRs(CCState &CCInfo,
   }
 
   if (UserSGPRInfo.hasFlatScratchInit() && !getSubtarget()->isAmdPalOS()) {
     Register FlatScratchInitReg = Info.addFlatScratchInit(TRI);
     MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
     CCInfo.AllocateReg(FlatScratchInitReg);
   }
 
+  // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
+  // these from the dispatch pointer.
+}
+
+// Allocate pre-loaded kernel arguemtns. Arguments to be preloading must be
+// sequential starting from the first argument.
+void SITargetLowering::allocatePreloadKernArgSGPRs(
+    CCState &CCInfo, SmallVectorImpl<CCValAssign> &ArgLocs,
+    const SmallVectorImpl<ISD::InputArg> &Ins, MachineFunction &MF,
+    const SIRegisterInfo &TRI, SIMachineFunctionInfo &Info) const {
+  Function &F = MF.getFunction();
+  unsigned LastExplicitArgOffset =
+      MF.getSubtarget<GCNSubtarget>().getExplicitKernelArgOffset();
+  GCNUserSGPRUsageInfo &SGPRInfo = Info.getUserSGPRInfo();
+  bool InPreloadSequence = true;
+  unsigned InIdx = 0;
+  for (auto &Arg : F.args()) {
+    if (!InPreloadSequence || !Arg.hasInRegAttr())
+      break;
+
+    int ArgIdx = Arg.getArgNo();
+    // Don't preload non-original args or parts not in the current preload
+    // sequence.
+    if (InIdx < Ins.size() && (!Ins[InIdx].isOrigArg() ||
+                               (int)Ins[InIdx].getOrigArgIndex() != ArgIdx))
+      break;
+
+    for (; InIdx < Ins.size() && Ins[InIdx].isOrigArg() &&
+           (int)Ins[InIdx].getOrigArgIndex() == ArgIdx;
+         InIdx++) {
+      assert(ArgLocs[ArgIdx].isMemLoc());
+      auto &ArgLoc = ArgLocs[InIdx];
+      const Align KernelArgBaseAlign = Align(16);
+      unsigned ArgOffset = ArgLoc.getLocMemOffset();
+      Align Alignment = commonAlignment(KernelArgBaseAlign, ArgOffset);
+      unsigned NumAllocSGPRs =
+          alignTo(ArgLoc.getLocVT().getFixedSizeInBits(), 32) / 32;
+
+      // Arg is preloaded into the previous SGPR.
+      if (ArgLoc.getLocVT().getStoreSize() < 4 && Alignment < 4) {
+        Info.getArgInfo().PreloadKernArgs[InIdx].Regs.push_back(
+            Info.getArgInfo().PreloadKernArgs[InIdx - 1].Regs[0]);
+        continue;
+      }
+
+      unsigned Padding = ArgOffset - LastExplicitArgOffset;
+      unsigned PaddingSGPRs = alignTo(Padding, 4) / 4;
+      // Check for free user SGPRs for preloading.
+      if (PaddingSGPRs + NumAllocSGPRs + 1 /*Synthetic SGPRs*/ >
+          SGPRInfo.getNumFreeUserSGPRs()) {
+        InPreloadSequence = false;
+        break;
+      }
+
+      // Preload this argument.
+      const TargetRegisterClass *RC =
+          TRI.getSGPRClassForBitWidth(NumAllocSGPRs * 32);
+      SmallVectorImpl<MCRegister> *PreloadRegs =
+          Info.addPreloadedKernArg(TRI, RC, NumAllocSGPRs, InIdx, PaddingSGPRs);
+
+      if (PreloadRegs->size() > 1)
+        RC = &AMDGPU::SGPR_32RegClass;
+      for (auto &Reg : *PreloadRegs) {
+        assert(Reg);
+        MF.addLiveIn(Reg, RC);
+        CCInfo.AllocateReg(Reg);
+      }
+
+      LastExplicitArgOffset = NumAllocSGPRs * 4 + ArgOffset;
+    }
+  }
+}
+
+void SITargetLowering::allocateLDSKernelId(CCState &CCInfo, MachineFunction &MF,
+                                           const SIRegisterInfo &TRI,
+                                           SIMachineFunctionInfo &Info) const {
+  // Always allocate this last since it is a synthetic preload.
   if (Info.hasLDSKernelId()) {
     Register Reg = Info.addLDSKernelId();
     MF.addLiveIn(Reg, &AMDGPU::SGPR_32RegClass);
     CCInfo.AllocateReg(Reg);
   }
-
-  // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
-  // these from the dispatch pointer.
 }
 
 // Allocate special input registers that are initialized per-wave.
 void SITargetLowering::allocateSystemSGPRs(CCState &CCInfo,
                                            MachineFunction &MF,
                                            SIMachineFunctionInfo &Info,
                                            CallingConv::ID CallConv,
                                            bool IsShader) const {
if (Subtarget->isAmdPalOS()) {
         Info->markPSInputEnabled(llvm::countr_zero(Info->getPSInputAddr()));
     }
   } else if (IsKernel) {
     assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX());
   } else {
     Splits.append(Ins.begin(), Ins.end());
   }
 
+  if (IsKernel)
+    analyzeFormalArgumentsCompute(CCInfo, Ins);
+
   if (IsEntryFunc) {
     allocateSpecialEntryInputVGPRs(CCInfo, MF, *TRI, *Info);
     allocateHSAUserSGPRs(CCInfo, MF, *TRI, *Info);
+    if (IsKernel && Subtarget->hasKernargPreload() &&
+        !Subtarget->needsKernargPreloadBackwardsCompatibility())
+      allocatePreloadKernArgSGPRs(CCInfo, ArgLocs, Ins, MF, *TRI, *Info);
+
+    allocateLDSKernelId(CCInfo, MF, *TRI, *Info);
   } else if (!IsGraphics) {
     // For the fixed ABI, pass workitem IDs in the last argument register.
     allocateSpecialInputVGPRsFixed(CCInfo, MF, *TRI, *Info);
   }
 
-  if (IsKernel) {
-    analyzeFormalArgumentsCompute(CCInfo, Ins);
-  } else {
+  if (!IsKernel) {
     CCAssignFn *AssignFn = CCAssignFnForCall(CallConv, isVarArg);
     CCInfo.AnalyzeFormalArguments(Splits, AssignFn);
   }
 
   SmallVector<SDValue, 16> Chains;
 
   // FIXME: This is the minimum kernel argument alignment. We should improve
   // this to the maximum alignment of the arguments.
if (IsEntryFunc && VA.isMemLoc()) {
           Ptr = DAG.getAddrSpaceCast(DL, VT, Ptr, AMDGPUAS::CONSTANT_ADDRESS,
                                      Arg.Flags.getPointerAddrSpace());
         }
 
         InVals.push_back(Ptr);
         continue;
       }
 
-      SDValue Arg = lowerKernargMemParameter(
-        DAG, VT, MemVT, DL, Chain, Offset, Alignment, Ins[i].Flags.isSExt(), &Ins[i]);
-      Chains.push_back(Arg.getValue(1));
+      SDValue NewArg;
+      if (Arg.isOrigArg() && Info->getArgInfo().PreloadKernArgs.count(i)) {
+        if (MemVT.getStoreSize() < 4 && Alignment < 4) {
+          // In this case the argument is packed into the previous preload SGPR.
+          int64_t AlignDownOffset = alignDown(Offset, 4);
+          int64_t OffsetDiff = Offset - AlignDownOffset;
+          EVT IntVT = MemVT.changeTypeToInteger();
+
+          const SIMachineFunctionInfo *Info =
+              MF.getInfo<SIMachineFunctionInfo>();
+          MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
+          Register Reg =
+              Info->getArgInfo().PreloadKernArgs.find(i)->getSecond().Regs[0];
+
+          assert(Reg);
+          Register VReg = MRI.getLiveInVirtReg(Reg);
+          SDValue Copy = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i32);
+
+          SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, DL, MVT::i32);
+          SDValue Extract = DAG.getNode(ISD::SRL, DL, MVT::i32, Copy, ShiftAmt);
+
+          SDValue ArgVal = DAG.getNode(ISD::TRUNCATE, DL, IntVT, Extract);
+          ArgVal = DAG.getNode(ISD::BITCAST, DL, MemVT, ArgVal);
+          NewArg = convertArgType(DAG, VT, MemVT, DL, ArgVal,
+                                  Ins[i].Flags.isSExt(), &Ins[i]);
+
+          NewArg = DAG.getMergeValues({NewArg, Copy.getValue(1)}, DL);
+        } else {
+          const SIMachineFunctionInfo *Info =
+              MF.getInfo<SIMachineFunctionInfo>();
+          MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
+          const SmallVectorImpl<MCRegister> &PreloadRegs =
+              Info->getArgInfo().PreloadKernArgs.find(i)->getSecond().Regs;
+
+          SDValue Copy;
+          if (PreloadRegs.size() == 1) {
+            Register VReg = MRI.getLiveInVirtReg(PreloadRegs[0]);
+            const TargetRegisterClass *RC = MRI.getRegClass(VReg);
+            NewArg = DAG.getCopyFromReg(
+                Chain, DL, VReg,
+                EVT::getIntegerVT(*DAG.getContext(),
+                                  TRI->getRegSizeInBits(*RC)));
+
+          } else {
+            // If the kernarg alignment does not match the alignment of the SGPR
+            // tuple RC that can accommodate this argument, it will be built up
+            // via copies from from the individual SGPRs that the argument was
+            // preloaded to.
+            SmallVector<SDValue, 4> Elts;
+            for (auto Reg : PreloadRegs) {
+              Register VReg = MRI.getLiveInVirtReg(Reg);
+              Copy = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i32);
+              Elts.push_back(Copy);
+            }
+            NewArg =
+                DAG.getBuildVector(EVT::getVectorVT(*DAG.getContext(), MVT::i32,
+                                                    PreloadRegs.size()),
+                                   DL, Elts);
+          }
+
+          SDValue CMemVT;
+          if (VT.isScalarInteger() && VT.bitsLT(NewArg.getSimpleValueType()))
+            CMemVT = DAG.getNode(ISD::TRUNCATE, DL, MemVT, NewArg);
+          else
+            CMemVT = DAG.getBitcast(MemVT, NewArg);
+          NewArg = convertArgType(DAG, VT, MemVT, DL, CMemVT,
+                                  Ins[i].Flags.isSExt(), &Ins[i]);
+          NewArg = DAG.getMergeValues({NewArg, Chain}, DL);
+        }
+      } else {
+        NewArg =
+            lowerKernargMemParameter(DAG, VT, MemVT, DL, Chain, Offset,
+                                     Alignment, Ins[i].Flags.isSExt(), &Ins[i]);
+      }
+      Chains.push_back(NewArg.getValue(1));
 
       auto *ParamTy =
         dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
       if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
           ParamTy && (ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
                       ParamTy->getAddressSpace() == AMDGPUAS::REGION_ADDRESS)) {
         // On SI local pointers are just offsets into LDS, so they are always
         // less than 16-bits.  On CI and newer they could potentially be
         // real pointers, so we can't guarantee their size.
-        Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
+        NewArg = DAG.getNode(ISD::AssertZext, DL, NewArg.getValueType(), NewArg,
                              DAG.getValueType(MVT::i16));
       }
 
-      InVals.push_back(Arg);
+      InVals.push_back(NewArg);
       continue;
     } else if (!IsEntryFunc && VA.isMemLoc()) {
       SDValue Val = lowerStackParameter(DAG, VA, DL, Chain, Arg);
       InVals.push_back(Val);
       if (!Arg.Flags.isByVal())
         Chains.push_back(Val.getValue(1));
       continue;
     }

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

 #include "AMDGPUArgumentUsageInfo.h"
 #include "AMDGPUMachineFunction.h"
 #include "AMDGPUTargetMachine.h"
 #include "GCNSubtarget.h"
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "SIInstrInfo.h"
 #include "SIModeRegisterDefaults.h"
 #include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MIRYamlMapping.h"
 #include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Support/raw_ostream.h"
 #include <optional>
 
 namespace llvm {
 
 class MachineFrameInfo;
public:
   ArrayRef<Register> getSGPRSpillVGPRs() const { return SpillVGPRs; }
   const WWMSpillsMap &getWWMSpills() const { return WWMSpills; }
   const ReservedRegSet &getWWMReservedRegs() const { return WWMReservedRegs; }
 
   const PrologEpilogSGPRSpillsMap &getPrologEpilogSGPRSpills() const {
     return PrologEpilogSGPRSpills;
   }
 
+  GCNUserSGPRUsageInfo &getUserSGPRInfo() { return UserSGPRInfo; }
+
   const GCNUserSGPRUsageInfo &getUserSGPRInfo() const { return UserSGPRInfo; }
 
   void addToPrologEpilogSGPRSpills(Register Reg,
                                    PrologEpilogSGPRSaveRestoreInfo SI) {
     PrologEpilogSGPRSpills.insert(std::make_pair(Reg, SI));
   }
 
   // Check if an entry created for \p Reg in PrologEpilogSGPRSpills. Return true
public:
   Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI);
   Register addDispatchPtr(const SIRegisterInfo &TRI);
   Register addQueuePtr(const SIRegisterInfo &TRI);
   Register addKernargSegmentPtr(const SIRegisterInfo &TRI);
   Register addDispatchID(const SIRegisterInfo &TRI);
   Register addFlatScratchInit(const SIRegisterInfo &TRI);
   Register addImplicitBufferPtr(const SIRegisterInfo &TRI);
   Register addLDSKernelId();
+  SmallVectorImpl<MCRegister> *
+  addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC,
+                      unsigned AllocSizeDWord, int KernArgIdx,
+                      int PaddingSGPRs);
 
   /// Increment user SGPRs used for padding the argument list only.
   Register addReservedUserSGPR() {
     Register Next = getNextUserSGPR();
     ++NumUserSGPRs;
     return Next;
   }
 
public:
   unsigned getNumUserSGPRs() const {
     return NumUserSGPRs;
   }
 
   unsigned getNumPreloadedSGPRs() const {
     return NumUserSGPRs + NumSystemSGPRs;
   }
 
+  unsigned getNumKernargPreloadedSGPRs() const {
+    return UserSGPRInfo.getNumKernargPreloadSGPRs();
+  }
+
   Register getPrivateSegmentWaveByteOffsetSystemSGPR() const {
     return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
   }
 
   /// Returns the physical register reserved for use as the resource
   /// descriptor for scratch accesses.
   Register getScratchRSrcReg() const {
     return ScratchRSrcReg;

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

 }
 
 Register SIMachineFunctionInfo::addLDSKernelId() {
   ArgInfo.LDSKernelId = ArgDescriptor::createRegister(getNextUserSGPR());
   NumUserSGPRs += 1;
   return ArgInfo.LDSKernelId.getRegister();
 }
 
+SmallVectorImpl<MCRegister> *SIMachineFunctionInfo::addPreloadedKernArg(
+    const SIRegisterInfo &TRI, const TargetRegisterClass *RC,
+    unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs) {
+  assert(!ArgInfo.PreloadKernArgs.count(KernArgIdx) &&
+         "Preload kernel argument allocated twice.");
+  NumUserSGPRs += PaddingSGPRs;
+  // If the available register tuples are aligned with the kernarg to be
+  // preloaded use that register, otherwise we need to use a set of SGPRs and
+  // merge them.
+  Register PreloadReg =
+      TRI.getMatchingSuperReg(getNextUserSGPR(), AMDGPU::sub0, RC);
+  if (PreloadReg &&
+      (RC == &AMDGPU::SReg_32RegClass || RC == &AMDGPU::SReg_64RegClass)) {
+    ArgInfo.PreloadKernArgs[KernArgIdx].Regs.push_back(PreloadReg);
+    NumUserSGPRs += AllocSizeDWord;
+  } else {
+    for (unsigned I = 0; I < AllocSizeDWord; ++I) {
+      ArgInfo.PreloadKernArgs[KernArgIdx].Regs.push_back(getNextUserSGPR());
+      NumUserSGPRs++;
+    }
+  }
+
+  // Track the actual number of SGPRs that HW will preload to.
+  UserSGPRInfo.allocKernargPreloadSGPRs(AllocSizeDWord + PaddingSGPRs);
+  return &ArgInfo.PreloadKernArgs[KernArgIdx].Regs;
+}
+
 void SIMachineFunctionInfo::allocateWWMSpill(MachineFunction &MF, Register VGPR,
                                              uint64_t Size, Align Alignment) {
   // Skip if it is an entry function or the register is already added.
   if (isEntryFunction() || WWMSpills.count(VGPR))
     return;
 
   WWMSpills.insert(std::make_pair(
       VGPR, MF.getFrameInfo().CreateSpillStackObject(Size, Alignment)));
auto convertArg = [&](std::optional<yaml::SIArgument> &A,
     // Check and update the optional mask.
     if (Arg.isMasked())
       SA.Mask = Arg.getMask();
 
     A = SA;
     return true;
   };
 
+  // TODO: Need to serialize kernarg preloads.
   bool Any = false;
   Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
   Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
   Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
   Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
   Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
   Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
   Any |= convertArg(AI.LDSKernelId, ArgInfo.LDSKernelId);

llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll

 declare double @llvm.amdgcn.global.atomic.fadd.f64.p1.f64(ptr addrspace(1) %ptr, double %data)
 declare double @llvm.amdgcn.global.atomic.fmin.f64.p1.f64(ptr addrspace(1) %ptr, double %data)
 declare double @llvm.amdgcn.global.atomic.fmax.f64.p1.f64(ptr addrspace(1) %ptr, double %data)
 declare double @llvm.amdgcn.flat.atomic.fadd.f64.p0.f64(ptr %ptr, double %data)
 declare double @llvm.amdgcn.flat.atomic.fmin.f64.p0.f64(ptr %ptr, double %data)
 declare double @llvm.amdgcn.flat.atomic.fmax.f64.p0.f64(ptr %ptr, double %data)
 declare double @llvm.amdgcn.ds.fadd.f64(ptr addrspace(3) nocapture, double, i32, i32, i1)
 
-define amdgpu_kernel void @raw_buffer_atomic_add_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_buffer_atomic_add_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_buffer_atomic_add_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_buffer_atomic_add_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_add_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_add_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_add_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_add_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_add_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_buffer_atomic_add_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_buffer_atomic_add_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_buffer_atomic_add_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_add_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_add_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_add_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_add_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @raw_buffer_atomic_min_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_buffer_atomic_min_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_buffer_atomic_min_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_buffer_atomic_min_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_min_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_min_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_min_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_min_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_min_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_buffer_atomic_min_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_buffer_atomic_min_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_buffer_atomic_min_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_min_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_min_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_min_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_min_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @raw_buffer_atomic_max_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_buffer_atomic_max_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_buffer_atomic_max_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_buffer_atomic_max_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_max_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_max_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_max_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_max_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_max_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_buffer_atomic_max_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_buffer_atomic_max_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_buffer_atomic_max_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_max_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_max_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_max_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_max_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

llvm/test/CodeGen/AMDGPU/dag-divergence-atomic.ll

; CHECK-NEXT:    s_endpgm
   %f64 = call double @llvm.amdgcn.global.atomic.fmax.f64.p1.f64(ptr addrspace(1) %p, double 1.0)
   %n32 = fptoui double %f64 to i32
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.swap(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.swap(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.swap:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_swap v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.swap.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.add(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.add(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.add:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_add v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.add.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.sub(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.sub(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.sub:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_sub v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.sub.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.smin(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.smin(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.smin:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_smin v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.smin.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.smax(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.smax(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.smax:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_smax v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.smax.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.umin(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.umin(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.umin:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_umin v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.umin.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.umax(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.umax(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.umax:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_umax v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.umax.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.and(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.and(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.and:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_and v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.and.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.or(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.or(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.or:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_or v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.or.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.xor(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.xor(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.xor:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_xor v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.xor.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.inc(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.inc(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.inc:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_inc v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.inc.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.dec(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.dec(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.dec:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v1, s2
 ; CHECK-NEXT:    buffer_atomic_dec v0, v1, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.dec.i32(i32 1, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.cmpswap(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.cmpswap(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.cmpswap:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 2
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 1
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v2, s2
 ; CHECK-NEXT:    buffer_atomic_cmpswap v[0:1], v2, s[4:7], 0 offen glc
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %n32 = call i32 @llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.i32(i32 1, i32 2, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.fadd(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.fadd(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.fadd:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 1.0
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v0, s2
 ; CHECK-NEXT:    buffer_atomic_add_f32 v1, v0, s[4:7], 0 offen glc
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_cvt_u32_f32_e32 v0, v1
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %f32 = call float @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f32(float 1.0, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n32 = fptoui float %f32 to i32
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.fmin(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.fmin(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.fmin:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0x3ff00000
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
 ; CHECK-NEXT:    v_mov_b32_e32 v2, s2
 ; CHECK-NEXT:    buffer_atomic_min_f64 v[0:1], v2, s[4:7], 0 offen glc
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 1.0
 ; CHECK-NEXT:    s_waitcnt vmcnt(0)
 ; CHECK-NEXT:    v_cvt_u32_f64_e32 v0, v[0:1]
 ; CHECK-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]
 ; CHECK-NEXT:    global_store_dword v[0:1], v2, off
 ; CHECK-NEXT:    s_endpgm
   %f64 = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double 1.0, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   %n32 = fptoui double %f64 to i32
   %n64 = zext i32 %n32 to i64
   %p1 = getelementptr inbounds %S, ptr addrspace(1) %q, i64 %n64, i32 0
   store float 1.0, ptr addrspace(1) %p1
   ret void
 }
 
-define protected amdgpu_kernel void @buffer.ptr.atomic.fmax(ptr addrspace(8) inreg %rsrc, i32 %vindex, ptr addrspace(1) %q) {
+define protected amdgpu_kernel void @buffer.ptr.atomic.fmax(ptr addrspace(8) %rsrc, i32 %vindex, ptr addrspace(1) %q) {
 ; CHECK-LABEL: buffer.ptr.atomic.fmax:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; CHECK-NEXT:    v_mov_b32_e32 v0, 0
 ; CHECK-NEXT:    v_mov_b32_e32 v1, 0x3ff00000
 ; CHECK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x3c
 ; CHECK-NEXT:    s_waitcnt lgkmcnt(0)

llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll

 declare double @llvm.amdgcn.global.atomic.fmin.f64.p1.f64(ptr addrspace(1) %ptr, double %data)
 declare double @llvm.amdgcn.global.atomic.fmax.f64.p1.f64(ptr addrspace(1) %ptr, double %data)
 declare double @llvm.amdgcn.flat.atomic.fadd.f64.p0.f64(ptr %ptr, double %data)
 declare double @llvm.amdgcn.flat.atomic.fadd.f64.p3.f64(ptr addrspace(3) %ptr, double %data)
 declare double @llvm.amdgcn.flat.atomic.fmin.f64.p0.f64(ptr %ptr, double %data)
 declare double @llvm.amdgcn.flat.atomic.fmax.f64.p0.f64(ptr %ptr, double %data)
 declare double @llvm.amdgcn.ds.fadd.f64(ptr addrspace(3) nocapture, double, i32, i32, i1)
 
-define amdgpu_kernel void @buffer_atomic_add_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @buffer_atomic_add_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: buffer_atomic_add_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: buffer_atomic_add_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i1 1)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @raw_buffer_atomic_add_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_buffer_atomic_add_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_buffer_atomic_add_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_buffer_atomic_add_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_add_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_add_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_add_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_add_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_add_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_buffer_atomic_add_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_buffer_atomic_add_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_buffer_atomic_add_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_add_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_add_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_add_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_add_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_add_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fadd.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @raw_buffer_atomic_min_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_buffer_atomic_min_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_buffer_atomic_min_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_buffer_atomic_min_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_min_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_min_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_min_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_min_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_min_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_buffer_atomic_min_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_buffer_atomic_min_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_buffer_atomic_min_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_min_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_min_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_min_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_min_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_min_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmin.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @raw_buffer_atomic_max_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_buffer_atomic_max_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_buffer_atomic_max_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_buffer_atomic_max_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_max_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_max_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_max_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @raw_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @raw_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: raw_ptr_buffer_atomic_max_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.raw.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 4, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_max_noret_f64(<4 x i32> inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_buffer_atomic_max_noret_f64(<4 x i32> %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_buffer_atomic_max_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_buffer_atomic_max_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

 ; GFX940-NEXT:    global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
   store double %ret, ptr addrspace(1) %out, align 8
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_max_noret_f64(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_max_noret_f64(ptr addrspace(8) %rsrc, double %data, i32 %vindex) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_max_noret_f64:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s8, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]
 ; GFX90A-NEXT:    v_mov_b32_e32 v2, s8

 ; GFX940-NEXT:    flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
 ; GFX940-NEXT:    s_endpgm
 main_body:
   %ret = call double @llvm.amdgcn.struct.ptr.buffer.atomic.fmax.f64(double %data, ptr addrspace(8) %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
   store double %ret, ptr undef
   ret void
 }
 
-define amdgpu_kernel void @struct_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr addrspace(8) inreg %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
+define amdgpu_kernel void @struct_ptr_buffer_atomic_max_rtn_f64_off4_slc(ptr addrspace(8) %rsrc, double %data, i32 %vindex, ptr addrspace(1) %out) {
 ; GFX90A-LABEL: struct_ptr_buffer_atomic_max_rtn_f64_off4_slc:
 ; GFX90A:       ; %bb.0: ; %main_body
 ; GFX90A-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX90A-NEXT:    s_load_dword s10, s[0:1], 0x3c
 ; GFX90A-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX90A-NEXT:    s_load_dwordx2 s[8:9], s[0:1], 0x44
 ; GFX90A-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX90A-NEXT:    v_pk_mov_b32 v[0:1], s[2:3], s[2:3] op_sel:[0,1]

llvm/test/CodeGen/AMDGPU/preload-kernarg-header.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -amdgpu-kernarg-preload-count=1 -asm-verbose=0 < %s | FileCheck -check-prefixes=GCN %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 -amdgpu-kernarg-preload-count=1 -filetype=obj < %s | llvm-objdump --arch=amdgcn --mcpu=gfx940 --disassemble - | FileCheck -check-prefixes=GCN %s
+
+; GCN: preload_kernarg_header
+; GCN-COUNT-64: s_nop 0
+define amdgpu_kernel void @preload_kernarg_header(ptr %arg) {
+    store ptr %arg, ptr %arg
+    ret void
+}
+
+; GCN: non_kernel_function
+; GCN-NOT: s_nop 0
+; GCN: flat_store
+define void @non_kernel_function(ptr %arg) {
+    store ptr %arg, ptr %arg
+    ret void
+}

llvm/test/CodeGen/AMDGPU/preload-kernargs.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx940 -verify-machineinstrs < %s | FileCheck -check-prefixes=NO-PRELOAD %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx940 -amdgpu-kernarg-preload-count=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRELOAD-1 %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx940 -amdgpu-kernarg-preload-count=2 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRELOAD-2 %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx940 -amdgpu-kernarg-preload-count=4 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRELOAD-4 %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx940 -amdgpu-kernarg-preload-count=8 -verify-machineinstrs < %s | FileCheck -check-prefixes=PRELOAD-8 %s
+
+define amdgpu_kernel void @ptr1_i8(ptr addrspace(1) %out, i8 %arg0) {
+; NO-PRELOAD-LABEL: ptr1_i8:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dword s4, s[0:1], 0x8
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    s_and_b32 s0, s4, 0xff
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s0
+; NO-PRELOAD-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: ptr1_i8:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dword s0, s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    s_and_b32 s0, s0, 0xff
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-1-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: ptr1_i8:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    s_and_b32 s0, s4, 0xff
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-2-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: ptr1_i8:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    s_and_b32 s0, s4, 0xff
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-4-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: ptr1_i8:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    s_and_b32 s0, s4, 0xff
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-8-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  %ext = zext i8 %arg0 to i32
+  store i32 %ext, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_kernel void @ptr1_i8_zext_arg(ptr addrspace(1) %out, i8 zeroext %arg0) {
+; NO-PRELOAD-LABEL: ptr1_i8_zext_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dword s4, s[0:1], 0x8
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    s_and_b32 s0, s4, 0xff
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s0
+; NO-PRELOAD-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: ptr1_i8_zext_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dword s0, s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    s_and_b32 s0, s0, 0xff
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-1-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: ptr1_i8_zext_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    s_mov_b32 s0, 0xffff
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s4
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-2-NEXT:    v_and_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; PRELOAD-2-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: ptr1_i8_zext_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    s_mov_b32 s0, 0xffff
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s4
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-4-NEXT:    v_and_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; PRELOAD-4-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: ptr1_i8_zext_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    s_mov_b32 s0, 0xffff
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s4
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-8-NEXT:    v_and_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; PRELOAD-8-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  %ext = zext i8 %arg0 to i32
+  store i32 %ext, ptr addrspace(1) %out, align 4
+  ret void
+}
+
+define amdgpu_kernel void @ptr1_i16_preload_arg(ptr addrspace(1) %out, i16 %arg0) {
+; NO-PRELOAD-LABEL: ptr1_i16_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dword s4, s[0:1], 0x8
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    s_and_b32 s0, s4, 0xffff
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s0
+; NO-PRELOAD-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: ptr1_i16_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dword s0, s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    s_and_b32 s0, s0, 0xffff
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-1-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: ptr1_i16_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    s_and_b32 s0, s4, 0xffff
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-2-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: ptr1_i16_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    s_and_b32 s0, s4, 0xffff
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-4-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: ptr1_i16_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    s_and_b32 s0, s4, 0xffff
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-8-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  %ext = zext i16 %arg0 to i32
+  store i32 %ext, ptr addrspace(1) %out, align 4
+  ret void
+}
+
+define amdgpu_kernel void @ptr1_i32_preload_arg(ptr addrspace(1) %out, i32 %arg0) {
+; NO-PRELOAD-LABEL: ptr1_i32_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dword s4, s[0:1], 0x8
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s4
+; NO-PRELOAD-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: ptr1_i32_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dword s0, s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-1-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: ptr1_i32_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s4
+; PRELOAD-2-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: ptr1_i32_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s4
+; PRELOAD-4-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: ptr1_i32_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s4
+; PRELOAD-8-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  store i32 %arg0, ptr addrspace(1) %out
+  ret void
+}
+
+; Check alignment on the second preloaded arg.
+
+define amdgpu_kernel void @i32_ptr1_i32_preload_arg(i32 %arg0, ptr addrspace(1) %out, i32 %arg1) {
+; NO-PRELOAD-LABEL: i32_ptr1_i32_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dword s4, s[0:1], 0x10
+; NO-PRELOAD-NEXT:    s_load_dword s5, s[0:1], 0x0
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x8
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    s_add_i32 s0, s5, s4
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s0
+; NO-PRELOAD-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: i32_ptr1_i32_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dword s3, s[0:1], 0x10
+; PRELOAD-1-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    s_add_i32 s0, s2, s3
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-1-NEXT:    global_store_dword v0, v1, s[4:5] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: i32_ptr1_i32_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    s_load_dword s0, s[0:1], 0x10
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-2-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-2-NEXT:    s_add_i32 s0, s2, s0
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-2-NEXT:    global_store_dword v0, v1, s[4:5] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: i32_ptr1_i32_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    s_add_i32 s0, s2, s6
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-4-NEXT:    global_store_dword v0, v1, s[4:5] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: i32_ptr1_i32_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    s_add_i32 s0, s2, s6
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-8-NEXT:    global_store_dword v0, v1, s[4:5] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  %add = add i32 %arg0, %arg1
+  store i32 %add, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_kernel void @ptr1_i16_i16_preload_arg(ptr addrspace(1) %out, i16 %arg0, i16 %arg1) {
+; NO-PRELOAD-LABEL: ptr1_i16_i16_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dword s4, s[0:1], 0x8
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    s_lshr_b32 s0, s4, 16
+; NO-PRELOAD-NEXT:    s_and_b32 s1, s4, 0xffff
+; NO-PRELOAD-NEXT:    s_add_i32 s0, s1, s0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s0
+; NO-PRELOAD-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: ptr1_i16_i16_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dword s0, s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    s_lshr_b32 s1, s0, 16
+; PRELOAD-1-NEXT:    s_and_b32 s0, s0, 0xffff
+; PRELOAD-1-NEXT:    s_add_i32 s0, s0, s1
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-1-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: ptr1_i16_i16_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    s_load_dword s0, s[0:1], 0x8
+; PRELOAD-2-NEXT:    s_and_b32 s1, s4, 0xffff
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-2-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-2-NEXT:    s_lshr_b32 s0, s0, 16
+; PRELOAD-2-NEXT:    s_add_i32 s0, s1, s0
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-2-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: ptr1_i16_i16_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    s_lshr_b32 s0, s4, 16
+; PRELOAD-4-NEXT:    s_and_b32 s1, s4, 0xffff
+; PRELOAD-4-NEXT:    s_add_i32 s0, s1, s0
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-4-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: ptr1_i16_i16_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    s_lshr_b32 s0, s4, 16
+; PRELOAD-8-NEXT:    s_and_b32 s1, s4, 0xffff
+; PRELOAD-8-NEXT:    s_add_i32 s0, s1, s0
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-8-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  %ext = zext i16 %arg0 to i32
+  %ext1 = zext i16 %arg1 to i32
+  %add = add i32 %ext, %ext1
+  store i32 %add, ptr addrspace(1) %out, align 4
+  ret void
+}
+
+define amdgpu_kernel void @ptr1_v2i8_preload_arg(ptr addrspace(1) %out, <2 x i8> %in) {
+; NO-PRELOAD-LABEL: ptr1_v2i8_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dword s4, s[0:1], 0x8
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s4
+; NO-PRELOAD-NEXT:    global_store_short v0, v1, s[2:3] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: ptr1_v2i8_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dword s0, s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-1-NEXT:    global_store_short v0, v1, s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: ptr1_v2i8_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    s_lshr_b32 s0, s4, 8
+; PRELOAD-2-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-2-NEXT:    v_or_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, 0
+; PRELOAD-2-NEXT:    global_store_short v1, v0, s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: ptr1_v2i8_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    s_lshr_b32 s0, s4, 8
+; PRELOAD-4-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-4-NEXT:    v_or_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, 0
+; PRELOAD-4-NEXT:    global_store_short v1, v0, s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: ptr1_v2i8_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    s_lshr_b32 s0, s4, 8
+; PRELOAD-8-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-8-NEXT:    v_or_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, 0
+; PRELOAD-8-NEXT:    global_store_short v1, v0, s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  store <2 x i8> %in, ptr addrspace(1) %out
+  ret void
+}
+
+; Don't try to preload byref args.
+
+define amdgpu_kernel void @byref_preload_arg(ptr addrspace(1) %out, ptr addrspace(4) byref(i32) align(256) %in.byref, i32 %after.offset) {
+; NO-PRELOAD-LABEL: byref_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x100
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s2
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, s3
+; NO-PRELOAD-NEXT:    global_store_dword v0, v1, s[4:5] sc0 sc1
+; NO-PRELOAD-NEXT:    s_waitcnt vmcnt(0)
+; NO-PRELOAD-NEXT:    global_store_dword v0, v2, s[4:5] sc0 sc1
+; NO-PRELOAD-NEXT:    s_waitcnt vmcnt(0)
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: byref_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x100
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, s1
+; PRELOAD-1-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_waitcnt vmcnt(0)
+; PRELOAD-1-NEXT:    global_store_dword v0, v2, s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_waitcnt vmcnt(0)
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: byref_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x100
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-2-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v2, s1
+; PRELOAD-2-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_waitcnt vmcnt(0)
+; PRELOAD-2-NEXT:    global_store_dword v0, v2, s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_waitcnt vmcnt(0)
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: byref_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x100
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-4-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v2, s1
+; PRELOAD-4-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_waitcnt vmcnt(0)
+; PRELOAD-4-NEXT:    global_store_dword v0, v2, s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_waitcnt vmcnt(0)
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: byref_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x100
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-8-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s0
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v2, s1
+; PRELOAD-8-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_waitcnt vmcnt(0)
+; PRELOAD-8-NEXT:    global_store_dword v0, v2, s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_waitcnt vmcnt(0)
+; PRELOAD-8-NEXT:    s_endpgm
+  %in = load i32, ptr addrspace(4) %in.byref
+  store volatile i32 %in, ptr addrspace(1) %out, align 4
+  store volatile i32 %after.offset, ptr addrspace(1) %out, align 4
+  ret void
+}
+
+; TODO: Should do partial preload in cases like these where only part of the arg
+; can be preloaded.
+
+define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture %out, <8 x i32> %in) nounwind {
+; NO-PRELOAD-LABEL: v8i32_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x20
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v4, 0
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, s8
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s9
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, s10
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v3, s11
+; NO-PRELOAD-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1] offset:16 sc0 sc1
+; NO-PRELOAD-NEXT:    s_nop 1
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, s4
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s5
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, s6
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v3, s7
+; NO-PRELOAD-NEXT:    global_store_dwordx4 v4, v[0:3], s[0:1] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: v8i32_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x20
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v4, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, s8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s9
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, s10
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v3, s11
+; PRELOAD-1-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] offset:16 sc0 sc1
+; PRELOAD-1-NEXT:    s_nop 1
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, s4
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, s6
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v3, s7
+; PRELOAD-1-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: v8i32_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x20
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v4, 0
+; PRELOAD-2-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, s8
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s9
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v2, s10
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v3, s11
+; PRELOAD-2-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] offset:16 sc0 sc1
+; PRELOAD-2-NEXT:    s_nop 1
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, s4
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v2, s6
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v3, s7
+; PRELOAD-2-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: v8i32_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x20
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v4, 0
+; PRELOAD-4-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, s8
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s9
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v2, s10
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v3, s11
+; PRELOAD-4-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] offset:16 sc0 sc1
+; PRELOAD-4-NEXT:    s_nop 1
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, s4
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v2, s6
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v3, s7
+; PRELOAD-4-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: v8i32_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x20
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v4, 0
+; PRELOAD-8-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, s8
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s9
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v2, s10
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v3, s11
+; PRELOAD-8-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] offset:16 sc0 sc1
+; PRELOAD-8-NEXT:    s_nop 1
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, s4
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v2, s6
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v3, s7
+; PRELOAD-8-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  store <8 x i32> %in, ptr addrspace(1) %out, align 4
+  ret void
+}
+
+define amdgpu_kernel void @v3i16_preload_arg(ptr addrspace(1) nocapture %out, <3 x i16> %in) nounwind {
+; NO-PRELOAD-LABEL: v3i16_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s3
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, s2
+; NO-PRELOAD-NEXT:    global_store_short v0, v1, s[0:1] offset:4 sc0 sc1
+; NO-PRELOAD-NEXT:    global_store_dword v0, v2, s[0:1] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: v3i16_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s1
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, s0
+; PRELOAD-1-NEXT:    global_store_short v0, v1, s[2:3] offset:4 sc0 sc1
+; PRELOAD-1-NEXT:    global_store_dword v0, v2, s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: v3i16_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-2-NEXT:    global_store_short v0, v1, s[2:3] offset:4 sc0 sc1
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s4
+; PRELOAD-2-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: v3i16_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-4-NEXT:    global_store_short v0, v1, s[2:3] offset:4 sc0 sc1
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s4
+; PRELOAD-4-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: v3i16_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-8-NEXT:    global_store_short v0, v1, s[2:3] offset:4 sc0 sc1
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s4
+; PRELOAD-8-NEXT:    global_store_dword v0, v1, s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  store <3 x i16> %in, ptr addrspace(1) %out, align 4
+  ret void
+}
+
+define amdgpu_kernel void @v3i32_preload_arg(ptr addrspace(1) nocapture %out, <3 x i32> %in) nounwind {
+; NO-PRELOAD-LABEL: v3i32_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x10
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v3, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, s4
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s5
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, s6
+; NO-PRELOAD-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: v3i32_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x10
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v3, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, s4
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, s6
+; PRELOAD-1-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: v3i32_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, s6
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s7
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v2, s8
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v3, 0
+; PRELOAD-2-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: v3i32_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, s6
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s7
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v2, s8
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v3, 0
+; PRELOAD-4-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: v3i32_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, s6
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s7
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v2, s8
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v3, 0
+; PRELOAD-8-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  store <3 x i32> %in, ptr addrspace(1) %out, align 4
+  ret void
+}
+
+define amdgpu_kernel void @v3f32_preload_arg(ptr addrspace(1) nocapture %out, <3 x float> %in) nounwind {
+; NO-PRELOAD-LABEL: v3f32_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x10
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v3, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, s4
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s5
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, s6
+; NO-PRELOAD-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: v3f32_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x10
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v3, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, s4
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, s6
+; PRELOAD-1-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: v3f32_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v3, 0
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, s6
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s7
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v2, s8
+; PRELOAD-2-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: v3f32_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v3, 0
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, s6
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s7
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v2, s8
+; PRELOAD-4-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: v3f32_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v3, 0
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, s6
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s7
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v2, s8
+; PRELOAD-8-NEXT:    global_store_dwordx3 v3, v[0:2], s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  store <3 x float> %in, ptr addrspace(1) %out, align 4
+  ret void
+}
+
+define amdgpu_kernel void @v5i8_preload_arg(ptr addrspace(1) nocapture %out, <5 x i8> %in) nounwind {
+; NO-PRELOAD-LABEL: v5i8_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s3
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, s2
+; NO-PRELOAD-NEXT:    global_store_byte v0, v1, s[0:1] offset:4 sc0 sc1
+; NO-PRELOAD-NEXT:    global_store_dword v0, v2, s[0:1] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: v5i8_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s1
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, s0
+; PRELOAD-1-NEXT:    global_store_byte v0, v1, s[2:3] offset:4 sc0 sc1
+; PRELOAD-1-NEXT:    global_store_dword v0, v2, s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: v5i8_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    s_lshr_b32 s0, s4, 8
+; PRELOAD-2-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-2-NEXT:    s_lshr_b32 s0, s4, 24
+; PRELOAD-2-NEXT:    v_lshlrev_b16_e64 v1, 8, s0
+; PRELOAD-2-NEXT:    s_lshr_b32 s0, s4, 16
+; PRELOAD-2-NEXT:    v_or_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-2-NEXT:    v_or_b32_sdwa v1, s0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v2, s5
+; PRELOAD-2-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, 0
+; PRELOAD-2-NEXT:    global_store_byte v1, v2, s[2:3] offset:4 sc0 sc1
+; PRELOAD-2-NEXT:    global_store_dword v1, v0, s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: v5i8_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    s_lshr_b32 s0, s4, 8
+; PRELOAD-4-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-4-NEXT:    s_lshr_b32 s0, s4, 24
+; PRELOAD-4-NEXT:    v_lshlrev_b16_e64 v1, 8, s0
+; PRELOAD-4-NEXT:    s_lshr_b32 s0, s4, 16
+; PRELOAD-4-NEXT:    v_or_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-4-NEXT:    v_or_b32_sdwa v1, s0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v2, s5
+; PRELOAD-4-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, 0
+; PRELOAD-4-NEXT:    global_store_byte v1, v2, s[2:3] offset:4 sc0 sc1
+; PRELOAD-4-NEXT:    global_store_dword v1, v0, s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: v5i8_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    s_lshr_b32 s0, s4, 8
+; PRELOAD-8-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-8-NEXT:    s_lshr_b32 s0, s4, 24
+; PRELOAD-8-NEXT:    v_lshlrev_b16_e64 v1, 8, s0
+; PRELOAD-8-NEXT:    s_lshr_b32 s0, s4, 16
+; PRELOAD-8-NEXT:    v_or_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-8-NEXT:    v_or_b32_sdwa v1, s0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v2, s5
+; PRELOAD-8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, 0
+; PRELOAD-8-NEXT:    global_store_byte v1, v2, s[2:3] offset:4 sc0 sc1
+; PRELOAD-8-NEXT:    global_store_dword v1, v0, s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  store <5 x i8> %in, ptr addrspace(1) %out, align 4
+  ret void
+}
+
+define amdgpu_kernel void @v5f64_arg(ptr addrspace(1) nocapture %out, <5 x double> %in) nounwind {
+; NO-PRELOAD-LABEL: v5f64_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x60
+; NO-PRELOAD-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x40
+; NO-PRELOAD-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v4, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b64_e32 v[2:3], s[2:3]
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, s8
+; NO-PRELOAD-NEXT:    global_store_dwordx2 v4, v[2:3], s[12:13] offset:32 sc0 sc1
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s9
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, s10
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v3, s11
+; NO-PRELOAD-NEXT:    global_store_dwordx4 v4, v[0:3], s[12:13] offset:16 sc0 sc1
+; NO-PRELOAD-NEXT:    s_nop 1
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, s4
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s5
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, s6
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v3, s7
+; NO-PRELOAD-NEXT:    global_store_dwordx4 v4, v[0:3], s[12:13] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: v5f64_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x60
+; PRELOAD-1-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x40
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v4, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b64_e32 v[2:3], s[12:13]
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, s8
+; PRELOAD-1-NEXT:    global_store_dwordx2 v4, v[2:3], s[2:3] offset:32 sc0 sc1
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s9
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, s10
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v3, s11
+; PRELOAD-1-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] offset:16 sc0 sc1
+; PRELOAD-1-NEXT:    s_nop 1
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v0, s4
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, s6
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v3, s7
+; PRELOAD-1-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: v5f64_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x60
+; PRELOAD-2-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x40
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v4, 0
+; PRELOAD-2-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-2-NEXT:    v_mov_b64_e32 v[2:3], s[12:13]
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, s8
+; PRELOAD-2-NEXT:    global_store_dwordx2 v4, v[2:3], s[2:3] offset:32 sc0 sc1
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s9
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v2, s10
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v3, s11
+; PRELOAD-2-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] offset:16 sc0 sc1
+; PRELOAD-2-NEXT:    s_nop 1
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v0, s4
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v2, s6
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v3, s7
+; PRELOAD-2-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: v5f64_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x60
+; PRELOAD-4-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x40
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v4, 0
+; PRELOAD-4-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-4-NEXT:    v_mov_b64_e32 v[2:3], s[12:13]
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, s8
+; PRELOAD-4-NEXT:    global_store_dwordx2 v4, v[2:3], s[2:3] offset:32 sc0 sc1
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s9
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v2, s10
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v3, s11
+; PRELOAD-4-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] offset:16 sc0 sc1
+; PRELOAD-4-NEXT:    s_nop 1
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v0, s4
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v2, s6
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v3, s7
+; PRELOAD-4-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: v5f64_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    s_load_dwordx2 s[12:13], s[0:1], 0x60
+; PRELOAD-8-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x40
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v4, 0
+; PRELOAD-8-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-8-NEXT:    v_mov_b64_e32 v[2:3], s[12:13]
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, s8
+; PRELOAD-8-NEXT:    global_store_dwordx2 v4, v[2:3], s[2:3] offset:32 sc0 sc1
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s9
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v2, s10
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v3, s11
+; PRELOAD-8-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] offset:16 sc0 sc1
+; PRELOAD-8-NEXT:    s_nop 1
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v0, s4
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v1, s5
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v2, s6
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v3, s7
+; PRELOAD-8-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  store <5 x double> %in, ptr addrspace(1) %out, align 8
+  ret void
+}
+
+define amdgpu_kernel void @v8i8_preload_arg(ptr addrspace(1) %out, <8 x i8> %in) {
+; NO-PRELOAD-LABEL: v8i8_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b64_e32 v[0:1], s[2:3]
+; NO-PRELOAD-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: v8i8_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]
+; PRELOAD-1-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: v8i8_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    s_lshr_b32 s0, s5, 8
+; PRELOAD-2-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-2-NEXT:    s_lshr_b32 s0, s5, 24
+; PRELOAD-2-NEXT:    v_lshlrev_b16_e64 v1, 8, s0
+; PRELOAD-2-NEXT:    s_lshr_b32 s0, s5, 16
+; PRELOAD-2-NEXT:    v_or_b32_sdwa v0, s5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-2-NEXT:    v_or_b32_sdwa v1, s0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-2-NEXT:    s_lshr_b32 s0, s4, 8
+; PRELOAD-2-NEXT:    v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; PRELOAD-2-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-2-NEXT:    s_lshr_b32 s0, s4, 24
+; PRELOAD-2-NEXT:    v_lshlrev_b16_e64 v2, 8, s0
+; PRELOAD-2-NEXT:    s_lshr_b32 s0, s4, 16
+; PRELOAD-2-NEXT:    v_or_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-2-NEXT:    v_or_b32_sdwa v2, s0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-2-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: v8i8_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    s_lshr_b32 s0, s5, 8
+; PRELOAD-4-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-4-NEXT:    s_lshr_b32 s0, s5, 24
+; PRELOAD-4-NEXT:    v_lshlrev_b16_e64 v1, 8, s0
+; PRELOAD-4-NEXT:    s_lshr_b32 s0, s5, 16
+; PRELOAD-4-NEXT:    v_or_b32_sdwa v0, s5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-4-NEXT:    v_or_b32_sdwa v1, s0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-4-NEXT:    s_lshr_b32 s0, s4, 8
+; PRELOAD-4-NEXT:    v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; PRELOAD-4-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-4-NEXT:    s_lshr_b32 s0, s4, 24
+; PRELOAD-4-NEXT:    v_lshlrev_b16_e64 v2, 8, s0
+; PRELOAD-4-NEXT:    s_lshr_b32 s0, s4, 16
+; PRELOAD-4-NEXT:    v_or_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-4-NEXT:    v_or_b32_sdwa v2, s0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-4-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: v8i8_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    s_lshr_b32 s0, s5, 8
+; PRELOAD-8-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-8-NEXT:    s_lshr_b32 s0, s5, 24
+; PRELOAD-8-NEXT:    v_lshlrev_b16_e64 v1, 8, s0
+; PRELOAD-8-NEXT:    s_lshr_b32 s0, s5, 16
+; PRELOAD-8-NEXT:    v_or_b32_sdwa v0, s5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-8-NEXT:    v_or_b32_sdwa v1, s0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-8-NEXT:    s_lshr_b32 s0, s4, 8
+; PRELOAD-8-NEXT:    v_or_b32_sdwa v1, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; PRELOAD-8-NEXT:    v_lshlrev_b16_e64 v0, 8, s0
+; PRELOAD-8-NEXT:    s_lshr_b32 s0, s4, 24
+; PRELOAD-8-NEXT:    v_lshlrev_b16_e64 v2, 8, s0
+; PRELOAD-8-NEXT:    s_lshr_b32 s0, s4, 16
+; PRELOAD-8-NEXT:    v_or_b32_sdwa v0, s4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-8-NEXT:    v_or_b32_sdwa v2, s0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-8-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  store <8 x i8> %in, ptr addrspace(1) %out
+  ret void
+}
+
+define amdgpu_kernel void @i64_kernel_preload_arg(ptr addrspace(1) %out, i64 %a) {
+; NO-PRELOAD-LABEL: i64_kernel_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, s2
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s3
+; NO-PRELOAD-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: i64_kernel_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]
+; PRELOAD-1-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: i64_kernel_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-2-NEXT:    v_mov_b64_e32 v[0:1], s[4:5]
+; PRELOAD-2-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: i64_kernel_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-4-NEXT:    v_mov_b64_e32 v[0:1], s[4:5]
+; PRELOAD-4-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: i64_kernel_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-8-NEXT:    v_mov_b64_e32 v[0:1], s[4:5]
+; PRELOAD-8-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  store i64 %a, ptr addrspace(1) %out, align 8
+  ret void
+}
+
+define amdgpu_kernel void @f64_kernel_preload_arg(ptr addrspace(1) %out, double %in) {
+; NO-PRELOAD-LABEL: f64_kernel_preload_arg:
+; NO-PRELOAD:       ; %bb.0:
+; NO-PRELOAD-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x0
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v2, 0
+; NO-PRELOAD-NEXT:    s_waitcnt lgkmcnt(0)
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v0, s2
+; NO-PRELOAD-NEXT:    v_mov_b32_e32 v1, s3
+; NO-PRELOAD-NEXT:    global_store_dwordx2 v2, v[0:1], s[0:1] sc0 sc1
+; NO-PRELOAD-NEXT:    s_endpgm
+;
+; PRELOAD-1-LABEL: f64_kernel_preload_arg:
+; PRELOAD-1:         s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:    s_nop 0
+; PRELOAD-1-NEXT:  ; %bb.0:
+; PRELOAD-1-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x8
+; PRELOAD-1-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-1-NEXT:    s_waitcnt lgkmcnt(0)
+; PRELOAD-1-NEXT:    v_mov_b64_e32 v[0:1], s[0:1]
+; PRELOAD-1-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-1-NEXT:    s_endpgm
+;
+; PRELOAD-2-LABEL: f64_kernel_preload_arg:
+; PRELOAD-2:         s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:    s_nop 0
+; PRELOAD-2-NEXT:  ; %bb.0:
+; PRELOAD-2-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-2-NEXT:    v_mov_b64_e32 v[0:1], s[4:5]
+; PRELOAD-2-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-2-NEXT:    s_endpgm
+;
+; PRELOAD-4-LABEL: f64_kernel_preload_arg:
+; PRELOAD-4:         s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:    s_nop 0
+; PRELOAD-4-NEXT:  ; %bb.0:
+; PRELOAD-4-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-4-NEXT:    v_mov_b64_e32 v[0:1], s[4:5]
+; PRELOAD-4-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-4-NEXT:    s_endpgm
+;
+; PRELOAD-8-LABEL: f64_kernel_preload_arg:
+; PRELOAD-8:         s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:    s_nop 0
+; PRELOAD-8-NEXT:  ; %bb.0:
+; PRELOAD-8-NEXT:    v_mov_b32_e32 v2, 0
+; PRELOAD-8-NEXT:    v_mov_b64_e32 v[0:1], s[4:5]
+; PRELOAD-8-NEXT:    global_store_dwordx2 v2, v[0:1], s[2:3] sc0 sc1
+; PRELOAD-8-NEXT:    s_endpgm
+  store double %in, ptr addrspace(1) %out
+  ret void
+}