[CodeGen] Make the MachineFunctionSplitter pass testable via MIR

[dhoekwater]

Summary

Because the MachineFunctionSplitter pass isn't initialized in
CodeGen.cpp, running LLC with --run-pass machine-function-splitter
doesn't work. Adding it to the initializeCodeGen makes the function
splitting directly testable with .mir tests.

[dhoekwater]

Remove an unnecessary line.

[dhoekwater]

Rebase onto main to hopefully make unrelated test failures go away

[snehasish]

Is there a specific reason to test MFS (on ARM) with MIR instead of .ll inputs? Only ~11% of the tests in test/CodeGen/AArch64 are in MIR, the rest are bitcode files. IMO bitcode is much easier to read, maintain and we can reuse most (all?) of the existing tests we have in machine-function-splitter.ll. So my preference would be to use bitcode unless there is a fundamental reason which blocks us from testing with bitcode.

[dhoekwater]

In D157063#4573702, @snehasish wrote:

Is there a specific reason to test MFS (on ARM) with MIR instead of .ll inputs?

In a different review, I was asked to make MIR tests so that they only targeted a single pass. That doesn't seem necessary here, so I'll use bitcode tests instead. Dropping this revision and updating its dependents.

[dhoekwater]

Try to replace with main to get this to work

[dhoekwater]

Try to replace with a different branch to get this to work

[dhoekwater]

Try to replace with yet another

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

for (const MachineInstr &MI : MBB) {
     case AArch64::JumpTableDest16:
     case AArch64::JumpTableDest8:
       return false;
     default:
       continue;
     }
   }
 
+  // Asm Goto blocks can contain conditional branches to goto labels, which can
+  // get moved out of range of the branch instruction.
+  auto isAsmGoto = [](const MachineInstr &MI) {
+    return MI.getOpcode() == AArch64::INLINEASM_BR;
+  };
+  if (llvm::any_of(MBB, isAsmGoto) || MBB.isInlineAsmBrIndirectTarget())
+    return false;
+
   // MBB isn't a special case, so it's safe to be split to the cold section.
   return true;
 }
 
 std::optional<ParamLoadedValue>
 AArch64InstrInfo::describeLoadedValue(const MachineInstr &MI,
                                       Register Reg) const {
   const MachineFunction *MF = MI.getMF();

llvm/test/CodeGen/Generic/machine-function-splitter.ll

cold1:                                            ; preds = %0
   %3 = tail call i32 @bam()
   ret i32 %3
 
 cold2:                                            ; preds = %0
   %4 = tail call i32 @qux()
   ret i32 %4
 }
 
+define void @foo20(i1 zeroext %0) !prof !14 !section_prefix !15 {
+;; Check that blocks containing or targeted by asm goto aren't split.
+; MFS-DEFAULTS-LABEL:        foo20
+; MFS-DEFAULTS-AARCH64-NOT:  foo20.cold:
+; MFS-DEFAULTS-X86:          .section        .text.split.foo20
+; MFS-DEFAULTS-X86:          foo20.cold:
+; MFS-DEFAULTS-X86-DAG:      # %cold_asm
+; MFS-DEFAULTS-X86-DAG:      # %cold_asm_target
+
+  br i1 %0, label %hot, label %cold_asm, !prof !17
+
+hot:
+  %2 = call i32 @bar()
+  ret void
+
+cold_asm:
+    callbr void asm sideeffect "nop", "!i"() #3
+          to label %asm.fallthrough [label %cold_asm_target]
+
+asm.fallthrough:
+    br label %cold_asm_target
+
+cold_asm_target:
+  %3 = call i32 @baz()
+  ret void
+}
+
 declare i32 @bar()
 declare i32 @baz()
 declare i32 @bam()
 declare i32 @qux()
 declare void @_Z1fv()
 declare i32 @__gxx_personality_v0(...)
 
 @_ZTIi = external constant ptr