This is an archive of the discontinued LLVM Phabricator instance.

Differential D156909

[RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
ClosedPublic

Authored by reames on Aug 2 2023, 8:53 AM.

Details

Reviewers
craig.topper
asb
frasercrmck
luke
kito-cheng
Commits
rGa63bd7e99b00: [RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands
Summary

In a recent series of refactorings (described here: https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295), I greatly increased the number of IMPLICIT_DEF operands to our vector instructions. This has turned out to have an unexpected negative impact because MachineCSE does not CSE IMPLICIT_DEFs, and thus does not CSE any instruction with an IMPLICIT_DEF operand. SelectionDAG *does* CSE the same case, but that only covers the same block case, not the cross block case. This lead to the performance regression reported in https://github.com/llvm/llvm-project/issues/64282.

This change is a slightly ugly hack to side step the issue. Instead of fixing the root cause (lack of CSE for IMPLICIT_DEF) or undoing the operand changes, we leave the extra operand in place, and use NoReg in place of IMPLICIT_DEF. I then convert back to IMPLICIT_DEF just before register allocation so that ProcessImplicitDefs and TwoAddressInstructions can do the normal transforms to Undef tied registers.

We may end up backporting this into the 17.x release branch.

Reviewers, please pay close attention to the test diffs. These are mostly schedule perturbations caused by the removal of the IMPLICIT_DEF instruction - basically undoing the changes from the refactoring sequence - but there could be other issues lurking within. I already found two correctness issues with earlier versions of the patch, and may have missed others.

Diff Detail

Event Timeline

reames created this revision.Aug 2 2023, 8:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 2 2023, 8:53 AM
Herald added subscribers: jobnoorman, VincentWu, armkevincheng and 31 others. · View Herald Transcript
reames requested review of this revision.Aug 2 2023, 8:53 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 2 2023, 8:53 AM
Herald added subscribers: wangpc, eopXD, MaskRay. · View Herald Transcript
reames edited the summary of this revision. (Show Details)Aug 2 2023, 8:54 AM
craig.topper added inline comments.Aug 2 2023, 10:37 AM
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
3245

Stray change

3606

intend -> intent?

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
57

thought -> though?

Harbormaster completed remote builds in B249797: Diff 546496.Aug 2 2023, 12:56 PM
reames updated this revision to Diff 546619.Aug 2 2023, 2:58 PM

Address review comments

Harbormaster completed remote builds in B249894: Diff 546619.Aug 2 2023, 7:05 PM
asb added a comment.EditedAug 9 2023, 6:22 AM

Some high level review comments:

  • The intended change and the problem being solved is very clear from the patch description and the bug description - thanks!
  • One minor request is that for the code comments, any time you refer to e.g. a "MachineCSE problem" (as in the comment in RISCVRVVInitUndef.cpp) please be more explicit that this is an issue related to the quality of generated code rather than correctness. Just referencing the bug number would be fine. This will be helpful for future code readers if this workaround lives longer than expected.
  • The approach implemented here seems sensible + pragmatic to me. Though my confidence of spotting a lurking subtle issue here is low - so it will be great to get input from other reivewers too.
  • Given we don't have concrete examples of this causing _big_ problems I think it wouldn't be the end of the world if this wasn't in 17.0.0, but I see the argument for backporting it and overall am probably slightly in favour. If it's going to happen, I think this needs reviewing and landing soon so there's at least a full release candidate cycle including it, giving a chance to back it out if unexpected problems are found.

Summary: I don't spot any issues and this seems sensible to me, but I think other reviewers on the list who work on vector codegen more are better placed to do a detailed line-by-line review.

luke added inline comments.Aug 9 2023, 7:36 AM
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
440

Possible regression here. Are the NoRegs coming into the InsertVSETVLI pass?

reames added inline comments.Aug 9 2023, 7:02 PM
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll
440

This turns out to be a known issue showing up in a slightly surprising way.

The cause is that InsertVSETVLI contains a peephole for VL=1 splats with tail undefined which is only applied in the forward direction - due to staleness issues.

The scheduling changes causing the two vmv.v.i instructions to be reordered. So previously the VL=4 e32 comes before the VL=1 e8. Afterward, the inverse order reaches InsertVSETVLI and the forward rule doesn't trigger.

The fix here would be to always apply peepholes in both directions, but that requires careful reasoning about working with stale MI. I'll think about that separately, but do not consider this a blocker for this patch.

reames updated this revision to Diff 549977.Aug 14 2023, 8:53 AM

Update comments as requested by @asb. Sorry for the delay, I'd missed that request in your comment.

At this point, I do not plan to request a backport for this change. I'd still like to get it landed, but it's too high risk to backport late in a release cycle, and at the moment, none of my performance data indicates a strong need to do so.

Harbormaster completed remote builds in B252390: Diff 549977.Aug 14 2023, 8:54 AM
craig.topper added inline comments.Aug 14 2023, 9:38 AM
llvm/test/CodeGen/RISCV/rvv/cross-block-cse.ll
3–4

This TODO needs to be dropped

reames updated this revision to Diff 549998.Aug 14 2023, 9:41 AM

Address comment from @craig.topper

Harbormaster completed remote builds in B252408: Diff 549998.Aug 14 2023, 9:42 AM
craig.topper added inline comments.Aug 14 2023, 9:48 AM
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
2787

I think I'm missing how this change comes from this patch. The sltu+addi+and looks like an optimized select lowering. The old code use a branch for the select. It looks to me like all of the changes for this patch should be after select lowering.

craig.topper added inline comments.Aug 14 2023, 10:01 AM
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
2787

I guess its just a scheduling difference due to the splitting. The select is further down on this side and the sltu is further down on the other side.

reames added inline comments.Aug 14 2023, 10:04 AM
llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
2787

That is a very good question!

However, I think the answer is that it isn't actually select lowering, it's scheduling run slightly amuck. If you look quite a bit further down the test diff, you see what appears to be a select-to-branch conversion going in the other direction.

I think what we actually have here is a massive rescheduling. However, that would seem to require cross block scheduling, which too my knowledge, we don't have? So maybe I'm still confused?

2897–2900

Here

craig.topper accepted this revision.Aug 14 2023, 11:02 AM

LGTM

This revision is now accepted and ready to land.Aug 14 2023, 11:02 AM
This revision was landed with ongoing or failed builds.Aug 14 2023, 1:01 PM
Closed by commit rGa63bd7e99b00: [RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands (authored by reames). · Explain Why
This revision was automatically updated to reflect the committed changes.
reames added a commit: rGa63bd7e99b00: [RISCV] Use NoReg in place of IMPLICIT_DEF for undefined passthru operands.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
1 line
46 lines
8 lines
22 lines
29 lines
10 lines
test/
CodeGen/
RISCV/
1 line
6 lines
rvv/
24 lines
276 lines
530 lines
282 lines
580 lines
8 lines
10 lines
298 lines
104 lines
4 lines
28 lines
12 lines
650 lines
220 lines
444 lines
238 lines
4 lines
84 lines
328 lines
406 lines
88 lines
24 lines
20 lines
3 lines
20 lines
12 lines
32 lines
30 lines
24 lines
24 lines
30 lines
80 lines
34 lines
44 lines
40 lines
388 lines
7 lines
522 lines
48 lines
3 lines
24 lines
114 lines
32 lines
59 lines
12 lines
24 lines
118 lines
234 lines
24 lines
57 lines
47 lines
24 lines
8 lines
94 lines
47 lines
47 lines
94 lines
24 lines
24 lines
46 lines
46 lines
46 lines
46 lines
481 lines
31 lines
75 lines
16 lines
2 lines
126 lines
90 lines
59 lines
522 lines
41 lines
41 lines
408 lines
3 lines
8 lines
24 lines
16 lines
54 lines
54 lines
80 lines
58 lines
406 lines
3 lines
4 lines
4 lines
2 lines
110 lines
26 lines
44 lines
14 lines
96 lines
32 lines
112 lines
60 lines
24 lines
63 lines
62 lines
7 lines
10 lines
40 lines
52 lines
3 lines
65 lines
18 lines
18 lines
26 lines
50 lines
58 lines
58 lines
48 lines
144 lines
52 lines
46 lines

Diff 550059

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.
#include "RISCVGenDAGISel.inc" #include "RISCVGenDAGISel.inc"
private: private:
bool doPeepholeSExtW(SDNode *Node); bool doPeepholeSExtW(SDNode *Node);
bool doPeepholeMaskedRVV(MachineSDNode *Node); bool doPeepholeMaskedRVV(MachineSDNode *Node);
bool doPeepholeMergeVVMFold(); bool doPeepholeMergeVVMFold();
bool doPeepholeNoRegPassThru();
bool performVMergeToVMv(SDNode *N); bool performVMergeToVMv(SDNode *N);
bool performCombineVMergeAndVOps(SDNode *N); bool performCombineVMergeAndVOps(SDNode *N);
}; };
namespace RISCV { namespace RISCV {
struct VLSEGPseudo { struct VLSEGPseudo {
uint16_t NF : 4; uint16_t NF : 4;
uint16_t Masked : 1; uint16_t Masked : 1;
▲ Show 20 Lines • Show All 83 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Show First 20 Lines • Show All 143 Lines • ▼ Show 20 Lines while (Position != CurDAG->allnodes_begin()) {
MadeChange |= doPeepholeSExtW(N); MadeChange |= doPeepholeSExtW(N);
MadeChange |= doPeepholeMaskedRVV(cast<MachineSDNode>(N)); MadeChange |= doPeepholeMaskedRVV(cast<MachineSDNode>(N));
} }
CurDAG->setRoot(Dummy.getValue()); CurDAG->setRoot(Dummy.getValue());
MadeChange |= doPeepholeMergeVVMFold(); MadeChange |= doPeepholeMergeVVMFold();
// After we're done with everything else, convert IMPLICIT_DEF
// passthru operands to NoRegister. This is required to workaround
// an optimization deficiency in MachineCSE. This really should
// be merged back into each of the patterns (i.e. there's no good
// reason not to go directly to NoReg), but is being done this way
// to allow easy backporting.
MadeChange |= doPeepholeNoRegPassThru();
if (MadeChange) if (MadeChange)
CurDAG->RemoveDeadNodes(); CurDAG->RemoveDeadNodes();
} }
static SDValue selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, static SDValue selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
RISCVMatInt::InstSeq &Seq) { RISCVMatInt::InstSeq &Seq) {
SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT); SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT);
for (const RISCVMatInt::Inst &Inst : Seq) { for (const RISCVMatInt::Inst &Inst : Seq) {
▲ Show 20 Lines • Show All 3,069 Lines • ▼ Show 20 Lines#ifndef NDEBUG
assert(RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) == assert(RISCVII::hasVecPolicyOp(MaskedMCID.TSFlags) ==
RISCVII::hasVecPolicyOp(MCID.TSFlags) && RISCVII::hasVecPolicyOp(MCID.TSFlags) &&
"Masked and unmasked pseudos are inconsistent"); "Masked and unmasked pseudos are inconsistent");
const bool HasTiedDest = RISCVII::isFirstDefTiedToFirstUse(MCID); const bool HasTiedDest = RISCVII::isFirstDefTiedToFirstUse(MCID);
assert(UseTUPseudo == HasTiedDest && "Unexpected pseudo structure"); assert(UseTUPseudo == HasTiedDest && "Unexpected pseudo structure");
#endif #endif
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
// Skip the merge operand at index 0 if !UseTUPseudo. // Skip the merge operand at index 0 if !UseTUPseudo.
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Stray change

craig.topper: Stray change
for (unsigned I = !UseTUPseudo, E = N->getNumOperands(); I != E; I++) { for (unsigned I = !UseTUPseudo, E = N->getNumOperands(); I != E; I++) {
// Skip the mask, and the Glue. // Skip the mask, and the Glue.
SDValue Op = N->getOperand(I); SDValue Op = N->getOperand(I);
if (I == MaskOpIdx || Op.getValueType() == MVT::Glue) if (I == MaskOpIdx || Op.getValueType() == MVT::Glue)
continue; continue;
Ops.push_back(Op); Ops.push_back(Op);
} }
▲ Show 20 Lines • Show All 342 Lines • ▼ Show 20 Lines while (Position != CurDAG->allnodes_begin()) {
if (IsVMerge(N) || IsVMv(N)) if (IsVMerge(N) || IsVMv(N))
MadeChange |= performCombineVMergeAndVOps(N); MadeChange |= performCombineVMergeAndVOps(N);
if (IsVMerge(N) && N->getOperand(0) == N->getOperand(1)) if (IsVMerge(N) && N->getOperand(0) == N->getOperand(1))
MadeChange |= performVMergeToVMv(N); MadeChange |= performVMergeToVMv(N);
} }
return MadeChange; return MadeChange;
} }
/// If our passthru is an implicit_def, use noreg instead. This side
/// steps issues with MachineCSE not being able to CSE expressions with
/// IMPLICIT_DEF operands while preserving the semantic intent. See
craig.topperUnsubmitted
Not Done
ReplyInline Actions

intend -> intent?

craig.topper: intend -> intent?
/// pr64282 for context. Note that this transform is the last one
/// performed at ISEL DAG to DAG.
bool RISCVDAGToDAGISel::doPeepholeNoRegPassThru() {
bool MadeChange = false;
SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_end();
while (Position != CurDAG->allnodes_begin()) {
SDNode *N = &*--Position;
if (N->use_empty() || !N->isMachineOpcode())
continue;
const unsigned Opc = N->getMachineOpcode();
if (!RISCVVPseudosTable::getPseudoInfo(Opc) ||
!RISCVII::isFirstDefTiedToFirstUse(TII->get(Opc)) ||
!isImplicitDef(N->getOperand(0)))
continue;
SmallVector<SDValue> Ops;
Ops.push_back(CurDAG->getRegister(RISCV::NoRegister, N->getValueType(0)));
for (unsigned I = 1, E = N->getNumOperands(); I != E; I++) {
SDValue Op = N->getOperand(I);
Ops.push_back(Op);
}
MachineSDNode *Result =
CurDAG->getMachineNode(Opc, SDLoc(N), N->getVTList(), Ops);
Result->setFlags(N->getFlags());
CurDAG->setNodeMemRefs(Result, cast<MachineSDNode>(N)->memoperands());
ReplaceUses(N, Result);
MadeChange = true;
}
return MadeChange;
}
// This pass converts a legalized DAG into a RISCV-specific DAG, ready // This pass converts a legalized DAG into a RISCV-specific DAG, ready
// for instruction scheduling. // for instruction scheduling.
FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM, FunctionPass *llvm::createRISCVISelDag(RISCVTargetMachine &TM,
CodeGenOpt::Level OptLevel) { CodeGenOpt::Level OptLevel) {
return new RISCVDAGToDAGISel(TM, OptLevel); return new RISCVDAGToDAGISel(TM, OptLevel);
} }
char RISCVDAGToDAGISel::ID = 0; char RISCVDAGToDAGISel::ID = 0;
INITIALIZE_PASS(RISCVDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false) INITIALIZE_PASS(RISCVDAGToDAGISel, DEBUG_TYPE, PASS_NAME, false, false)

llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Linesstatic bool hasUndefinedMergeOp(const MachineInstr &MI,
const MachineRegisterInfo &MRI) { const MachineRegisterInfo &MRI) {
unsigned UseOpIdx; unsigned UseOpIdx;
if (!MI.isRegTiedToUseOperand(0, &UseOpIdx)) if (!MI.isRegTiedToUseOperand(0, &UseOpIdx))
// If there is no passthrough operand, then the pass through // If there is no passthrough operand, then the pass through
// lanes are undefined. // lanes are undefined.
return true; return true;
// If the tied operand is an IMPLICIT_DEF (or a REG_SEQUENCE whose operands // If the tied operand is NoReg, an IMPLICIT_DEF, or a REG_SEQEUENCE whose
// are solely IMPLICIT_DEFS), the pass through lanes are undefined. // operands are solely IMPLICIT_DEFS, then the pass through lanes are
// undefined.
const MachineOperand &UseMO = MI.getOperand(UseOpIdx); const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
if (UseMO.getReg() == RISCV::NoRegister)
return true;
if (MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg())) { if (MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg())) {
if (UseMI->isImplicitDef()) if (UseMI->isImplicitDef())
return true; return true;
if (UseMI->isRegSequence()) { if (UseMI->isRegSequence()) {
for (unsigned i = 1, e = UseMI->getNumOperands(); i < e; i += 2) { for (unsigned i = 1, e = UseMI->getNumOperands(); i < e; i += 2) {
MachineInstr *SourceMI = MRI.getVRegDef(UseMI->getOperand(i).getReg()); MachineInstr *SourceMI = MRI.getVRegDef(UseMI->getOperand(i).getReg());
if (!SourceMI || !SourceMI->isImplicitDef()) if (!SourceMI || !SourceMI->isImplicitDef())
▲ Show 20 Lines • Show All 1,410 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
/// * For fields which do impact register classes (and a few bits of /// * For fields which do impact register classes (and a few bits of
/// legacy - see policy discussion below), we define a family of pseudo /// legacy - see policy discussion below), we define a family of pseudo
/// instructions for each actual instruction. Said differently, we encode /// instructions for each actual instruction. Said differently, we encode
/// each of the preceding fields which are relevant for a given instruction /// each of the preceding fields which are relevant for a given instruction
/// in the opcode space. /// in the opcode space.
/// ///
/// Currently, the policy is represented via the following instrinsic families: /// Currently, the policy is represented via the following instrinsic families:
/// * _MASK - Can represent all three policy states for both tail and mask. If /// * _MASK - Can represent all three policy states for both tail and mask. If
/// passthrough is IMPLICIT_DEF, then represents "undefined". Otherwise, /// passthrough is IMPLICIT_DEF (or NoReg), then represents "undefined".
/// policy operand and tablegen flags drive the interpretation. (If policy /// Otherwise, policy operand and tablegen flags drive the interpretation.
/// operand is not present - there are a couple, thought we're rapidly /// (If policy operand is not present - there are a couple, though we're
craig.topperUnsubmitted
Not Done
ReplyInline Actions

thought -> though?

craig.topper: thought -> though?
/// removing them - a non-undefined policy defaults to "tail agnostic", and /// rapidly removing them - a non-undefined policy defaults to "tail
/// "mask undisturbed". Since this is the only variant with a mask, all /// agnostic", and "mask undisturbed". Since this is the only variant with
/// other variants are "mask undefined". /// a mask, all other variants are "mask undefined".
/// * Unsuffixed w/ both passthrough and policy operand. Can represent all /// * Unsuffixed w/ both passthrough and policy operand. Can represent all
/// three policy states. If passthrough is IMPLICIT_DEF, then represents /// three policy states. If passthrough is IMPLICIT_DEF (or NoReg), then
/// "undefined". Otherwise, policy operand and tablegen flags drive the /// represents "undefined". Otherwise, policy operand and tablegen flags
/// interpretation. /// drive the interpretation.
/// * Unsuffixed w/o passthrough or policy operand -- Does not have a /// * Unsuffixed w/o passthrough or policy operand -- Does not have a
/// passthrough operand, and thus represents the "undefined" state. Note /// passthrough operand, and thus represents the "undefined" state. Note
/// that terminology in code frequently refers to these as "TA" which is /// that terminology in code frequently refers to these as "TA" which is
/// confusing. We're in the process of migrating away from this /// confusing. We're in the process of migrating away from this
/// representation. /// representation.
/// * _TU w/o policy operand -- Has a passthrough operand, and always /// * _TU w/o policy operand -- Has a passthrough operand, and always
/// represents the tail undisturbed state. /// represents the tail undisturbed state.
/// * _TU w/policy operand - Can represent all three policy states. If /// * _TU w/policy operand - Can represent all three policy states. If
/// passthrough is IMPLICIT_DEF, then represents "undefined". Otherwise, /// passthrough is IMPLICIT_DEF (or NoReg), then represents "undefined".
/// policy operand and tablegen flags drive the interpretation. /// Otherwise, policy operand and tablegen flags drive the interpretation.
/// ///
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S", def riscv_vmv_x_s : SDNode<"RISCVISD::VMV_X_S",
SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>, SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>,
SDTCisInt<1>]>>; SDTCisInt<1>]>>;
def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB", def riscv_read_vlenb : SDNode<"RISCVISD::READ_VLENB",
SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>; SDTypeProfile<1, 0, [SDTCisVT<0, XLenVT>]>>;
▲ Show 20 Lines • Show All 7,215 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp

//===- RISCVRVVInitUndef.cpp - Initialize undef vector value to pseudo ----===// //===- RISCVRVVInitUndef.cpp - Initialize undef vector value to pseudo ----===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements a function pass that initializes undef vector value to // This file implements a function pass that initializes undef vector value to
// temporary pseudo instruction and remove it in expandpseudo pass to prevent // temporary pseudo instruction and remove it in expandpseudo pass to prevent
// register allocation resulting in a constraint violated result for vector // register allocation resulting in a constraint violated result for vector
// instruction. // instruction. It also rewrites the NoReg tied operand back to an
// IMPLICIT_DEF.
// //
// RISC-V vector instruction has register overlapping constraint for certain // RISC-V vector instruction has register overlapping constraint for certain
// instructions, and will cause illegal instruction trap if violated, we use // instructions, and will cause illegal instruction trap if violated, we use
// early clobber to model this constraint, but it can't prevent register // early clobber to model this constraint, but it can't prevent register
// allocator allocated same or overlapped if the input register is undef value, // allocator allocated same or overlapped if the input register is undef value,
// so convert IMPLICIT_DEF to temporary pseudo instruction and remove it later // so convert IMPLICIT_DEF to temporary pseudo instruction and remove it later
// could prevent that happen, it's not best way to resolve this, and it might // could prevent that happen, it's not best way to resolve this, and it might
// change the order of program or increase the register pressure, so ideally we // change the order of program or increase the register pressure, so ideally we
// should model the constraint right, but before we model the constraint right, // should model the constraint right, but before we model the constraint right,
// it's the only way to prevent that happen. // it's the only way to prevent that happen.
// //
// When we enable the subregister liveness option, it will also trigger same // When we enable the subregister liveness option, it will also trigger same
// issue due to the partial of register is undef. If we pseudoinit the whole // issue due to the partial of register is undef. If we pseudoinit the whole
// register, then it will generate redundant COPY instruction. Currently, it // register, then it will generate redundant COPY instruction. Currently, it
// will generate INSERT_SUBREG to make sure the whole register is occupied // will generate INSERT_SUBREG to make sure the whole register is occupied
// when program encounter operation that has early-clobber constraint. // when program encounter operation that has early-clobber constraint.
// //
// //
// See also: https://github.com/llvm/llvm-project/issues/50157 // See also: https://github.com/llvm/llvm-project/issues/50157
// //
// Additionally, this pass rewrites tied operands of vector instructions
// from NoReg to IMPLICIT_DEF. (Not that this is a non-overlapping set of
// operands to the above.) We use NoReg to side step a MachineCSE
// optimization quality problem but need to convert back before
// TwoAddressInstruction. See pr64282 for context.
//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "RISCV.h" #include "RISCV.h"
#include "RISCVSubtarget.h" #include "RISCVSubtarget.h"
#include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallSet.h"
#include "llvm/CodeGen/DetectDeadLanes.h" #include "llvm/CodeGen/DetectDeadLanes.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
using namespace llvm; using namespace llvm;
▲ Show 20 Lines • Show All 198 Lines • ▼ Show 20 Lines
} }
bool RISCVInitUndef::processBasicBlock(MachineFunction &MF, bool RISCVInitUndef::processBasicBlock(MachineFunction &MF,
MachineBasicBlock &MBB, MachineBasicBlock &MBB,
const DeadLaneDetector &DLD) { const DeadLaneDetector &DLD) {
bool Changed = false; bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) { for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
MachineInstr &MI = *I; MachineInstr &MI = *I;
// If we used NoReg to represent the passthru, switch this back to being
// an IMPLICIT_DEF before TwoAddressInstructions.
unsigned UseOpIdx;
if (MI.getNumDefs() != 0 && MI.isRegTiedToUseOperand(0, &UseOpIdx)) {
MachineOperand &UseMO = MI.getOperand(UseOpIdx);
if (UseMO.getReg() == RISCV::NoRegister) {
const TargetRegisterClass *RC =
TII->getRegClass(MI.getDesc(), UseOpIdx, TRI, MF);
Register NewDest = MRI->createVirtualRegister(RC);
// We don't have a way to update dead lanes, so keep track of the
// new register so that we avoid querying it later.
NewRegs.insert(NewDest);
BuildMI(MBB, I, I->getDebugLoc(),
TII->get(TargetOpcode::IMPLICIT_DEF), NewDest);
UseMO.setReg(NewDest);
Changed = true;
}
}
if (ST->enableSubRegLiveness() && isEarlyClobberMI(MI)) if (ST->enableSubRegLiveness() && isEarlyClobberMI(MI))
Changed |= handleSubReg(MF, MI, DLD); Changed |= handleSubReg(MF, MI, DLD);
if (MI.isImplicitDef()) { if (MI.isImplicitDef()) {
auto DstReg = MI.getOperand(0).getReg(); auto DstReg = MI.getOperand(0).getReg();
if (isVectorRegClass(DstReg)) if (isVectorRegClass(DstReg))
Changed |= handleImplicitDef(MBB, I); Changed |= handleImplicitDef(MBB, I);
} }
} }
Show All 23 Lines

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Show First 20 Lines • Show All 267 Lines • ▼ Show 20 Linespublic:
bool addGlobalInstructionSelect() override; bool addGlobalInstructionSelect() override;
void addPreEmitPass() override; void addPreEmitPass() override;
void addPreEmitPass2() override; void addPreEmitPass2() override;
void addPreSched2() override; void addPreSched2() override;
void addMachineSSAOptimization() override; void addMachineSSAOptimization() override;
void addPreRegAlloc() override; void addPreRegAlloc() override;
void addPostRegAlloc() override; void addPostRegAlloc() override;
void addOptimizedRegAlloc() override; void addOptimizedRegAlloc() override;
void addFastRegAlloc() override;
}; };
} // namespace } // namespace
TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
return new RISCVPassConfig(*this, PM); return new RISCVPassConfig(*this, PM);
} }
void RISCVPassConfig::addIRPasses() { void RISCVPassConfig::addIRPasses() {
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Linesvoid RISCVPassConfig::addPreRegAlloc() {
addPass(createRISCVPreRAExpandPseudoPass()); addPass(createRISCVPreRAExpandPseudoPass());
if (TM->getOptLevel() != CodeGenOpt::None) if (TM->getOptLevel() != CodeGenOpt::None)
addPass(createRISCVMergeBaseOffsetOptPass()); addPass(createRISCVMergeBaseOffsetOptPass());
addPass(createRISCVInsertVSETVLIPass()); addPass(createRISCVInsertVSETVLIPass());
addPass(createRISCVInsertReadWriteCSRPass()); addPass(createRISCVInsertReadWriteCSRPass());
} }
void RISCVPassConfig::addOptimizedRegAlloc() { void RISCVPassConfig::addOptimizedRegAlloc() {
if (getOptimizeRegAlloc())
insertPass(&DetectDeadLanesID, &RISCVInitUndefID); insertPass(&DetectDeadLanesID, &RISCVInitUndefID);
TargetPassConfig::addOptimizedRegAlloc(); TargetPassConfig::addOptimizedRegAlloc();
} }
void RISCVPassConfig::addFastRegAlloc() {
addPass(createRISCVInitUndefPass());
TargetPassConfig::addFastRegAlloc();
}
void RISCVPassConfig::addPostRegAlloc() { void RISCVPassConfig::addPostRegAlloc() {
if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination) if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
addPass(createRISCVRedundantCopyEliminationPass()); addPass(createRISCVRedundantCopyEliminationPass());
} }
yaml::MachineFunctionInfo * yaml::MachineFunctionInfo *
RISCVTargetMachine::createDefaultFuncInfoYAML() const { RISCVTargetMachine::createDefaultFuncInfoYAML() const {
return new yaml::RISCVMachineFunctionInfo(); return new yaml::RISCVMachineFunctionInfo();
Show All 16 Lines

llvm/test/CodeGen/RISCV/O0-pipeline.ll

Show All 36 Lines
; CHECK-NEXT: Module Verifier ; CHECK-NEXT: Module Verifier
; CHECK-NEXT: Assignment Tracking Analysis ; CHECK-NEXT: Assignment Tracking Analysis
; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection ; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Local Stack Slot Allocation ; CHECK-NEXT: Local Stack Slot Allocation
; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass ; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
; CHECK-NEXT: RISC-V Insert VSETVLI pass ; CHECK-NEXT: RISC-V Insert VSETVLI pass
; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass ; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
; CHECK-NEXT: RISC-V init undef pass
; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Two-Address instruction pass
; CHECK-NEXT: Fast Register Allocator ; CHECK-NEXT: Fast Register Allocator
; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis ; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
; CHECK-NEXT: Fixup Statepoint Caller Saved ; CHECK-NEXT: Fixup Statepoint Caller Saved
; CHECK-NEXT: Lazy Machine Block Frequency Analysis ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Machine Optimization Remark Emitter
; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
Show All 22 Lines

llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll

Show All 11 Lines
; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 72(sp) # 8-byte Folded Spill
; CHECK-NEXT: addi s0, sp, 96 ; CHECK-NEXT: addi s0, sp, 96
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0 ; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -64 ; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: mv s1, sp ; CHECK-NEXT: mv s1, sp
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: addi a0, s1, 64 ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: sd a0, 0(sp)
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: addi a0, s1, 64
; CHECK-NEXT: vs8r.v v8, (a0) ; CHECK-NEXT: vs8r.v v8, (a0)
; CHECK-NEXT: sd a0, 0(sp)
; CHECK-NEXT: li a0, 0 ; CHECK-NEXT: li a0, 0
; CHECK-NEXT: li a1, 0 ; CHECK-NEXT: li a1, 0
; CHECK-NEXT: li a2, 0 ; CHECK-NEXT: li a2, 0
; CHECK-NEXT: li a3, 0 ; CHECK-NEXT: li a3, 0
; CHECK-NEXT: li a4, 0 ; CHECK-NEXT: li a4, 0
; CHECK-NEXT: li a5, 0 ; CHECK-NEXT: li a5, 0
; CHECK-NEXT: li a6, 0 ; CHECK-NEXT: li a6, 0
; CHECK-NEXT: li a7, 0 ; CHECK-NEXT: li a7, 0
Show All 15 Lines

llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %tc) %mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %tc)
ret <8 x i1> %mask ret <8 x i1> %mask
} }
define <32 x i1> @fv32(ptr %p, i64 %index, i64 %tc) { define <32 x i1> @fv32(ptr %p, i64 %index, i64 %tc) {
; CHECK-LABEL: fv32: ; CHECK-LABEL: fv32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: lui a0, %hi(.LCPI8_0) ; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI8_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI8_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vsaddu.vx v8, v8, a1 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2 ; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2 ; CHECK-NEXT: vslideup.vi v0, v16, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 %index, i64 %tc) %mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 %index, i64 %tc)
ret <32 x i1> %mask ret <32 x i1> %mask
} }
define <64 x i1> @fv64(ptr %p, i64 %index, i64 %tc) { define <64 x i1> @fv64(ptr %p, i64 %index, i64 %tc) {
; CHECK-LABEL: fv64: ; CHECK-LABEL: fv64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: lui a0, %hi(.LCPI9_0) ; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vsaddu.vx v8, v8, a1 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2 ; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2 ; CHECK-NEXT: vslideup.vi v0, v16, 2
; CHECK-NEXT: lui a0, %hi(.LCPI9_1) ; CHECK-NEXT: lui a0, %hi(.LCPI9_1)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_1) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_1)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsaddu.vx v8, v8, a1 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2 ; CHECK-NEXT: vmsltu.vx v16, v8, a2
Show All 10 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 %index, i64 %tc) %mask = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 %index, i64 %tc)
ret <64 x i1> %mask ret <64 x i1> %mask
} }
define <128 x i1> @fv128(ptr %p, i64 %index, i64 %tc) { define <128 x i1> @fv128(ptr %p, i64 %index, i64 %tc) {
; CHECK-LABEL: fv128: ; CHECK-LABEL: fv128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: lui a0, %hi(.LCPI10_0) ; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vsaddu.vx v8, v8, a1 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2 ; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma ; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2 ; CHECK-NEXT: vslideup.vi v0, v16, 2
; CHECK-NEXT: lui a0, %hi(.LCPI10_1) ; CHECK-NEXT: lui a0, %hi(.LCPI10_1)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_1) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_1)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsaddu.vx v8, v8, a1 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2 ; CHECK-NEXT: vmsltu.vx v16, v8, a2
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll

Show First 20 Lines • Show All 1,088 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a0 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: mv a3, sp
; RV32-NEXT: vlse64.v v11, (a3), zero
; RV32-NEXT: vand.vx v10, v10, a2 ; RV32-NEXT: vand.vx v10, v10, a2
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsrl.vi v10, v8, 8 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vand.vv v10, v10, v11 ; RV32-NEXT: mv a3, sp
; RV32-NEXT: vsrl.vi v12, v8, 24 ; RV32-NEXT: vlse64.v v11, (a3), zero
; RV32-NEXT: lui a3, 4080 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vand.vx v10, v10, a3
; RV32-NEXT: vor.vv v10, v10, v12 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: vand.vv v12, v12, v11
; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsll.vx v10, v8, a0 ; RV32-NEXT: vsll.vx v10, v8, a0
; RV32-NEXT: vand.vx v12, v8, a2 ; RV32-NEXT: vand.vx v12, v8, a2
; RV32-NEXT: vsll.vx v12, v12, a1 ; RV32-NEXT: vsll.vx v12, v12, a1
; RV32-NEXT: vor.vv v10, v10, v12 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vand.vx v12, v8, a3 ; RV32-NEXT: vand.vx v12, v8, a3
; RV32-NEXT: vsll.vi v12, v12, 24 ; RV32-NEXT: vsll.vi v12, v12, 24
; RV32-NEXT: vand.vv v8, v8, v11 ; RV32-NEXT: vand.vv v8, v8, v11
Show All 22 Lines
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v9, v8 ; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 32 ; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bitreverse_nxv1i64: ; RV64-LABEL: bitreverse_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV64-NEXT: vand.vx v9, v8, a0 ; RV64-NEXT: vsrl.vx v9, v8, a0
; RV64-NEXT: vsll.vi v9, v9, 24 ; RV64-NEXT: li a1, 40
; RV64-NEXT: li a1, 255 ; RV64-NEXT: vsrl.vx v10, v8, a1
; RV64-NEXT: slli a1, a1, 24 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: vand.vx v10, v8, a1 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vsll.vi v10, v10, 8 ; RV64-NEXT: vand.vx v10, v10, a2
; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: li a2, 56
; RV64-NEXT: vsll.vx v10, v8, a2
; RV64-NEXT: lui a3, 16
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: vand.vx v11, v8, a3
; RV64-NEXT: li a4, 40
; RV64-NEXT: vsll.vx v11, v11, a4
; RV64-NEXT: vor.vv v10, v10, v11
; RV64-NEXT: vor.vv v9, v10, v9 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vsrl.vx v10, v8, a2 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vsrl.vx v11, v8, a4 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v11, v11, a3 ; RV64-NEXT: vand.vx v10, v10, a3
; RV64-NEXT: vsrl.vi v11, v8, 8
; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v11, v11, a4
; RV64-NEXT: vor.vv v10, v11, v10 ; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vsrl.vi v11, v8, 24 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vand.vx v11, v11, a0 ; RV64-NEXT: vand.vx v10, v8, a3
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsll.vi v10, v10, 24
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vand.vx v11, v8, a4
; RV64-NEXT: vor.vv v8, v8, v11 ; RV64-NEXT: vsll.vi v11, v11, 8
; RV64-NEXT: vor.vv v10, v10, v11
; RV64-NEXT: vsll.vx v11, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: vor.vv v8, v11, v8
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v9, v8 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsrl.vi v9, v8, 4 ; RV64-NEXT: vsrl.vi v9, v8, 4
; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: slli a1, a0, 32
; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: vand.vx v9, v9, a0 ; RV64-NEXT: vand.vx v9, v9, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vsll.vi v8, v8, 4 ; RV64-NEXT: vsll.vi v8, v8, 4
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a0 ; RV32-NEXT: vsrl.vx v10, v8, a0
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: mv a3, sp
; RV32-NEXT: vlse64.v v14, (a3), zero
; RV32-NEXT: vand.vx v12, v12, a2 ; RV32-NEXT: vand.vx v12, v12, a2
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: vand.vv v12, v12, v14 ; RV32-NEXT: mv a3, sp
; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vlse64.v v14, (a3), zero
; RV32-NEXT: lui a3, 4080 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vand.vx v12, v12, a3
; RV32-NEXT: vor.vv v12, v12, v16 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vand.vv v16, v16, v14
; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v12, v8, a0 ; RV32-NEXT: vsll.vx v12, v8, a0
; RV32-NEXT: vand.vx v16, v8, a2 ; RV32-NEXT: vand.vx v16, v8, a2
; RV32-NEXT: vsll.vx v16, v16, a1 ; RV32-NEXT: vsll.vx v16, v16, a1
; RV32-NEXT: vor.vv v12, v12, v16 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vand.vx v16, v8, a3 ; RV32-NEXT: vand.vx v16, v8, a3
; RV32-NEXT: vsll.vi v16, v16, 24 ; RV32-NEXT: vsll.vi v16, v16, 24
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v14
Show All 22 Lines
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 32 ; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bitreverse_nxv2i64: ; RV64-LABEL: bitreverse_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV64-NEXT: vand.vx v10, v8, a0 ; RV64-NEXT: vsrl.vx v10, v8, a0
; RV64-NEXT: vsll.vi v10, v10, 24 ; RV64-NEXT: li a1, 40
; RV64-NEXT: li a1, 255 ; RV64-NEXT: vsrl.vx v12, v8, a1
; RV64-NEXT: slli a1, a1, 24 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: vand.vx v12, v8, a1 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vsll.vi v12, v12, 8 ; RV64-NEXT: vand.vx v12, v12, a2
; RV64-NEXT: vor.vv v10, v10, v12
; RV64-NEXT: li a2, 56
; RV64-NEXT: vsll.vx v12, v8, a2
; RV64-NEXT: lui a3, 16
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: vand.vx v14, v8, a3
; RV64-NEXT: li a4, 40
; RV64-NEXT: vsll.vx v14, v14, a4
; RV64-NEXT: vor.vv v12, v12, v14
; RV64-NEXT: vor.vv v10, v12, v10 ; RV64-NEXT: vor.vv v10, v12, v10
; RV64-NEXT: vsrl.vx v12, v8, a2 ; RV64-NEXT: vsrl.vi v12, v8, 24
; RV64-NEXT: vsrl.vx v14, v8, a4 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v14, v14, a3 ; RV64-NEXT: vand.vx v12, v12, a3
; RV64-NEXT: vsrl.vi v14, v8, 8
; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v14, v14, a4
; RV64-NEXT: vor.vv v12, v14, v12 ; RV64-NEXT: vor.vv v12, v14, v12
; RV64-NEXT: vsrl.vi v14, v8, 24 ; RV64-NEXT: vor.vv v10, v12, v10
; RV64-NEXT: vand.vx v14, v14, a0 ; RV64-NEXT: vand.vx v12, v8, a3
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsll.vi v12, v12, 24
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vand.vx v14, v8, a4
; RV64-NEXT: vor.vv v8, v8, v14 ; RV64-NEXT: vsll.vi v14, v14, 8
; RV64-NEXT: vor.vv v12, v12, v14
; RV64-NEXT: vsll.vx v14, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: vor.vv v8, v14, v8
; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vor.vv v8, v10, v8 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vsrl.vi v10, v8, 4 ; RV64-NEXT: vsrl.vi v10, v8, 4
; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: slli a1, a0, 32
; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: vand.vx v10, v10, a0 ; RV64-NEXT: vand.vx v10, v10, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vsll.vi v8, v8, 4 ; RV64-NEXT: vsll.vi v8, v8, 4
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a0 ; RV32-NEXT: vsrl.vx v12, v8, a0
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: vsrl.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: mv a3, sp
; RV32-NEXT: vlse64.v v20, (a3), zero
; RV32-NEXT: vand.vx v16, v16, a2 ; RV32-NEXT: vand.vx v16, v16, a2
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vand.vv v16, v16, v20 ; RV32-NEXT: mv a3, sp
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vlse64.v v20, (a3), zero
; RV32-NEXT: lui a3, 4080 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v16, v16, a3
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v24, v24, v20
; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vx v16, v8, a0 ; RV32-NEXT: vsll.vx v16, v8, a0
; RV32-NEXT: vand.vx v24, v8, a2 ; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: vsll.vx v24, v24, a1 ; RV32-NEXT: vsll.vx v24, v24, a1
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vand.vx v24, v8, a3 ; RV32-NEXT: vand.vx v24, v8, a3
; RV32-NEXT: vsll.vi v24, v24, 24 ; RV32-NEXT: vsll.vi v24, v24, 24
; RV32-NEXT: vand.vv v8, v8, v20 ; RV32-NEXT: vand.vv v8, v8, v20
Show All 22 Lines
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 32 ; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bitreverse_nxv4i64: ; RV64-LABEL: bitreverse_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a0 ; RV64-NEXT: vsrl.vx v12, v8, a0
; RV64-NEXT: vsll.vi v12, v12, 24 ; RV64-NEXT: li a1, 40
; RV64-NEXT: li a1, 255 ; RV64-NEXT: vsrl.vx v16, v8, a1
; RV64-NEXT: slli a1, a1, 24 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: vand.vx v16, v8, a1 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vsll.vi v16, v16, 8 ; RV64-NEXT: vand.vx v16, v16, a2
; RV64-NEXT: vor.vv v12, v12, v16
; RV64-NEXT: li a2, 56
; RV64-NEXT: vsll.vx v16, v8, a2
; RV64-NEXT: lui a3, 16
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: vand.vx v20, v8, a3
; RV64-NEXT: li a4, 40
; RV64-NEXT: vsll.vx v20, v20, a4
; RV64-NEXT: vor.vv v16, v16, v20
; RV64-NEXT: vor.vv v12, v16, v12 ; RV64-NEXT: vor.vv v12, v16, v12
; RV64-NEXT: vsrl.vx v16, v8, a2 ; RV64-NEXT: vsrl.vi v16, v8, 24
; RV64-NEXT: vsrl.vx v20, v8, a4 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v20, v20, a3 ; RV64-NEXT: vand.vx v16, v16, a3
; RV64-NEXT: vsrl.vi v20, v8, 8
; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v20, v20, a4
; RV64-NEXT: vor.vv v16, v20, v16 ; RV64-NEXT: vor.vv v16, v20, v16
; RV64-NEXT: vsrl.vi v20, v8, 24 ; RV64-NEXT: vor.vv v12, v16, v12
; RV64-NEXT: vand.vx v20, v20, a0 ; RV64-NEXT: vand.vx v16, v8, a3
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsll.vi v16, v16, 24
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vand.vx v20, v8, a4
; RV64-NEXT: vor.vv v8, v8, v20 ; RV64-NEXT: vsll.vi v20, v20, 8
; RV64-NEXT: vor.vv v16, v16, v20
; RV64-NEXT: vsll.vx v20, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: vor.vv v8, v20, v8
; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vor.vv v8, v12, v8 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vsrl.vi v12, v8, 4 ; RV64-NEXT: vsrl.vi v12, v8, 4
; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: slli a1, a0, 32
; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: vand.vx v12, v12, a0 ; RV64-NEXT: vand.vx v12, v12, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vsll.vi v8, v8, 4 ; RV64-NEXT: vsll.vi v8, v8, 4
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; RV32-NEXT: lui a0, 349525 ; RV32-NEXT: lui a0, 349525
; RV32-NEXT: addi a0, a0, 1365 ; RV32-NEXT: addi a0, a0, 1365
; RV32-NEXT: sw a0, 28(sp) ; RV32-NEXT: sw a0, 28(sp)
; RV32-NEXT: sw a0, 24(sp) ; RV32-NEXT: sw a0, 24(sp)
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a0 ; RV32-NEXT: vsrl.vx v16, v8, a0
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: vsrl.vx v0, v8, a1 ; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: addi a3, sp, 16 ; RV32-NEXT: vand.vx v24, v24, a2
; RV32-NEXT: vlse64.v v24, (a3), zero ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vor.vv v16, v0, v16
; RV32-NEXT: addi a3, sp, 48 ; RV32-NEXT: addi a3, sp, 48
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v0, v8, 8 ; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: vand.vv v0, v0, v24 ; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vlse64.v v0, (a3), zero
; RV32-NEXT: lui a3, 4080 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vor.vv v16, v0, v16 ; RV32-NEXT: vand.vv v16, v16, v0
; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: addi a4, sp, 48 ; RV32-NEXT: addi a4, sp, 48
; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a2 ; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: vsll.vx v0, v0, a1 ; RV32-NEXT: vsll.vx v24, v24, a1
; RV32-NEXT: vsll.vx v16, v8, a0 ; RV32-NEXT: vsll.vx v16, v8, a0
; RV32-NEXT: vor.vv v0, v16, v0 ; RV32-NEXT: vor.vv v24, v16, v24
; RV32-NEXT: vand.vv v16, v8, v24 ; RV32-NEXT: vand.vv v16, v8, v0
; RV32-NEXT: vand.vx v8, v8, a3 ; RV32-NEXT: vand.vx v8, v8, a3
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 40 ; RV32-NEXT: addi a0, sp, 40
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vor.vv v8, v0, v8 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: addi a0, sp, 48 ; RV32-NEXT: addi a0, sp, 48
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vsrl.vi v24, v8, 4 ; RV32-NEXT: vsrl.vi v24, v8, 4
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 32 ; RV32-NEXT: addi a0, sp, 32
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
Show All 14 Lines
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 48 ; RV32-NEXT: addi sp, sp, 48
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bitreverse_nxv8i64: ; RV64-LABEL: bitreverse_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a0 ; RV64-NEXT: vsrl.vx v16, v8, a0
; RV64-NEXT: vsll.vi v16, v16, 24 ; RV64-NEXT: li a1, 40
; RV64-NEXT: li a1, 255 ; RV64-NEXT: vsrl.vx v24, v8, a1
; RV64-NEXT: slli a1, a1, 24 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: vand.vx v24, v8, a1 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vsll.vi v24, v24, 8 ; RV64-NEXT: vand.vx v24, v24, a2
; RV64-NEXT: vor.vv v16, v16, v24
; RV64-NEXT: li a2, 56
; RV64-NEXT: vsll.vx v24, v8, a2
; RV64-NEXT: lui a3, 16
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: vand.vx v0, v8, a3
; RV64-NEXT: li a4, 40
; RV64-NEXT: vsll.vx v0, v0, a4
; RV64-NEXT: vor.vv v24, v24, v0
; RV64-NEXT: vor.vv v16, v24, v16 ; RV64-NEXT: vor.vv v16, v24, v16
; RV64-NEXT: vsrl.vx v24, v8, a2 ; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: vsrl.vx v0, v8, a4 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v0, v0, a3 ; RV64-NEXT: vand.vx v24, v24, a3
; RV64-NEXT: vsrl.vi v0, v8, 8
; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v0, v0, a4
; RV64-NEXT: vor.vv v24, v0, v24 ; RV64-NEXT: vor.vv v24, v0, v24
; RV64-NEXT: vsrl.vi v0, v8, 24 ; RV64-NEXT: vor.vv v16, v24, v16
; RV64-NEXT: vand.vx v0, v0, a0 ; RV64-NEXT: vand.vx v24, v8, a3
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsll.vi v24, v24, 24
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vand.vx v0, v8, a4
; RV64-NEXT: vor.vv v8, v8, v0 ; RV64-NEXT: vsll.vi v0, v0, 8
; RV64-NEXT: vor.vv v24, v24, v0
; RV64-NEXT: vsll.vx v0, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: vor.vv v8, v0, v8
; RV64-NEXT: vor.vv v8, v8, v24 ; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v16, v8 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vsrl.vi v16, v8, 4 ; RV64-NEXT: vsrl.vi v16, v8, 4
; RV64-NEXT: lui a0, 61681 ; RV64-NEXT: lui a0, 61681
; RV64-NEXT: addiw a0, a0, -241 ; RV64-NEXT: addiw a0, a0, -241
; RV64-NEXT: slli a1, a0, 32 ; RV64-NEXT: slli a1, a0, 32
; RV64-NEXT: add a0, a0, a1 ; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: vand.vx v16, v16, a0 ; RV64-NEXT: vand.vx v16, v16, a0
; RV64-NEXT: vand.vx v8, v8, a0 ; RV64-NEXT: vand.vx v8, v8, a0
; RV64-NEXT: vsll.vi v8, v8, 4 ; RV64-NEXT: vsll.vi v8, v8, 4
Show All 30 Lines

llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll

Show First 20 Lines • Show All 2,202 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a1, 20(sp) ; RV32-NEXT: sw a1, 20(sp)
; RV32-NEXT: sw a1, 16(sp) ; RV32-NEXT: sw a1, 16(sp)
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a1, v0.t ; RV32-NEXT: vsll.vx v9, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v10, v8, a2, v0.t
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v10, v10, a3, v0.t ; RV32-NEXT: vsll.vx v10, v10, a3, v0.t
; RV32-NEXT: vor.vv v9, v10, v9, v0.t ; RV32-NEXT: vor.vv v9, v9, v10, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v10, a4, v0.t ; RV32-NEXT: vand.vx v10, v8, a4, v0.t
; RV32-NEXT: vsrl.vi v11, v8, 8, v0.t ; RV32-NEXT: vsll.vi v10, v10, 24, v0.t
; RV32-NEXT: mv a5, sp ; RV32-NEXT: mv a5, sp
; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v12, (a5), zero ; RV32-NEXT: vlse64.v v11, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v11, v11, v12, v0.t ; RV32-NEXT: vand.vv v12, v8, v11, v0.t
; RV32-NEXT: vor.vv v10, v11, v10, v0.t ; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
; RV32-NEXT: vor.vv v9, v10, v9, v0.t ; RV32-NEXT: vor.vv v10, v10, v12, v0.t
; RV32-NEXT: vsll.vx v10, v8, a1, v0.t ; RV32-NEXT: vor.vv v9, v9, v10, v0.t
; RV32-NEXT: vand.vx v11, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t
; RV32-NEXT: vsll.vx v11, v11, a2, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a3, v0.t
; RV32-NEXT: vor.vv v10, v10, v11, v0.t ; RV32-NEXT: vand.vx v12, v12, a2, v0.t
; RV32-NEXT: vand.vx v11, v8, a4, v0.t ; RV32-NEXT: vor.vv v10, v12, v10, v0.t
; RV32-NEXT: vsll.vi v11, v11, 24, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v12, v0.t ; RV32-NEXT: vand.vx v12, v12, a4, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v11, v8, v0.t ; RV32-NEXT: vand.vv v8, v8, v11, v0.t
; RV32-NEXT: vor.vv v8, v10, v8, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: vor.vv v8, v9, v8, v0.t
; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v9, v8, 4, v0.t
; RV32-NEXT: addi a1, sp, 24 ; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetvli a2, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v10, (a1), zero ; RV32-NEXT: vlse64.v v10, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v9, v9, v10, v0.t ; RV32-NEXT: vand.vv v9, v9, v10, v0.t
; RV32-NEXT: vand.vv v8, v8, v10, v0.t ; RV32-NEXT: vand.vv v8, v8, v10, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t ; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a1, 20(sp) ; RV32-NEXT: sw a1, 20(sp)
; RV32-NEXT: sw a1, 16(sp) ; RV32-NEXT: sw a1, 16(sp)
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a1 ; RV32-NEXT: vsll.vx v9, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v10, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v10, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v10, v10, a3 ; RV32-NEXT: vsll.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v10, a4 ; RV32-NEXT: vand.vx v10, v8, a4
; RV32-NEXT: vsrl.vi v11, v8, 8 ; RV32-NEXT: vsll.vi v10, v10, 24
; RV32-NEXT: mv a5, sp ; RV32-NEXT: mv a5, sp
; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v12, (a5), zero ; RV32-NEXT: vlse64.v v11, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v11, v11, v12 ; RV32-NEXT: vand.vv v12, v8, v11
; RV32-NEXT: vor.vv v10, v11, v10 ; RV32-NEXT: vsll.vi v12, v12, 8
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vsll.vx v10, v8, a1 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vand.vx v11, v8, a3 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: vsll.vx v11, v11, a2 ; RV32-NEXT: vsrl.vx v12, v8, a3
; RV32-NEXT: vor.vv v10, v10, v11 ; RV32-NEXT: vand.vx v12, v12, a2
; RV32-NEXT: vand.vx v11, v8, a4 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vi v11, v11, 24 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vx v12, v12, a4
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsrl.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v11, v8 ; RV32-NEXT: vand.vv v8, v8, v11
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vsrl.vi v9, v8, 4
; RV32-NEXT: addi a1, sp, 24 ; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetvli a2, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v10, (a1), zero ; RV32-NEXT: vlse64.v v10, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v9, v9, v10 ; RV32-NEXT: vand.vv v9, v9, v10
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a1, 20(sp) ; RV32-NEXT: sw a1, 20(sp)
; RV32-NEXT: sw a1, 16(sp) ; RV32-NEXT: sw a1, 16(sp)
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t ; RV32-NEXT: vsll.vx v10, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v12, v8, a2, v0.t
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v12, v12, a3, v0.t ; RV32-NEXT: vsll.vx v12, v12, a3, v0.t
; RV32-NEXT: vor.vv v10, v12, v10, v0.t ; RV32-NEXT: vor.vv v10, v10, v12, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v12, v12, a4, v0.t ; RV32-NEXT: vand.vx v12, v8, a4, v0.t
; RV32-NEXT: vsrl.vi v14, v8, 8, v0.t ; RV32-NEXT: vsll.vi v12, v12, 24, v0.t
; RV32-NEXT: mv a5, sp ; RV32-NEXT: mv a5, sp
; RV32-NEXT: vsetvli a6, zero, e64, m2, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v16, (a5), zero ; RV32-NEXT: vlse64.v v14, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v14, v14, v16, v0.t ; RV32-NEXT: vand.vv v16, v8, v14, v0.t
; RV32-NEXT: vor.vv v12, v14, v12, v0.t ; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: vor.vv v10, v12, v10, v0.t ; RV32-NEXT: vor.vv v12, v12, v16, v0.t
; RV32-NEXT: vsll.vx v12, v8, a1, v0.t ; RV32-NEXT: vor.vv v10, v10, v12, v0.t
; RV32-NEXT: vand.vx v14, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
; RV32-NEXT: vsll.vx v14, v14, a2, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
; RV32-NEXT: vor.vv v12, v12, v14, v0.t ; RV32-NEXT: vand.vx v16, v16, a2, v0.t
; RV32-NEXT: vand.vx v14, v8, a4, v0.t ; RV32-NEXT: vor.vv v12, v16, v12, v0.t
; RV32-NEXT: vsll.vi v14, v14, 24, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vx v16, v16, a4, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v14, v8, v0.t ; RV32-NEXT: vand.vv v8, v8, v14, v0.t
; RV32-NEXT: vor.vv v8, v12, v8, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vor.vv v8, v10, v8, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v10, v8, 4, v0.t
; RV32-NEXT: addi a1, sp, 24 ; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetvli a2, zero, e64, m2, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v12, (a1), zero ; RV32-NEXT: vlse64.v v12, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v10, v10, v12, v0.t ; RV32-NEXT: vand.vv v10, v10, v12, v0.t
; RV32-NEXT: vand.vv v8, v8, v12, v0.t ; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t ; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a1, 20(sp) ; RV32-NEXT: sw a1, 20(sp)
; RV32-NEXT: sw a1, 16(sp) ; RV32-NEXT: sw a1, 16(sp)
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsll.vx v10, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v12, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v12, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vsll.vx v12, v12, a3
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v12, v12, a4 ; RV32-NEXT: vand.vx v12, v8, a4
; RV32-NEXT: vsrl.vi v14, v8, 8 ; RV32-NEXT: vsll.vi v12, v12, 24
; RV32-NEXT: mv a5, sp ; RV32-NEXT: mv a5, sp
; RV32-NEXT: vsetvli a6, zero, e64, m2, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v16, (a5), zero ; RV32-NEXT: vlse64.v v14, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v14, v14, v16 ; RV32-NEXT: vand.vv v16, v8, v14
; RV32-NEXT: vor.vv v12, v14, v12 ; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vsll.vx v12, v8, a1 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vand.vx v14, v8, a3 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: vsll.vx v14, v14, a2 ; RV32-NEXT: vsrl.vx v16, v8, a3
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vand.vx v16, v16, a2
; RV32-NEXT: vand.vx v14, v8, a4 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vi v14, v14, 24 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsrl.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v14, v8 ; RV32-NEXT: vand.vv v8, v8, v14
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vsrl.vi v10, v8, 4 ; RV32-NEXT: vsrl.vi v10, v8, 4
; RV32-NEXT: addi a1, sp, 24 ; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetvli a2, zero, e64, m2, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v12, (a1), zero ; RV32-NEXT: vlse64.v v12, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v10, v10, v12 ; RV32-NEXT: vand.vv v10, v10, v12
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a1, 20(sp) ; RV32-NEXT: sw a1, 20(sp)
; RV32-NEXT: sw a1, 16(sp) ; RV32-NEXT: sw a1, 16(sp)
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t ; RV32-NEXT: vsll.vx v12, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v16, v8, a2, v0.t
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v16, v16, a3, v0.t ; RV32-NEXT: vsll.vx v16, v16, a3, v0.t
; RV32-NEXT: vor.vv v12, v16, v12, v0.t ; RV32-NEXT: vor.vv v16, v12, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v20, v16, a4, v0.t ; RV32-NEXT: vand.vx v12, v8, a4, v0.t
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t ; RV32-NEXT: vsll.vi v20, v12, 24, v0.t
; RV32-NEXT: mv a5, sp ; RV32-NEXT: mv a5, sp
; RV32-NEXT: vsetvli a6, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v16, (a5), zero ; RV32-NEXT: vlse64.v v12, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v24, v24, v16, v0.t ; RV32-NEXT: vand.vv v24, v8, v12, v0.t
; RV32-NEXT: vor.vv v20, v24, v20, v0.t ; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
; RV32-NEXT: vor.vv v12, v20, v12, v0.t
; RV32-NEXT: vsll.vx v20, v8, a1, v0.t
; RV32-NEXT: vand.vx v24, v8, a3, v0.t
; RV32-NEXT: vsll.vx v24, v24, a2, v0.t
; RV32-NEXT: vor.vv v20, v20, v24, v0.t ; RV32-NEXT: vor.vv v20, v20, v24, v0.t
; RV32-NEXT: vand.vx v24, v8, a4, v0.t ; RV32-NEXT: vor.vv v16, v16, v20, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t ; RV32-NEXT: vsrl.vx v20, v8, a1, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vand.vx v24, v24, a2, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v20, v24, v20, v0.t
; RV32-NEXT: vor.vv v8, v20, v8, v0.t ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vand.vx v24, v24, a4, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: vor.vv v8, v8, v20, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV32-NEXT: addi a1, sp, 24 ; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetvli a2, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v12, v12, v16, v0.t ; RV32-NEXT: vand.vv v12, v12, v16, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t ; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a1, 20(sp) ; RV32-NEXT: sw a1, 20(sp)
; RV32-NEXT: sw a1, 16(sp) ; RV32-NEXT: sw a1, 16(sp)
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: sw a1, 12(sp) ; RV32-NEXT: sw a1, 12(sp)
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsll.vx v12, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v16, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vsll.vx v16, v16, a3
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4 ; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsrl.vi v20, v8, 8 ; RV32-NEXT: vsll.vi v16, v16, 24
; RV32-NEXT: mv a5, sp ; RV32-NEXT: mv a5, sp
; RV32-NEXT: vsetvli a6, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero ; RV32-NEXT: vlse64.v v20, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v20, v20, v24 ; RV32-NEXT: vand.vv v24, v8, v20
; RV32-NEXT: vor.vv v16, v20, v16 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vand.vx v20, v8, a3 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vsll.vx v20, v20, a2 ; RV32-NEXT: vsrl.vx v24, v8, a3
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vand.vx v24, v24, a2
; RV32-NEXT: vand.vx v20, v8, a4 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vsll.vi v20, v20, 24 ; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vx v24, v24, a4
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsrl.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v20, v8 ; RV32-NEXT: vand.vv v8, v8, v20
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vsrl.vi v12, v8, 4 ; RV32-NEXT: vsrl.vi v12, v8, 4
; RV32-NEXT: addi a1, sp, 24 ; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetvli a2, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v12, v12, v16 ; RV32-NEXT: vand.vv v12, v12, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a1, 36(sp) ; RV32-NEXT: sw a1, 36(sp)
; RV32-NEXT: sw a1, 32(sp) ; RV32-NEXT: sw a1, 32(sp)
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: sw a1, 28(sp) ; RV32-NEXT: sw a1, 28(sp)
; RV32-NEXT: sw a1, 24(sp) ; RV32-NEXT: sw a1, 24(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v24, v8, a2, v0.t
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v24, v24, a3, v0.t ; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: addi a4, sp, 48
; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 48
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4, v0.t ; RV32-NEXT: vand.vx v16, v8, a4, v0.t
; RV32-NEXT: addi a5, sp, 48 ; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 4
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 48
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: addi a5, sp, 16 ; RV32-NEXT: addi a5, sp, 16
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero ; RV32-NEXT: vlse64.v v16, (a5), zero
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 3 ; RV32-NEXT: slli a5, a5, 3
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 48 ; RV32-NEXT: addi a5, a5, 48
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: addi a5, sp, 48 ; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 4 ; RV32-NEXT: slli a5, a5, 4
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 48 ; RV32-NEXT: addi a5, a5, 48
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: addi a5, sp, 48
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 4 ; RV32-NEXT: slli a5, a5, 4
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 48 ; RV32-NEXT: addi a5, a5, 48
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v24, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
; RV32-NEXT: vand.vx v16, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
; RV32-NEXT: vsll.vx v16, v16, a2, v0.t ; RV32-NEXT: vand.vx v16, v16, a2, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: addi a1, sp, 48 ; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v16, v8, a4, v0.t ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t ; RV32-NEXT: vand.vx v24, v24, a4, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 48 ; RV32-NEXT: addi a1, a1, 48
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: addi a1, sp, 48 ; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4 ; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 48 ; RV32-NEXT: addi a1, a1, 48
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: addi a1, sp, 40 ; RV32-NEXT: addi a1, sp, 40
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a1), zero ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24, v0.t ; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vand.vv v8, v8, v24, v0.t ; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t ; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a1, 36(sp) ; RV32-NEXT: sw a1, 36(sp)
; RV32-NEXT: sw a1, 32(sp) ; RV32-NEXT: sw a1, 32(sp)
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: sw a1, 28(sp) ; RV32-NEXT: sw a1, 28(sp)
; RV32-NEXT: sw a1, 24(sp) ; RV32-NEXT: sw a1, 24(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vsll.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: addi a4, sp, 48 ; RV32-NEXT: addi a4, sp, 48
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v0, v24, a4 ; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsll.vi v0, v16, 24
; RV32-NEXT: addi a5, sp, 16 ; RV32-NEXT: addi a5, sp, 16
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero ; RV32-NEXT: vlse64.v v16, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: addi a5, sp, 48 ; RV32-NEXT: addi a5, sp, 48
; RV32-NEXT: vl8r.v v0, (a5) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a5) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vsrl.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vand.vv v24, v8, v24 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: addi a1, sp, 48 ; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: addi a1, sp, 40 ; RV32-NEXT: addi a1, sp, 40
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a1), zero ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a1, 36(sp) ; RV32-NEXT: sw a1, 36(sp)
; RV32-NEXT: sw a1, 32(sp) ; RV32-NEXT: sw a1, 32(sp)
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: sw a1, 28(sp) ; RV32-NEXT: sw a1, 28(sp)
; RV32-NEXT: sw a1, 24(sp) ; RV32-NEXT: sw a1, 24(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v24, v8, a2, v0.t
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v24, v24, a3, v0.t ; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: addi a4, sp, 48
; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 48
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4, v0.t ; RV32-NEXT: vand.vx v16, v8, a4, v0.t
; RV32-NEXT: addi a5, sp, 48 ; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 4
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 48
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: addi a5, sp, 16 ; RV32-NEXT: addi a5, sp, 16
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero ; RV32-NEXT: vlse64.v v16, (a5), zero
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 3 ; RV32-NEXT: slli a5, a5, 3
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 48 ; RV32-NEXT: addi a5, a5, 48
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: addi a5, sp, 48 ; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 4 ; RV32-NEXT: slli a5, a5, 4
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 48 ; RV32-NEXT: addi a5, a5, 48
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: addi a5, sp, 48
; RV32-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 4 ; RV32-NEXT: slli a5, a5, 4
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 48 ; RV32-NEXT: addi a5, a5, 48
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v24, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
; RV32-NEXT: vand.vx v16, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
; RV32-NEXT: vsll.vx v16, v16, a2, v0.t ; RV32-NEXT: vand.vx v16, v16, a2, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: addi a1, sp, 48 ; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v16, v8, a4, v0.t ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t ; RV32-NEXT: vand.vx v24, v24, a4, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 48 ; RV32-NEXT: addi a1, a1, 48
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: addi a1, sp, 48 ; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4 ; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 48 ; RV32-NEXT: addi a1, a1, 48
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: addi a1, sp, 40 ; RV32-NEXT: addi a1, sp, 40
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a1), zero ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24, v0.t ; RV32-NEXT: vand.vv v16, v16, v24, v0.t
; RV32-NEXT: vand.vv v8, v8, v24, v0.t ; RV32-NEXT: vand.vv v8, v8, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t ; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
▲ Show 20 Lines • Show All 130 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a1, 36(sp) ; RV32-NEXT: sw a1, 36(sp)
; RV32-NEXT: sw a1, 32(sp) ; RV32-NEXT: sw a1, 32(sp)
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: sw a1, 28(sp) ; RV32-NEXT: sw a1, 28(sp)
; RV32-NEXT: sw a1, 24(sp) ; RV32-NEXT: sw a1, 24(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vsll.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: addi a4, sp, 48 ; RV32-NEXT: addi a4, sp, 48
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v0, v24, a4 ; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsll.vi v0, v16, 24
; RV32-NEXT: addi a5, sp, 16 ; RV32-NEXT: addi a5, sp, 16
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero ; RV32-NEXT: vlse64.v v16, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: addi a5, sp, 48 ; RV32-NEXT: addi a5, sp, 48
; RV32-NEXT: vl8r.v v0, (a5) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a5) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vsrl.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vand.vv v24, v8, v24 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: addi a1, sp, 48 ; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: addi a1, sp, 40 ; RV32-NEXT: addi a1, sp, 40
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a1), zero ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
▲ Show 20 Lines • Show All 512 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll

Show First 20 Lines • Show All 342 Lines • ▼ Show 20 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a0 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vlse64.v v11, (a3), zero
; RV32-NEXT: vand.vx v10, v10, a2 ; RV32-NEXT: vand.vx v10, v10, a2
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsrl.vi v10, v8, 8 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vand.vv v10, v10, v11 ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vsrl.vi v12, v8, 24 ; RV32-NEXT: vlse64.v v11, (a3), zero
; RV32-NEXT: lui a3, 4080 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vand.vx v10, v10, a3
; RV32-NEXT: vor.vv v10, v10, v12 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: vand.vv v12, v12, v11
; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsll.vx v10, v8, a0 ; RV32-NEXT: vsll.vx v10, v8, a0
; RV32-NEXT: vand.vx v12, v8, a2 ; RV32-NEXT: vand.vx v12, v8, a2
; RV32-NEXT: vsll.vx v12, v12, a1 ; RV32-NEXT: vsll.vx v12, v12, a1
; RV32-NEXT: vor.vv v10, v10, v12 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vand.vx v12, v8, a3 ; RV32-NEXT: vand.vx v12, v8, a3
; RV32-NEXT: vsll.vi v12, v12, 24 ; RV32-NEXT: vsll.vi v12, v12, 24
; RV32-NEXT: vand.vv v8, v8, v11 ; RV32-NEXT: vand.vv v8, v8, v11
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv1i64: ; RV64-LABEL: bswap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; RV64-NEXT: vand.vx v9, v8, a0 ; RV64-NEXT: vsrl.vx v9, v8, a0
; RV64-NEXT: vsll.vi v9, v9, 24 ; RV64-NEXT: li a1, 40
; RV64-NEXT: li a1, 255 ; RV64-NEXT: vsrl.vx v10, v8, a1
; RV64-NEXT: slli a1, a1, 24 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: vand.vx v10, v8, a1 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vsll.vi v10, v10, 8 ; RV64-NEXT: vand.vx v10, v10, a2
; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: li a2, 56
; RV64-NEXT: vsll.vx v10, v8, a2
; RV64-NEXT: lui a3, 16
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: vand.vx v11, v8, a3
; RV64-NEXT: li a4, 40
; RV64-NEXT: vsll.vx v11, v11, a4
; RV64-NEXT: vor.vv v10, v10, v11
; RV64-NEXT: vor.vv v9, v10, v9 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vsrl.vx v10, v8, a2 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vsrl.vx v11, v8, a4 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v11, v11, a3 ; RV64-NEXT: vand.vx v10, v10, a3
; RV64-NEXT: vsrl.vi v11, v8, 8
; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v11, v11, a4
; RV64-NEXT: vor.vv v10, v11, v10 ; RV64-NEXT: vor.vv v10, v11, v10
; RV64-NEXT: vsrl.vi v11, v8, 24 ; RV64-NEXT: vor.vv v9, v10, v9
; RV64-NEXT: vand.vx v11, v11, a0 ; RV64-NEXT: vand.vx v10, v8, a3
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsll.vi v10, v10, 24
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vand.vx v11, v8, a4
; RV64-NEXT: vor.vv v8, v8, v11 ; RV64-NEXT: vsll.vi v11, v11, 8
; RV64-NEXT: vor.vv v10, v10, v11
; RV64-NEXT: vsll.vx v11, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: vor.vv v8, v11, v8
; RV64-NEXT: vor.vv v8, v8, v10 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v9, v8 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: bswap_nxv1i64: ; CHECK-ZVBB-LABEL: bswap_nxv1i64:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vrev8.v v8, v8 ; CHECK-ZVBB-NEXT: vrev8.v v8, v8
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%a = call <vscale x 1 x i64> @llvm.bswap.nxv1i64(<vscale x 1 x i64> %va) %a = call <vscale x 1 x i64> @llvm.bswap.nxv1i64(<vscale x 1 x i64> %va)
Show All 11 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a0 ; RV32-NEXT: vsrl.vx v10, v8, a0
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vlse64.v v14, (a3), zero
; RV32-NEXT: vand.vx v12, v12, a2 ; RV32-NEXT: vand.vx v12, v12, a2
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: vand.vv v12, v12, v14 ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vlse64.v v14, (a3), zero
; RV32-NEXT: lui a3, 4080 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vand.vx v12, v12, a3
; RV32-NEXT: vor.vv v12, v12, v16 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vand.vv v16, v16, v14
; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v12, v8, a0 ; RV32-NEXT: vsll.vx v12, v8, a0
; RV32-NEXT: vand.vx v16, v8, a2 ; RV32-NEXT: vand.vx v16, v8, a2
; RV32-NEXT: vsll.vx v16, v16, a1 ; RV32-NEXT: vsll.vx v16, v16, a1
; RV32-NEXT: vor.vv v12, v12, v16 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vand.vx v16, v8, a3 ; RV32-NEXT: vand.vx v16, v8, a3
; RV32-NEXT: vsll.vi v16, v16, 24 ; RV32-NEXT: vsll.vi v16, v16, 24
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v14
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv2i64: ; RV64-LABEL: bswap_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; RV64-NEXT: vand.vx v10, v8, a0 ; RV64-NEXT: vsrl.vx v10, v8, a0
; RV64-NEXT: vsll.vi v10, v10, 24 ; RV64-NEXT: li a1, 40
; RV64-NEXT: li a1, 255 ; RV64-NEXT: vsrl.vx v12, v8, a1
; RV64-NEXT: slli a1, a1, 24 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: vand.vx v12, v8, a1 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vsll.vi v12, v12, 8 ; RV64-NEXT: vand.vx v12, v12, a2
; RV64-NEXT: vor.vv v10, v10, v12
; RV64-NEXT: li a2, 56
; RV64-NEXT: vsll.vx v12, v8, a2
; RV64-NEXT: lui a3, 16
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: vand.vx v14, v8, a3
; RV64-NEXT: li a4, 40
; RV64-NEXT: vsll.vx v14, v14, a4
; RV64-NEXT: vor.vv v12, v12, v14
; RV64-NEXT: vor.vv v10, v12, v10 ; RV64-NEXT: vor.vv v10, v12, v10
; RV64-NEXT: vsrl.vx v12, v8, a2 ; RV64-NEXT: vsrl.vi v12, v8, 24
; RV64-NEXT: vsrl.vx v14, v8, a4 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v14, v14, a3 ; RV64-NEXT: vand.vx v12, v12, a3
; RV64-NEXT: vsrl.vi v14, v8, 8
; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v14, v14, a4
; RV64-NEXT: vor.vv v12, v14, v12 ; RV64-NEXT: vor.vv v12, v14, v12
; RV64-NEXT: vsrl.vi v14, v8, 24 ; RV64-NEXT: vor.vv v10, v12, v10
; RV64-NEXT: vand.vx v14, v14, a0 ; RV64-NEXT: vand.vx v12, v8, a3
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsll.vi v12, v12, 24
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vand.vx v14, v8, a4
; RV64-NEXT: vor.vv v8, v8, v14 ; RV64-NEXT: vsll.vi v14, v14, 8
; RV64-NEXT: vor.vv v12, v12, v14
; RV64-NEXT: vsll.vx v14, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: vor.vv v8, v14, v8
; RV64-NEXT: vor.vv v8, v8, v12 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: vor.vv v8, v10, v8 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: bswap_nxv2i64: ; CHECK-ZVBB-LABEL: bswap_nxv2i64:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vrev8.v v8, v8 ; CHECK-ZVBB-NEXT: vrev8.v v8, v8
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%a = call <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64> %va) %a = call <vscale x 2 x i64> @llvm.bswap.nxv2i64(<vscale x 2 x i64> %va)
Show All 11 Lines
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a0 ; RV32-NEXT: vsrl.vx v12, v8, a0
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: vsrl.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vlse64.v v20, (a3), zero
; RV32-NEXT: vand.vx v16, v16, a2 ; RV32-NEXT: vand.vx v16, v16, a2
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vand.vv v16, v16, v20 ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vlse64.v v20, (a3), zero
; RV32-NEXT: lui a3, 4080 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v16, v16, a3
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v24, v24, v20
; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vx v16, v8, a0 ; RV32-NEXT: vsll.vx v16, v8, a0
; RV32-NEXT: vand.vx v24, v8, a2 ; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: vsll.vx v24, v24, a1 ; RV32-NEXT: vsll.vx v24, v24, a1
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vand.vx v24, v8, a3 ; RV32-NEXT: vand.vx v24, v8, a3
; RV32-NEXT: vsll.vi v24, v24, 24 ; RV32-NEXT: vsll.vi v24, v24, 24
; RV32-NEXT: vand.vv v8, v8, v20 ; RV32-NEXT: vand.vv v8, v8, v20
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv4i64: ; RV64-LABEL: bswap_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a0 ; RV64-NEXT: vsrl.vx v12, v8, a0
; RV64-NEXT: vsll.vi v12, v12, 24 ; RV64-NEXT: li a1, 40
; RV64-NEXT: li a1, 255 ; RV64-NEXT: vsrl.vx v16, v8, a1
; RV64-NEXT: slli a1, a1, 24 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: vand.vx v16, v8, a1 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vsll.vi v16, v16, 8 ; RV64-NEXT: vand.vx v16, v16, a2
; RV64-NEXT: vor.vv v12, v12, v16
; RV64-NEXT: li a2, 56
; RV64-NEXT: vsll.vx v16, v8, a2
; RV64-NEXT: lui a3, 16
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: vand.vx v20, v8, a3
; RV64-NEXT: li a4, 40
; RV64-NEXT: vsll.vx v20, v20, a4
; RV64-NEXT: vor.vv v16, v16, v20
; RV64-NEXT: vor.vv v12, v16, v12 ; RV64-NEXT: vor.vv v12, v16, v12
; RV64-NEXT: vsrl.vx v16, v8, a2 ; RV64-NEXT: vsrl.vi v16, v8, 24
; RV64-NEXT: vsrl.vx v20, v8, a4 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v20, v20, a3 ; RV64-NEXT: vand.vx v16, v16, a3
; RV64-NEXT: vsrl.vi v20, v8, 8
; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v20, v20, a4
; RV64-NEXT: vor.vv v16, v20, v16 ; RV64-NEXT: vor.vv v16, v20, v16
; RV64-NEXT: vsrl.vi v20, v8, 24 ; RV64-NEXT: vor.vv v12, v16, v12
; RV64-NEXT: vand.vx v20, v20, a0 ; RV64-NEXT: vand.vx v16, v8, a3
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsll.vi v16, v16, 24
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vand.vx v20, v8, a4
; RV64-NEXT: vor.vv v8, v8, v20 ; RV64-NEXT: vsll.vi v20, v20, 8
; RV64-NEXT: vor.vv v16, v16, v20
; RV64-NEXT: vsll.vx v20, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: vor.vv v8, v20, v8
; RV64-NEXT: vor.vv v8, v8, v16 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: vor.vv v8, v12, v8 ; RV64-NEXT: vor.vv v8, v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: bswap_nxv4i64: ; CHECK-ZVBB-LABEL: bswap_nxv4i64:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vrev8.v v8, v8 ; CHECK-ZVBB-NEXT: vrev8.v v8, v8
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%a = call <vscale x 4 x i64> @llvm.bswap.nxv4i64(<vscale x 4 x i64> %va) %a = call <vscale x 4 x i64> @llvm.bswap.nxv4i64(<vscale x 4 x i64> %va)
Show All 10 Lines
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: sub sp, sp, a0 ; RV32-NEXT: sub sp, sp, a0
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a0, 1044480 ; RV32-NEXT: lui a0, 1044480
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: li a0, 56 ; RV32-NEXT: li a0, 56
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v24, v8, a0 ; RV32-NEXT: vsrl.vx v16, v8, a0
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: vsrl.vx v0, v8, a1 ; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: addi a3, sp, 8 ; RV32-NEXT: vand.vx v24, v24, a2
; RV32-NEXT: vlse64.v v16, (a3), zero ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: addi a3, sp, 16 ; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v0, v8, 8 ; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: vand.vv v0, v0, v16 ; RV32-NEXT: addi a3, sp, 8
; RV32-NEXT: vlse64.v v24, (a3), zero
; RV32-NEXT: lui a3, 4080 ; RV32-NEXT: lui a3, 4080
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vand.vx v0, v0, a3
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a2 ; RV32-NEXT: vand.vx v0, v8, a2
; RV32-NEXT: vsll.vx v0, v0, a1 ; RV32-NEXT: vsll.vx v0, v0, a1
; RV32-NEXT: vsll.vx v24, v8, a0 ; RV32-NEXT: vsll.vx v16, v8, a0
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v24
; RV32-NEXT: vand.vx v8, v8, a3 ; RV32-NEXT: vand.vx v8, v8, a3
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_nxv8i64: ; RV64-LABEL: bswap_nxv8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, 4080 ; RV64-NEXT: li a0, 56
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vand.vx v16, v8, a0 ; RV64-NEXT: vsrl.vx v16, v8, a0
; RV64-NEXT: vsll.vi v16, v16, 24 ; RV64-NEXT: li a1, 40
; RV64-NEXT: li a1, 255 ; RV64-NEXT: vsrl.vx v24, v8, a1
; RV64-NEXT: slli a1, a1, 24 ; RV64-NEXT: lui a2, 16
; RV64-NEXT: vand.vx v24, v8, a1 ; RV64-NEXT: addiw a2, a2, -256
; RV64-NEXT: vsll.vi v24, v24, 8 ; RV64-NEXT: vand.vx v24, v24, a2
; RV64-NEXT: vor.vv v16, v16, v24
; RV64-NEXT: li a2, 56
; RV64-NEXT: vsll.vx v24, v8, a2
; RV64-NEXT: lui a3, 16
; RV64-NEXT: addiw a3, a3, -256
; RV64-NEXT: vand.vx v0, v8, a3
; RV64-NEXT: li a4, 40
; RV64-NEXT: vsll.vx v0, v0, a4
; RV64-NEXT: vor.vv v24, v24, v0
; RV64-NEXT: vor.vv v16, v24, v16 ; RV64-NEXT: vor.vv v16, v24, v16
; RV64-NEXT: vsrl.vx v24, v8, a2 ; RV64-NEXT: vsrl.vi v24, v8, 24
; RV64-NEXT: vsrl.vx v0, v8, a4 ; RV64-NEXT: lui a3, 4080
; RV64-NEXT: vand.vx v0, v0, a3 ; RV64-NEXT: vand.vx v24, v24, a3
; RV64-NEXT: vsrl.vi v0, v8, 8
; RV64-NEXT: li a4, 255
; RV64-NEXT: slli a4, a4, 24
; RV64-NEXT: vand.vx v0, v0, a4
; RV64-NEXT: vor.vv v24, v0, v24 ; RV64-NEXT: vor.vv v24, v0, v24
; RV64-NEXT: vsrl.vi v0, v8, 24 ; RV64-NEXT: vor.vv v16, v24, v16
; RV64-NEXT: vand.vx v0, v0, a0 ; RV64-NEXT: vand.vx v24, v8, a3
; RV64-NEXT: vsrl.vi v8, v8, 8 ; RV64-NEXT: vsll.vi v24, v24, 24
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vand.vx v0, v8, a4
; RV64-NEXT: vor.vv v8, v8, v0 ; RV64-NEXT: vsll.vi v0, v0, 8
; RV64-NEXT: vor.vv v24, v24, v0
; RV64-NEXT: vsll.vx v0, v8, a0
; RV64-NEXT: vand.vx v8, v8, a2
; RV64-NEXT: vsll.vx v8, v8, a1
; RV64-NEXT: vor.vv v8, v0, v8
; RV64-NEXT: vor.vv v8, v8, v24 ; RV64-NEXT: vor.vv v8, v8, v24
; RV64-NEXT: vor.vv v8, v16, v8 ; RV64-NEXT: vor.vv v8, v8, v16
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: bswap_nxv8i64: ; CHECK-ZVBB-LABEL: bswap_nxv8i64:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vrev8.v v8, v8 ; CHECK-ZVBB-NEXT: vrev8.v v8, v8
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%a = call <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64> %va) %a = call <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64> %va)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64>) declare <vscale x 8 x i64> @llvm.bswap.nxv8i64(<vscale x 8 x i64>)

llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll

Show First 20 Lines • Show All 694 Lines • ▼ Show 20 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a1, v0.t ; RV32-NEXT: vsll.vx v9, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v10, v8, a2, v0.t
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v10, v10, a3, v0.t ; RV32-NEXT: vsll.vx v10, v10, a3, v0.t
; RV32-NEXT: vor.vv v9, v10, v9, v0.t ; RV32-NEXT: vor.vv v9, v9, v10, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v10, a4, v0.t ; RV32-NEXT: vand.vx v10, v8, a4, v0.t
; RV32-NEXT: vsrl.vi v11, v8, 8, v0.t ; RV32-NEXT: vsll.vi v10, v10, 24, v0.t
; RV32-NEXT: addi a5, sp, 8 ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v12, (a5), zero ; RV32-NEXT: vlse64.v v11, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v11, v11, v12, v0.t ; RV32-NEXT: vand.vv v12, v8, v11, v0.t
; RV32-NEXT: vor.vv v10, v11, v10, v0.t ; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
; RV32-NEXT: vor.vv v9, v10, v9, v0.t ; RV32-NEXT: vor.vv v10, v10, v12, v0.t
; RV32-NEXT: vsll.vx v10, v8, a1, v0.t ; RV32-NEXT: vor.vv v9, v9, v10, v0.t
; RV32-NEXT: vand.vx v11, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t
; RV32-NEXT: vsll.vx v11, v11, a2, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a3, v0.t
; RV32-NEXT: vor.vv v10, v10, v11, v0.t ; RV32-NEXT: vand.vx v12, v12, a2, v0.t
; RV32-NEXT: vand.vx v11, v8, a4, v0.t ; RV32-NEXT: vor.vv v10, v12, v10, v0.t
; RV32-NEXT: vsll.vi v11, v11, 24, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v12, v0.t ; RV32-NEXT: vand.vx v12, v12, a4, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v11, v8, v0.t ; RV32-NEXT: vand.vv v8, v8, v11, v0.t
; RV32-NEXT: vor.vv v8, v10, v8, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: vor.vv v8, v9, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv1i64: ; RV64-LABEL: vp_bswap_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vand.vx v9, v8, a1, v0.t ; RV64-NEXT: vand.vx v9, v8, a1, v0.t
Show All 39 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a1 ; RV32-NEXT: vsll.vx v9, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v10, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v10, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v10, v10, a3 ; RV32-NEXT: vsll.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v10, a4 ; RV32-NEXT: vand.vx v10, v8, a4
; RV32-NEXT: vsrl.vi v11, v8, 8 ; RV32-NEXT: vsll.vi v10, v10, 24
; RV32-NEXT: addi a5, sp, 8 ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v12, (a5), zero ; RV32-NEXT: vlse64.v v11, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v11, v11, v12 ; RV32-NEXT: vand.vv v12, v8, v11
; RV32-NEXT: vor.vv v10, v11, v10 ; RV32-NEXT: vsll.vi v12, v12, 8
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vsll.vx v10, v8, a1 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vand.vx v11, v8, a3 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: vsll.vx v11, v11, a2 ; RV32-NEXT: vsrl.vx v12, v8, a3
; RV32-NEXT: vor.vv v10, v10, v11 ; RV32-NEXT: vand.vx v12, v12, a2
; RV32-NEXT: vand.vx v11, v8, a4 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vi v11, v11, 24 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vx v12, v12, a4
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsrl.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v11, v8 ; RV32-NEXT: vand.vv v8, v8, v11
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv1i64_unmasked: ; RV64-LABEL: vp_bswap_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vand.vx v9, v8, a1 ; RV64-NEXT: vand.vx v9, v8, a1
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t ; RV32-NEXT: vsll.vx v10, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v12, v8, a2, v0.t ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v12, v8, a2, v0.t
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v12, v12, a3, v0.t ; RV32-NEXT: vsll.vx v12, v12, a3, v0.t
; RV32-NEXT: vor.vv v10, v12, v10, v0.t ; RV32-NEXT: vor.vv v10, v10, v12, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v12, v12, a4, v0.t ; RV32-NEXT: vand.vx v12, v8, a4, v0.t
; RV32-NEXT: vsrl.vi v14, v8, 8, v0.t ; RV32-NEXT: vsll.vi v12, v12, 24, v0.t
; RV32-NEXT: addi a5, sp, 8 ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m2, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v16, (a5), zero ; RV32-NEXT: vlse64.v v14, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v14, v14, v16, v0.t ; RV32-NEXT: vand.vv v16, v8, v14, v0.t
; RV32-NEXT: vor.vv v12, v14, v12, v0.t ; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: vor.vv v10, v12, v10, v0.t ; RV32-NEXT: vor.vv v12, v12, v16, v0.t
; RV32-NEXT: vsll.vx v12, v8, a1, v0.t ; RV32-NEXT: vor.vv v10, v10, v12, v0.t
; RV32-NEXT: vand.vx v14, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
; RV32-NEXT: vsll.vx v14, v14, a2, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
; RV32-NEXT: vor.vv v12, v12, v14, v0.t ; RV32-NEXT: vand.vx v16, v16, a2, v0.t
; RV32-NEXT: vand.vx v14, v8, a4, v0.t ; RV32-NEXT: vor.vv v12, v16, v12, v0.t
; RV32-NEXT: vsll.vi v14, v14, 24, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vx v16, v16, a4, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v14, v8, v0.t ; RV32-NEXT: vand.vv v8, v8, v14, v0.t
; RV32-NEXT: vor.vv v8, v12, v8, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: vor.vv v8, v8, v10, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vor.vv v8, v10, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv2i64: ; RV64-LABEL: vp_bswap_nxv2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vand.vx v10, v8, a1, v0.t ; RV64-NEXT: vand.vx v10, v8, a1, v0.t
Show All 39 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsll.vx v10, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v12, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v12, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vsll.vx v12, v12, a3
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v12, v12, a4 ; RV32-NEXT: vand.vx v12, v8, a4
; RV32-NEXT: vsrl.vi v14, v8, 8 ; RV32-NEXT: vsll.vi v12, v12, 24
; RV32-NEXT: addi a5, sp, 8 ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m2, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v16, (a5), zero ; RV32-NEXT: vlse64.v v14, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v14, v14, v16 ; RV32-NEXT: vand.vv v16, v8, v14
; RV32-NEXT: vor.vv v12, v14, v12 ; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vsll.vx v12, v8, a1 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vand.vx v14, v8, a3 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: vsll.vx v14, v14, a2 ; RV32-NEXT: vsrl.vx v16, v8, a3
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vand.vx v16, v16, a2
; RV32-NEXT: vand.vx v14, v8, a4 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vi v14, v14, 24 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsrl.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v14, v8 ; RV32-NEXT: vand.vv v8, v8, v14
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv2i64_unmasked: ; RV64-LABEL: vp_bswap_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vand.vx v10, v8, a1 ; RV64-NEXT: vand.vx v10, v8, a1
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t ; RV32-NEXT: vsll.vx v12, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v16, v8, a2, v0.t
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v16, v16, a3, v0.t ; RV32-NEXT: vsll.vx v16, v16, a3, v0.t
; RV32-NEXT: vor.vv v12, v16, v12, v0.t ; RV32-NEXT: vor.vv v16, v12, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v20, v16, a4, v0.t ; RV32-NEXT: vand.vx v12, v8, a4, v0.t
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t ; RV32-NEXT: vsll.vi v20, v12, 24, v0.t
; RV32-NEXT: addi a5, sp, 8 ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v16, (a5), zero ; RV32-NEXT: vlse64.v v12, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v24, v24, v16, v0.t ; RV32-NEXT: vand.vv v24, v8, v12, v0.t
; RV32-NEXT: vor.vv v20, v24, v20, v0.t ; RV32-NEXT: vsll.vi v24, v24, 8, v0.t
; RV32-NEXT: vor.vv v12, v20, v12, v0.t
; RV32-NEXT: vsll.vx v20, v8, a1, v0.t
; RV32-NEXT: vand.vx v24, v8, a3, v0.t
; RV32-NEXT: vsll.vx v24, v24, a2, v0.t
; RV32-NEXT: vor.vv v20, v20, v24, v0.t ; RV32-NEXT: vor.vv v20, v20, v24, v0.t
; RV32-NEXT: vand.vx v24, v8, a4, v0.t ; RV32-NEXT: vor.vv v16, v16, v20, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t ; RV32-NEXT: vsrl.vx v20, v8, a1, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vand.vx v24, v24, a2, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v20, v24, v20, v0.t
; RV32-NEXT: vor.vv v8, v20, v8, v0.t ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vand.vx v24, v24, a4, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: vand.vv v8, v8, v12, v0.t
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: vor.vv v8, v8, v20, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv4i64: ; RV64-LABEL: vp_bswap_nxv4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a1, v0.t ; RV64-NEXT: vand.vx v12, v8, a1, v0.t
Show All 39 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsll.vx v12, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v16, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vsll.vx v16, v16, a3
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4 ; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsrl.vi v20, v8, 8 ; RV32-NEXT: vsll.vi v16, v16, 24
; RV32-NEXT: addi a5, sp, 8 ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero ; RV32-NEXT: vlse64.v v20, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v20, v20, v24 ; RV32-NEXT: vand.vv v24, v8, v20
; RV32-NEXT: vor.vv v16, v20, v16 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vand.vx v20, v8, a3 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vsll.vx v20, v20, a2 ; RV32-NEXT: vsrl.vx v24, v8, a3
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vand.vx v24, v24, a2
; RV32-NEXT: vand.vx v20, v8, a4 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vsll.vi v20, v20, 24 ; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vx v24, v24, a4
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsrl.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v20, v8 ; RV32-NEXT: vand.vv v8, v8, v20
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv4i64_unmasked: ; RV64-LABEL: vp_bswap_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a1 ; RV64-NEXT: vand.vx v12, v8, a1
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v24, v8, a2, v0.t
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v24, v24, a3, v0.t ; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4, v0.t ; RV32-NEXT: vand.vx v16, v8, a4, v0.t
; RV32-NEXT: addi a5, sp, 16 ; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 4
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: addi a5, sp, 8 ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero ; RV32-NEXT: vlse64.v v16, (a5), zero
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 3 ; RV32-NEXT: slli a5, a5, 3
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16 ; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v24, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
; RV32-NEXT: vand.vx v16, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
; RV32-NEXT: vsll.vx v16, v16, a2, v0.t ; RV32-NEXT: vand.vx v16, v16, a2, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v16, v8, a4, v0.t ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t ; RV32-NEXT: vand.vx v24, v24, a4, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv7i64: ; RV64-LABEL: vp_bswap_nxv7i64:
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vsll.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v0, v24, a4 ; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsll.vi v0, v16, 24
; RV32-NEXT: addi a5, sp, 8 ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero ; RV32-NEXT: vlse64.v v16, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vsrl.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vand.vv v24, v8, v24 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv7i64_unmasked: ; RV64-LABEL: vp_bswap_nxv7i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsll.vx v16, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v24, v8, a2, v0.t
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v24, v24, a3, v0.t ; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4, v0.t ; RV32-NEXT: vand.vx v16, v8, a4, v0.t
; RV32-NEXT: addi a5, sp, 16 ; RV32-NEXT: vsll.vi v16, v16, 24, v0.t
; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 4
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: addi a5, sp, 8 ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero ; RV32-NEXT: vlse64.v v16, (a5), zero
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 3 ; RV32-NEXT: slli a5, a5, 3
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16 ; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v24, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
; RV32-NEXT: vand.vx v16, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t
; RV32-NEXT: vsll.vx v16, v16, a2, v0.t ; RV32-NEXT: vand.vx v16, v16, a2, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v16, v8, a4, v0.t ; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t ; RV32-NEXT: vand.vx v24, v24, a4, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv8i64: ; RV64-LABEL: vp_bswap_nxv8i64:
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v24, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vsll.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v0, v24, a4 ; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsll.vi v0, v16, 24
; RV32-NEXT: addi a5, sp, 8 ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero ; RV32-NEXT: vlse64.v v16, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vsrl.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v16, v16, v0 ; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vand.vv v24, v8, v24 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv8i64_unmasked: ; RV64-LABEL: vp_bswap_nxv8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Lines
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: lui a1, 1044480
; RV32-NEXT: sw a1, 8(sp) ; RV32-NEXT: sw a1, 8(sp)
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a1, v0.t ; RV32-NEXT: vsll.vx v9, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v10, v8, a2, v0.t ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v10, v8, a2, v0.t
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v10, v10, a3, v0.t ; RV32-NEXT: vsll.vx v10, v10, a3, v0.t
; RV32-NEXT: vor.vv v9, v10, v9, v0.t ; RV32-NEXT: vor.vv v9, v9, v10, v0.t
; RV32-NEXT: vsrl.vi v10, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v10, a4, v0.t ; RV32-NEXT: vand.vx v10, v8, a4, v0.t
; RV32-NEXT: vsrl.vi v11, v8, 8, v0.t ; RV32-NEXT: vsll.vi v10, v10, 24, v0.t
; RV32-NEXT: addi a5, sp, 8 ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v12, (a5), zero ; RV32-NEXT: vlse64.v v11, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v11, v11, v12, v0.t ; RV32-NEXT: vand.vv v12, v8, v11, v0.t
; RV32-NEXT: vor.vv v10, v11, v10, v0.t ; RV32-NEXT: vsll.vi v12, v12, 8, v0.t
; RV32-NEXT: vor.vv v9, v10, v9, v0.t ; RV32-NEXT: vor.vv v10, v10, v12, v0.t
; RV32-NEXT: vsll.vx v10, v8, a1, v0.t ; RV32-NEXT: vor.vv v9, v9, v10, v0.t
; RV32-NEXT: vand.vx v11, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t
; RV32-NEXT: vsll.vx v11, v11, a2, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a3, v0.t
; RV32-NEXT: vor.vv v10, v10, v11, v0.t ; RV32-NEXT: vand.vx v12, v12, a2, v0.t
; RV32-NEXT: vand.vx v11, v8, a4, v0.t ; RV32-NEXT: vor.vv v10, v12, v10, v0.t
; RV32-NEXT: vsll.vi v11, v11, 24, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v12, v0.t ; RV32-NEXT: vand.vx v12, v12, a4, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v11, v8, v0.t ; RV32-NEXT: vand.vv v8, v8, v11, v0.t
; RV32-NEXT: vor.vv v8, v10, v8, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vor.vv v8, v8, v9, v0.t ; RV32-NEXT: vor.vv v8, v8, v10, v0.t
; RV32-NEXT: vor.vv v8, v9, v8, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 16, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 16, v0.t
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv1i48: ; RV64-LABEL: vp_bswap_nxv1i48:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
Show All 39 Lines

llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll

Show First 20 Lines • Show All 259 Lines • ▼ Show 20 Lines
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vadd.vv v8, v24, v8 ; CHECK-NEXT: vadd.vv v8, v24, v8
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vadd.vv v24, v8, v24 ; CHECK-NEXT: vadd.vv v8, v8, v24
; CHECK-NEXT: vadd.vv v8, v0, v16 ; CHECK-NEXT: vadd.vv v24, v0, v16
; CHECK-NEXT: vadd.vx v8, v8, a4 ; CHECK-NEXT: vadd.vx v16, v8, a4
; CHECK-NEXT: vadd.vx v16, v24, a4 ; CHECK-NEXT: vadd.vx v8, v24, a4
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = add <vscale x 32 x i32> %x, %y %r = add <vscale x 32 x i32> %x, %y
%s = add <vscale x 32 x i32> %r, %z %s = add <vscale x 32 x i32> %r, %z
%head = insertelement <vscale x 32 x i32> poison, i32 %w, i32 0 %head = insertelement <vscale x 32 x i32> poison, i32 %w, i32 0
▲ Show 20 Lines • Show All 345 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/cross-block-cse.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -O3 -mtriple=riscv64 -mattr=+v | FileCheck %s ; RUN: llc < %s -O3 -mtriple=riscv64 -mattr=+v | FileCheck %s
; TODO: The case below demonstrates a regression in cross block CSE of vector ; The case below demonstrates cross block CSE of vector instructions with
craig.topperUnsubmitted
Not Done
ReplyInline Actions

This TODO needs to be dropped

craig.topper: This TODO needs to be dropped
; instructions with undefined passthru operands. The second vadd.vv should be ; undefined passthru operands.
; removed.
define void @foo(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, ptr %p1, ptr %p2, i1 zeroext %cond) { define void @foo(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, ptr %p1, ptr %p2, i1 zeroext %cond) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
; CHECK-NEXT: vadd.vv v10, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vs1r.v v10, (a0) ; CHECK-NEXT: vs1r.v v8, (a0)
; CHECK-NEXT: bnez a2, .LBB0_2 ; CHECK-NEXT: bnez a2, .LBB0_2
; CHECK-NEXT: # %bb.1: # %falsebb ; CHECK-NEXT: # %bb.1: # %falsebb
; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vs1r.v v8, (a1) ; CHECK-NEXT: vs1r.v v8, (a1)
; CHECK-NEXT: .LBB0_2: # %mergebb ; CHECK-NEXT: .LBB0_2: # %mergebb
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = add <vscale x 2 x i32> %x, %y %a = add <vscale x 2 x i32> %x, %y
store <vscale x 2 x i32> %a, ptr %p1 store <vscale x 2 x i32> %a, ptr %p1
br i1 %cond, label %mergebb, label %falsebb br i1 %cond, label %mergebb, label %falsebb
falsebb: falsebb:
%b = add <vscale x 2 x i32> %x, %y %b = add <vscale x 2 x i32> %x, %y
store <vscale x 2 x i32> %b, ptr %p2 store <vscale x 2 x i32> %b, ptr %p2
br label %mergebb br label %mergebb
mergebb: mergebb:
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll

Show First 20 Lines • Show All 2,746 Lines • ▼ Show 20 Lines
declare <vscale x 16 x i64> @llvm.vp.ctpop.nxv16i64(<vscale x 16 x i64>, <vscale x 16 x i1>, i32) declare <vscale x 16 x i64> @llvm.vp.ctpop.nxv16i64(<vscale x 16 x i64>, <vscale x 16 x i1>, i32)
define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_ctpop_nxv16i64(<vscale x 16 x i64> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_ctpop_nxv16i64: ; RV32-LABEL: vp_ctpop_nxv16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -48 ; RV32-NEXT: addi sp, sp, -48
; RV32-NEXT: .cfi_def_cfa_offset 48 ; RV32-NEXT: .cfi_def_cfa_offset 48
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 56 ; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 56 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x30, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 48 * vlenb
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 48 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 48 ; RV32-NEXT: addi a1, a1, 48
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: srli a2, a1, 3 ; RV32-NEXT: srli a2, a1, 3
; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; RV32-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vx v24, v0, a2 ; RV32-NEXT: vslidedown.vx v0, v0, a2
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a2, 349525
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: sw a2, 44(sp) ; RV32-NEXT: sw a2, 44(sp)
; RV32-NEXT: sw a2, 40(sp) ; RV32-NEXT: sw a2, 40(sp)
; RV32-NEXT: lui a2, 209715 ; RV32-NEXT: lui a2, 209715
; RV32-NEXT: addi a2, a2, 819 ; RV32-NEXT: addi a2, a2, 819
; RV32-NEXT: sw a2, 36(sp) ; RV32-NEXT: sw a2, 36(sp)
; RV32-NEXT: sw a2, 32(sp) ; RV32-NEXT: sw a2, 32(sp)
; RV32-NEXT: lui a2, 61681 ; RV32-NEXT: lui a2, 61681
; RV32-NEXT: addi a2, a2, -241 ; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: sw a2, 28(sp) ; RV32-NEXT: sw a2, 28(sp)
; RV32-NEXT: sw a2, 24(sp) ; RV32-NEXT: sw a2, 24(sp)
; RV32-NEXT: lui a2, 4112 ; RV32-NEXT: lui a2, 4112
; RV32-NEXT: addi a2, a2, 257 ; RV32-NEXT: addi a2, a2, 257
; RV32-NEXT: sw a2, 20(sp) ; RV32-NEXT: sw a2, 20(sp)
; RV32-NEXT: sw a2, 16(sp) ; RV32-NEXT: sw a2, 16(sp)
; RV32-NEXT: mv a2, a0 ; RV32-NEXT: sub a2, a0, a1
; RV32-NEXT: bltu a0, a1, .LBB46_2 ; RV32-NEXT: sltu a3, a0, a2
craig.topperUnsubmitted
Not Done
ReplyInline Actions

I think I'm missing how this change comes from this patch. The sltu+addi+and looks like an optimized select lowering. The old code use a branch for the select. It looks to me like all of the changes for this patch should be after select lowering.

craig.topper: I think I'm missing how this change comes from this patch. The sltu+addi+and looks like an…
reamesAuthorUnsubmitted
Done
ReplyInline Actions

That is a very good question!

However, I think the answer is that it isn't actually select lowering, it's scheduling run slightly amuck. If you look quite a bit further down the test diff, you see what appears to be a select-to-branch conversion going in the other direction.

I think what we actually have here is a massive rescheduling. However, that would seem to require cross block scheduling, which too my knowledge, we don't have? So maybe I'm still confused?

reames: That is a very good question! However, I think the answer is that it isn't actually select…
craig.topperUnsubmitted
Not Done
ReplyInline Actions

I guess its just a scheduling difference due to the splitting. The select is further down on this side and the sltu is further down on the other side.

craig.topper: I guess its just a scheduling difference due to the splitting. The select is further down on…
; RV32-NEXT: # %bb.1: ; RV32-NEXT: addi a3, a3, -1
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: and a2, a3, a2
; RV32-NEXT: .LBB46_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v24, v16, 1, v0.t
; RV32-NEXT: addi a3, sp, 40
; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 40
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 48
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vlse64.v v8, (a3), zero
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 24 ; RV32-NEXT: li a4, 40
; RV32-NEXT: mul a3, a3, a4 ; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: addi a3, sp, 40
; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 40 ; RV32-NEXT: li a4, 40
; RV32-NEXT: mul a3, a3, a4 ; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5 ; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 40
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: addi a3, sp, 32 ; RV32-NEXT: addi a3, sp, 32
; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v8, (a3), zero ; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 40 ; RV32-NEXT: li a4, 40
; RV32-NEXT: mul a3, a3, a4 ; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vand.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5 ; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vl8r.v v16, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: li a4, 40
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v24, v24, 2, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5 ; RV32-NEXT: li a4, 40
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vl8r.v v16, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t ; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v16, v8, v16, v0.t ; RV32-NEXT: vadd.vv v16, v24, v16, v0.t
; RV32-NEXT: vsrl.vi v8, v16, 4, v0.t ; RV32-NEXT: vsrl.vi v24, v16, 4, v0.t
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t ; RV32-NEXT: vadd.vv v24, v16, v24, v0.t
; RV32-NEXT: addi a3, sp, 24 ; RV32-NEXT: addi a3, sp, 24
; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a3), zero ; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5 ; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vand.vv v24, v24, v16, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: addi a3, sp, 16 ; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a3), zero ; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: addi a3, sp, 48
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 48
; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vmul.vv v16, v24, v16, v0.t
; RV32-NEXT: li a2, 56 ; RV32-NEXT: li a2, 56
; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v8, v16, a2, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: sub a1, a0, a1 ; RV32-NEXT: bltu a0, a1, .LBB46_2
; RV32-NEXT: sltu a0, a0, a1 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: mv a0, a1
; RV32-NEXT: and a0, a0, a1 ; RV32-NEXT: .LBB46_2:
reamesAuthorUnsubmitted
Done
ReplyInline Actions

Here

reames: Here
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
; RV32-NEXT: addi a0, sp, 48 ; RV32-NEXT: addi a0, sp, 48
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: addi a0, sp, 48 ; RV32-NEXT: vsrl.vi v24, v8, 1, v0.t
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48 ; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48 ; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v8, v16, v0.t ; RV32-NEXT: vand.vv v24, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: vadd.vv v8, v24, v8, v0.t
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48 ; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48 ; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48 ; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 48 ; RV32-NEXT: addi sp, sp, 48
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_ctpop_nxv16i64: ; RV64-LABEL: vp_ctpop_nxv16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
} }
define <vscale x 16 x i64> @vp_ctpop_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) { define <vscale x 16 x i64> @vp_ctpop_nxv16i64_unmasked(<vscale x 16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctpop_nxv16i64_unmasked: ; RV32-LABEL: vp_ctpop_nxv16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -48 ; RV32-NEXT: addi sp, sp, -48
; RV32-NEXT: .cfi_def_cfa_offset 48 ; RV32-NEXT: .cfi_def_cfa_offset 48
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 40 * vlenb
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 5 ; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: addi a1, a1, 48 ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 32 * vlenb
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: sw a1, 44(sp) ; RV32-NEXT: sw a1, 44(sp)
; RV32-NEXT: sw a1, 40(sp) ; RV32-NEXT: sw a1, 40(sp)
; RV32-NEXT: lui a1, 209715 ; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819 ; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: sw a1, 36(sp) ; RV32-NEXT: sw a1, 36(sp)
; RV32-NEXT: sw a1, 32(sp) ; RV32-NEXT: sw a1, 32(sp)
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: sw a1, 28(sp) ; RV32-NEXT: sw a1, 28(sp)
; RV32-NEXT: sw a1, 24(sp) ; RV32-NEXT: sw a1, 24(sp)
; RV32-NEXT: lui a1, 4112 ; RV32-NEXT: lui a1, 4112
; RV32-NEXT: addi a2, a1, 257 ; RV32-NEXT: addi a1, a1, 257
; RV32-NEXT: sw a2, 20(sp) ; RV32-NEXT: sw a1, 20(sp)
; RV32-NEXT: sw a1, 16(sp)
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: sw a2, 16(sp) ; RV32-NEXT: sub a2, a0, a1
; RV32-NEXT: mv a2, a0 ; RV32-NEXT: sltu a3, a0, a2
; RV32-NEXT: bltu a0, a1, .LBB47_2 ; RV32-NEXT: addi a3, a3, -1
; RV32-NEXT: # %bb.1: ; RV32-NEXT: and a2, a3, a2
; RV32-NEXT: mv a2, a1
; RV32-NEXT: .LBB47_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v24, v16, 1
; RV32-NEXT: addi a3, sp, 40 ; RV32-NEXT: addi a3, sp, 40
; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a3), zero ; RV32-NEXT: vlse64.v v0, (a3), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 24 ; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4 ; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v0, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vand.vv v24, v24, v0
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vsub.vv v16, v16, v24
; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: addi a3, sp, 32 ; RV32-NEXT: addi a3, sp, 32
; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v0, (a3), zero ; RV32-NEXT: vlse64.v v0, (a3), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v0 ; RV32-NEXT: vand.vv v24, v16, v0
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v16, v16, 2
; RV32-NEXT: vand.vv v8, v8, v0 ; RV32-NEXT: vand.vv v16, v16, v0
; RV32-NEXT: vadd.vv v8, v16, v8 ; RV32-NEXT: vadd.vv v16, v24, v16
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v24, v16, 4
; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: vadd.vv v24, v16, v24
; RV32-NEXT: addi a3, sp, 24 ; RV32-NEXT: addi a3, sp, 24
; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a3), zero ; RV32-NEXT: vlse64.v v16, (a3), zero
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: addi a3, a3, 48
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vand.vv v16, v24, v16
; RV32-NEXT: vand.vv v16, v8, v16
; RV32-NEXT: addi a3, sp, 16 ; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a4, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v8, (a3), zero ; RV32-NEXT: vlse64.v v24, (a3), zero
; RV32-NEXT: addi a3, sp, 48
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v16, v16, v8 ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 48
; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vmul.vv v16, v16, v24
; RV32-NEXT: li a2, 56 ; RV32-NEXT: li a2, 56
; RV32-NEXT: vsrl.vx v8, v16, a2 ; RV32-NEXT: vsrl.vx v16, v16, a2
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: addi a3, sp, 48
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: bltu a0, a1, .LBB47_2
; RV32-NEXT: addi a3, a3, 48 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; RV32-NEXT: mv a0, a1
; RV32-NEXT: sub a1, a0, a1 ; RV32-NEXT: .LBB47_2:
; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48 ; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vsub.vv v16, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: vand.vv v8, v16, v0 ; RV32-NEXT: vand.vv v16, v8, v0
; RV32-NEXT: vsrl.vi v16, v16, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v16, v16, v0 ; RV32-NEXT: vand.vv v8, v8, v0
; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: vadd.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v16 ; RV32-NEXT: vadd.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48 ; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 48
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsrl.vx v16, v8, a2
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 48 ; RV32-NEXT: addi a0, a0, 48
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsrl.vx v8, v8, a2
; RV32-NEXT: addi a0, sp, 48
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 48 ; RV32-NEXT: addi sp, sp, 48
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_ctpop_nxv16i64_unmasked: ; RV64-LABEL: vp_ctpop_nxv16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: mv a2, a0 ; RV64-NEXT: mv a2, a0
▲ Show 20 Lines • Show All 144 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll

Show First 20 Lines • Show All 1,530 Lines • ▼ Show 20 Lines
; RV64I-NEXT: vmul.vx v8, v8, a0 ; RV64I-NEXT: vmul.vx v8, v8, a0
; RV64I-NEXT: li a0, 56 ; RV64I-NEXT: li a0, 56
; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32F-LABEL: cttz_nxv1i64: ; RV32F-LABEL: cttz_nxv1i64:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v9, v8, 0 ; RV32F-NEXT: vrsub.vi v9, v8, 0
; RV32F-NEXT: vand.vv v9, v8, v9 ; RV32F-NEXT: vand.vv v8, v8, v9
; RV32F-NEXT: fsrmi a0, 1 ; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v10, v9 ; RV32F-NEXT: vfncvt.f.xu.w v9, v8
; RV32F-NEXT: vsrl.vi v9, v10, 23 ; RV32F-NEXT: vsrl.vi v8, v9, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32F-NEXT: vzext.vf2 v10, v9 ; RV32F-NEXT: vzext.vf2 v9, v8
; RV32F-NEXT: li a1, 127 ; RV32F-NEXT: li a1, 127
; RV32F-NEXT: vsub.vx v9, v10, a1 ; RV32F-NEXT: vsub.vx v8, v9, a1
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: li a1, 64 ; RV32F-NEXT: li a1, 64
; RV32F-NEXT: vmerge.vxm v8, v9, a1, v0 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32F-NEXT: fsrm a0 ; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV64F-LABEL: cttz_nxv1i64: ; RV64F-LABEL: cttz_nxv1i64:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64F-NEXT: vrsub.vi v9, v8, 0 ; RV64F-NEXT: vrsub.vi v9, v8, 0
; RV64F-NEXT: vand.vv v9, v8, v9 ; RV64F-NEXT: vand.vv v9, v8, v9
Show All 9 Lines
; RV64F-NEXT: li a1, 64 ; RV64F-NEXT: li a1, 64
; RV64F-NEXT: vmerge.vxm v8, v9, a1, v0 ; RV64F-NEXT: vmerge.vxm v8, v9, a1, v0
; RV64F-NEXT: fsrm a0 ; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv1i64: ; RV32D-LABEL: cttz_nxv1i64:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v9, v8, 0 ; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v9, v8, v9 ; RV32D-NEXT: vand.vv v8, v8, v9
; RV32D-NEXT: fsrmi a0, 1 ; RV32D-NEXT: fsrmi a0, 1
; RV32D-NEXT: vfcvt.f.xu.v v9, v9 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
; RV32D-NEXT: li a1, 52 ; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v9, v9, a1 ; RV32D-NEXT: vsrl.vx v8, v8, a1
; RV32D-NEXT: li a1, 1023 ; RV32D-NEXT: li a1, 1023
; RV32D-NEXT: vsub.vx v9, v9, a1 ; RV32D-NEXT: vsub.vx v8, v8, a1
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: li a1, 64 ; RV32D-NEXT: li a1, 64
; RV32D-NEXT: vmerge.vxm v8, v9, a1, v0 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32D-NEXT: fsrm a0 ; RV32D-NEXT: fsrm a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv1i64: ; RV64D-LABEL: cttz_nxv1i64:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64D-NEXT: vrsub.vi v9, v8, 0 ; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v9, v8, v9 ; RV64D-NEXT: vand.vv v9, v8, v9
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; RV64I-NEXT: vmul.vx v8, v8, a0 ; RV64I-NEXT: vmul.vx v8, v8, a0
; RV64I-NEXT: li a0, 56 ; RV64I-NEXT: li a0, 56
; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32F-LABEL: cttz_nxv2i64: ; RV32F-LABEL: cttz_nxv2i64:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v10, v8, 0 ; RV32F-NEXT: vrsub.vi v10, v8, 0
; RV32F-NEXT: vand.vv v10, v8, v10 ; RV32F-NEXT: vand.vv v8, v8, v10
; RV32F-NEXT: fsrmi a0, 1 ; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v12, v10 ; RV32F-NEXT: vfncvt.f.xu.w v10, v8
; RV32F-NEXT: vsrl.vi v10, v12, 23 ; RV32F-NEXT: vsrl.vi v8, v10, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32F-NEXT: vzext.vf2 v12, v10 ; RV32F-NEXT: vzext.vf2 v10, v8
; RV32F-NEXT: li a1, 127 ; RV32F-NEXT: li a1, 127
; RV32F-NEXT: vsub.vx v10, v12, a1 ; RV32F-NEXT: vsub.vx v8, v10, a1
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: li a1, 64 ; RV32F-NEXT: li a1, 64
; RV32F-NEXT: vmerge.vxm v8, v10, a1, v0 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32F-NEXT: fsrm a0 ; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV64F-LABEL: cttz_nxv2i64: ; RV64F-LABEL: cttz_nxv2i64:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV64F-NEXT: vrsub.vi v10, v8, 0 ; RV64F-NEXT: vrsub.vi v10, v8, 0
; RV64F-NEXT: vand.vv v10, v8, v10 ; RV64F-NEXT: vand.vv v10, v8, v10
Show All 9 Lines
; RV64F-NEXT: li a1, 64 ; RV64F-NEXT: li a1, 64
; RV64F-NEXT: vmerge.vxm v8, v10, a1, v0 ; RV64F-NEXT: vmerge.vxm v8, v10, a1, v0
; RV64F-NEXT: fsrm a0 ; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv2i64: ; RV32D-LABEL: cttz_nxv2i64:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV32D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v10, v8, 0 ; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v10, v8, v10 ; RV32D-NEXT: vand.vv v8, v8, v10
; RV32D-NEXT: fsrmi a0, 1 ; RV32D-NEXT: fsrmi a0, 1
; RV32D-NEXT: vfcvt.f.xu.v v10, v10 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
; RV32D-NEXT: li a1, 52 ; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v10, v10, a1 ; RV32D-NEXT: vsrl.vx v8, v8, a1
; RV32D-NEXT: li a1, 1023 ; RV32D-NEXT: li a1, 1023
; RV32D-NEXT: vsub.vx v10, v10, a1 ; RV32D-NEXT: vsub.vx v8, v8, a1
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: li a1, 64 ; RV32D-NEXT: li a1, 64
; RV32D-NEXT: vmerge.vxm v8, v10, a1, v0 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32D-NEXT: fsrm a0 ; RV32D-NEXT: fsrm a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv2i64: ; RV64D-LABEL: cttz_nxv2i64:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV64D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV64D-NEXT: vrsub.vi v10, v8, 0 ; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v10, v8, v10 ; RV64D-NEXT: vand.vv v10, v8, v10
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; RV64I-NEXT: vmul.vx v8, v8, a0 ; RV64I-NEXT: vmul.vx v8, v8, a0
; RV64I-NEXT: li a0, 56 ; RV64I-NEXT: li a0, 56
; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32F-LABEL: cttz_nxv4i64: ; RV32F-LABEL: cttz_nxv4i64:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v12, v8, 0 ; RV32F-NEXT: vrsub.vi v12, v8, 0
; RV32F-NEXT: vand.vv v12, v8, v12 ; RV32F-NEXT: vand.vv v8, v8, v12
; RV32F-NEXT: fsrmi a0, 1 ; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v16, v12 ; RV32F-NEXT: vfncvt.f.xu.w v12, v8
; RV32F-NEXT: vsrl.vi v12, v16, 23 ; RV32F-NEXT: vsrl.vi v8, v12, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32F-NEXT: vzext.vf2 v16, v12 ; RV32F-NEXT: vzext.vf2 v12, v8
; RV32F-NEXT: li a1, 127 ; RV32F-NEXT: li a1, 127
; RV32F-NEXT: vsub.vx v12, v16, a1 ; RV32F-NEXT: vsub.vx v8, v12, a1
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: li a1, 64 ; RV32F-NEXT: li a1, 64
; RV32F-NEXT: vmerge.vxm v8, v12, a1, v0 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32F-NEXT: fsrm a0 ; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV64F-LABEL: cttz_nxv4i64: ; RV64F-LABEL: cttz_nxv4i64:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV64F-NEXT: vrsub.vi v12, v8, 0 ; RV64F-NEXT: vrsub.vi v12, v8, 0
; RV64F-NEXT: vand.vv v12, v8, v12 ; RV64F-NEXT: vand.vv v12, v8, v12
Show All 9 Lines
; RV64F-NEXT: li a1, 64 ; RV64F-NEXT: li a1, 64
; RV64F-NEXT: vmerge.vxm v8, v12, a1, v0 ; RV64F-NEXT: vmerge.vxm v8, v12, a1, v0
; RV64F-NEXT: fsrm a0 ; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv4i64: ; RV32D-LABEL: cttz_nxv4i64:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v12, v8, 0 ; RV32D-NEXT: vrsub.vi v12, v8, 0
; RV32D-NEXT: vand.vv v12, v8, v12 ; RV32D-NEXT: vand.vv v8, v8, v12
; RV32D-NEXT: fsrmi a0, 1 ; RV32D-NEXT: fsrmi a0, 1
; RV32D-NEXT: vfcvt.f.xu.v v12, v12 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
; RV32D-NEXT: li a1, 52 ; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v12, v12, a1 ; RV32D-NEXT: vsrl.vx v8, v8, a1
; RV32D-NEXT: li a1, 1023 ; RV32D-NEXT: li a1, 1023
; RV32D-NEXT: vsub.vx v12, v12, a1 ; RV32D-NEXT: vsub.vx v8, v8, a1
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: li a1, 64 ; RV32D-NEXT: li a1, 64
; RV32D-NEXT: vmerge.vxm v8, v12, a1, v0 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32D-NEXT: fsrm a0 ; RV32D-NEXT: fsrm a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv4i64: ; RV64D-LABEL: cttz_nxv4i64:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV64D-NEXT: vrsub.vi v12, v8, 0 ; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v12, v8, v12 ; RV64D-NEXT: vand.vv v12, v8, v12
▲ Show 20 Lines • Show All 105 Lines • ▼ Show 20 Lines
; RV64I-NEXT: vmul.vx v8, v8, a0 ; RV64I-NEXT: vmul.vx v8, v8, a0
; RV64I-NEXT: li a0, 56 ; RV64I-NEXT: li a0, 56
; RV64I-NEXT: vsrl.vx v8, v8, a0 ; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret ; RV64I-NEXT: ret
; ;
; RV32F-LABEL: cttz_nxv8i64: ; RV32F-LABEL: cttz_nxv8i64:
; RV32F: # %bb.0: ; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v16, v8, 0 ; RV32F-NEXT: vrsub.vi v16, v8, 0
; RV32F-NEXT: vand.vv v16, v8, v16 ; RV32F-NEXT: vand.vv v8, v8, v16
; RV32F-NEXT: fsrmi a0, 1 ; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v24, v16 ; RV32F-NEXT: vfncvt.f.xu.w v16, v8
; RV32F-NEXT: vsrl.vi v16, v24, 23 ; RV32F-NEXT: vsrl.vi v8, v16, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32F-NEXT: vzext.vf2 v24, v16 ; RV32F-NEXT: vzext.vf2 v16, v8
; RV32F-NEXT: li a1, 127 ; RV32F-NEXT: li a1, 127
; RV32F-NEXT: vsub.vx v16, v24, a1 ; RV32F-NEXT: vsub.vx v8, v16, a1
; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: li a1, 64 ; RV32F-NEXT: li a1, 64
; RV32F-NEXT: vmerge.vxm v8, v16, a1, v0 ; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32F-NEXT: fsrm a0 ; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret ; RV32F-NEXT: ret
; ;
; RV64F-LABEL: cttz_nxv8i64: ; RV64F-LABEL: cttz_nxv8i64:
; RV64F: # %bb.0: ; RV64F: # %bb.0:
; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64F-NEXT: vrsub.vi v16, v8, 0 ; RV64F-NEXT: vrsub.vi v16, v8, 0
; RV64F-NEXT: vand.vv v16, v8, v16 ; RV64F-NEXT: vand.vv v16, v8, v16
Show All 9 Lines
; RV64F-NEXT: li a1, 64 ; RV64F-NEXT: li a1, 64
; RV64F-NEXT: vmerge.vxm v8, v16, a1, v0 ; RV64F-NEXT: vmerge.vxm v8, v16, a1, v0
; RV64F-NEXT: fsrm a0 ; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret ; RV64F-NEXT: ret
; ;
; RV32D-LABEL: cttz_nxv8i64: ; RV32D-LABEL: cttz_nxv8i64:
; RV32D: # %bb.0: ; RV32D: # %bb.0:
; RV32D-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV32D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: vrsub.vi v16, v8, 0 ; RV32D-NEXT: vrsub.vi v16, v8, 0
; RV32D-NEXT: vand.vv v16, v8, v16 ; RV32D-NEXT: vand.vv v8, v8, v16
; RV32D-NEXT: fsrmi a0, 1 ; RV32D-NEXT: fsrmi a0, 1
; RV32D-NEXT: vfcvt.f.xu.v v16, v16 ; RV32D-NEXT: vfcvt.f.xu.v v8, v8
; RV32D-NEXT: li a1, 52 ; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v16, v16, a1 ; RV32D-NEXT: vsrl.vx v8, v8, a1
; RV32D-NEXT: li a1, 1023 ; RV32D-NEXT: li a1, 1023
; RV32D-NEXT: vsub.vx v16, v16, a1 ; RV32D-NEXT: vsub.vx v8, v8, a1
; RV32D-NEXT: vmseq.vx v0, v8, zero
; RV32D-NEXT: li a1, 64 ; RV32D-NEXT: li a1, 64
; RV32D-NEXT: vmerge.vxm v8, v16, a1, v0 ; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32D-NEXT: fsrm a0 ; RV32D-NEXT: fsrm a0
; RV32D-NEXT: ret ; RV32D-NEXT: ret
; ;
; RV64D-LABEL: cttz_nxv8i64: ; RV64D-LABEL: cttz_nxv8i64:
; RV64D: # %bb.0: ; RV64D: # %bb.0:
; RV64D-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV64D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64D-NEXT: vrsub.vi v16, v8, 0 ; RV64D-NEXT: vrsub.vi v16, v8, 0
; RV64D-NEXT: vand.vv v16, v8, v16 ; RV64D-NEXT: vand.vv v16, v8, v16
▲ Show 20 Lines • Show All 1,868 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
; RV32-NEXT: vl8r.v v24, (a0) ; RV32-NEXT: vl8r.v v24, (a0)
; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-NEXT: vmseq.vi v8, v16, 0 ; RV32-NEXT: vmseq.vi v8, v16, 0
; RV32-NEXT: vmseq.vi v0, v24, 0 ; RV32-NEXT: vmseq.vi v0, v24, 0
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: vmerge.vim v24, v16, 1, v0 ; RV32-NEXT: vmerge.vim v24, v16, 1, v0
; RV32-NEXT: vs8r.v v24, (a3) ; RV32-NEXT: vs8r.v v24, (a3)
; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: vmv1r.v v0, v8 ; RV32-NEXT: vmv1r.v v0, v8
; RV32-NEXT: vmerge.vim v8, v16, 1, v0 ; RV32-NEXT: vmerge.vim v8, v16, 1, v0
; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: vs8r.v v8, (a2) ; RV32-NEXT: vs8r.v v8, (a2)
; RV32-NEXT: lbu a0, 0(a1) ; RV32-NEXT: lbu a0, 0(a1)
; RV32-NEXT: addi sp, s0, -80 ; RV32-NEXT: addi sp, s0, -80
; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload ; RV32-NEXT: lw ra, 76(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload ; RV32-NEXT: lw s0, 72(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 80 ; RV32-NEXT: addi sp, sp, 80
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
Show All 21 Lines
; RV64-NEXT: vl8r.v v24, (a0) ; RV64-NEXT: vl8r.v v24, (a0)
; RV64-NEXT: add a1, a3, a1 ; RV64-NEXT: add a1, a3, a1
; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-NEXT: vmseq.vi v8, v16, 0 ; RV64-NEXT: vmseq.vi v8, v16, 0
; RV64-NEXT: vmseq.vi v0, v24, 0 ; RV64-NEXT: vmseq.vi v0, v24, 0
; RV64-NEXT: vmv.v.i v16, 0 ; RV64-NEXT: vmv.v.i v16, 0
; RV64-NEXT: vmerge.vim v24, v16, 1, v0 ; RV64-NEXT: vmerge.vim v24, v16, 1, v0
; RV64-NEXT: vs8r.v v24, (a3) ; RV64-NEXT: vs8r.v v24, (a3)
; RV64-NEXT: add a2, a3, a2
; RV64-NEXT: vmv1r.v v0, v8 ; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vmerge.vim v8, v16, 1, v0 ; RV64-NEXT: vmerge.vim v8, v16, 1, v0
; RV64-NEXT: add a2, a3, a2
; RV64-NEXT: vs8r.v v8, (a2) ; RV64-NEXT: vs8r.v v8, (a2)
; RV64-NEXT: lbu a0, 0(a1) ; RV64-NEXT: lbu a0, 0(a1)
; RV64-NEXT: addi sp, s0, -80 ; RV64-NEXT: addi sp, s0, -80
; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload ; RV64-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 80 ; RV64-NEXT: addi sp, sp, 80
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <vscale x 128 x i8>, <vscale x 128 x i8>* %x %a = load <vscale x 128 x i8>, <vscale x 128 x i8>* %x
▲ Show 20 Lines • Show All 109 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

Show First 20 Lines • Show All 593 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret i64 %r ret i64 %r
} }
define i64 @extractelt_nxv1i64_imm(<vscale x 1 x i64> %v) { define i64 @extractelt_nxv1i64_imm(<vscale x 1 x i64> %v) {
; CHECK-LABEL: extractelt_nxv1i64_imm: ; CHECK-LABEL: extractelt_nxv1i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsrl.vx v9, v8, a0
; CHECK-NEXT: vmv.x.s a1, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 1 x i64> %v, i32 2 %r = extractelement <vscale x 1 x i64> %v, i32 2
ret i64 %r ret i64 %r
} }
define i64 @extractelt_nxv1i64_idx(<vscale x 1 x i64> %v, i32 %idx) { define i64 @extractelt_nxv1i64_idx(<vscale x 1 x i64> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv1i64_idx: ; CHECK-LABEL: extractelt_nxv1i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 21 Lines; CHECK-NEXT: ret
ret i64 %r ret i64 %r
} }
define i64 @extractelt_nxv2i64_imm(<vscale x 2 x i64> %v) { define i64 @extractelt_nxv2i64_imm(<vscale x 2 x i64> %v) {
; CHECK-LABEL: extractelt_nxv2i64_imm: ; CHECK-LABEL: extractelt_nxv2i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsrl.vx v10, v8, a0
; CHECK-NEXT: vmv.x.s a1, v10
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 2 x i64> %v, i32 2 %r = extractelement <vscale x 2 x i64> %v, i32 2
ret i64 %r ret i64 %r
} }
define i64 @extractelt_nxv2i64_idx(<vscale x 2 x i64> %v, i32 %idx) { define i64 @extractelt_nxv2i64_idx(<vscale x 2 x i64> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv2i64_idx: ; CHECK-LABEL: extractelt_nxv2i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 21 Lines; CHECK-NEXT: ret
ret i64 %r ret i64 %r
} }
define i64 @extractelt_nxv4i64_imm(<vscale x 4 x i64> %v) { define i64 @extractelt_nxv4i64_imm(<vscale x 4 x i64> %v) {
; CHECK-LABEL: extractelt_nxv4i64_imm: ; CHECK-LABEL: extractelt_nxv4i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e64, m4, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsrl.vx v12, v8, a0
; CHECK-NEXT: vmv.x.s a1, v12
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 4 x i64> %v, i32 2 %r = extractelement <vscale x 4 x i64> %v, i32 2
ret i64 %r ret i64 %r
} }
define i64 @extractelt_nxv4i64_idx(<vscale x 4 x i64> %v, i32 %idx) { define i64 @extractelt_nxv4i64_idx(<vscale x 4 x i64> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv4i64_idx: ; CHECK-LABEL: extractelt_nxv4i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 21 Lines; CHECK-NEXT: ret
ret i64 %r ret i64 %r
} }
define i64 @extractelt_nxv8i64_imm(<vscale x 8 x i64> %v) { define i64 @extractelt_nxv8i64_imm(<vscale x 8 x i64> %v) {
; CHECK-LABEL: extractelt_nxv8i64_imm: ; CHECK-LABEL: extractelt_nxv8i64_imm:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslidedown.vi v8, v8, 2
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsrl.vx v16, v8, a0
; CHECK-NEXT: vmv.x.s a1, v16
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsrl.vx v8, v8, a1
; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 8 x i64> %v, i32 2 %r = extractelement <vscale x 8 x i64> %v, i32 2
ret i64 %r ret i64 %r
} }
define i64 @extractelt_nxv8i64_idx(<vscale x 8 x i64> %v, i32 %idx) { define i64 @extractelt_nxv8i64_idx(<vscale x 8 x i64> %v, i32 %idx) {
; CHECK-LABEL: extractelt_nxv8i64_idx: ; CHECK-LABEL: extractelt_nxv8i64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
▲ Show 20 Lines • Show All 215 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%r = extractelement <vscale x 32 x i32> %v, i32 %idx %r = extractelement <vscale x 32 x i32> %v, i32 %idx
ret i32 %r ret i32 %r
} }
define i64 @extractelt_nxv16i64_0(<vscale x 16 x i64> %v) { define i64 @extractelt_nxv16i64_0(<vscale x 16 x i64> %v) {
; CHECK-LABEL: extractelt_nxv16i64_0: ; CHECK-LABEL: extractelt_nxv16i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v16, v8, 1
; CHECK-NEXT: vmv.x.s a1, v16
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vmv.x.s a1, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = extractelement <vscale x 16 x i64> %v, i32 0 %r = extractelement <vscale x 16 x i64> %v, i32 0
ret i64 %r ret i64 %r
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Lines
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ELEN32-LABEL: bitcast_v8i8_i64: ; RV32ELEN32-LABEL: bitcast_v8i8_i64:
; RV32ELEN32: # %bb.0: ; RV32ELEN32: # %bb.0:
; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32ELEN32-NEXT: vslidedown.vi v9, v8, 1
; RV32ELEN32-NEXT: vmv.x.s a1, v9
; RV32ELEN32-NEXT: vmv.x.s a0, v8 ; RV32ELEN32-NEXT: vmv.x.s a0, v8
; RV32ELEN32-NEXT: vslidedown.vi v8, v8, 1
; RV32ELEN32-NEXT: vmv.x.s a1, v8
; RV32ELEN32-NEXT: ret ; RV32ELEN32-NEXT: ret
; ;
; RV64ELEN32-LABEL: bitcast_v8i8_i64: ; RV64ELEN32-LABEL: bitcast_v8i8_i64:
; RV64ELEN32: # %bb.0: ; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16 ; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16 ; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: addi a0, sp, 8 ; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV64ELEN32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
Show All 19 Lines
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ELEN32-LABEL: bitcast_v4i16_i64: ; RV32ELEN32-LABEL: bitcast_v4i16_i64:
; RV32ELEN32: # %bb.0: ; RV32ELEN32: # %bb.0:
; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32ELEN32-NEXT: vslidedown.vi v9, v8, 1
; RV32ELEN32-NEXT: vmv.x.s a1, v9
; RV32ELEN32-NEXT: vmv.x.s a0, v8 ; RV32ELEN32-NEXT: vmv.x.s a0, v8
; RV32ELEN32-NEXT: vslidedown.vi v8, v8, 1
; RV32ELEN32-NEXT: vmv.x.s a1, v8
; RV32ELEN32-NEXT: ret ; RV32ELEN32-NEXT: ret
; ;
; RV64ELEN32-LABEL: bitcast_v4i16_i64: ; RV64ELEN32-LABEL: bitcast_v4i16_i64:
; RV64ELEN32: # %bb.0: ; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16 ; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16 ; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: addi a0, sp, 8 ; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; RV64ELEN32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
Show All 19 Lines
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32ELEN32-LABEL: bitcast_v2i32_i64: ; RV32ELEN32-LABEL: bitcast_v2i32_i64:
; RV32ELEN32: # %bb.0: ; RV32ELEN32: # %bb.0:
; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32ELEN32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32ELEN32-NEXT: vslidedown.vi v9, v8, 1
; RV32ELEN32-NEXT: vmv.x.s a1, v9
; RV32ELEN32-NEXT: vmv.x.s a0, v8 ; RV32ELEN32-NEXT: vmv.x.s a0, v8
; RV32ELEN32-NEXT: vslidedown.vi v8, v8, 1
; RV32ELEN32-NEXT: vmv.x.s a1, v8
; RV32ELEN32-NEXT: ret ; RV32ELEN32-NEXT: ret
; ;
; RV64ELEN32-LABEL: bitcast_v2i32_i64: ; RV64ELEN32-LABEL: bitcast_v2i32_i64:
; RV64ELEN32: # %bb.0: ; RV64ELEN32: # %bb.0:
; RV64ELEN32-NEXT: addi sp, sp, -16 ; RV64ELEN32-NEXT: addi sp, sp, -16
; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16 ; RV64ELEN32-NEXT: .cfi_def_cfa_offset 16
; RV64ELEN32-NEXT: addi a0, sp, 8 ; RV64ELEN32-NEXT: addi a0, sp, 8
; RV64ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ELEN32-NEXT: vsetivli zero, 2, e32, m1, ta, ma
▲ Show 20 Lines • Show All 361 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll

Show First 20 Lines • Show All 1,390 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v11, v11, a3, v0.t ; RV32-NEXT: vand.vx v11, v11, a3, v0.t
; RV32-NEXT: vor.vv v10, v11, v10, v0.t ; RV32-NEXT: vor.vv v10, v11, v10, v0.t
; RV32-NEXT: vsrl.vi v11, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v11, v8, 8, v0.t
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v12, 0 ; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v12, v12, a4, v0 ; RV32-NEXT: vmerge.vxm v12, v12, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vmv1r.v v0, v9 ; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vand.vv v11, v11, v12, v0.t ; RV32-NEXT: vand.vv v11, v11, v12, v0.t
; RV32-NEXT: vsrl.vi v13, v8, 24, v0.t ; RV32-NEXT: vsrl.vi v13, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v13, v13, a4, v0.t ; RV32-NEXT: vand.vx v13, v13, a4, v0.t
▲ Show 20 Lines • Show All 115 Lines • ▼ Show 20 Lines
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vand.vx v10, v8, a2 ; RV32-NEXT: vand.vx v10, v8, a2
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vsll.vx v10, v10, a3 ; RV32-NEXT: vsll.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v8, a4 ; RV32-NEXT: vand.vx v10, v8, a4
; RV32-NEXT: vsll.vi v10, v10, 24 ; RV32-NEXT: vsll.vi v10, v10, 24
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v11, v11, a5, v0 ; RV32-NEXT: vmerge.vxm v11, v11, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v12, v8, v11 ; RV32-NEXT: vand.vv v12, v8, v11
; RV32-NEXT: vsll.vi v12, v12, 8 ; RV32-NEXT: vsll.vi v12, v12, 8
; RV32-NEXT: vor.vv v10, v10, v12 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsrl.vx v10, v8, a1
▲ Show 20 Lines • Show All 114 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v14, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v14, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v14, v14, a3, v0.t ; RV32-NEXT: vand.vx v14, v14, a3, v0.t
; RV32-NEXT: vor.vv v12, v14, v12, v0.t ; RV32-NEXT: vor.vv v12, v14, v12, v0.t
; RV32-NEXT: vsrl.vi v14, v8, 24, v0.t ; RV32-NEXT: vsrl.vi v14, v8, 8, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: li a4, 85
; RV32-NEXT: vand.vx v14, v14, a4, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: li a5, 85
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a4
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.i v18, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v18, v18, a5, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vmv1r.v v0, v10 ; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: vand.vv v16, v16, v18, v0.t ; RV32-NEXT: vand.vv v14, v14, v16, v0.t
; RV32-NEXT: vor.vv v14, v16, v14, v0.t ; RV32-NEXT: vsrl.vi v18, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v18, v18, a4, v0.t
; RV32-NEXT: vor.vv v14, v14, v18, v0.t
; RV32-NEXT: vor.vv v12, v14, v12, v0.t ; RV32-NEXT: vor.vv v12, v14, v12, v0.t
; RV32-NEXT: vsll.vx v14, v8, a1, v0.t ; RV32-NEXT: vsll.vx v14, v8, a1, v0.t
; RV32-NEXT: vand.vx v16, v8, a3, v0.t ; RV32-NEXT: vand.vx v18, v8, a3, v0.t
; RV32-NEXT: vsll.vx v16, v16, a2, v0.t ; RV32-NEXT: vsll.vx v18, v18, a2, v0.t
; RV32-NEXT: vor.vv v14, v14, v16, v0.t ; RV32-NEXT: vor.vv v14, v14, v18, v0.t
; RV32-NEXT: vand.vx v16, v8, a4, v0.t ; RV32-NEXT: vand.vx v18, v8, a4, v0.t
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t ; RV32-NEXT: vsll.vi v18, v18, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v18, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v18, v8, v0.t
; RV32-NEXT: vor.vv v8, v14, v8, v0.t ; RV32-NEXT: vor.vv v8, v14, v8, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v12, v8, 4, v0.t
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v14, a1 ; RV32-NEXT: vmv.v.x v14, a1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vp_bitreverse_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { define <4 x i64> @vp_bitreverse_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bitreverse_v4i64_unmasked: ; RV32-LABEL: vp_bitreverse_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsll.vx v10, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v12, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v12, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vsll.vx v12, v12, a3
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v12, v12, a4 ; RV32-NEXT: vand.vx v12, v8, a4
; RV32-NEXT: vsrl.vi v14, v8, 8 ; RV32-NEXT: vsll.vi v12, v12, 24
; RV32-NEXT: li a5, 85 ; RV32-NEXT: li a5, 85
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v14, 0
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v16, v16, a5, v0 ; RV32-NEXT: vmerge.vxm v14, v14, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v14, v14, v16 ; RV32-NEXT: vand.vv v16, v8, v14
; RV32-NEXT: vor.vv v12, v14, v12 ; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vsll.vx v12, v8, a1 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vand.vx v14, v8, a3 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: vsll.vx v14, v14, a2 ; RV32-NEXT: vsrl.vx v16, v8, a3
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vand.vx v16, v16, a2
; RV32-NEXT: vand.vx v14, v8, a4 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vi v14, v14, 24 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v14, v16, v14
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vor.vv v8, v14, v8 ; RV32-NEXT: vor.vv v8, v14, v8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vsrl.vi v10, v8, 4 ; RV32-NEXT: vsrl.vi v10, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a1 ; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v10, v10, v12 ; RV32-NEXT: vand.vv v10, v10, v12
; RV32-NEXT: vand.vv v8, v8, v12 ; RV32-NEXT: vand.vv v8, v8, v12
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v20, v20, a3, v0.t ; RV32-NEXT: vand.vx v20, v20, a3, v0.t
; RV32-NEXT: vor.vv v16, v20, v16, v0.t ; RV32-NEXT: vor.vv v20, v20, v16, v0.t
; RV32-NEXT: vsrl.vi v20, v8, 24, v0.t ; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 5
; RV32-NEXT: vand.vx v24, v20, a4, v0.t ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsrl.vi v28, v8, 8, v0.t
; RV32-NEXT: lui a5, 5
; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a4
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.i v20, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v20, v20, a5, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: vand.vv v28, v28, v20, v0.t ; RV32-NEXT: vand.vv v24, v24, v16, v0.t
; RV32-NEXT: vor.vv v24, v28, v24, v0.t ; RV32-NEXT: vsrl.vi v28, v8, 24, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v28, v28, a4, v0.t
; RV32-NEXT: vor.vv v24, v24, v28, v0.t
; RV32-NEXT: vor.vv v20, v24, v20, v0.t
; RV32-NEXT: vsll.vx v24, v8, a1, v0.t ; RV32-NEXT: vsll.vx v24, v8, a1, v0.t
; RV32-NEXT: vand.vx v28, v8, a3, v0.t ; RV32-NEXT: vand.vx v28, v8, a3, v0.t
; RV32-NEXT: vsll.vx v28, v28, a2, v0.t ; RV32-NEXT: vsll.vx v28, v28, a2, v0.t
; RV32-NEXT: vor.vv v24, v24, v28, v0.t ; RV32-NEXT: vor.vv v24, v24, v28, v0.t
; RV32-NEXT: vand.vx v28, v8, a4, v0.t ; RV32-NEXT: vand.vx v28, v8, a4, v0.t
; RV32-NEXT: vsll.vi v28, v28, 24, v0.t ; RV32-NEXT: vsll.vi v28, v28, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v20, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v28, v8, v0.t ; RV32-NEXT: vor.vv v8, v28, v8, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v8, v20, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.x v20, a1 ; RV32-NEXT: vmv.v.x v20, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v16, v16, v20, v0.t ; RV32-NEXT: vand.vv v16, v16, v20, v0.t
; RV32-NEXT: vand.vv v8, v8, v20, v0.t ; RV32-NEXT: vand.vv v8, v8, v20, v0.t
▲ Show 20 Lines • Show All 84 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vp_bitreverse_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { define <8 x i64> @vp_bitreverse_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bitreverse_v8i64_unmasked: ; RV32-LABEL: vp_bitreverse_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsll.vx v12, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v16, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vsll.vx v16, v16, a3
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4 ; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsrl.vi v20, v8, 8 ; RV32-NEXT: vsll.vi v16, v16, 24
; RV32-NEXT: lui a5, 5 ; RV32-NEXT: lui a5, 5
; RV32-NEXT: addi a5, a5, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.i v24, 0 ; RV32-NEXT: vmv.v.i v20, 0
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v24, v24, a5, v0 ; RV32-NEXT: vmerge.vxm v20, v20, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v20, v20, v24 ; RV32-NEXT: vand.vv v24, v8, v20
; RV32-NEXT: vor.vv v16, v20, v16 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vand.vx v20, v8, a3 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vsll.vx v20, v20, a2 ; RV32-NEXT: vsrl.vx v24, v8, a3
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vand.vx v24, v24, a2
; RV32-NEXT: vand.vx v20, v8, a4 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vsll.vi v20, v20, 24 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v20, v24, v20
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vor.vv v8, v20, v8 ; RV32-NEXT: vor.vv v8, v20, v8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vsrl.vi v12, v8, 4 ; RV32-NEXT: vsrl.vi v12, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.x v16, a1 ; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v12, v12, v16 ; RV32-NEXT: vand.vv v12, v12, v16
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
declare <15 x i64> @llvm.vp.bitreverse.v15i64(<15 x i64>, <15 x i1>, i32) declare <15 x i64> @llvm.vp.bitreverse.v15i64(<15 x i64>, <15 x i1>, i32)
define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { define <15 x i64> @vp_bitreverse_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_bitreverse_v15i64: ; RV32-LABEL: vp_bitreverse_v15i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 5 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: vmv1r.v v1, v0 ; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a3, 56 ; RV32-NEXT: li a3, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t ; RV32-NEXT: vsll.vx v24, v8, a3, v0.t
; RV32-NEXT: li a4, 40 ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t ; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a1, 16
; RV32-NEXT: addi a5, a1, -256 ; RV32-NEXT: addi a4, a1, -256
; RV32-NEXT: vand.vx v24, v24, a5, v0.t ; RV32-NEXT: vand.vx v24, v8, a4, v0.t
; RV32-NEXT: li a5, 40
; RV32-NEXT: vsll.vx v24, v24, a5, v0.t
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4 ; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: lui a6, 4080 ; RV32-NEXT: lui a6, 4080
; RV32-NEXT: vand.vx v24, v24, a6, v0.t ; RV32-NEXT: vand.vx v24, v8, a6, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a2, 349525
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vmv.v.i v24, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v24, a7, v0 ; RV32-NEXT: vmerge.vxm v24, v24, a7, v0
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: addi a7, sp, 16
; RV32-NEXT: li t0, 24 ; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill
; RV32-NEXT: mul a7, a7, t0
; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vs8r.v v16, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: addi a7, sp, 16 ; RV32-NEXT: vand.vv v16, v8, v24, v0.t
; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: li t0, 24
; RV32-NEXT: mul a7, a7, t0
; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v16, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 3 ; RV32-NEXT: slli a7, a7, 3
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 4 ; RV32-NEXT: slli a7, a7, 4
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v16, v24, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 4 ; RV32-NEXT: slli a7, a7, 4
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v16, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
; RV32-NEXT: vand.vx v24, v8, a5, v0.t
; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: vand.vx v24, v8, a6, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a5, v0.t
; RV32-NEXT: vand.vx v16, v24, a4, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 24 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t ; RV32-NEXT: vor.vv v24, v16, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV32-NEXT: vand.vx v8, v8, a6, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v8, v24, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v24, 4, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 4, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: lui a3, 61681 ; RV32-NEXT: lui a3, 61681
; RV32-NEXT: addi a3, a3, -241 ; RV32-NEXT: addi a3, a3, -241
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a3 ; RV32-NEXT: vmv.v.x v8, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t ; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
; RV32-NEXT: vor.vv v24, v16, v8, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: lui a3, 209715 ; RV32-NEXT: lui a3, 209715
; RV32-NEXT: addi a3, a3, 819 ; RV32-NEXT: addi a3, a3, 819
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a3 ; RV32-NEXT: vmv.v.x v8, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 2, v0.t ; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
; RV32-NEXT: vor.vv v24, v16, v8, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vsrl.vi v16, v24, 1, v0.t ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a2 ; RV32-NEXT: vmv.v.x v8, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t ; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bitreverse_v15i64: ; RV64-LABEL: vp_bitreverse_v15i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: li a4, 32 ; RV32-NEXT: li a4, 32
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: lui a5, 349525 ; RV32-NEXT: lui a5, 349525
; RV32-NEXT: addi a5, a5, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a6, 1044480
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: lui a6, 1044480
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a6, v0 ; RV32-NEXT: vmerge.vxm v24, v24, a6, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v0, v0, v24
; RV32-NEXT: lui a6, 4080 ; RV32-NEXT: lui a6, 4080
; RV32-NEXT: vsrl.vi v0, v8, 24 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vand.vx v0, v0, a6 ; RV32-NEXT: vand.vx v16, v16, a6
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v0, v16
; RV32-NEXT: addi a7, sp, 16 ; RV32-NEXT: addi a7, sp, 16
; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsll.vx v24, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v24
; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vand.vx v8, v8, a6 ; RV32-NEXT: vand.vx v8, v8, a6
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1 ; RV32-NEXT: vmv.v.x v24, a1
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
declare <16 x i64> @llvm.vp.bitreverse.v16i64(<16 x i64>, <16 x i1>, i32) declare <16 x i64> @llvm.vp.bitreverse.v16i64(<16 x i64>, <16 x i1>, i32)
define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vp_bitreverse_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_bitreverse_v16i64: ; RV32-LABEL: vp_bitreverse_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 5 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: vmv1r.v v1, v0 ; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a3, 56 ; RV32-NEXT: li a3, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a3, v0.t ; RV32-NEXT: vsll.vx v24, v8, a3, v0.t
; RV32-NEXT: li a4, 40 ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: vsrl.vx v24, v8, a4, v0.t ; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a1, 16
; RV32-NEXT: addi a5, a1, -256 ; RV32-NEXT: addi a4, a1, -256
; RV32-NEXT: vand.vx v24, v24, a5, v0.t ; RV32-NEXT: vand.vx v24, v8, a4, v0.t
; RV32-NEXT: li a5, 40
; RV32-NEXT: vsll.vx v24, v24, a5, v0.t
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 4 ; RV32-NEXT: slli a1, a1, 4
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: lui a6, 4080 ; RV32-NEXT: lui a6, 4080
; RV32-NEXT: vand.vx v24, v24, a6, v0.t ; RV32-NEXT: vand.vx v24, v8, a6, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: lui a2, 349525 ; RV32-NEXT: lui a2, 349525
; RV32-NEXT: addi a2, a2, 1365 ; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: vmv.v.i v24, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v24, a7, v0 ; RV32-NEXT: vmerge.vxm v24, v24, a7, v0
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: addi a7, sp, 16
; RV32-NEXT: li t0, 24 ; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill
; RV32-NEXT: mul a7, a7, t0
; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vs8r.v v16, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: addi a7, sp, 16 ; RV32-NEXT: vand.vv v16, v8, v24, v0.t
; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: li t0, 24
; RV32-NEXT: mul a7, a7, t0
; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v16, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 3 ; RV32-NEXT: slli a7, a7, 3
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 4 ; RV32-NEXT: slli a7, a7, 4
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v16, v24, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a7, vlenb ; RV32-NEXT: csrr a7, vlenb
; RV32-NEXT: slli a7, a7, 4 ; RV32-NEXT: slli a7, a7, 4
; RV32-NEXT: add a7, sp, a7 ; RV32-NEXT: add a7, sp, a7
; RV32-NEXT: addi a7, a7, 16 ; RV32-NEXT: addi a7, a7, 16
; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v16, v8, a3, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
; RV32-NEXT: vand.vx v24, v8, a5, v0.t
; RV32-NEXT: vsll.vx v24, v24, a4, v0.t
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: vand.vx v24, v8, a6, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a5, v0.t
; RV32-NEXT: vand.vx v16, v24, a4, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 24 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t ; RV32-NEXT: vor.vv v24, v16, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV32-NEXT: vand.vx v8, v8, a6, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v8, v24, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v24, 4, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 4, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: lui a3, 61681 ; RV32-NEXT: lui a3, 61681
; RV32-NEXT: addi a3, a3, -241 ; RV32-NEXT: addi a3, a3, -241
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a3 ; RV32-NEXT: vmv.v.x v8, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 4, v0.t ; RV32-NEXT: vsll.vi v8, v8, 4, v0.t
; RV32-NEXT: vor.vv v24, v16, v8, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vsrl.vi v16, v24, 2, v0.t ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: lui a3, 209715 ; RV32-NEXT: lui a3, 209715
; RV32-NEXT: addi a3, a3, 819 ; RV32-NEXT: addi a3, a3, 819
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a3 ; RV32-NEXT: vmv.v.x v8, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 2, v0.t ; RV32-NEXT: vsll.vi v8, v8, 2, v0.t
; RV32-NEXT: vor.vv v24, v16, v8, v0.t ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vsrl.vi v16, v24, 1, v0.t ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v24, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a2 ; RV32-NEXT: vmv.v.x v8, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v24, v8, v0.t ; RV32-NEXT: vand.vv v8, v24, v8, v0.t
; RV32-NEXT: vsll.vi v8, v8, 1, v0.t ; RV32-NEXT: vsll.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bitreverse_v16i64: ; RV64-LABEL: vp_bitreverse_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
▲ Show 20 Lines • Show All 88 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: li a4, 32 ; RV32-NEXT: li a4, 32
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: lui a5, 349525 ; RV32-NEXT: lui a5, 349525
; RV32-NEXT: addi a5, a5, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a6, 1044480
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: lui a6, 1044480
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a6, v0 ; RV32-NEXT: vmerge.vxm v24, v24, a6, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v0, v0, v24
; RV32-NEXT: lui a6, 4080 ; RV32-NEXT: lui a6, 4080
; RV32-NEXT: vsrl.vi v0, v8, 24 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vand.vx v0, v0, a6 ; RV32-NEXT: vand.vx v16, v16, a6
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v0, v16
; RV32-NEXT: addi a7, sp, 16 ; RV32-NEXT: addi a7, sp, 16
; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsll.vx v24, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v24
; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vand.vx v8, v8, a6 ; RV32-NEXT: vand.vx v8, v8, a6
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1 ; RV32-NEXT: vmv.v.x v24, a1
▲ Show 20 Lines • Show All 391 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

Show First 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vsrl.vi v9, v8, 8 ; RV32-NEXT: vsrl.vi v9, v8, 8
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a1, 16
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: addi a1, a1, -256
; RV32-NEXT: vand.vx v9, v9, a1 ; RV32-NEXT: vand.vx v9, v9, a1
; RV32-NEXT: vsrl.vi v10, v8, 24 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsll.vi v10, v8, 24 ; RV32-NEXT: vand.vx v10, v8, a1
; RV32-NEXT: vand.vx v8, v8, a1 ; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vsrl.vi v9, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vand.vx v9, v9, a1 ; RV32-NEXT: vand.vx v9, v9, a1
; RV32-NEXT: vand.vx v8, v8, a1 ; RV32-NEXT: vand.vx v8, v8, a1
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v9, v8 ; RV32-NEXT: vor.vv v8, v9, v8
Show All 19 Lines
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vsrl.vi v9, v8, 8 ; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a1, 16 ; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -256 ; RV64-NEXT: addiw a1, a1, -256
; RV64-NEXT: vand.vx v9, v9, a1 ; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10 ; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: vsll.vi v10, v8, 24 ; RV64-NEXT: vand.vx v10, v8, a1
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vsll.vi v8, v8, 8 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v10, v8 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vsrl.vi v9, v8, 4 ; RV64-NEXT: vsrl.vi v9, v8, 4
; RV64-NEXT: lui a1, 61681 ; RV64-NEXT: lui a1, 61681
; RV64-NEXT: addiw a1, a1, -241 ; RV64-NEXT: addiw a1, a1, -241
; RV64-NEXT: vand.vx v9, v9, a1 ; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vand.vx v8, v8, a1
; RV64-NEXT: vsll.vi v8, v8, 4 ; RV64-NEXT: vsll.vi v8, v8, 4
; RV64-NEXT: vor.vv v8, v9, v8 ; RV64-NEXT: vor.vv v8, v9, v8
Show All 29 Lines
} }
declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>) declare <4 x i32> @llvm.bitreverse.v4i32(<4 x i32>)
define void @bitreverse_v2i64(ptr %x, ptr %y) { define void @bitreverse_v2i64(ptr %x, ptr %y) {
; RV32-LABEL: bitreverse_v2i64: ; RV32-LABEL: bitreverse_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: li a1, 56
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vsrl.vx v9, v8, a1
; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v10, v8, a2
; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vmv.v.i v0, 5 ; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmerge.vxm v9, v9, a1, v0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v10, v10, a4, v0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 8 ; RV32-NEXT: vsrl.vi v11, v8, 8
; RV32-NEXT: vand.vv v10, v10, v9 ; RV32-NEXT: vand.vv v11, v11, v10
; RV32-NEXT: vsrl.vi v11, v8, 24 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: lui a1, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v11, v11, a1
; RV32-NEXT: vor.vv v10, v10, v11
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsrl.vx v11, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsrl.vx v12, v8, a3
; RV32-NEXT: lui a4, 16
; RV32-NEXT: addi a4, a4, -256
; RV32-NEXT: vand.vx v12, v12, a4 ; RV32-NEXT: vand.vx v12, v12, a4
; RV32-NEXT: vor.vv v11, v12, v11 ; RV32-NEXT: vor.vv v11, v11, v12
; RV32-NEXT: vor.vv v10, v10, v11
; RV32-NEXT: vand.vv v9, v8, v9
; RV32-NEXT: vsll.vi v9, v9, 8
; RV32-NEXT: vand.vx v11, v8, a1
; RV32-NEXT: vsll.vi v11, v11, 24
; RV32-NEXT: vor.vv v9, v11, v9 ; RV32-NEXT: vor.vv v9, v11, v9
; RV32-NEXT: vsll.vx v11, v8, a2 ; RV32-NEXT: vsll.vx v11, v8, a1
; RV32-NEXT: vand.vx v12, v8, a3
; RV32-NEXT: vsll.vx v12, v12, a2
; RV32-NEXT: vor.vv v11, v11, v12
; RV32-NEXT: vand.vv v10, v8, v10
; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vx v8, v8, a3 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v11, v8 ; RV32-NEXT: vor.vv v8, v11, v8
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vsrl.vi v9, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v10, a1 ; RV32-NEXT: vmv.v.x v10, a1
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vand.vv v9, v9, v10 ; RV32-NEXT: vand.vv v9, v9, v10
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
▲ Show 20 Lines • Show All 287 Lines • ▼ Show 20 Lines
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV32-NEXT: lui a1, 16 ; LMULMAX2-RV32-NEXT: lui a1, 16
; LMULMAX2-RV32-NEXT: addi a1, a1, -256 ; LMULMAX2-RV32-NEXT: addi a1, a1, -256
; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV32-NEXT: vor.vv v10, v10, v12 ; LMULMAX2-RV32-NEXT: vor.vv v10, v10, v12
; LMULMAX2-RV32-NEXT: vsll.vi v12, v8, 24 ; LMULMAX2-RV32-NEXT: vand.vx v12, v8, a1
; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV32-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8 ; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX2-RV32-NEXT: vor.vv v8, v12, v8 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241
; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4 ; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 4
; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8 ; LMULMAX2-RV32-NEXT: vor.vv v8, v10, v8
Show All 19 Lines
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV64-NEXT: lui a1, 16 ; LMULMAX2-RV64-NEXT: lui a1, 16
; LMULMAX2-RV64-NEXT: addiw a1, a1, -256 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -256
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12 ; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12
; LMULMAX2-RV64-NEXT: vsll.vi v12, v8, 24 ; LMULMAX2-RV64-NEXT: vand.vx v12, v8, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 8 ; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 24
; LMULMAX2-RV64-NEXT: vor.vv v8, v12, v8 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV64-NEXT: lui a1, 61681 ; LMULMAX2-RV64-NEXT: lui a1, 61681
; LMULMAX2-RV64-NEXT: addiw a1, a1, -241 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -241
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1
; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4 ; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 4
; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
Show All 21 Lines
; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV32-NEXT: lui a2, 16 ; LMULMAX1-RV32-NEXT: lui a2, 16
; LMULMAX1-RV32-NEXT: addi a2, a2, -256 ; LMULMAX1-RV32-NEXT: addi a2, a2, -256
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v8, 24 ; LMULMAX1-RV32-NEXT: vand.vx v11, v8, a2
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a2 ; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v8, v11, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV32-NEXT: lui a3, 61681 ; LMULMAX1-RV32-NEXT: lui a3, 61681
; LMULMAX1-RV32-NEXT: addi a3, a3, -241 ; LMULMAX1-RV32-NEXT: addi a3, a3, -241
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a3
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
Show All 10 Lines
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8 ; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v9, 24 ; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a2
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a2 ; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v9, v11, v9 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3 ; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a3
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 4 ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 4
; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 2
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a4
Show All 16 Lines
; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV64-NEXT: lui a2, 16 ; LMULMAX1-RV64-NEXT: lui a2, 16
; LMULMAX1-RV64-NEXT: addiw a2, a2, -256 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -256
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: vand.vx v11, v8, a2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a2 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 8 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v8, v11, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 4
; LMULMAX1-RV64-NEXT: lui a3, 61681 ; LMULMAX1-RV64-NEXT: lui a3, 61681
; LMULMAX1-RV64-NEXT: addiw a3, a3, -241 ; LMULMAX1-RV64-NEXT: addiw a3, a3, -241
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a3
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
Show All 10 Lines
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v8, v8
; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: vand.vx v11, v9, a2
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a2 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 8 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v9, v11, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 4
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a3
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3 ; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a3
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 4
; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v10, v9
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 2
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a4
Show All 32 Lines
; LMULMAX2-RV32-NEXT: li a1, 56 ; LMULMAX2-RV32-NEXT: li a1, 56
; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a1 ; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a1
; LMULMAX2-RV32-NEXT: li a2, 40 ; LMULMAX2-RV32-NEXT: li a2, 40
; LMULMAX2-RV32-NEXT: vsrl.vx v12, v8, a2 ; LMULMAX2-RV32-NEXT: vsrl.vx v12, v8, a2
; LMULMAX2-RV32-NEXT: lui a3, 16 ; LMULMAX2-RV32-NEXT: lui a3, 16
; LMULMAX2-RV32-NEXT: addi a3, a3, -256 ; LMULMAX2-RV32-NEXT: addi a3, a3, -256
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a3 ; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a3
; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10 ; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 8
; LMULMAX2-RV32-NEXT: li a4, 85 ; LMULMAX2-RV32-NEXT: li a4, 85
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a4 ; LMULMAX2-RV32-NEXT: vmv.v.x v0, a4
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0 ; LMULMAX2-RV32-NEXT: vmv.v.i v12, 0
; LMULMAX2-RV32-NEXT: lui a4, 1044480 ; LMULMAX2-RV32-NEXT: lui a4, 1044480
; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v14, a4, v0 ; LMULMAX2-RV32-NEXT: vmerge.vxm v12, v12, a4, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vand.vv v12, v12, v14 ; LMULMAX2-RV32-NEXT: vsrl.vi v14, v8, 8
; LMULMAX2-RV32-NEXT: vand.vv v14, v14, v12
; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 24 ; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 24
; LMULMAX2-RV32-NEXT: lui a4, 4080 ; LMULMAX2-RV32-NEXT: lui a4, 4080
; LMULMAX2-RV32-NEXT: vand.vx v16, v16, a4 ; LMULMAX2-RV32-NEXT: vand.vx v16, v16, a4
; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v16 ; LMULMAX2-RV32-NEXT: vor.vv v14, v14, v16
; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10 ; LMULMAX2-RV32-NEXT: vor.vv v10, v14, v10
; LMULMAX2-RV32-NEXT: vsll.vx v12, v8, a1 ; LMULMAX2-RV32-NEXT: vsll.vx v14, v8, a1
; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a3 ; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a3
; LMULMAX2-RV32-NEXT: vsll.vx v16, v16, a2 ; LMULMAX2-RV32-NEXT: vsll.vx v16, v16, a2
; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v16 ; LMULMAX2-RV32-NEXT: vor.vv v14, v14, v16
; LMULMAX2-RV32-NEXT: vand.vv v14, v8, v14 ; LMULMAX2-RV32-NEXT: vand.vv v12, v8, v12
; LMULMAX2-RV32-NEXT: vsll.vi v14, v14, 8 ; LMULMAX2-RV32-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a4 ; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a4
; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24 ; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v14 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vor.vv v8, v12, v8 ; LMULMAX2-RV32-NEXT: vor.vv v8, v14, v8
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4 ; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 4
; LMULMAX2-RV32-NEXT: lui a1, 61681 ; LMULMAX2-RV32-NEXT: lui a1, 61681
; LMULMAX2-RV32-NEXT: addi a1, a1, -241 ; LMULMAX2-RV32-NEXT: addi a1, a1, -241
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12 ; LMULMAX2-RV32-NEXT: vand.vv v10, v10, v12
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8 ; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v8
; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8 ; LMULMAX2-RV64-NEXT: vor.vv v8, v10, v8
; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: bitreverse_v4i64: ; LMULMAX1-RV32-LABEL: bitreverse_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle64.v v10, (a1) ; LMULMAX1-RV32-NEXT: vle64.v v10, (a1)
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: li a2, 56
; LMULMAX1-RV32-NEXT: vsrl.vx v9, v10, a2
; LMULMAX1-RV32-NEXT: li a3, 40
; LMULMAX1-RV32-NEXT: vsrl.vx v11, v10, a3
; LMULMAX1-RV32-NEXT: lui a4, 16
; LMULMAX1-RV32-NEXT: addi a4, a4, -256
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v9
; LMULMAX1-RV32-NEXT: vmv.v.i v0, 5
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0 ; LMULMAX1-RV32-NEXT: vmv.v.i v9, 0
; LMULMAX1-RV32-NEXT: vmv.v.i v0, 5 ; LMULMAX1-RV32-NEXT: lui a5, 1044480
; LMULMAX1-RV32-NEXT: lui a2, 1044480 ; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a5, v0
; LMULMAX1-RV32-NEXT: vmerge.vxm v9, v9, a2, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v10, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v12, v10, 8
; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v9 ; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v12, v10, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v13, v10, 24
; LMULMAX1-RV32-NEXT: lui a2, 4080 ; LMULMAX1-RV32-NEXT: lui a5, 4080
; LMULMAX1-RV32-NEXT: vand.vx v12, v12, a2
; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v12
; LMULMAX1-RV32-NEXT: li a3, 56
; LMULMAX1-RV32-NEXT: vsrl.vx v12, v10, a3
; LMULMAX1-RV32-NEXT: li a4, 40
; LMULMAX1-RV32-NEXT: vsrl.vx v13, v10, a4
; LMULMAX1-RV32-NEXT: lui a5, 16
; LMULMAX1-RV32-NEXT: addi a5, a5, -256
; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a5 ; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a5
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12 ; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v12 ; LMULMAX1-RV32-NEXT: vor.vv v11, v12, v11
; LMULMAX1-RV32-NEXT: vand.vv v12, v10, v9 ; LMULMAX1-RV32-NEXT: vsll.vx v12, v10, a2
; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 8 ; LMULMAX1-RV32-NEXT: vand.vx v13, v10, a4
; LMULMAX1-RV32-NEXT: vand.vx v13, v10, a2 ; LMULMAX1-RV32-NEXT: vsll.vx v13, v13, a3
; LMULMAX1-RV32-NEXT: vsll.vi v13, v13, 24 ; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12 ; LMULMAX1-RV32-NEXT: vand.vv v13, v10, v9
; LMULMAX1-RV32-NEXT: vsll.vx v13, v10, a3 ; LMULMAX1-RV32-NEXT: vsll.vi v13, v13, 8
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a5
; LMULMAX1-RV32-NEXT: vsll.vx v10, v10, a4 ; LMULMAX1-RV32-NEXT: vsll.vi v10, v10, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v13, v10 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v13
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v12 ; LMULMAX1-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v10, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v10, 4
; LMULMAX1-RV32-NEXT: lui a6, 61681 ; LMULMAX1-RV32-NEXT: lui a6, 61681
; LMULMAX1-RV32-NEXT: addi a6, a6, -241 ; LMULMAX1-RV32-NEXT: addi a6, a6, -241
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v12, a6 ; LMULMAX1-RV32-NEXT: vmv.v.x v12, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v12 ; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v12
Show All 15 Lines
; LMULMAX1-RV32-NEXT: addi a6, a6, 1365 ; LMULMAX1-RV32-NEXT: addi a6, a6, 1365
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.x v14, a6 ; LMULMAX1-RV32-NEXT: vmv.v.x v14, a6
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v14 ; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v14
; LMULMAX1-RV32-NEXT: vand.vv v10, v10, v14 ; LMULMAX1-RV32-NEXT: vand.vv v10, v10, v14
; LMULMAX1-RV32-NEXT: vadd.vv v10, v10, v10 ; LMULMAX1-RV32-NEXT: vadd.vv v10, v10, v10
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10 ; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 8 ; LMULMAX1-RV32-NEXT: vsrl.vx v11, v8, a2
; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v15, v8, 24
; LMULMAX1-RV32-NEXT: vand.vx v15, v15, a2
; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v15
; LMULMAX1-RV32-NEXT: vsrl.vx v15, v8, a3 ; LMULMAX1-RV32-NEXT: vsrl.vx v15, v8, a3
; LMULMAX1-RV32-NEXT: vsrl.vx v16, v8, a4 ; LMULMAX1-RV32-NEXT: vand.vx v15, v15, a4
; LMULMAX1-RV32-NEXT: vor.vv v11, v15, v11
; LMULMAX1-RV32-NEXT: vsrl.vi v15, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v15, v15, v9
; LMULMAX1-RV32-NEXT: vsrl.vi v16, v8, 24
; LMULMAX1-RV32-NEXT: vand.vx v16, v16, a5 ; LMULMAX1-RV32-NEXT: vand.vx v16, v16, a5
; LMULMAX1-RV32-NEXT: vor.vv v15, v16, v15 ; LMULMAX1-RV32-NEXT: vor.vv v15, v15, v16
; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v15 ; LMULMAX1-RV32-NEXT: vor.vv v11, v15, v11
; LMULMAX1-RV32-NEXT: vsll.vx v15, v8, a2
; LMULMAX1-RV32-NEXT: vand.vx v16, v8, a4
; LMULMAX1-RV32-NEXT: vsll.vx v16, v16, a3
; LMULMAX1-RV32-NEXT: vor.vv v15, v15, v16
; LMULMAX1-RV32-NEXT: vand.vv v9, v8, v9 ; LMULMAX1-RV32-NEXT: vand.vv v9, v8, v9
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 8
; LMULMAX1-RV32-NEXT: vand.vx v15, v8, a2
; LMULMAX1-RV32-NEXT: vsll.vi v15, v15, 24
; LMULMAX1-RV32-NEXT: vor.vv v9, v15, v9
; LMULMAX1-RV32-NEXT: vsll.vx v15, v8, a3
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a4 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v8, v15, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v9 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v9
; LMULMAX1-RV32-NEXT: vor.vv v8, v15, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 4
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v12 ; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v12 ; LMULMAX1-RV32-NEXT: vand.vv v8, v8, v12
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 4
; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v9, v8
; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2 ; LMULMAX1-RV32-NEXT: vsrl.vi v9, v8, 2
; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v13 ; LMULMAX1-RV32-NEXT: vand.vv v9, v9, v13
▲ Show 20 Lines • Show All 127 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll

Show First 20 Lines • Show All 430 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v10, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v11, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v11, v11, a3, v0.t ; RV32-NEXT: vand.vx v11, v11, a3, v0.t
; RV32-NEXT: vor.vv v10, v11, v10, v0.t ; RV32-NEXT: vor.vv v10, v11, v10, v0.t
; RV32-NEXT: vsrl.vi v11, v8, 8, v0.t ; RV32-NEXT: vsrl.vi v11, v8, 8, v0.t
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 5
lukeUnsubmitted
Not Done
ReplyInline Actions

Possible regression here. Are the NoRegs coming into the InsertVSETVLI pass?

luke: Possible regression here. Are the NoRegs coming into the InsertVSETVLI pass?
reamesAuthorUnsubmitted
Done
ReplyInline Actions

This turns out to be a known issue showing up in a slightly surprising way.

The cause is that InsertVSETVLI contains a peephole for VL=1 splats with tail undefined which is only applied in the forward direction - due to staleness issues.

The scheduling changes causing the two vmv.v.i instructions to be reordered. So previously the VL=4 e32 comes before the VL=1 e8. Afterward, the inverse order reaches InsertVSETVLI and the forward rule doesn't trigger.

The fix here would be to always apply peepholes in both directions, but that requires careful reasoning about working with stale MI. I'll think about that separately, but do not consider this a blocker for this patch.

reames: This turns out to be a known issue showing up in a slightly surprising way. The cause is that…
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v12, 0 ; RV32-NEXT: vmv.v.i v12, 0
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v12, v12, a4, v0 ; RV32-NEXT: vmerge.vxm v12, v12, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vmv1r.v v0, v9 ; RV32-NEXT: vmv1r.v v0, v9
; RV32-NEXT: vand.vv v11, v11, v12, v0.t ; RV32-NEXT: vand.vv v11, v11, v12, v0.t
; RV32-NEXT: vsrl.vi v13, v8, 24, v0.t ; RV32-NEXT: vsrl.vi v13, v8, 24, v0.t
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v13, v13, a0, v0.t ; RV32-NEXT: vand.vx v13, v13, a0, v0.t
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vand.vx v10, v8, a2 ; RV32-NEXT: vand.vx v10, v8, a2
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vsll.vx v10, v10, a3 ; RV32-NEXT: vsll.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v8, a4 ; RV32-NEXT: vand.vx v10, v8, a4
; RV32-NEXT: vsll.vi v10, v10, 24 ; RV32-NEXT: vsll.vi v10, v10, 24
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v11, v11, a5, v0 ; RV32-NEXT: vmerge.vxm v11, v11, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v12, v8, v11 ; RV32-NEXT: vand.vv v12, v8, v11
; RV32-NEXT: vsll.vi v12, v12, 8 ; RV32-NEXT: vsll.vi v12, v12, 8
; RV32-NEXT: vor.vv v10, v10, v12 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsrl.vx v10, v8, a1
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v12, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v14, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v14, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v14, v14, a3, v0.t ; RV32-NEXT: vand.vx v14, v14, a3, v0.t
; RV32-NEXT: vor.vv v12, v14, v12, v0.t ; RV32-NEXT: vor.vv v12, v14, v12, v0.t
; RV32-NEXT: vsrl.vi v14, v8, 24, v0.t ; RV32-NEXT: vsrl.vi v14, v8, 8, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: li a4, 85
; RV32-NEXT: vand.vx v14, v14, a4, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: li a5, 85
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a4
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.i v18, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v18, v18, a5, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vmv1r.v v0, v10 ; RV32-NEXT: vmv1r.v v0, v10
; RV32-NEXT: vand.vv v16, v16, v18, v0.t ; RV32-NEXT: vand.vv v14, v14, v16, v0.t
; RV32-NEXT: vor.vv v14, v16, v14, v0.t ; RV32-NEXT: vsrl.vi v18, v8, 24, v0.t
; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v18, v18, a0, v0.t
; RV32-NEXT: vor.vv v14, v14, v18, v0.t
; RV32-NEXT: vor.vv v12, v14, v12, v0.t ; RV32-NEXT: vor.vv v12, v14, v12, v0.t
; RV32-NEXT: vsll.vx v14, v8, a1, v0.t ; RV32-NEXT: vsll.vx v14, v8, a1, v0.t
; RV32-NEXT: vand.vx v16, v8, a3, v0.t ; RV32-NEXT: vand.vx v18, v8, a3, v0.t
; RV32-NEXT: vsll.vx v16, v16, a2, v0.t ; RV32-NEXT: vsll.vx v18, v18, a2, v0.t
; RV32-NEXT: vor.vv v14, v14, v16, v0.t ; RV32-NEXT: vor.vv v14, v14, v18, v0.t
; RV32-NEXT: vand.vx v16, v8, a4, v0.t ; RV32-NEXT: vand.vx v18, v8, a0, v0.t
; RV32-NEXT: vsll.vi v16, v16, 24, v0.t ; RV32-NEXT: vsll.vi v18, v18, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v18, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vor.vv v8, v18, v8, v0.t
; RV32-NEXT: vor.vv v8, v14, v8, v0.t ; RV32-NEXT: vor.vv v8, v14, v8, v0.t
; RV32-NEXT: vor.vv v8, v8, v12, v0.t ; RV32-NEXT: vor.vv v8, v8, v12, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v4i64: ; RV64-LABEL: vp_bswap_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
Show All 29 Lines; RV64-NEXT: ret
ret <4 x i64> %v ret <4 x i64> %v
} }
define <4 x i64> @vp_bswap_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { define <4 x i64> @vp_bswap_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_v4i64_unmasked: ; RV32-LABEL: vp_bswap_v4i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsll.vx v10, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v12, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v12, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vsll.vx v12, v12, a3
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v12, v12, a4 ; RV32-NEXT: vand.vx v12, v8, a4
; RV32-NEXT: vsrl.vi v14, v8, 8 ; RV32-NEXT: vsll.vi v12, v12, 24
; RV32-NEXT: li a5, 85 ; RV32-NEXT: li a5, 85
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v14, 0
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v16, v16, a5, v0 ; RV32-NEXT: vmerge.vxm v14, v14, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v14, v14, v16 ; RV32-NEXT: vand.vv v16, v8, v14
; RV32-NEXT: vor.vv v12, v14, v12 ; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vsll.vx v12, v8, a1 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vand.vx v14, v8, a3 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: vsll.vx v14, v14, a2 ; RV32-NEXT: vsrl.vx v16, v8, a3
; RV32-NEXT: vor.vv v12, v12, v14 ; RV32-NEXT: vand.vx v16, v16, a2
; RV32-NEXT: vand.vx v14, v8, a4 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vi v14, v14, 24 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v14, v16, v14
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vor.vv v8, v14, v8 ; RV32-NEXT: vor.vv v8, v14, v8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v4i64_unmasked: ; RV64-LABEL: vp_bswap_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV64-NEXT: vand.vx v10, v8, a1 ; RV64-NEXT: vand.vx v10, v8, a1
; RV64-NEXT: vsll.vi v10, v10, 24 ; RV64-NEXT: vsll.vi v10, v10, 24
Show All 38 Lines
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v20, v8, a2, v0.t
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v20, v20, a3, v0.t ; RV32-NEXT: vand.vx v20, v20, a3, v0.t
; RV32-NEXT: vor.vv v16, v20, v16, v0.t ; RV32-NEXT: vor.vv v20, v20, v16, v0.t
; RV32-NEXT: vsrl.vi v20, v8, 24, v0.t ; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 5
; RV32-NEXT: vand.vx v24, v20, a4, v0.t ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsrl.vi v28, v8, 8, v0.t
; RV32-NEXT: lui a5, 5
; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a4
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.i v20, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v20, v20, a5, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a4, v0
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: vand.vv v28, v28, v20, v0.t ; RV32-NEXT: vand.vv v24, v24, v16, v0.t
; RV32-NEXT: vor.vv v24, v28, v24, v0.t ; RV32-NEXT: vsrl.vi v28, v8, 24, v0.t
; RV32-NEXT: vor.vv v16, v24, v16, v0.t ; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v28, v28, a0, v0.t
; RV32-NEXT: vor.vv v24, v24, v28, v0.t
; RV32-NEXT: vor.vv v20, v24, v20, v0.t
; RV32-NEXT: vsll.vx v24, v8, a1, v0.t ; RV32-NEXT: vsll.vx v24, v8, a1, v0.t
; RV32-NEXT: vand.vx v28, v8, a3, v0.t ; RV32-NEXT: vand.vx v28, v8, a3, v0.t
; RV32-NEXT: vsll.vx v28, v28, a2, v0.t ; RV32-NEXT: vsll.vx v28, v28, a2, v0.t
; RV32-NEXT: vor.vv v24, v24, v28, v0.t ; RV32-NEXT: vor.vv v24, v24, v28, v0.t
; RV32-NEXT: vand.vx v28, v8, a4, v0.t ; RV32-NEXT: vand.vx v28, v8, a0, v0.t
; RV32-NEXT: vsll.vi v28, v28, 24, v0.t ; RV32-NEXT: vsll.vi v28, v28, 24, v0.t
; RV32-NEXT: vand.vv v8, v8, v20, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t ; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: vor.vv v8, v28, v8, v0.t ; RV32-NEXT: vor.vv v8, v28, v8, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v8, v20, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v8i64: ; RV64-LABEL: vp_bswap_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a1, v0.t ; RV64-NEXT: vand.vx v12, v8, a1, v0.t
; RV64-NEXT: vsll.vi v12, v12, 24, v0.t ; RV64-NEXT: vsll.vi v12, v12, 24, v0.t
Show All 27 Lines; RV64-NEXT: ret
ret <8 x i64> %v ret <8 x i64> %v
} }
define <8 x i64> @vp_bswap_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { define <8 x i64> @vp_bswap_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_v8i64_unmasked: ; RV32-LABEL: vp_bswap_v8i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsll.vx v12, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v16, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vsll.vx v16, v16, a3
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4 ; RV32-NEXT: vand.vx v16, v8, a4
; RV32-NEXT: vsrl.vi v20, v8, 8 ; RV32-NEXT: vsll.vi v16, v16, 24
; RV32-NEXT: lui a5, 5 ; RV32-NEXT: lui a5, 5
; RV32-NEXT: addi a5, a5, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.i v24, 0 ; RV32-NEXT: vmv.v.i v20, 0
; RV32-NEXT: lui a5, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v24, v24, a5, v0 ; RV32-NEXT: vmerge.vxm v20, v20, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v20, v20, v24 ; RV32-NEXT: vand.vv v24, v8, v20
; RV32-NEXT: vor.vv v16, v20, v16 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vand.vx v20, v8, a3 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: vsll.vx v20, v20, a2 ; RV32-NEXT: vsrl.vx v24, v8, a3
; RV32-NEXT: vor.vv v16, v16, v20 ; RV32-NEXT: vand.vx v24, v24, a2
; RV32-NEXT: vand.vx v20, v8, a4 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: vsll.vi v20, v20, 24 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v20, v24, v20
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vor.vv v8, v20, v8 ; RV32-NEXT: vor.vv v8, v20, v8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v8i64_unmasked: ; RV64-LABEL: vp_bswap_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a1 ; RV64-NEXT: vand.vx v12, v8, a1
; RV64-NEXT: vsll.vi v12, v12, 24 ; RV64-NEXT: vsll.vi v12, v12, 24
Show All 32 Lines
declare <15 x i64> @llvm.vp.bswap.v15i64(<15 x i64>, <15 x i1>, i32) declare <15 x i64> @llvm.vp.bswap.v15i64(<15 x i64>, <15 x i1>, i32)
define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { define <15 x i64> @vp_bswap_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_v15i64: ; RV32-LABEL: vp_bswap_v15i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 5 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: vmv1r.v v1, v0 ; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsll.vx v24, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t ; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vand.vx v24, v24, a3, v0.t ; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vand.vx v24, v8, a2, v0.t
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v24, (a4) # Unknown-size Folded Reload
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v24, v24, a4, v0.t ; RV32-NEXT: vand.vx v24, v8, a4, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 3 ; RV32-NEXT: slli a5, a5, 3
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16 ; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill
; RV32-NEXT: li a5, 32 ; RV32-NEXT: li a5, 32
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: addi a6, sp, 16
; RV32-NEXT: vs8r.v v24, (a6) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: lui a6, 349525 ; RV32-NEXT: lui a6, 349525
; RV32-NEXT: addi a6, a6, 1365 ; RV32-NEXT: addi a6, a6, 1365
; RV32-NEXT: vmv.v.i v24, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: vmv.v.x v0, a6 ; RV32-NEXT: vmv.v.x v0, a6
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v24, a7, v0 ; RV32-NEXT: vmerge.vxm v24, v24, a7, v0
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: addi a5, sp, 16
; RV32-NEXT: li a6, 24 ; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vand.vv v16, v8, v24, v0.t
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a0, a0, a5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v16, v24, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v16, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
; RV32-NEXT: vand.vx v24, v8, a3, v0.t
; RV32-NEXT: vsll.vx v24, v24, a2, v0.t
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: vand.vx v24, v8, a4, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
; RV32-NEXT: vand.vx v16, v24, a2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t ; RV32-NEXT: vor.vv v24, v16, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV32-NEXT: vand.vx v8, v8, a4, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v15i64: ; RV64-LABEL: vp_bswap_v15i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: li a4, 32 ; RV32-NEXT: li a4, 32
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: lui a5, 349525 ; RV32-NEXT: lui a5, 349525
; RV32-NEXT: addi a5, a5, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a6, 1044480
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a6, v0 ; RV32-NEXT: vmerge.vxm v24, v24, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v0, v0, v24
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vsrl.vi v0, v8, 24 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vand.vx v0, v0, a0 ; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v0, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsll.vx v24, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v24
; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vx v8, v8, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
Show All 39 Lines
declare <16 x i64> @llvm.vp.bswap.v16i64(<16 x i64>, <16 x i1>, i32) declare <16 x i64> @llvm.vp.bswap.v16i64(<16 x i64>, <16 x i1>, i32)
define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @vp_bswap_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_v16i64: ; RV32-LABEL: vp_bswap_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 5 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; RV32-NEXT: vmv1r.v v1, v0 ; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vx v16, v8, a1, v0.t ; RV32-NEXT: vsll.vx v24, v8, a1, v0.t
; RV32-NEXT: li a2, 40 ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vsrl.vx v24, v8, a2, v0.t ; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vand.vx v24, v24, a3, v0.t ; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; RV32-NEXT: lui a2, 16
; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: vand.vx v24, v8, a2, v0.t
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsll.vx v24, v24, a3, v0.t
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v24, (a4) # Unknown-size Folded Reload
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 3
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v16, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 24, v0.t
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v24, v24, a4, v0.t ; RV32-NEXT: vand.vx v24, v8, a4, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: slli a5, a5, 3 ; RV32-NEXT: slli a5, a5, 3
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16 ; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill
; RV32-NEXT: li a5, 32 ; RV32-NEXT: li a5, 32
; RV32-NEXT: vsrl.vi v24, v8, 8, v0.t
; RV32-NEXT: addi a6, sp, 16
; RV32-NEXT: vs8r.v v24, (a6) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: lui a6, 349525 ; RV32-NEXT: lui a6, 349525
; RV32-NEXT: addi a6, a6, 1365 ; RV32-NEXT: addi a6, a6, 1365
; RV32-NEXT: vmv.v.i v24, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a7, 1044480
; RV32-NEXT: vmv.v.x v0, a6 ; RV32-NEXT: vmv.v.x v0, a6
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v24, a7, v0 ; RV32-NEXT: vmerge.vxm v24, v24, a7, v0
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: addi a5, sp, 16
; RV32-NEXT: li a6, 24 ; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill
; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: vand.vv v16, v8, v24, v0.t
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vsll.vi v16, v16, 8, v0.t
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a0, a0, a5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v24, v0.t ; RV32-NEXT: vor.vv v16, v24, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v16, v24, v0.t ; RV32-NEXT: vor.vv v24, v24, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsll.vx v16, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v24, v8, a1, v0.t
; RV32-NEXT: vand.vx v24, v8, a3, v0.t
; RV32-NEXT: vsll.vx v24, v24, a2, v0.t
; RV32-NEXT: vor.vv v16, v16, v24, v0.t
; RV32-NEXT: vand.vx v24, v8, a4, v0.t
; RV32-NEXT: vsll.vi v24, v24, 24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v24, v8, a3, v0.t
; RV32-NEXT: vand.vx v16, v24, a2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v24, v0.t ; RV32-NEXT: vor.vv v24, v16, v24, v0.t
; RV32-NEXT: vsll.vi v8, v8, 8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 8, v0.t
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v16, v24, v0.t
; RV32-NEXT: vsrl.vi v8, v8, 24, v0.t
; RV32-NEXT: vand.vx v8, v8, a4, v0.t
; RV32-NEXT: vor.vv v8, v24, v8, v0.t ; RV32-NEXT: vor.vv v8, v24, v8, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v24, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v16i64: ; RV64-LABEL: vp_bswap_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: li a4, 32 ; RV32-NEXT: li a4, 32
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: lui a5, 349525 ; RV32-NEXT: lui a5, 349525
; RV32-NEXT: addi a5, a5, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a6, 1044480
; RV32-NEXT: vmv.v.x v0, a5 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a6, v0 ; RV32-NEXT: vmerge.vxm v24, v24, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v24, v16 ; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v0, v0, v24
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vsrl.vi v0, v8, 24 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: vand.vx v0, v0, a0 ; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v0, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsll.vx v24, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v24
; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vx v8, v8, a0
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
▲ Show 20 Lines • Show All 121 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

Show All 37 Lines
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vsrl.vi v9, v8, 8 ; RV32-NEXT: vsrl.vi v9, v8, 8
; RV32-NEXT: lui a1, 16 ; RV32-NEXT: lui a1, 16
; RV32-NEXT: addi a1, a1, -256 ; RV32-NEXT: addi a1, a1, -256
; RV32-NEXT: vand.vx v9, v9, a1 ; RV32-NEXT: vand.vx v9, v9, a1
; RV32-NEXT: vsrl.vi v10, v8, 24 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: vor.vv v9, v9, v10 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vsll.vi v10, v8, 24 ; RV32-NEXT: vand.vx v10, v8, a1
; RV32-NEXT: vand.vx v8, v8, a1 ; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: vse32.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_v4i32: ; RV64-LABEL: bswap_v4i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vsrl.vi v9, v8, 8 ; RV64-NEXT: vsrl.vi v9, v8, 8
; RV64-NEXT: lui a1, 16 ; RV64-NEXT: lui a1, 16
; RV64-NEXT: addiw a1, a1, -256 ; RV64-NEXT: addiw a1, a1, -256
; RV64-NEXT: vand.vx v9, v9, a1 ; RV64-NEXT: vand.vx v9, v9, a1
; RV64-NEXT: vsrl.vi v10, v8, 24 ; RV64-NEXT: vsrl.vi v10, v8, 24
; RV64-NEXT: vor.vv v9, v9, v10 ; RV64-NEXT: vor.vv v9, v9, v10
; RV64-NEXT: vsll.vi v10, v8, 24 ; RV64-NEXT: vand.vx v10, v8, a1
; RV64-NEXT: vand.vx v8, v8, a1 ; RV64-NEXT: vsll.vi v10, v10, 8
; RV64-NEXT: vsll.vi v8, v8, 8 ; RV64-NEXT: vsll.vi v8, v8, 24
; RV64-NEXT: vor.vv v8, v10, v8 ; RV64-NEXT: vor.vv v8, v8, v10
; RV64-NEXT: vor.vv v8, v8, v9 ; RV64-NEXT: vor.vv v8, v8, v9
; RV64-NEXT: vse32.v v8, (a0) ; RV64-NEXT: vse32.v v8, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; ZVBB-LABEL: bswap_v4i32: ; ZVBB-LABEL: bswap_v4i32:
; ZVBB: # %bb.0: ; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; ZVBB-NEXT: vle32.v v8, (a0) ; ZVBB-NEXT: vle32.v v8, (a0)
; ZVBB-NEXT: vrev8.v v8, v8 ; ZVBB-NEXT: vrev8.v v8, v8
; ZVBB-NEXT: vse32.v v8, (a0) ; ZVBB-NEXT: vse32.v v8, (a0)
; ZVBB-NEXT: ret ; ZVBB-NEXT: ret
%a = load <4 x i32>, ptr %x %a = load <4 x i32>, ptr %x
%b = load <4 x i32>, ptr %y %b = load <4 x i32>, ptr %y
%c = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %a) %c = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %a)
store <4 x i32> %c, ptr %x store <4 x i32> %c, ptr %x
ret void ret void
} }
declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
define void @bswap_v2i64(ptr %x, ptr %y) { define void @bswap_v2i64(ptr %x, ptr %y) {
; RV32-LABEL: bswap_v2i64: ; RV32-LABEL: bswap_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: li a1, 56
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vsrl.vx v9, v8, a1
; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v10, v8, a2
; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vmv.v.i v0, 5 ; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a1, 1044480 ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmerge.vxm v9, v9, a1, v0 ; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: lui a4, 1044480
; RV32-NEXT: vmerge.vxm v10, v10, a4, v0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v10, v8, 8 ; RV32-NEXT: vsrl.vi v11, v8, 8
; RV32-NEXT: vand.vv v10, v10, v9 ; RV32-NEXT: vand.vv v11, v11, v10
; RV32-NEXT: vsrl.vi v11, v8, 24 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: lui a1, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v11, v11, a1
; RV32-NEXT: vor.vv v10, v10, v11
; RV32-NEXT: li a2, 56
; RV32-NEXT: vsrl.vx v11, v8, a2
; RV32-NEXT: li a3, 40
; RV32-NEXT: vsrl.vx v12, v8, a3
; RV32-NEXT: lui a4, 16
; RV32-NEXT: addi a4, a4, -256
; RV32-NEXT: vand.vx v12, v12, a4 ; RV32-NEXT: vand.vx v12, v12, a4
; RV32-NEXT: vor.vv v11, v12, v11 ; RV32-NEXT: vor.vv v11, v11, v12
; RV32-NEXT: vor.vv v10, v10, v11
; RV32-NEXT: vand.vv v9, v8, v9
; RV32-NEXT: vsll.vi v9, v9, 8
; RV32-NEXT: vand.vx v11, v8, a1
; RV32-NEXT: vsll.vi v11, v11, 24
; RV32-NEXT: vor.vv v9, v11, v9 ; RV32-NEXT: vor.vv v9, v11, v9
; RV32-NEXT: vsll.vx v11, v8, a2 ; RV32-NEXT: vsll.vx v11, v8, a1
; RV32-NEXT: vand.vx v12, v8, a3
; RV32-NEXT: vsll.vx v12, v12, a2
; RV32-NEXT: vor.vv v11, v11, v12
; RV32-NEXT: vand.vv v10, v8, v10
; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vx v8, v8, a3 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v11, v8 ; RV32-NEXT: vor.vv v8, v11, v8
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bswap_v2i64: ; RV64-LABEL: bswap_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: li a1, 56 ; RV64-NEXT: li a1, 56
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX2-RV32-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV32-NEXT: lui a1, 16 ; LMULMAX2-RV32-NEXT: lui a1, 16
; LMULMAX2-RV32-NEXT: addi a1, a1, -256 ; LMULMAX2-RV32-NEXT: addi a1, a1, -256
; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV32-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV32-NEXT: vor.vv v10, v10, v12 ; LMULMAX2-RV32-NEXT: vor.vv v10, v10, v12
; LMULMAX2-RV32-NEXT: vsll.vi v12, v8, 24 ; LMULMAX2-RV32-NEXT: vand.vx v12, v8, a1
; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV32-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 8 ; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX2-RV32-NEXT: vor.vv v8, v12, v8 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: bswap_v8i32: ; LMULMAX2-RV64-LABEL: bswap_v8i32:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle32.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX2-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX2-RV64-NEXT: lui a1, 16 ; LMULMAX2-RV64-NEXT: lui a1, 16
; LMULMAX2-RV64-NEXT: addiw a1, a1, -256 ; LMULMAX2-RV64-NEXT: addiw a1, a1, -256
; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1 ; LMULMAX2-RV64-NEXT: vand.vx v10, v10, a1
; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24 ; LMULMAX2-RV64-NEXT: vsrl.vi v12, v8, 24
; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12 ; LMULMAX2-RV64-NEXT: vor.vv v10, v10, v12
; LMULMAX2-RV64-NEXT: vsll.vi v12, v8, 24 ; LMULMAX2-RV64-NEXT: vand.vx v12, v8, a1
; LMULMAX2-RV64-NEXT: vand.vx v8, v8, a1 ; LMULMAX2-RV64-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 8 ; LMULMAX2-RV64-NEXT: vsll.vi v8, v8, 24
; LMULMAX2-RV64-NEXT: vor.vv v8, v12, v8 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vse32.v v8, (a0) ; LMULMAX2-RV64-NEXT: vse32.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: bswap_v8i32: ; LMULMAX1-RV32-LABEL: bswap_v8i32:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV32-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV32-NEXT: lui a2, 16 ; LMULMAX1-RV32-NEXT: lui a2, 16
; LMULMAX1-RV32-NEXT: addi a2, a2, -256 ; LMULMAX1-RV32-NEXT: addi a2, a2, -256
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v8, 24 ; LMULMAX1-RV32-NEXT: vand.vx v11, v8, a2
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a2 ; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v8, v11, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v10, v9, 8
; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV32-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV32-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v9, 24 ; LMULMAX1-RV32-NEXT: vand.vx v11, v9, a2
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a2 ; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 8 ; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v9, v11, v9 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vse32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: bswap_v8i32: ; LMULMAX1-RV64-LABEL: bswap_v8i32:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle32.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v8, 8
; LMULMAX1-RV64-NEXT: lui a2, 16 ; LMULMAX1-RV64-NEXT: lui a2, 16
; LMULMAX1-RV64-NEXT: addiw a2, a2, -256 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -256
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v8, 24 ; LMULMAX1-RV64-NEXT: vand.vx v11, v8, a2
; LMULMAX1-RV64-NEXT: vand.vx v8, v8, a2 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 8 ; LMULMAX1-RV64-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV64-NEXT: vor.vv v8, v11, v8 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8 ; LMULMAX1-RV64-NEXT: vsrl.vi v10, v9, 8
; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2 ; LMULMAX1-RV64-NEXT: vand.vx v10, v10, a2
; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: vsrl.vi v11, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11 ; LMULMAX1-RV64-NEXT: vor.vv v10, v10, v11
; LMULMAX1-RV64-NEXT: vsll.vi v11, v9, 24 ; LMULMAX1-RV64-NEXT: vand.vx v11, v9, a2
; LMULMAX1-RV64-NEXT: vand.vx v9, v9, a2 ; LMULMAX1-RV64-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 8 ; LMULMAX1-RV64-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV64-NEXT: vor.vv v9, v11, v9 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10 ; LMULMAX1-RV64-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vse32.v v9, (a0) ; LMULMAX1-RV64-NEXT: vse32.v v9, (a0)
; LMULMAX1-RV64-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vse32.v v8, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
; ;
; ZVBB-LABEL: bswap_v8i32: ; ZVBB-LABEL: bswap_v8i32:
; ZVBB: # %bb.0: ; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; ZVBB-NEXT: vsetivli zero, 8, e32, m2, ta, ma
Show All 17 Lines
; LMULMAX2-RV32-NEXT: li a1, 56 ; LMULMAX2-RV32-NEXT: li a1, 56
; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a1 ; LMULMAX2-RV32-NEXT: vsrl.vx v10, v8, a1
; LMULMAX2-RV32-NEXT: li a2, 40 ; LMULMAX2-RV32-NEXT: li a2, 40
; LMULMAX2-RV32-NEXT: vsrl.vx v12, v8, a2 ; LMULMAX2-RV32-NEXT: vsrl.vx v12, v8, a2
; LMULMAX2-RV32-NEXT: lui a3, 16 ; LMULMAX2-RV32-NEXT: lui a3, 16
; LMULMAX2-RV32-NEXT: addi a3, a3, -256 ; LMULMAX2-RV32-NEXT: addi a3, a3, -256
; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a3 ; LMULMAX2-RV32-NEXT: vand.vx v12, v12, a3
; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10 ; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX2-RV32-NEXT: vsrl.vi v12, v8, 8
; LMULMAX2-RV32-NEXT: li a4, 85 ; LMULMAX2-RV32-NEXT: li a4, 85
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a4 ; LMULMAX2-RV32-NEXT: vmv.v.x v0, a4
; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0 ; LMULMAX2-RV32-NEXT: vmv.v.i v12, 0
; LMULMAX2-RV32-NEXT: lui a4, 1044480 ; LMULMAX2-RV32-NEXT: lui a4, 1044480
; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v14, a4, v0 ; LMULMAX2-RV32-NEXT: vmerge.vxm v12, v12, a4, v0
; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32-NEXT: vand.vv v12, v12, v14 ; LMULMAX2-RV32-NEXT: vsrl.vi v14, v8, 8
; LMULMAX2-RV32-NEXT: vand.vv v14, v14, v12
; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 24 ; LMULMAX2-RV32-NEXT: vsrl.vi v16, v8, 24
; LMULMAX2-RV32-NEXT: lui a4, 4080 ; LMULMAX2-RV32-NEXT: lui a4, 4080
; LMULMAX2-RV32-NEXT: vand.vx v16, v16, a4 ; LMULMAX2-RV32-NEXT: vand.vx v16, v16, a4
; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v16 ; LMULMAX2-RV32-NEXT: vor.vv v14, v14, v16
; LMULMAX2-RV32-NEXT: vor.vv v10, v12, v10 ; LMULMAX2-RV32-NEXT: vor.vv v10, v14, v10
; LMULMAX2-RV32-NEXT: vsll.vx v12, v8, a1 ; LMULMAX2-RV32-NEXT: vsll.vx v14, v8, a1
; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a3 ; LMULMAX2-RV32-NEXT: vand.vx v16, v8, a3
; LMULMAX2-RV32-NEXT: vsll.vx v16, v16, a2 ; LMULMAX2-RV32-NEXT: vsll.vx v16, v16, a2
; LMULMAX2-RV32-NEXT: vor.vv v12, v12, v16 ; LMULMAX2-RV32-NEXT: vor.vv v14, v14, v16
; LMULMAX2-RV32-NEXT: vand.vv v14, v8, v14 ; LMULMAX2-RV32-NEXT: vand.vv v12, v8, v12
; LMULMAX2-RV32-NEXT: vsll.vi v14, v14, 8 ; LMULMAX2-RV32-NEXT: vsll.vi v12, v12, 8
; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a4 ; LMULMAX2-RV32-NEXT: vand.vx v8, v8, a4
; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24 ; LMULMAX2-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v14 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vor.vv v8, v12, v8 ; LMULMAX2-RV32-NEXT: vor.vv v8, v14, v8
; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: bswap_v4i64: ; LMULMAX2-RV64-LABEL: bswap_v4i64:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
Show All 26 Lines
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: vor.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: bswap_v4i64: ; LMULMAX1-RV32-LABEL: bswap_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle64.v v9, (a1) ; LMULMAX1-RV32-NEXT: vle64.v v8, (a1)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vle64.v v9, (a0)
; LMULMAX1-RV32-NEXT: vmv.v.i v10, 0 ; LMULMAX1-RV32-NEXT: li a2, 56
; LMULMAX1-RV32-NEXT: vsrl.vx v10, v8, a2
; LMULMAX1-RV32-NEXT: li a3, 40
; LMULMAX1-RV32-NEXT: vsrl.vx v11, v8, a3
; LMULMAX1-RV32-NEXT: lui a4, 16
; LMULMAX1-RV32-NEXT: addi a4, a4, -256
; LMULMAX1-RV32-NEXT: vand.vx v11, v11, a4
; LMULMAX1-RV32-NEXT: vor.vv v10, v11, v10
; LMULMAX1-RV32-NEXT: vmv.v.i v0, 5 ; LMULMAX1-RV32-NEXT: vmv.v.i v0, 5
; LMULMAX1-RV32-NEXT: lui a2, 1044480 ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmerge.vxm v10, v10, a2, v0 ; LMULMAX1-RV32-NEXT: vmv.v.i v11, 0
; LMULMAX1-RV32-NEXT: lui a5, 1044480
; LMULMAX1-RV32-NEXT: vmerge.vxm v11, v11, a5, v0
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v9, 8 ; LMULMAX1-RV32-NEXT: vsrl.vi v12, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v10 ; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v11
; LMULMAX1-RV32-NEXT: vsrl.vi v12, v9, 24 ; LMULMAX1-RV32-NEXT: vsrl.vi v13, v8, 24
; LMULMAX1-RV32-NEXT: lui a2, 4080 ; LMULMAX1-RV32-NEXT: lui a5, 4080
; LMULMAX1-RV32-NEXT: vand.vx v12, v12, a2
; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v12
; LMULMAX1-RV32-NEXT: li a3, 56
; LMULMAX1-RV32-NEXT: vsrl.vx v12, v9, a3
; LMULMAX1-RV32-NEXT: li a4, 40
; LMULMAX1-RV32-NEXT: vsrl.vx v13, v9, a4
; LMULMAX1-RV32-NEXT: lui a5, 16
; LMULMAX1-RV32-NEXT: addi a5, a5, -256
; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a5
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v12
; LMULMAX1-RV32-NEXT: vand.vv v12, v9, v10
; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 8
; LMULMAX1-RV32-NEXT: vand.vx v13, v9, a2
; LMULMAX1-RV32-NEXT: vsll.vi v13, v13, 24
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12
; LMULMAX1-RV32-NEXT: vsll.vx v13, v9, a3
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV32-NEXT: vsll.vx v9, v9, a4
; LMULMAX1-RV32-NEXT: vor.vv v9, v13, v9
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vsrl.vi v11, v8, 8
; LMULMAX1-RV32-NEXT: vand.vv v11, v11, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v12, v8, 24
; LMULMAX1-RV32-NEXT: vand.vx v12, v12, a2
; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v12
; LMULMAX1-RV32-NEXT: vsrl.vx v12, v8, a3
; LMULMAX1-RV32-NEXT: vsrl.vx v13, v8, a4
; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a5 ; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a5
; LMULMAX1-RV32-NEXT: vor.vv v12, v13, v12 ; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
; LMULMAX1-RV32-NEXT: vor.vv v11, v11, v12
; LMULMAX1-RV32-NEXT: vand.vv v10, v8, v10
; LMULMAX1-RV32-NEXT: vsll.vi v10, v10, 8
; LMULMAX1-RV32-NEXT: vand.vx v12, v8, a2
; LMULMAX1-RV32-NEXT: vsll.vi v12, v12, 24
; LMULMAX1-RV32-NEXT: vor.vv v10, v12, v10 ; LMULMAX1-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX1-RV32-NEXT: vsll.vx v12, v8, a3 ; LMULMAX1-RV32-NEXT: vsll.vx v12, v8, a2
; LMULMAX1-RV32-NEXT: vand.vx v13, v8, a4
; LMULMAX1-RV32-NEXT: vsll.vx v13, v13, a3
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
; LMULMAX1-RV32-NEXT: vand.vv v13, v8, v11
; LMULMAX1-RV32-NEXT: vsll.vi v13, v13, 8
; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5 ; LMULMAX1-RV32-NEXT: vand.vx v8, v8, a5
; LMULMAX1-RV32-NEXT: vsll.vx v8, v8, a4 ; LMULMAX1-RV32-NEXT: vsll.vi v8, v8, 24
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v13
; LMULMAX1-RV32-NEXT: vor.vv v8, v12, v8 ; LMULMAX1-RV32-NEXT: vor.vv v8, v12, v8
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10 ; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vor.vv v8, v8, v11 ; LMULMAX1-RV32-NEXT: vsrl.vx v10, v9, a2
; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vsrl.vx v12, v9, a3
; LMULMAX1-RV32-NEXT: vse64.v v9, (a1) ; LMULMAX1-RV32-NEXT: vand.vx v12, v12, a4
; LMULMAX1-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX1-RV32-NEXT: vsrl.vi v12, v9, 8
; LMULMAX1-RV32-NEXT: vand.vv v12, v12, v11
; LMULMAX1-RV32-NEXT: vsrl.vi v13, v9, 24
; LMULMAX1-RV32-NEXT: vand.vx v13, v13, a5
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
; LMULMAX1-RV32-NEXT: vor.vv v10, v12, v10
; LMULMAX1-RV32-NEXT: vsll.vx v12, v9, a2
; LMULMAX1-RV32-NEXT: vand.vx v13, v9, a4
; LMULMAX1-RV32-NEXT: vsll.vx v13, v13, a3
; LMULMAX1-RV32-NEXT: vor.vv v12, v12, v13
; LMULMAX1-RV32-NEXT: vand.vv v11, v9, v11
; LMULMAX1-RV32-NEXT: vsll.vi v11, v11, 8
; LMULMAX1-RV32-NEXT: vand.vx v9, v9, a5
; LMULMAX1-RV32-NEXT: vsll.vi v9, v9, 24
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vor.vv v9, v12, v9
; LMULMAX1-RV32-NEXT: vor.vv v9, v9, v10
; LMULMAX1-RV32-NEXT: vse64.v v9, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v8, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: bswap_v4i64: ; LMULMAX1-RV64-LABEL: bswap_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle64.v v8, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v9, (a0) ; LMULMAX1-RV64-NEXT: vle64.v v9, (a0)
▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll

Show First 20 Lines • Show All 406 Lines • ▼ Show 20 Lines
; LMULMAX4-NEXT: .cfi_def_cfa_offset 256 ; LMULMAX4-NEXT: .cfi_def_cfa_offset 256
; LMULMAX4-NEXT: sd ra, 248(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd ra, 248(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: sd s0, 240(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd s0, 240(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: .cfi_offset ra, -8 ; LMULMAX4-NEXT: .cfi_offset ra, -8
; LMULMAX4-NEXT: .cfi_offset s0, -16 ; LMULMAX4-NEXT: .cfi_offset s0, -16
; LMULMAX4-NEXT: addi s0, sp, 256 ; LMULMAX4-NEXT: addi s0, sp, 256
; LMULMAX4-NEXT: .cfi_def_cfa s0, 0 ; LMULMAX4-NEXT: .cfi_def_cfa s0, 0
; LMULMAX4-NEXT: andi sp, sp, -128 ; LMULMAX4-NEXT: andi sp, sp, -128
; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vmv.v.i v8, 0 ; LMULMAX4-NEXT: vmv.v.i v8, 0
; LMULMAX4-NEXT: addi a0, sp, 64
; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: mv a0, sp ; LMULMAX4-NEXT: mv a0, sp
; LMULMAX4-NEXT: li a1, 1 ; LMULMAX4-NEXT: li a1, 1
; LMULMAX4-NEXT: li a2, 2 ; LMULMAX4-NEXT: li a2, 2
; LMULMAX4-NEXT: li a3, 3 ; LMULMAX4-NEXT: li a3, 3
; LMULMAX4-NEXT: li a4, 4 ; LMULMAX4-NEXT: li a4, 4
; LMULMAX4-NEXT: li a5, 5 ; LMULMAX4-NEXT: li a5, 5
; LMULMAX4-NEXT: li a6, 6 ; LMULMAX4-NEXT: li a6, 6
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; LMULMAX4-NEXT: addi sp, sp, -160 ; LMULMAX4-NEXT: addi sp, sp, -160
; LMULMAX4-NEXT: .cfi_def_cfa_offset 160 ; LMULMAX4-NEXT: .cfi_def_cfa_offset 160
; LMULMAX4-NEXT: sd ra, 152(sp) # 8-byte Folded Spill ; LMULMAX4-NEXT: sd ra, 152(sp) # 8-byte Folded Spill
; LMULMAX4-NEXT: .cfi_offset ra, -8 ; LMULMAX4-NEXT: .cfi_offset ra, -8
; LMULMAX4-NEXT: li a0, 1 ; LMULMAX4-NEXT: li a0, 1
; LMULMAX4-NEXT: sd a0, 136(sp) ; LMULMAX4-NEXT: sd a0, 136(sp)
; LMULMAX4-NEXT: li a0, 13 ; LMULMAX4-NEXT: li a0, 13
; LMULMAX4-NEXT: sd a0, 0(sp) ; LMULMAX4-NEXT: sd a0, 0(sp)
; LMULMAX4-NEXT: addi a0, sp, 72
; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; LMULMAX4-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; LMULMAX4-NEXT: vmv.v.i v8, 0 ; LMULMAX4-NEXT: vmv.v.i v8, 0
; LMULMAX4-NEXT: addi a0, sp, 72
; LMULMAX4-NEXT: vse32.v v8, (a0) ; LMULMAX4-NEXT: vse32.v v8, (a0)
; LMULMAX4-NEXT: addi a0, sp, 8 ; LMULMAX4-NEXT: addi a0, sp, 8
; LMULMAX4-NEXT: li a1, 1 ; LMULMAX4-NEXT: li a1, 1
; LMULMAX4-NEXT: li a2, 2 ; LMULMAX4-NEXT: li a2, 2
; LMULMAX4-NEXT: li a3, 3 ; LMULMAX4-NEXT: li a3, 3
; LMULMAX4-NEXT: li a4, 4 ; LMULMAX4-NEXT: li a4, 4
; LMULMAX4-NEXT: li a5, 5 ; LMULMAX4-NEXT: li a5, 5
; LMULMAX4-NEXT: li a6, 6 ; LMULMAX4-NEXT: li a6, 6
Show All 32 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll

Show First 20 Lines • Show All 561 Lines • ▼ Show 20 Lines
; LMULMAX2-RV64I-NEXT: vmul.vx v8, v8, a1 ; LMULMAX2-RV64I-NEXT: vmul.vx v8, v8, a1
; LMULMAX2-RV64I-NEXT: li a1, 56 ; LMULMAX2-RV64I-NEXT: li a1, 56
; LMULMAX2-RV64I-NEXT: vsrl.vx v8, v8, a1 ; LMULMAX2-RV64I-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV64I-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64I-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64I-NEXT: ret ; LMULMAX2-RV64I-NEXT: ret
; ;
; LMULMAX2-RV32F-LABEL: ctlz_v2i64: ; LMULMAX2-RV32F-LABEL: ctlz_v2i64:
; LMULMAX2-RV32F: # %bb.0: ; LMULMAX2-RV32F: # %bb.0:
; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v9, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV32F-NEXT: li a1, 190 ; LMULMAX2-RV32F-NEXT: li a1, 190
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.x v9, a1 ; LMULMAX2-RV32F-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: vwsubu.wv v9, v9, v8 ; LMULMAX2-RV32F-NEXT: vwsubu.wv v9, v9, v8
; LMULMAX2-RV32F-NEXT: li a1, 64 ; LMULMAX2-RV32F-NEXT: li a1, 64
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vminu.vx v8, v9, a1 ; LMULMAX2-RV32F-NEXT: vminu.vx v8, v9, a1
; LMULMAX2-RV32F-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32F-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: ret ; LMULMAX2-RV32F-NEXT: ret
; ;
; LMULMAX2-RV64F-LABEL: ctlz_v2i64: ; LMULMAX2-RV64F-LABEL: ctlz_v2i64:
; LMULMAX2-RV64F: # %bb.0: ; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX2-RV64F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: li a1, 190
; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1 ; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v8 ; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v9, v8
; LMULMAX2-RV64F-NEXT: fsrm a1 ; LMULMAX2-RV64F-NEXT: fsrm a1
; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v10, 23 ; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV64F-NEXT: li a1, 190
; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8 ; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8
; LMULMAX2-RV64F-NEXT: li a1, 64 ; LMULMAX2-RV64F-NEXT: li a1, 64
; LMULMAX2-RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; LMULMAX2-RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX2-RV64F-NEXT: vminu.vx v8, v10, a1 ; LMULMAX2-RV64F-NEXT: vminu.vx v8, v10, a1
; LMULMAX2-RV64F-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64F-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: ret ; LMULMAX2-RV64F-NEXT: ret
; ;
; LMULMAX2-RV32D-LABEL: ctlz_v2i64: ; LMULMAX2-RV32D-LABEL: ctlz_v2i64:
▲ Show 20 Lines • Show All 654 Lines • ▼ Show 20 Lines
; LMULMAX2-RV64I-NEXT: vmul.vx v8, v8, a1 ; LMULMAX2-RV64I-NEXT: vmul.vx v8, v8, a1
; LMULMAX2-RV64I-NEXT: li a1, 56 ; LMULMAX2-RV64I-NEXT: li a1, 56
; LMULMAX2-RV64I-NEXT: vsrl.vx v8, v8, a1 ; LMULMAX2-RV64I-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV64I-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64I-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64I-NEXT: ret ; LMULMAX2-RV64I-NEXT: ret
; ;
; LMULMAX2-RV32F-LABEL: ctlz_v4i64: ; LMULMAX2-RV32F-LABEL: ctlz_v4i64:
; LMULMAX2-RV32F: # %bb.0: ; LMULMAX2-RV32F: # %bb.0:
; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: li a1, 190 ; LMULMAX2-RV32F-NEXT: li a1, 190
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32F-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v12, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v12, 23
; LMULMAX2-RV32F-NEXT: vwsubu.wv v10, v10, v8 ; LMULMAX2-RV32F-NEXT: vwsubu.wv v10, v10, v8
; LMULMAX2-RV32F-NEXT: li a1, 64 ; LMULMAX2-RV32F-NEXT: li a1, 64
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vminu.vx v8, v10, a1 ; LMULMAX2-RV32F-NEXT: vminu.vx v8, v10, a1
; LMULMAX2-RV32F-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32F-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: ret ; LMULMAX2-RV32F-NEXT: ret
; ;
; LMULMAX2-RV64F-LABEL: ctlz_v4i64: ; LMULMAX2-RV64F-LABEL: ctlz_v4i64:
; LMULMAX2-RV64F: # %bb.0: ; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX2-RV64F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: li a1, 190
; LMULMAX2-RV64F-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1 ; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v11, v8 ; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v8
; LMULMAX2-RV64F-NEXT: fsrm a1 ; LMULMAX2-RV64F-NEXT: fsrm a1
; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v11, 23 ; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV64F-NEXT: vwsubu.vv v12, v10, v8 ; LMULMAX2-RV64F-NEXT: li a1, 190
; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8
; LMULMAX2-RV64F-NEXT: li a1, 64 ; LMULMAX2-RV64F-NEXT: li a1, 64
; LMULMAX2-RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; LMULMAX2-RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; LMULMAX2-RV64F-NEXT: vminu.vx v8, v12, a1 ; LMULMAX2-RV64F-NEXT: vminu.vx v8, v10, a1
; LMULMAX2-RV64F-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64F-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: ret ; LMULMAX2-RV64F-NEXT: ret
; ;
; LMULMAX2-RV32D-LABEL: ctlz_v4i64: ; LMULMAX2-RV32D-LABEL: ctlz_v4i64:
; LMULMAX2-RV32D: # %bb.0: ; LMULMAX2-RV32D: # %bb.0:
; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32D-NEXT: fsrmi a1, 1 ; LMULMAX2-RV32D-NEXT: fsrmi a1, 1
▲ Show 20 Lines • Show All 578 Lines • ▼ Show 20 Lines
; LMULMAX2-RV64I-NEXT: vmul.vx v8, v8, a1 ; LMULMAX2-RV64I-NEXT: vmul.vx v8, v8, a1
; LMULMAX2-RV64I-NEXT: li a1, 56 ; LMULMAX2-RV64I-NEXT: li a1, 56
; LMULMAX2-RV64I-NEXT: vsrl.vx v8, v8, a1 ; LMULMAX2-RV64I-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV64I-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64I-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64I-NEXT: ret ; LMULMAX2-RV64I-NEXT: ret
; ;
; LMULMAX2-RV32F-LABEL: ctlz_zero_undef_v2i64: ; LMULMAX2-RV32F-LABEL: ctlz_zero_undef_v2i64:
; LMULMAX2-RV32F: # %bb.0: ; LMULMAX2-RV32F: # %bb.0:
; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v9, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV32F-NEXT: li a1, 190 ; LMULMAX2-RV32F-NEXT: li a1, 190
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.x v9, a1 ; LMULMAX2-RV32F-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: vwsubu.wv v9, v9, v8 ; LMULMAX2-RV32F-NEXT: vwsubu.wv v9, v9, v8
; LMULMAX2-RV32F-NEXT: vse64.v v9, (a0) ; LMULMAX2-RV32F-NEXT: vse64.v v9, (a0)
; LMULMAX2-RV32F-NEXT: ret ; LMULMAX2-RV32F-NEXT: ret
; ;
; LMULMAX2-RV64F-LABEL: ctlz_zero_undef_v2i64: ; LMULMAX2-RV64F-LABEL: ctlz_zero_undef_v2i64:
; LMULMAX2-RV64F: # %bb.0: ; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; LMULMAX2-RV64F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: li a1, 190
; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1 ; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v8 ; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v9, v8
; LMULMAX2-RV64F-NEXT: fsrm a1 ; LMULMAX2-RV64F-NEXT: fsrm a1
; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v10, 23 ; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV64F-NEXT: li a1, 190
; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8 ; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8
; LMULMAX2-RV64F-NEXT: vse64.v v10, (a0) ; LMULMAX2-RV64F-NEXT: vse64.v v10, (a0)
; LMULMAX2-RV64F-NEXT: ret ; LMULMAX2-RV64F-NEXT: ret
; ;
; LMULMAX2-RV32D-LABEL: ctlz_zero_undef_v2i64: ; LMULMAX2-RV32D-LABEL: ctlz_zero_undef_v2i64:
; LMULMAX2-RV32D: # %bb.0: ; LMULMAX2-RV32D: # %bb.0:
; LMULMAX2-RV32D-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV32D-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0)
▲ Show 20 Lines • Show All 627 Lines • ▼ Show 20 Lines
; LMULMAX2-RV64I-NEXT: vmul.vx v8, v8, a1 ; LMULMAX2-RV64I-NEXT: vmul.vx v8, v8, a1
; LMULMAX2-RV64I-NEXT: li a1, 56 ; LMULMAX2-RV64I-NEXT: li a1, 56
; LMULMAX2-RV64I-NEXT: vsrl.vx v8, v8, a1 ; LMULMAX2-RV64I-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV64I-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64I-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64I-NEXT: ret ; LMULMAX2-RV64I-NEXT: ret
; ;
; LMULMAX2-RV32F-LABEL: ctlz_zero_undef_v4i64: ; LMULMAX2-RV32F-LABEL: ctlz_zero_undef_v4i64:
; LMULMAX2-RV32F: # %bb.0: ; LMULMAX2-RV32F: # %bb.0:
; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: li a1, 190 ; LMULMAX2-RV32F-NEXT: li a1, 190
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.x v10, a1 ; LMULMAX2-RV32F-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v12, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v12, 23
; LMULMAX2-RV32F-NEXT: vwsubu.wv v10, v10, v8 ; LMULMAX2-RV32F-NEXT: vwsubu.wv v10, v10, v8
; LMULMAX2-RV32F-NEXT: vse64.v v10, (a0) ; LMULMAX2-RV32F-NEXT: vse64.v v10, (a0)
; LMULMAX2-RV32F-NEXT: ret ; LMULMAX2-RV32F-NEXT: ret
; ;
; LMULMAX2-RV64F-LABEL: ctlz_zero_undef_v4i64: ; LMULMAX2-RV64F-LABEL: ctlz_zero_undef_v4i64:
; LMULMAX2-RV64F: # %bb.0: ; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX2-RV64F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: li a1, 190
; LMULMAX2-RV64F-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1 ; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v11, v8 ; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v8
; LMULMAX2-RV64F-NEXT: fsrm a1 ; LMULMAX2-RV64F-NEXT: fsrm a1
; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v11, 23 ; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV64F-NEXT: vwsubu.vv v12, v10, v8 ; LMULMAX2-RV64F-NEXT: li a1, 190
; LMULMAX2-RV64F-NEXT: vse64.v v12, (a0) ; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8
; LMULMAX2-RV64F-NEXT: vse64.v v10, (a0)
; LMULMAX2-RV64F-NEXT: ret ; LMULMAX2-RV64F-NEXT: ret
; ;
; LMULMAX2-RV32D-LABEL: ctlz_zero_undef_v4i64: ; LMULMAX2-RV32D-LABEL: ctlz_zero_undef_v4i64:
; LMULMAX2-RV32D: # %bb.0: ; LMULMAX2-RV32D: # %bb.0:
; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32D-NEXT: fsrmi a1, 1 ; LMULMAX2-RV32D-NEXT: fsrmi a1, 1
; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8 ; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll

Show First 20 Lines • Show All 1,865 Lines • ▼ Show 20 Lines
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 48 ; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: li a2, 16
; RV32-NEXT: vslidedown.vi v24, v0, 2 ; RV32-NEXT: vslidedown.vi v24, v0, 2
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: addi a2, a1, 1365 ; RV32-NEXT: bltu a0, a2, .LBB34_2
; RV32-NEXT: li a1, 32 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: li a1, 16
; RV32-NEXT: li a3, 16 ; RV32-NEXT: .LBB34_2:
; RV32-NEXT: vmv.v.x v16, a2 ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: lui a2, 349525
; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 40
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vmv.v.x v8, a2
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a2, a2, a4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a4, 40 ; RV32-NEXT: li a4, 40
; RV32-NEXT: mul a2, a2, a4 ; RV32-NEXT: mul a2, a2, a4
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; RV32-NEXT: mv a2, a0 ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: bltu a0, a3, .LBB34_2 ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: # %bb.1: ; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: li a2, 16 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: .LBB34_2: ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: lui a2, 209715
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: addi a2, a2, 819
; RV32-NEXT: slli a3, a3, 5 ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: vmv.v.x v8, a2
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 40 ; RV32-NEXT: li a4, 40
; RV32-NEXT: mul a3, a3, a4 ; RV32-NEXT: mul a2, a2, a4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a3, a3, 5 ; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: li a4, 24 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: mul a3, a3, a4 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: lui a3, 209715 ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: addi a3, a3, 819 ; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: vmv.v.x v16, a3 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; RV32-NEXT: slli a3, a3, 5 ; RV32-NEXT: vadd.vv v16, v8, v16, v0.t
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: vsrl.vi v8, v16, 4, v0.t
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vadd.vv v16, v16, v8, v0.t
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill ; RV32-NEXT: lui a2, 61681
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: li a4, 24 ; RV32-NEXT: vmv.v.x v8, a2
; RV32-NEXT: mul a3, a3, a4 ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: slli a2, a2, 5
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: lui a2, 4112
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a2, a2, 257
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: vmv.v.x v16, a2
; RV32-NEXT: li a4, 24 ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: mul a3, a3, a4 ; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload ; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vl8r.v v16, (a3) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: lui a3, 61681
; RV32-NEXT: addi a3, a3, -241
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: lui a3, 4112
; RV32-NEXT: addi a3, a3, 257
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a3
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t ; RV32-NEXT: vsrl.vx v8, v8, a1, v0.t
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 4 ; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: addi a2, a0, -16 ; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: vmv1r.v v0, v24
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 48 ; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v16, v8, v0.t ; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 48 ; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t ; RV32-NEXT: vsub.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v8, v16, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 48 ; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 48 ; RV32-NEXT: li a2, 48
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t ; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
▲ Show 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl) %v = call <32 x i64> @llvm.vp.ctpop.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vp_ctpop_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { define <32 x i64> @vp_ctpop_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctpop_v32i64_unmasked: ; RV32-LABEL: vp_ctpop_v32i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a2, a1, 1365
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: li a3, 16
; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: mv a2, a0
; RV32-NEXT: bltu a0, a3, .LBB35_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB35_2:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a3, a3, 5 ; RV32-NEXT: li a2, 40
; RV32-NEXT: sub sp, sp, a3 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; RV32-NEXT: vsrl.vi v24, v8, 1 ; RV32-NEXT: li a2, 16
; RV32-NEXT: vand.vv v24, v24, v0 ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: vsub.vv v8, v8, v24 ; RV32-NEXT: slli a1, a1, 5
; RV32-NEXT: lui a3, 209715 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a3, a3, 819 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: mv a1, a0
; RV32-NEXT: li a5, 24 ; RV32-NEXT: bltu a0, a2, .LBB35_2
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: li a1, 16
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: .LBB35_2:
; RV32-NEXT: vs8r.v v0, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv.v.x v0, a3 ; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: lui a2, 349525
; RV32-NEXT: vand.vv v24, v8, v0 ; RV32-NEXT: addi a2, a2, 1365
; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a2
; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a4, 24
; RV32-NEXT: mul a2, a2, a4
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: lui a2, 209715
; RV32-NEXT: addi a2, a2, 819
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v8, v0
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v0 ; RV32-NEXT: vand.vv v8, v8, v0
; RV32-NEXT: vadd.vv v8, v24, v8 ; RV32-NEXT: vadd.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v24, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v24 ; RV32-NEXT: vadd.vv v8, v8, v16
; RV32-NEXT: lui a3, 61681 ; RV32-NEXT: lui a2, 61681
; RV32-NEXT: addi a3, a3, -241 ; RV32-NEXT: addi a2, a2, -241
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a3 ; RV32-NEXT: vmv.v.x v16, a2
; RV32-NEXT: csrr a3, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a3, a3, 4 ; RV32-NEXT: slli a2, a2, 4
; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: lui a3, 4112 ; RV32-NEXT: lui a2, 4112
; RV32-NEXT: addi a3, a3, 257 ; RV32-NEXT: addi a2, a2, 257
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a3 ; RV32-NEXT: vmv.v.x v8, a2
; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v24, v24, v8
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v24, a1
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3 ; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: addi a2, a0, -16 ; RV32-NEXT: addi a2, a0, -16
; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: and a0, a0, a2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v24, v16, 1 ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v24, v8, 1
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v24, v24, v8 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vsub.vv v24, v16, v24 ; RV32-NEXT: vsub.vv v24, v8, v24
; RV32-NEXT: vand.vv v8, v24, v0 ; RV32-NEXT: vand.vv v8, v24, v0
; RV32-NEXT: vsrl.vi v24, v24, 2 ; RV32-NEXT: vsrl.vi v24, v24, 2
; RV32-NEXT: vand.vv v24, v24, v0 ; RV32-NEXT: vand.vv v24, v24, v0
; RV32-NEXT: vadd.vv v8, v8, v24 ; RV32-NEXT: vadd.vv v8, v8, v24
; RV32-NEXT: vsrl.vi v24, v8, 4 ; RV32-NEXT: vsrl.vi v24, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v24 ; RV32-NEXT: vadd.vv v8, v8, v24
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmul.vv v8, v8, v16 ; RV32-NEXT: vmul.vv v8, v8, v16
; RV32-NEXT: vsrl.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_ctpop_v32i64_unmasked: ; RV64-LABEL: vp_ctpop_v32i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a2, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: mv a1, a0 ; RV64-NEXT: mv a1, a0
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll

Show First 20 Lines • Show All 2,127 Lines • ▼ Show 20 Lines
; RV32-LABEL: vp_cttz_v32i64: ; RV32-LABEL: vp_cttz_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 6 ; RV32-NEXT: slli a1, a1, 6
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 64 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 64 * vlenb
; RV32-NEXT: vmv1r.v v24, v0
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vmv8r.v v16, v8
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: li a1, 16
; RV32-NEXT: addi a1, a0, -16 ; RV32-NEXT: vslidedown.vi v24, v0, 2
; RV32-NEXT: sltu a2, a0, a1 ; RV32-NEXT: mv a2, a0
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: bltu a0, a1, .LBB34_2
; RV32-NEXT: and a2, a2, a1 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB34_2:
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v8, v16, a1, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 56
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: li a3, 32 ; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v8, -1 ; RV32-NEXT: vmv.v.i v8, -1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: li a1, 1
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 5 ; RV32-NEXT: slli a4, a4, 5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vxor.vv v8, v16, v8, v0.t ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v16, a1, v0.t ; RV32-NEXT: vxor.vv v16, v16, v8, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 349525 ; RV32-NEXT: lui a4, 349525
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: li a6, 56 ; RV32-NEXT: li a6, 56
; RV32-NEXT: mul a5, a5, a6 ; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16 ; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 24 ; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56 ; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 209715 ; RV32-NEXT: lui a4, 209715
; RV32-NEXT: addi a4, a4, 819 ; RV32-NEXT: addi a4, a4, 819
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t ; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v16, v8, v16, v0.t ; RV32-NEXT: vadd.vv v16, v8, v16, v0.t
; RV32-NEXT: lui a4, 61681 ; RV32-NEXT: lui a4, 61681
; RV32-NEXT: addi a4, a4, -241 ; RV32-NEXT: addi a4, a4, -241
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: lui a4, 4112 ; RV32-NEXT: lui a4, 4112
; RV32-NEXT: addi a4, a4, 257 ; RV32-NEXT: addi a4, a4, 257
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v16, a4
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vmul.vv v8, v16, v8, v0.t
; RV32-NEXT: li a2, 56 ; RV32-NEXT: li a2, 56
; RV32-NEXT: li a3, 16
; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: bltu a0, a3, .LBB34_2 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: # %bb.1: ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: li a0, 16 ; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: .LBB34_2: ; RV32-NEXT: addi a3, a0, -16
; RV32-NEXT: sltu a0, a0, a3
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: vmv1r.v v0, v24
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a0, a0, a3 ; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vx v8, v16, a1, v0.t
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vxor.vv v8, v16, v8, v0.t ; RV32-NEXT: vxor.vv v16, v16, v8, v0.t
; RV32-NEXT: vsub.vx v16, v16, a1, v0.t ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v8, v16, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t ; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 6 ; RV32-NEXT: slli a0, a0, 6
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_cttz_v32i64: ; RV64-LABEL: vp_cttz_v32i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; RV32-NEXT: .LBB35_2: ; RV32-NEXT: .LBB35_2:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a2, a2, a3 ; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2 ; RV32-NEXT: sub sp, sp, a2
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 1
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, -1
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vxor.vv v16, v8, v16 ; RV32-NEXT: vsub.vx v16, v8, a2
; RV32-NEXT: li a3, 1 ; RV32-NEXT: li a3, 32
; RV32-NEXT: vsub.vx v8, v8, a3 ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vand.vv v8, v16, v8 ; RV32-NEXT: vmv.v.i v24, -1
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vxor.vv v8, v8, v24
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: lui a4, 349525 ; RV32-NEXT: lui a4, 349525
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 24 ; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: lui a4, 209715 ; RV32-NEXT: lui a4, 209715
; RV32-NEXT: addi a4, a4, 819 ; RV32-NEXT: addi a4, a4, 819
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a4 ; RV32-NEXT: vmv.v.x v16, a4
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v24, v8 ; RV32-NEXT: vadd.vv v8, v24, v8
; RV32-NEXT: vsrl.vi v24, v8, 4 ; RV32-NEXT: vsrl.vi v24, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v24 ; RV32-NEXT: vadd.vv v8, v8, v24
; RV32-NEXT: lui a4, 61681 ; RV32-NEXT: lui a4, 61681
; RV32-NEXT: addi a4, a4, -241 ; RV32-NEXT: addi a4, a4, -241
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: lui a4, 4112 ; RV32-NEXT: lui a4, 4112
; RV32-NEXT: addi a4, a4, 257 ; RV32-NEXT: addi a4, a4, 257
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a2, a2, 3 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: addi a2, a0, -16 ; RV32-NEXT: addi a3, a0, -16
; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sltu a0, a0, a3
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vxor.vv v8, v0, v8 ; RV32-NEXT: vxor.vv v8, v0, v8
; RV32-NEXT: vsub.vx v0, v0, a3 ; RV32-NEXT: vsub.vx v0, v0, a2
; RV32-NEXT: vand.vv v8, v8, v0 ; RV32-NEXT: vand.vv v8, v8, v0
; RV32-NEXT: vsrl.vi v0, v8, 1 ; RV32-NEXT: vsrl.vi v0, v8, 1
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
▲ Show 20 Lines • Show All 2,184 Lines • ▼ Show 20 Lines
; RV32-LABEL: vp_cttz_zero_undef_v32i64: ; RV32-LABEL: vp_cttz_zero_undef_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 6 ; RV32-NEXT: slli a1, a1, 6
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 64 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 64 * vlenb
; RV32-NEXT: vmv1r.v v24, v0
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: mul a1, a1, a2
; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: add a1, sp, a1
; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: addi a1, a1, 16
; RV32-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-NEXT: vmv8r.v v16, v8
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: li a1, 16
; RV32-NEXT: addi a1, a0, -16 ; RV32-NEXT: vslidedown.vi v24, v0, 2
; RV32-NEXT: sltu a2, a0, a1 ; RV32-NEXT: mv a2, a0
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: bltu a0, a1, .LBB70_2
; RV32-NEXT: and a2, a2, a1 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB70_2:
; RV32-NEXT: li a1, 1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v8, v16, a1, v0.t
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: li a4, 56
; RV32-NEXT: mul a3, a3, a4
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: li a3, 32 ; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v8, -1 ; RV32-NEXT: vmv.v.i v8, -1
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: li a1, 1
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 5 ; RV32-NEXT: slli a4, a4, 5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vxor.vv v8, v16, v8, v0.t ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vsub.vx v16, v16, a1, v0.t ; RV32-NEXT: vxor.vv v16, v16, v8, v0.t
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 349525 ; RV32-NEXT: lui a4, 349525
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 1, v0.t
; RV32-NEXT: csrr a5, vlenb ; RV32-NEXT: csrr a5, vlenb
; RV32-NEXT: li a6, 56 ; RV32-NEXT: li a6, 56
; RV32-NEXT: mul a5, a5, a6 ; RV32-NEXT: mul a5, a5, a6
; RV32-NEXT: add a5, sp, a5 ; RV32-NEXT: add a5, sp, a5
; RV32-NEXT: addi a5, a5, 16 ; RV32-NEXT: addi a5, a5, 16
; RV32-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 24 ; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56 ; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v16, v8, v0.t ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 209715 ; RV32-NEXT: lui a4, 209715
; RV32-NEXT: addi a4, a4, 819 ; RV32-NEXT: addi a4, a4, 819
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 48 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t ; RV32-NEXT: vsrl.vi v16, v16, 2, v0.t
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 56
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v16, v8, v0.t
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v16, v8, v16, v0.t ; RV32-NEXT: vadd.vv v16, v8, v16, v0.t
; RV32-NEXT: lui a4, 61681 ; RV32-NEXT: lui a4, 61681
; RV32-NEXT: addi a4, a4, -241 ; RV32-NEXT: addi a4, a4, -241
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v8, a4
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: li a5, 48
; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: lui a4, 4112 ; RV32-NEXT: lui a4, 4112
; RV32-NEXT: addi a4, a4, 257 ; RV32-NEXT: addi a4, a4, 257
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v8, a4 ; RV32-NEXT: vmv.v.x v16, a4
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: add a2, sp, a2
; RV32-NEXT: addi a2, a2, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vmul.vv v8, v16, v8, v0.t
; RV32-NEXT: li a2, 56 ; RV32-NEXT: li a2, 56
; RV32-NEXT: li a3, 16
; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: vs8r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: slli a3, a3, 4
; RV32-NEXT: bltu a0, a3, .LBB70_2 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: # %bb.1: ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: li a0, 16 ; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: .LBB70_2: ; RV32-NEXT: addi a3, a0, -16
; RV32-NEXT: sltu a0, a0, a3
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: vmv1r.v v0, v24
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a0, a0, a3 ; RV32-NEXT: mul a0, a0, a3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vx v8, v16, a1, v0.t
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vxor.vv v8, v16, v8, v0.t ; RV32-NEXT: vxor.vv v16, v16, v8, v0.t
; RV32-NEXT: vsub.vx v16, v16, a1, v0.t ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v16, v8, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 1, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 24 ; RV32-NEXT: li a1, 24
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v8, v16, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsub.vv v8, v8, v16, v0.t ; RV32-NEXT: vsub.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v16, v16, v8, v0.t ; RV32-NEXT: vand.vv v16, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t ; RV32-NEXT: vsrl.vi v8, v8, 2, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a1, 40 ; RV32-NEXT: li a1, 40
; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vadd.vv v8, v16, v8, v0.t ; RV32-NEXT: vadd.vv v8, v16, v8, v0.t
; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t ; RV32-NEXT: vsrl.vi v16, v8, 4, v0.t
; RV32-NEXT: vadd.vv v8, v8, v16, v0.t ; RV32-NEXT: vadd.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 4 ; RV32-NEXT: li a1, 48
; RV32-NEXT: mul a0, a0, a1
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vand.vv v8, v8, v16, v0.t ; RV32-NEXT: vand.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vmul.vv v8, v8, v16, v0.t ; RV32-NEXT: vmul.vv v8, v8, v16, v0.t
; RV32-NEXT: vsrl.vx v8, v8, a2, v0.t ; RV32-NEXT: vsrl.vx v16, v8, a2, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: slli a0, a0, 4
; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 6 ; RV32-NEXT: slli a0, a0, 6
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_cttz_zero_undef_v32i64: ; RV64-LABEL: vp_cttz_zero_undef_v32i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; RV32-NEXT: .LBB71_2: ; RV32-NEXT: .LBB71_2:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: li a3, 40 ; RV32-NEXT: li a3, 40
; RV32-NEXT: mul a2, a2, a3 ; RV32-NEXT: mul a2, a2, a3
; RV32-NEXT: sub sp, sp, a2 ; RV32-NEXT: sub sp, sp, a2
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 1
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, -1
; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a3, a3, 5
; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vxor.vv v16, v8, v16 ; RV32-NEXT: vsub.vx v16, v8, a2
; RV32-NEXT: li a3, 1 ; RV32-NEXT: li a3, 32
; RV32-NEXT: vsub.vx v8, v8, a3 ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vand.vv v8, v16, v8 ; RV32-NEXT: vmv.v.i v24, -1
; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 5
; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vxor.vv v8, v8, v24
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: lui a4, 349525 ; RV32-NEXT: lui a4, 349525
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a4, a4, 1365
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: li a5, 24 ; RV32-NEXT: li a5, 24
; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: mul a4, a4, a5
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: lui a4, 209715 ; RV32-NEXT: lui a4, 209715
; RV32-NEXT: addi a4, a4, 819 ; RV32-NEXT: addi a4, a4, 819
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a4 ; RV32-NEXT: vmv.v.x v16, a4
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
; RV32-NEXT: vand.vv v8, v8, v16 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vadd.vv v8, v24, v8 ; RV32-NEXT: vadd.vv v8, v24, v8
; RV32-NEXT: vsrl.vi v24, v8, 4 ; RV32-NEXT: vsrl.vi v24, v8, 4
; RV32-NEXT: vadd.vv v8, v8, v24 ; RV32-NEXT: vadd.vv v8, v8, v24
; RV32-NEXT: lui a4, 61681 ; RV32-NEXT: lui a4, 61681
; RV32-NEXT: addi a4, a4, -241 ; RV32-NEXT: addi a4, a4, -241
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: csrr a4, vlenb ; RV32-NEXT: csrr a4, vlenb
; RV32-NEXT: slli a4, a4, 4 ; RV32-NEXT: slli a4, a4, 4
; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: add a4, sp, a4
; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: addi a4, a4, 16
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: lui a4, 4112 ; RV32-NEXT: lui a4, 4112
; RV32-NEXT: addi a4, a4, 257 ; RV32-NEXT: addi a4, a4, 257
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a4 ; RV32-NEXT: vmv.v.x v24, a4
; RV32-NEXT: addi a2, sp, 16 ; RV32-NEXT: addi a3, sp, 16
; RV32-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmul.vv v8, v8, v24 ; RV32-NEXT: vmul.vv v8, v8, v24
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: slli a2, a2, 3 ; RV32-NEXT: slli a3, a3, 3
; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: add a3, sp, a3
; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: addi a3, a3, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill
; RV32-NEXT: addi a2, a0, -16 ; RV32-NEXT: addi a3, a0, -16
; RV32-NEXT: sltu a0, a0, a2 ; RV32-NEXT: sltu a0, a0, a3
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a2 ; RV32-NEXT: and a0, a0, a3
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 5 ; RV32-NEXT: slli a0, a0, 5
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vxor.vv v8, v0, v8 ; RV32-NEXT: vxor.vv v8, v0, v8
; RV32-NEXT: vsub.vx v0, v0, a3 ; RV32-NEXT: vsub.vx v0, v0, a2
; RV32-NEXT: vand.vv v8, v8, v0 ; RV32-NEXT: vand.vv v8, v8, v0
; RV32-NEXT: vsrl.vi v0, v8, 1 ; RV32-NEXT: vsrl.vi v0, v8, 1
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: li a2, 24 ; RV32-NEXT: li a2, 24
; RV32-NEXT: mul a0, a0, a2 ; RV32-NEXT: mul a0, a0, a2
; RV32-NEXT: add a0, sp, a0 ; RV32-NEXT: add a0, sp, a0
; RV32-NEXT: addi a0, a0, 16 ; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
▲ Show 20 Lines • Show All 98 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

Show First 20 Lines • Show All 542 Lines • ▼ Show 20 Lines
; ;
; LMULMAX2-RV32F-LABEL: cttz_v2i64: ; LMULMAX2-RV32F-LABEL: cttz_v2i64:
; LMULMAX2-RV32F: # %bb.0: ; LMULMAX2-RV32F: # %bb.0:
; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.i v9, 0 ; LMULMAX2-RV32F-NEXT: vmv.v.i v9, 0
; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vsub.vv v10, v9, v8 ; LMULMAX2-RV32F-NEXT: vmseq.vv v0, v8, v9
; LMULMAX2-RV32F-NEXT: vand.vv v10, v8, v10 ; LMULMAX2-RV32F-NEXT: vsub.vv v9, v9, v8
; LMULMAX2-RV32F-NEXT: vand.vv v8, v8, v9
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1 ; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v11, v10 ; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v9, v8
; LMULMAX2-RV32F-NEXT: fsrm a1 ; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v10, v11, 23 ; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vzext.vf2 v11, v10 ; LMULMAX2-RV32F-NEXT: vzext.vf2 v9, v8
; LMULMAX2-RV32F-NEXT: li a1, 127 ; LMULMAX2-RV32F-NEXT: li a1, 127
; LMULMAX2-RV32F-NEXT: vsub.vx v10, v11, a1 ; LMULMAX2-RV32F-NEXT: vsub.vx v8, v9, a1
; LMULMAX2-RV32F-NEXT: vmseq.vv v0, v8, v9
; LMULMAX2-RV32F-NEXT: li a1, 64 ; LMULMAX2-RV32F-NEXT: li a1, 64
; LMULMAX2-RV32F-NEXT: vmerge.vxm v8, v10, a1, v0 ; LMULMAX2-RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX2-RV32F-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32F-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: ret ; LMULMAX2-RV32F-NEXT: ret
; ;
; LMULMAX2-RV64F-LABEL: cttz_v2i64: ; LMULMAX2-RV64F-LABEL: cttz_v2i64:
; LMULMAX2-RV64F: # %bb.0: ; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV64F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: vrsub.vi v9, v8, 0 ; LMULMAX2-RV64F-NEXT: vrsub.vi v9, v8, 0
Show All 14 Lines
; ;
; LMULMAX2-RV32D-LABEL: cttz_v2i64: ; LMULMAX2-RV32D-LABEL: cttz_v2i64:
; LMULMAX2-RV32D: # %bb.0: ; LMULMAX2-RV32D: # %bb.0:
; LMULMAX2-RV32D-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV32D-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV32D-NEXT: vmv.v.i v9, 0 ; LMULMAX2-RV32D-NEXT: vmv.v.i v9, 0
; LMULMAX2-RV32D-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV32D-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32D-NEXT: vsub.vv v10, v9, v8 ; LMULMAX2-RV32D-NEXT: vmseq.vv v0, v8, v9
; LMULMAX2-RV32D-NEXT: vand.vv v10, v8, v10 ; LMULMAX2-RV32D-NEXT: vsub.vv v9, v9, v8
; LMULMAX2-RV32D-NEXT: vand.vv v8, v8, v9
; LMULMAX2-RV32D-NEXT: fsrmi a1, 1 ; LMULMAX2-RV32D-NEXT: fsrmi a1, 1
; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v10, v10 ; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV32D-NEXT: fsrm a1 ; LMULMAX2-RV32D-NEXT: fsrm a1
; LMULMAX2-RV32D-NEXT: li a1, 52 ; LMULMAX2-RV32D-NEXT: li a1, 52
; LMULMAX2-RV32D-NEXT: vsrl.vx v10, v10, a1 ; LMULMAX2-RV32D-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV32D-NEXT: li a1, 1023 ; LMULMAX2-RV32D-NEXT: li a1, 1023
; LMULMAX2-RV32D-NEXT: vsub.vx v10, v10, a1 ; LMULMAX2-RV32D-NEXT: vsub.vx v8, v8, a1
; LMULMAX2-RV32D-NEXT: vmseq.vv v0, v8, v9
; LMULMAX2-RV32D-NEXT: li a1, 64 ; LMULMAX2-RV32D-NEXT: li a1, 64
; LMULMAX2-RV32D-NEXT: vmerge.vxm v8, v10, a1, v0 ; LMULMAX2-RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX2-RV32D-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32D-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32D-NEXT: ret ; LMULMAX2-RV32D-NEXT: ret
; ;
; LMULMAX2-RV64D-LABEL: cttz_v2i64: ; LMULMAX2-RV64D-LABEL: cttz_v2i64:
; LMULMAX2-RV64D: # %bb.0: ; LMULMAX2-RV64D: # %bb.0:
; LMULMAX2-RV64D-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX2-RV64D-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV64D-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64D-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64D-NEXT: vrsub.vi v9, v8, 0 ; LMULMAX2-RV64D-NEXT: vrsub.vi v9, v8, 0
Show All 13 Lines
; ;
; LMULMAX8-RV32-LABEL: cttz_v2i64: ; LMULMAX8-RV32-LABEL: cttz_v2i64:
; LMULMAX8-RV32: # %bb.0: ; LMULMAX8-RV32: # %bb.0:
; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX8-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX8-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX8-RV32-NEXT: vmv.v.i v9, 0 ; LMULMAX8-RV32-NEXT: vmv.v.i v9, 0
; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX8-RV32-NEXT: vsub.vv v10, v9, v8 ; LMULMAX8-RV32-NEXT: vmseq.vv v0, v8, v9
; LMULMAX8-RV32-NEXT: vand.vv v10, v8, v10 ; LMULMAX8-RV32-NEXT: vsub.vv v9, v9, v8
; LMULMAX8-RV32-NEXT: vand.vv v8, v8, v9
; LMULMAX8-RV32-NEXT: fsrmi a1, 1 ; LMULMAX8-RV32-NEXT: fsrmi a1, 1
; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v10, v10 ; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8-RV32-NEXT: fsrm a1 ; LMULMAX8-RV32-NEXT: fsrm a1
; LMULMAX8-RV32-NEXT: li a1, 52 ; LMULMAX8-RV32-NEXT: li a1, 52
; LMULMAX8-RV32-NEXT: vsrl.vx v10, v10, a1 ; LMULMAX8-RV32-NEXT: vsrl.vx v8, v8, a1
; LMULMAX8-RV32-NEXT: li a1, 1023 ; LMULMAX8-RV32-NEXT: li a1, 1023
; LMULMAX8-RV32-NEXT: vsub.vx v10, v10, a1 ; LMULMAX8-RV32-NEXT: vsub.vx v8, v8, a1
; LMULMAX8-RV32-NEXT: vmseq.vv v0, v8, v9
; LMULMAX8-RV32-NEXT: li a1, 64 ; LMULMAX8-RV32-NEXT: li a1, 64
; LMULMAX8-RV32-NEXT: vmerge.vxm v8, v10, a1, v0 ; LMULMAX8-RV32-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX8-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX8-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX8-RV32-NEXT: ret ; LMULMAX8-RV32-NEXT: ret
; ;
; LMULMAX8-RV64-LABEL: cttz_v2i64: ; LMULMAX8-RV64-LABEL: cttz_v2i64:
; LMULMAX8-RV64: # %bb.0: ; LMULMAX8-RV64: # %bb.0:
; LMULMAX8-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX8-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX8-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX8-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX8-RV64-NEXT: vrsub.vi v9, v8, 0 ; LMULMAX8-RV64-NEXT: vrsub.vi v9, v8, 0
▲ Show 20 Lines • Show All 571 Lines • ▼ Show 20 Lines
; ;
; LMULMAX2-RV32F-LABEL: cttz_v4i64: ; LMULMAX2-RV32F-LABEL: cttz_v4i64:
; LMULMAX2-RV32F: # %bb.0: ; LMULMAX2-RV32F: # %bb.0:
; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.i v10, 0 ; LMULMAX2-RV32F-NEXT: vmv.v.i v10, 0
; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vsub.vv v12, v10, v8 ; LMULMAX2-RV32F-NEXT: vmseq.vv v0, v8, v10
; LMULMAX2-RV32F-NEXT: vand.vv v12, v8, v12 ; LMULMAX2-RV32F-NEXT: vsub.vv v10, v10, v8
; LMULMAX2-RV32F-NEXT: vand.vv v8, v8, v10
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1 ; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v14, v12 ; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8
; LMULMAX2-RV32F-NEXT: fsrm a1 ; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v12, v14, 23 ; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vzext.vf2 v14, v12 ; LMULMAX2-RV32F-NEXT: vzext.vf2 v10, v8
; LMULMAX2-RV32F-NEXT: li a1, 127 ; LMULMAX2-RV32F-NEXT: li a1, 127
; LMULMAX2-RV32F-NEXT: vsub.vx v12, v14, a1 ; LMULMAX2-RV32F-NEXT: vsub.vx v8, v10, a1
; LMULMAX2-RV32F-NEXT: vmseq.vv v0, v8, v10
; LMULMAX2-RV32F-NEXT: li a1, 64 ; LMULMAX2-RV32F-NEXT: li a1, 64
; LMULMAX2-RV32F-NEXT: vmerge.vxm v8, v12, a1, v0 ; LMULMAX2-RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX2-RV32F-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32F-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: ret ; LMULMAX2-RV32F-NEXT: ret
; ;
; LMULMAX2-RV64F-LABEL: cttz_v4i64: ; LMULMAX2-RV64F-LABEL: cttz_v4i64:
; LMULMAX2-RV64F: # %bb.0: ; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV64F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: vrsub.vi v10, v8, 0 ; LMULMAX2-RV64F-NEXT: vrsub.vi v10, v8, 0
Show All 14 Lines
; ;
; LMULMAX2-RV32D-LABEL: cttz_v4i64: ; LMULMAX2-RV32D-LABEL: cttz_v4i64:
; LMULMAX2-RV32D: # %bb.0: ; LMULMAX2-RV32D: # %bb.0:
; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32D-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-RV32D-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32D-NEXT: vmv.v.i v10, 0 ; LMULMAX2-RV32D-NEXT: vmv.v.i v10, 0
; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32D-NEXT: vsub.vv v12, v10, v8 ; LMULMAX2-RV32D-NEXT: vmseq.vv v0, v8, v10
; LMULMAX2-RV32D-NEXT: vand.vv v12, v8, v12 ; LMULMAX2-RV32D-NEXT: vsub.vv v10, v10, v8
; LMULMAX2-RV32D-NEXT: vand.vv v8, v8, v10
; LMULMAX2-RV32D-NEXT: fsrmi a1, 1 ; LMULMAX2-RV32D-NEXT: fsrmi a1, 1
; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v12, v12 ; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV32D-NEXT: fsrm a1 ; LMULMAX2-RV32D-NEXT: fsrm a1
; LMULMAX2-RV32D-NEXT: li a1, 52 ; LMULMAX2-RV32D-NEXT: li a1, 52
; LMULMAX2-RV32D-NEXT: vsrl.vx v12, v12, a1 ; LMULMAX2-RV32D-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV32D-NEXT: li a1, 1023 ; LMULMAX2-RV32D-NEXT: li a1, 1023
; LMULMAX2-RV32D-NEXT: vsub.vx v12, v12, a1 ; LMULMAX2-RV32D-NEXT: vsub.vx v8, v8, a1
; LMULMAX2-RV32D-NEXT: vmseq.vv v0, v8, v10
; LMULMAX2-RV32D-NEXT: li a1, 64 ; LMULMAX2-RV32D-NEXT: li a1, 64
; LMULMAX2-RV32D-NEXT: vmerge.vxm v8, v12, a1, v0 ; LMULMAX2-RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX2-RV32D-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32D-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32D-NEXT: ret ; LMULMAX2-RV32D-NEXT: ret
; ;
; LMULMAX2-RV64D-LABEL: cttz_v4i64: ; LMULMAX2-RV64D-LABEL: cttz_v4i64:
; LMULMAX2-RV64D: # %bb.0: ; LMULMAX2-RV64D: # %bb.0:
; LMULMAX2-RV64D-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV64D-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64D-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64D-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64D-NEXT: vrsub.vi v10, v8, 0 ; LMULMAX2-RV64D-NEXT: vrsub.vi v10, v8, 0
Show All 13 Lines
; ;
; LMULMAX8-RV32-LABEL: cttz_v4i64: ; LMULMAX8-RV32-LABEL: cttz_v4i64:
; LMULMAX8-RV32: # %bb.0: ; LMULMAX8-RV32: # %bb.0:
; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX8-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX8-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX8-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX8-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX8-RV32-NEXT: vmv.v.i v10, 0 ; LMULMAX8-RV32-NEXT: vmv.v.i v10, 0
; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX8-RV32-NEXT: vsub.vv v12, v10, v8 ; LMULMAX8-RV32-NEXT: vmseq.vv v0, v8, v10
; LMULMAX8-RV32-NEXT: vand.vv v12, v8, v12 ; LMULMAX8-RV32-NEXT: vsub.vv v10, v10, v8
; LMULMAX8-RV32-NEXT: vand.vv v8, v8, v10
; LMULMAX8-RV32-NEXT: fsrmi a1, 1 ; LMULMAX8-RV32-NEXT: fsrmi a1, 1
; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v12, v12 ; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8-RV32-NEXT: fsrm a1 ; LMULMAX8-RV32-NEXT: fsrm a1
; LMULMAX8-RV32-NEXT: li a1, 52 ; LMULMAX8-RV32-NEXT: li a1, 52
; LMULMAX8-RV32-NEXT: vsrl.vx v12, v12, a1 ; LMULMAX8-RV32-NEXT: vsrl.vx v8, v8, a1
; LMULMAX8-RV32-NEXT: li a1, 1023 ; LMULMAX8-RV32-NEXT: li a1, 1023
; LMULMAX8-RV32-NEXT: vsub.vx v12, v12, a1 ; LMULMAX8-RV32-NEXT: vsub.vx v8, v8, a1
; LMULMAX8-RV32-NEXT: vmseq.vv v0, v8, v10
; LMULMAX8-RV32-NEXT: li a1, 64 ; LMULMAX8-RV32-NEXT: li a1, 64
; LMULMAX8-RV32-NEXT: vmerge.vxm v8, v12, a1, v0 ; LMULMAX8-RV32-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX8-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX8-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX8-RV32-NEXT: ret ; LMULMAX8-RV32-NEXT: ret
; ;
; LMULMAX8-RV64-LABEL: cttz_v4i64: ; LMULMAX8-RV64-LABEL: cttz_v4i64:
; LMULMAX8-RV64: # %bb.0: ; LMULMAX8-RV64: # %bb.0:
; LMULMAX8-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX8-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX8-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX8-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX8-RV64-NEXT: vrsub.vi v10, v8, 0 ; LMULMAX8-RV64-NEXT: vrsub.vi v10, v8, 0
▲ Show 20 Lines • Show All 1,282 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret i32 %b ret i32 %b
} }
define i64 @extractelt_v2i64(ptr %x) nounwind { define i64 @extractelt_v2i64(ptr %x) nounwind {
; RV32-LABEL: extractelt_v2i64: ; RV32-LABEL: extractelt_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: extractelt_v2i64: ; RV64-LABEL: extractelt_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
define i64 @extractelt_v4i64(ptr %x) nounwind { define i64 @extractelt_v4i64(ptr %x) nounwind {
; RV32-LABEL: extractelt_v4i64: ; RV32-LABEL: extractelt_v4i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m2, ta, ma
; RV32-NEXT: vslidedown.vi v8, v8, 3 ; RV32-NEXT: vslidedown.vi v8, v8, 3
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v10, v8, a0
; RV32-NEXT: vmv.x.s a1, v10
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: extractelt_v4i64: ; RV64-LABEL: extractelt_v4i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 3 ; RV64-NEXT: vslidedown.vi v8, v8, 3
▲ Show 20 Lines • Show All 629 Lines • ▼ Show 20 Lines
; RV64NOM-NEXT: vslidedown.vi v8, v8, 2 ; RV64NOM-NEXT: vslidedown.vi v8, v8, 2
; RV64NOM-NEXT: vmv.x.s a0, v8 ; RV64NOM-NEXT: vmv.x.s a0, v8
; RV64NOM-NEXT: slli a0, a0, 33 ; RV64NOM-NEXT: slli a0, a0, 33
; RV64NOM-NEXT: srli a0, a0, 35 ; RV64NOM-NEXT: srli a0, a0, 35
; RV64NOM-NEXT: ret ; RV64NOM-NEXT: ret
; ;
; RV64M-LABEL: extractelt_udiv_v4i32: ; RV64M-LABEL: extractelt_udiv_v4i32:
; RV64M: # %bb.0: ; RV64M: # %bb.0:
; RV64M-NEXT: lui a0, 322639
; RV64M-NEXT: addiw a0, a0, -945
; RV64M-NEXT: slli a0, a0, 32
; RV64M-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64M-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64M-NEXT: vslidedown.vi v8, v8, 2 ; RV64M-NEXT: vslidedown.vi v8, v8, 2
; RV64M-NEXT: vmv.x.s a0, v8 ; RV64M-NEXT: vmv.x.s a1, v8
; RV64M-NEXT: slli a0, a0, 32
; RV64M-NEXT: lui a1, 322639
; RV64M-NEXT: addiw a1, a1, -945
; RV64M-NEXT: slli a1, a1, 32 ; RV64M-NEXT: slli a1, a1, 32
; RV64M-NEXT: mulhu a0, a0, a1 ; RV64M-NEXT: mulhu a0, a1, a0
; RV64M-NEXT: srli a0, a0, 34 ; RV64M-NEXT: srli a0, a0, 34
; RV64M-NEXT: ret ; RV64M-NEXT: ret
%bo = udiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14> %bo = udiv <4 x i32> %x, <i32 11, i32 12, i32 13, i32 14>
%ext = extractelement <4 x i32> %bo, i32 2 %ext = extractelement <4 x i32> %bo, i32 2
ret i32 %ext ret i32 %ext
} }
define float @extractelt_fadd_v4f32(<4 x float> %x) { define float @extractelt_fadd_v4f32(<4 x float> %x) {
▲ Show 20 Lines • Show All 58 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll

Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Lines
} }
; FIXME: The nnan from fadd isn't propagating. ; FIXME: The nnan from fadd isn't propagating.
define <2 x half> @vfmax_v2f16_vv_nnana(<2 x half> %a, <2 x half> %b) { define <2 x half> @vfmax_v2f16_vv_nnana(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: vfmax_v2f16_vv_nnana: ; CHECK-LABEL: vfmax_v2f16_vv_nnana:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfadd.vv v10, v8, v8 ; CHECK-NEXT: vfadd.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vv v0, v10, v10 ; CHECK-NEXT: vmfeq.vv v0, v9, v9
; CHECK-NEXT: vmfeq.vv v8, v9, v9 ; CHECK-NEXT: vmfeq.vv v8, v10, v10
; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0 ; CHECK-NEXT: vmerge.vvm v11, v9, v10, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
; CHECK-NEXT: vfmax.vv v8, v8, v11 ; CHECK-NEXT: vfmax.vv v8, v11, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = fadd nnan <2 x half> %a, %a %c = fadd nnan <2 x half> %a, %a
%v = call <2 x half> @llvm.maximum.v2f16(<2 x half> %c, <2 x half> %b) %v = call <2 x half> @llvm.maximum.v2f16(<2 x half> %c, <2 x half> %b)
ret <2 x half> %v ret <2 x half> %v
} }
; FIXME: The nnan from fadd isn't propagating. ; FIXME: The nnan from fadd isn't propagating.
define <2 x half> @vfmax_v2f16_vv_nnanb(<2 x half> %a, <2 x half> %b) { define <2 x half> @vfmax_v2f16_vv_nnanb(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: vfmax_v2f16_vv_nnanb: ; CHECK-LABEL: vfmax_v2f16_vv_nnanb:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfadd.vv v10, v9, v9 ; CHECK-NEXT: vfadd.vv v10, v9, v9
; CHECK-NEXT: vmfeq.vv v0, v10, v10 ; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmfeq.vv v9, v8, v8 ; CHECK-NEXT: vmfeq.vv v9, v10, v10
; CHECK-NEXT: vmerge.vvm v11, v10, v8, v0 ; CHECK-NEXT: vmerge.vvm v11, v8, v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: vfmax.vv v8, v11, v8 ; CHECK-NEXT: vfmax.vv v8, v8, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = fadd nnan <2 x half> %b, %b %c = fadd nnan <2 x half> %b, %b
%v = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %c) %v = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %c)
ret <2 x half> %v ret <2 x half> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=-1 -stop-after=finalize-isel | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=-1 -stop-after=finalize-isel | FileCheck %s
define <2 x double> @foo(<2 x double> %x, <2 x double> %y) { define <2 x double> @foo(<2 x double> %x, <2 x double> %y) {
; CHECK-LABEL: name: foo ; CHECK-LABEL: name: foo
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $v8, $v9 ; CHECK-NEXT: liveins: $v8, $v9
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v9
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: [[PseudoVFADD_VV_M1_:%[0-9]+]]:vr = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFADD_VV_M1 $noreg, [[COPY1]], [[COPY]], 7, 2, 6 /* e64 */, 1 /* ta, mu */, implicit $frm
; CHECK-NEXT: [[PseudoVFADD_VV_M1_:%[0-9]+]]:vr = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFADD_VV_M1 [[DEF]], [[COPY1]], [[COPY]], 7, 2, 6 /* e64 */, 1 /* ta, mu */
; CHECK-NEXT: $v8 = COPY [[PseudoVFADD_VV_M1_]] ; CHECK-NEXT: $v8 = COPY [[PseudoVFADD_VV_M1_]]
; CHECK-NEXT: PseudoRET implicit $v8 ; CHECK-NEXT: PseudoRET implicit $v8
%1 = fadd fast <2 x double> %x, %y %1 = fadd fast <2 x double> %x, %y
ret <2 x double> %1 ret <2 x double> %1
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll

Show First 20 Lines • Show All 229 Lines • ▼ Show 20 Lines
} }
; FIXME: The nnan from fadd isn't propagating. ; FIXME: The nnan from fadd isn't propagating.
define <2 x half> @vfmin_v2f16_vv_nnana(<2 x half> %a, <2 x half> %b) { define <2 x half> @vfmin_v2f16_vv_nnana(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: vfmin_v2f16_vv_nnana: ; CHECK-LABEL: vfmin_v2f16_vv_nnana:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfadd.vv v10, v8, v8 ; CHECK-NEXT: vfadd.vv v10, v8, v8
; CHECK-NEXT: vmfeq.vv v0, v10, v10 ; CHECK-NEXT: vmfeq.vv v0, v9, v9
; CHECK-NEXT: vmfeq.vv v8, v9, v9 ; CHECK-NEXT: vmfeq.vv v8, v10, v10
; CHECK-NEXT: vmerge.vvm v11, v10, v9, v0 ; CHECK-NEXT: vmerge.vvm v11, v9, v10, v0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vvm v8, v9, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
; CHECK-NEXT: vfmin.vv v8, v8, v11 ; CHECK-NEXT: vfmin.vv v8, v11, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = fadd nnan <2 x half> %a, %a %c = fadd nnan <2 x half> %a, %a
%v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %c, <2 x half> %b) %v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %c, <2 x half> %b)
ret <2 x half> %v ret <2 x half> %v
} }
; FIXME: The nnan from fadd isn't propagating. ; FIXME: The nnan from fadd isn't propagating.
define <2 x half> @vfmin_v2f16_vv_nnanb(<2 x half> %a, <2 x half> %b) { define <2 x half> @vfmin_v2f16_vv_nnanb(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: vfmin_v2f16_vv_nnanb: ; CHECK-LABEL: vfmin_v2f16_vv_nnanb:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vfadd.vv v10, v9, v9 ; CHECK-NEXT: vfadd.vv v10, v9, v9
; CHECK-NEXT: vmfeq.vv v0, v10, v10 ; CHECK-NEXT: vmfeq.vv v0, v8, v8
; CHECK-NEXT: vmfeq.vv v9, v8, v8 ; CHECK-NEXT: vmfeq.vv v9, v10, v10
; CHECK-NEXT: vmerge.vvm v11, v10, v8, v0 ; CHECK-NEXT: vmerge.vvm v11, v8, v10, v0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: vfmin.vv v8, v11, v8 ; CHECK-NEXT: vfmin.vv v8, v8, v11
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%c = fadd nnan <2 x half> %b, %b %c = fadd nnan <2 x half> %b, %b
%v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %c) %v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %c)
ret <2 x half> %v ret <2 x half> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll

Show First 20 Lines • Show All 154 Lines • ▼ Show 20 Lines
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_16f16: ; LMULMAX1-LABEL: splat_zero_16f16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: vse16.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <16 x half> poison, half 0.0, i32 0 %a = insertelement <16 x half> poison, half 0.0, i32 0
%b = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> zeroinitializer %b = shufflevector <16 x half> %a, <16 x half> poison, <16 x i32> zeroinitializer
store <16 x half> %b, ptr %x store <16 x half> %b, ptr %x
ret void ret void
} }
define void @splat_zero_v8f32(ptr %x) { define void @splat_zero_v8f32(ptr %x) {
; LMULMAX2-LABEL: splat_zero_v8f32: ; LMULMAX2-LABEL: splat_zero_v8f32:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_v8f32: ; LMULMAX1-LABEL: splat_zero_v8f32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <8 x float> poison, float 0.0, i32 0 %a = insertelement <8 x float> poison, float 0.0, i32 0
%b = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> zeroinitializer %b = shufflevector <8 x float> %a, <8 x float> poison, <8 x i32> zeroinitializer
store <8 x float> %b, ptr %x store <8 x float> %b, ptr %x
ret void ret void
} }
define void @splat_zero_v4f64(ptr %x) { define void @splat_zero_v4f64(ptr %x) {
; LMULMAX2-LABEL: splat_zero_v4f64: ; LMULMAX2-LABEL: splat_zero_v4f64:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_v4f64: ; LMULMAX1-LABEL: splat_zero_v4f64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse64.v v8, (a0)
; LMULMAX1-NEXT: vse64.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vse64.v v8, (a0) ; LMULMAX1-NEXT: vse64.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <4 x double> poison, double 0.0, i32 0 %a = insertelement <4 x double> poison, double 0.0, i32 0
%b = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> zeroinitializer %b = shufflevector <4 x double> %a, <4 x double> poison, <4 x i32> zeroinitializer
store <4 x double> %b, ptr %x store <4 x double> %b, ptr %x
ret void ret void
} }
▲ Show 20 Lines • Show All 145 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines
} }
declare <8 x i32> @llvm.fptoui.sat.v8i32.v8f32(<8 x float>) declare <8 x i32> @llvm.fptoui.sat.v8i32.v8f32(<8 x float>)
define void @fp2si_v2f32_v2i64(ptr %x, ptr %y) { define void @fp2si_v2f32_v2i64(ptr %x, ptr %y) {
; CHECK-LABEL: fp2si_v2f32_v2i64: ; CHECK-LABEL: fp2si_v2f32_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x float>, ptr %x %a = load <2 x float>, ptr %x
%d = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f32(<2 x float> %a) %d = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f32(<2 x float> %a)
store <2 x i64> %d, ptr %y store <2 x i64> %d, ptr %y
ret void ret void
} }
declare <2 x i64> @llvm.fptosi.sat.v2i64.v2f32(<2 x float>) declare <2 x i64> @llvm.fptosi.sat.v2i64.v2f32(<2 x float>)
define void @fp2ui_v2f32_v2i64(ptr %x, ptr %y) { define void @fp2ui_v2f32_v2i64(ptr %x, ptr %y) {
; CHECK-LABEL: fp2ui_v2f32_v2i64: ; CHECK-LABEL: fp2ui_v2f32_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x float>, ptr %x %a = load <2 x float>, ptr %x
%d = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f32(<2 x float> %a) %d = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f32(<2 x float> %a)
store <2 x i64> %d, ptr %y store <2 x i64> %d, ptr %y
ret void ret void
} }
declare <2 x i64> @llvm.fptoui.sat.v2i64.v2f32(<2 x float>) declare <2 x i64> @llvm.fptoui.sat.v2i64.v2f32(<2 x float>)
define void @fp2si_v8f32_v8i64(ptr %x, ptr %y) { define void @fp2si_v8f32_v8i64(ptr %x, ptr %y) {
; ;
; CHECK-LABEL: fp2si_v8f32_v8i64: ; CHECK-LABEL: fp2si_v8f32_v8i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x float>, ptr %x %a = load <8 x float>, ptr %x
%d = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float> %a) %d = call <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float> %a)
store <8 x i64> %d, ptr %y store <8 x i64> %d, ptr %y
ret void ret void
} }
declare <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float>) declare <8 x i64> @llvm.fptosi.sat.v8i64.v8f32(<8 x float>)
define void @fp2ui_v8f32_v8i64(ptr %x, ptr %y) { define void @fp2ui_v8f32_v8i64(ptr %x, ptr %y) {
; ;
; CHECK-LABEL: fp2ui_v8f32_v8i64: ; CHECK-LABEL: fp2ui_v8f32_v8i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x float>, ptr %x %a = load <8 x float>, ptr %x
%d = call <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float> %a) %d = call <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float> %a)
store <8 x i64> %d, ptr %y store <8 x i64> %d, ptr %y
ret void ret void
} }
declare <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float>) declare <8 x i64> @llvm.fptoui.sat.v8i64.v8f32(<8 x float>)
define void @fp2si_v2f16_v2i64(ptr %x, ptr %y) { define void @fp2si_v2f16_v2i64(ptr %x, ptr %y) {
; CHECK-LABEL: fp2si_v2f16_v2i64: ; CHECK-LABEL: fp2si_v2f16_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v9 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x half>, ptr %x %a = load <2 x half>, ptr %x
%d = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f16(<2 x half> %a) %d = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f16(<2 x half> %a)
store <2 x i64> %d, ptr %y store <2 x i64> %d, ptr %y
ret void ret void
} }
declare <2 x i64> @llvm.fptosi.sat.v2i64.v2f16(<2 x half>) declare <2 x i64> @llvm.fptosi.sat.v2i64.v2f16(<2 x half>)
define void @fp2ui_v2f16_v2i64(ptr %x, ptr %y) { define void @fp2ui_v2f16_v2i64(ptr %x, ptr %y) {
; CHECK-LABEL: fp2ui_v2f16_v2i64: ; CHECK-LABEL: fp2ui_v2f16_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v9 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: vse64.v v8, (a1) ; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x half>, ptr %x %a = load <2 x half>, ptr %x
%d = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f16(<2 x half> %a) %d = call <2 x i64> @llvm.fptoui.sat.v2i64.v2f16(<2 x half> %a)
store <2 x i64> %d, ptr %y store <2 x i64> %d, ptr %y
ret void ret void
} }
declare <2 x i64> @llvm.fptoui.sat.v2i64.v2f16(<2 x half>) declare <2 x i64> @llvm.fptoui.sat.v2i64.v2f16(<2 x half>)
▲ Show 20 Lines • Show All 468 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
store <8 x i8> %d, ptr %y store <8 x i8> %d, ptr %y
ret void ret void
} }
declare <8 x i8> @llvm.fptoui.sat.v8i8.v8f64(<8 x double> %a) declare <8 x i8> @llvm.fptoui.sat.v8i8.v8f64(<8 x double> %a)
define void @fp2si_v2f64_v2i32(ptr %x, ptr %y) { define void @fp2si_v2f64_v2i32(ptr %x, ptr %y) {
; CHECK-LABEL: fp2si_v2f64_v2i32: ; CHECK-LABEL: fp2si_v2f64_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, ptr %x %a = load <2 x double>, ptr %x
%d = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %a) %d = call <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %a)
store <2 x i32> %d, ptr %y store <2 x i32> %d, ptr %y
ret void ret void
} }
declare <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double>) declare <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double>)
define void @fp2ui_v2f64_v2i32(ptr %x, ptr %y) { define void @fp2ui_v2f64_v2i32(ptr %x, ptr %y) {
; CHECK-LABEL: fp2ui_v2f64_v2i32: ; CHECK-LABEL: fp2ui_v2f64_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v9, v8
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, ptr %x %a = load <2 x double>, ptr %x
%d = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %a) %d = call <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %a)
store <2 x i32> %d, ptr %y store <2 x i32> %d, ptr %y
ret void ret void
} }
declare <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double>) declare <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fpext-vp.ll

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <15 x double> %v ret <15 x double> %v
} }
declare <32 x double> @llvm.vp.fpext.v32f64.v32f32(<32 x float>, <32 x i1>, i32) declare <32 x double> @llvm.vp.fpext.v32f64.v32f32(<32 x float>, <32 x i1>, i32)
define <32 x double> @vfpext_v32f32_v32f64(<32 x float> %a, <32 x i1> %m, i32 zeroext %vl) { define <32 x double> @vfpext_v32f32_v32f64(<32 x float> %a, <32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vfpext_v32f32_v32f64: ; CHECK-LABEL: vfpext_v32f32_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v16, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v8, 16
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vfwcvt.f.f.v v16, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB7_2: ; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vfwcvt.f.f.v v24, v8, v0.t ; CHECK-NEXT: vfwcvt.f.f.v v24, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 16
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vfwcvt.f.f.v v16, v8, v0.t
; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.fpext.v32f64.v32f32(<32 x float> %a, <32 x i1> %m, i32 %vl) %v = call <32 x double> @llvm.vp.fpext.v32f64.v32f32(<32 x float> %a, <32 x i1> %m, i32 %vl)
ret <32 x double> %v ret <32 x double> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll

Show First 20 Lines • Show All 310 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <4 x i64> %v ret <4 x i64> %v
} }
declare <32 x i64> @llvm.vp.fptosi.v32i64.v32f64(<32 x double>, <32 x i1>, i32) declare <32 x i64> @llvm.vp.fptosi.v32i64.v32f64(<32 x double>, <32 x i1>, i32)
define <32 x i64> @vfptosi_v32i64_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vfptosi_v32i64_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_v32i64_v32f64: ; CHECK-LABEL: vfptosi_v32i64_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB25_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB25_2: ; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t ; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.fptosi.v32i64.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) %v = call <32 x i64> @llvm.vp.fptosi.v32i64.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vfptosi_v32i64_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) { define <32 x i64> @vfptosi_v32i64_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_v32i64_v32f64_unmasked: ; CHECK-LABEL: vfptosi_v32i64_v32f64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 18 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll

Show First 20 Lines • Show All 310 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <4 x i64> %v ret <4 x i64> %v
} }
declare <32 x i64> @llvm.vp.fptoui.v32i64.v32f64(<32 x double>, <32 x i1>, i32) declare <32 x i64> @llvm.vp.fptoui.v32i64.v32f64(<32 x double>, <32 x i1>, i32)
define <32 x i64> @vfptoui_v32i64_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vfptoui_v32i64_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_v32i64_v32f64: ; CHECK-LABEL: vfptoui_v32i64_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vfcvt.rtz.xu.f.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB25_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB25_2: ; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfcvt.rtz.xu.f.v v8, v8, v0.t ; CHECK-NEXT: vfcvt.rtz.xu.f.v v16, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.fptoui.v32i64.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) %v = call <32 x i64> @llvm.vp.fptoui.v32i64.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vfptoui_v32i64_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) { define <32 x i64> @vfptoui_v32i64_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfptoui_v32i64_v32f64_unmasked: ; CHECK-LABEL: vfptoui_v32i64_v32f64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 18 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptrunc-vp.ll

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <15 x float> %v ret <15 x float> %v
} }
declare <32 x float> @llvm.vp.fptrunc.v32f64.v32f32(<32 x double>, <32 x i1>, i32) declare <32 x float> @llvm.vp.fptrunc.v32f64.v32f32(<32 x double>, <32 x i1>, i32)
define <32 x float> @vfptrunc_v32f32_v32f64(<32 x double> %a, <32 x i1> %m, i32 zeroext %vl) { define <32 x float> @vfptrunc_v32f32_v32f64(<32 x double> %a, <32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vfptrunc_v32f32_v32f64: ; CHECK-LABEL: vfptrunc_v32f32_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v28, v0 ; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v12, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vfncvt.f.f.w v24, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB7_2: ; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v8, v24, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v28 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vfncvt.f.f.w v16, v8, v0.t ; CHECK-NEXT: vfncvt.f.f.w v24, v16, v0.t
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vslideup.vi v16, v24, 16 ; CHECK-NEXT: vslideup.vi v8, v24, 16
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x float> @llvm.vp.fptrunc.v32f64.v32f32(<32 x double> %a, <32 x i1> %m, i32 %vl) %v = call <32 x float> @llvm.vp.fptrunc.v32f64.v32f32(<32 x double> %a, <32 x i1> %m, i32 %vl)
ret <32 x float> %v ret <32 x float> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fshr-fshl-vp.ll

Show First 20 Lines • Show All 796 Lines • ▼ Show 20 Lines
; RV32-LABEL: fshr_v16i64: ; RV32-LABEL: fshr_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3 ; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: sub sp, sp, a2 ; RV32-NEXT: sub sp, sp, a2
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vle64.v v24, (a0) ; RV32-NEXT: vle64.v v24, (a0)
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-NEXT: li a0, 63
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsll.vi v16, v8, 1, v0.t ; RV32-NEXT: vand.vx v8, v24, a0, v0.t
; RV32-NEXT: li a0, 32 ; RV32-NEXT: vsrl.vv v16, v16, v8, v0.t
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v8, -1 ; RV32-NEXT: vmv.v.i v8, -1
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vxor.vv v8, v24, v8, v0.t ; RV32-NEXT: vxor.vv v8, v24, v8, v0.t
; RV32-NEXT: li a0, 63
; RV32-NEXT: vand.vx v8, v8, a0, v0.t ; RV32-NEXT: vand.vx v8, v8, a0, v0.t
; RV32-NEXT: vsll.vv v8, v16, v8, v0.t
; RV32-NEXT: vand.vx v16, v24, a0, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsrl.vv v16, v24, v16, v0.t ; RV32-NEXT: vsll.vi v24, v24, 1, v0.t
; RV32-NEXT: vsll.vv v8, v24, v8, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t ; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: fshr_v16i64: ; RV64-LABEL: fshr_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 3 ; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: sub sp, sp, a2 ; RV64-NEXT: sub sp, sp, a2
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vle64.v v24, (a0) ; RV64-NEXT: vle64.v v24, (a0)
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vsll.vi v16, v8, 1, v0.t ; RV64-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV64-NEXT: li a0, 63 ; RV64-NEXT: li a0, 63
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vand.vx v8, v24, a0, v0.t
; RV64-NEXT: vsrl.vv v16, v16, v8, v0.t
; RV64-NEXT: vnot.v v8, v24, v0.t ; RV64-NEXT: vnot.v v8, v24, v0.t
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v8, a0, v0.t
; RV64-NEXT: vsll.vv v8, v16, v8, v0.t
; RV64-NEXT: vand.vx v16, v24, a0, v0.t
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV64-NEXT: vsrl.vv v16, v24, v16, v0.t ; RV64-NEXT: vsll.vi v24, v24, 1, v0.t
; RV64-NEXT: vsll.vv v8, v24, v8, v0.t
; RV64-NEXT: vor.vv v8, v8, v16, v0.t ; RV64-NEXT: vor.vv v8, v8, v16, v0.t
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3 ; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%res = call <16 x i64> @llvm.vp.fshr.v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 %evl) %res = call <16 x i64> @llvm.vp.fshr.v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 %evl)
ret <16 x i64> %res ret <16 x i64> %res
} }
declare <16 x i64> @llvm.vp.fshl.v16i64(<16 x i64>, <16 x i64>, <16 x i64>, <16 x i1>, i32) declare <16 x i64> @llvm.vp.fshl.v16i64(<16 x i64>, <16 x i64>, <16 x i64>, <16 x i1>, i32)
define <16 x i64> @fshl_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 zeroext %evl) { define <16 x i64> @fshl_v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: fshl_v16i64: ; RV32-LABEL: fshl_v16i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a2, vlenb
; RV32-NEXT: slli a2, a2, 3 ; RV32-NEXT: slli a2, a2, 3
; RV32-NEXT: sub sp, sp, a2 ; RV32-NEXT: sub sp, sp, a2
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: addi a2, sp, 16
; RV32-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vle64.v v24, (a0) ; RV32-NEXT: vle64.v v24, (a0)
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vmv8r.v v16, v8
; RV32-NEXT: li a0, 63
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v16, 1, v0.t ; RV32-NEXT: vand.vx v8, v24, a0, v0.t
; RV32-NEXT: li a0, 32 ; RV32-NEXT: vsll.vv v8, v16, v8, v0.t
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-NEXT: li a2, 32
; RV32-NEXT: vmv.v.i v8, -1 ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, -1
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vxor.vv v8, v24, v8, v0.t ; RV32-NEXT: vxor.vv v16, v24, v16, v0.t
; RV32-NEXT: li a0, 63 ; RV32-NEXT: vand.vx v16, v16, a0, v0.t
; RV32-NEXT: vand.vx v8, v8, a0, v0.t
; RV32-NEXT: vsrl.vv v8, v16, v8, v0.t
; RV32-NEXT: vand.vx v16, v24, a0, v0.t
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vsll.vv v16, v24, v16, v0.t ; RV32-NEXT: vsrl.vi v24, v24, 1, v0.t
; RV32-NEXT: vor.vv v8, v16, v8, v0.t ; RV32-NEXT: vsrl.vv v16, v24, v16, v0.t
; RV32-NEXT: vor.vv v8, v8, v16, v0.t
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: fshl_v16i64: ; RV64-LABEL: fshl_v16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 3 ; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: sub sp, sp, a2 ; RV64-NEXT: sub sp, sp, a2
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vle64.v v24, (a0) ; RV64-NEXT: vle64.v v24, (a0)
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vsrl.vi v16, v16, 1, v0.t ; RV64-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV64-NEXT: vmv8r.v v16, v8
; RV64-NEXT: li a0, 63 ; RV64-NEXT: li a0, 63
; RV64-NEXT: vnot.v v8, v24, v0.t ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vand.vx v8, v8, a0, v0.t ; RV64-NEXT: vand.vx v8, v24, a0, v0.t
; RV64-NEXT: vsrl.vv v8, v16, v8, v0.t ; RV64-NEXT: vsll.vv v8, v16, v8, v0.t
; RV64-NEXT: vand.vx v16, v24, a0, v0.t ; RV64-NEXT: vnot.v v16, v24, v0.t
; RV64-NEXT: vand.vx v16, v16, a0, v0.t
; RV64-NEXT: addi a0, sp, 16 ; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV64-NEXT: vsll.vv v16, v24, v16, v0.t ; RV64-NEXT: vsrl.vi v24, v24, 1, v0.t
; RV64-NEXT: vor.vv v8, v16, v8, v0.t ; RV64-NEXT: vsrl.vv v16, v24, v16, v0.t
; RV64-NEXT: vor.vv v8, v8, v16, v0.t
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3 ; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%res = call <16 x i64> @llvm.vp.fshl.v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 %evl) %res = call <16 x i64> @llvm.vp.fshl.v16i64(<16 x i64> %a, <16 x i64> %b, <16 x i64> %c, <16 x i1> %m, i32 %evl)
ret <16 x i64> %res ret <16 x i64> %res
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll

Show All 16 Lines
} }
define <1 x i1> @insertelt_idx_v1i1(<1 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind { define <1 x i1> @insertelt_idx_v1i1(<1 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind {
; CHECK-LABEL: insertelt_idx_v1i1: ; CHECK-LABEL: insertelt_idx_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf8, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <1 x i1> %x, i1 %elt, i32 %idx %y = insertelement <1 x i1> %x, i1 %elt, i32 %idx
ret <1 x i1> %y ret <1 x i1> %y
} }
Show All 14 Lines
} }
define <2 x i1> @insertelt_idx_v2i1(<2 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind { define <2 x i1> @insertelt_idx_v2i1(<2 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind {
; CHECK-LABEL: insertelt_idx_v2i1: ; CHECK-LABEL: insertelt_idx_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf8, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <2 x i1> %x, i1 %elt, i32 %idx %y = insertelement <2 x i1> %x, i1 %elt, i32 %idx
ret <2 x i1> %y ret <2 x i1> %y
} }
Show All 16 Lines
} }
define <8 x i1> @insertelt_idx_v8i1(<8 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind { define <8 x i1> @insertelt_idx_v8i1(<8 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind {
; CHECK-LABEL: insertelt_idx_v8i1: ; CHECK-LABEL: insertelt_idx_v8i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf2, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <8 x i1> %x, i1 %elt, i32 %idx %y = insertelement <8 x i1> %x, i1 %elt, i32 %idx
ret <8 x i1> %y ret <8 x i1> %y
} }
define <64 x i1> @insertelt_v64i1(<64 x i1> %x, i1 %elt) nounwind { define <64 x i1> @insertelt_v64i1(<64 x i1> %x, i1 %elt) nounwind {
; CHECK-LABEL: insertelt_v64i1: ; CHECK-LABEL: insertelt_v64i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: vsetivli zero, 2, e8, m4, tu, ma ; CHECK-NEXT: vsetivli zero, 2, e8, m4, tu, ma
; CHECK-NEXT: vslideup.vi v12, v8, 1 ; CHECK-NEXT: vslideup.vi v8, v12, 1
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: vand.vi v8, v12, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <64 x i1> %x, i1 %elt, i64 1 %y = insertelement <64 x i1> %x, i1 %elt, i64 1
ret <64 x i1> %y ret <64 x i1> %y
} }
define <64 x i1> @insertelt_idx_v64i1(<64 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind { define <64 x i1> @insertelt_idx_v64i1(<64 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind {
; CHECK-LABEL: insertelt_idx_v64i1: ; CHECK-LABEL: insertelt_idx_v64i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m1, ta, ma
; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; CHECK-NEXT: vmv.v.i v12, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v12, v12, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vmv.s.x v12, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: addi a0, a1, 1
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, ma
; CHECK-NEXT: vslideup.vx v12, v8, a1 ; CHECK-NEXT: vslideup.vx v8, v12, a1
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; CHECK-NEXT: vand.vi v8, v12, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <64 x i1> %x, i1 %elt, i32 %idx %y = insertelement <64 x i1> %x, i1 %elt, i32 %idx
ret <64 x i1> %y ret <64 x i1> %y
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Show First 20 Lines • Show All 416 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i0we4: ; CHECK-LABEL: splat_ve2_we0_ins_i0we4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: li a0, 67
; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 4 ; CHECK-NEXT: vmv.v.i v8, 4
; CHECK-NEXT: li a0, 67
; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t ; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 12, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 12, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
Show All 28 Lines; RV64-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i2we4: ; CHECK-LABEL: splat_ve2_we0_ins_i2we4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: vmv.v.i v10, 4
; CHECK-NEXT: vmv.v.i v8, 4
; CHECK-NEXT: vmv.v.i v11, 0 ; CHECK-NEXT: vmv.v.i v11, 0
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma ; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v11, v8, 2 ; CHECK-NEXT: vslideup.vi v11, v10, 2
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: li a0, 70 ; CHECK-NEXT: li a0, 70
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t ; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) {
; RV32-LABEL: splat_ve2_we0_ins_i2ve4_i5we6: ; RV32-LABEL: splat_ve2_we0_ins_i2ve4_i5we6:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: lui a0, 8256
; RV32-NEXT: addi a0, a0, 2
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vmv.v.x v11, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vrgather.vv v10, v8, v11 ; RV32-NEXT: vmv.v.i v10, 6
; RV32-NEXT: vmv.v.i v8, 6
; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 6, e8, mf2, tu, ma ; RV32-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
; RV32-NEXT: vslideup.vi v11, v8, 5 ; RV32-NEXT: vslideup.vi v11, v10, 5
; RV32-NEXT: lui a0, 8256
; RV32-NEXT: addi a0, a0, 2
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vmv.v.x v12, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: li a0, 98 ; RV32-NEXT: li a0, 98
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vrgather.vv v10, v8, v12
; RV32-NEXT: vrgather.vv v10, v9, v11, v0.t ; RV32-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: splat_ve2_we0_ins_i2ve4_i5we6: ; RV64-LABEL: splat_ve2_we0_ins_i2ve4_i5we6:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, 8256
; RV64-NEXT: addiw a0, a0, 2
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vmv.v.x v11, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-NEXT: vrgather.vv v10, v8, v11 ; RV64-NEXT: vmv.v.i v10, 6
; RV64-NEXT: vmv.v.i v8, 6
; RV64-NEXT: vmv.v.i v11, 0 ; RV64-NEXT: vmv.v.i v11, 0
; RV64-NEXT: vsetivli zero, 6, e8, mf2, tu, ma ; RV64-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
; RV64-NEXT: vslideup.vi v11, v8, 5 ; RV64-NEXT: vslideup.vi v11, v10, 5
; RV64-NEXT: lui a0, 8256
; RV64-NEXT: addiw a0, a0, 2
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vmv.v.x v12, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: li a0, 98 ; RV64-NEXT: li a0, 98
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vrgather.vv v10, v8, v12
; RV64-NEXT: vrgather.vv v10, v9, v11, v0.t ; RV64-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 14, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 14, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @widen_splat_ve3(<4 x i8> %v) { define <8 x i8> @widen_splat_ve3(<4 x i8> %v) {
▲ Show 20 Lines • Show All 249 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

Show First 20 Lines • Show All 333 Lines • ▼ Show 20 Lines
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_v32i8: ; LMULMAX1-LABEL: splat_zero_v32i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: vse8.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> poison, i8 0, i32 0 %a = insertelement <32 x i8> poison, i8 0, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> zeroinitializer %b = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> zeroinitializer
store <32 x i8> %b, ptr %x store <32 x i8> %b, ptr %x
ret void ret void
} }
Show All 11 Lines
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_v16i16: ; LMULMAX1-LABEL: splat_zero_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: vse16.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> poison, i16 0, i32 0 %a = insertelement <16 x i16> poison, i16 0, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> zeroinitializer %b = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> zeroinitializer
store <16 x i16> %b, ptr %x store <16 x i16> %b, ptr %x
ret void ret void
} }
Show All 11 Lines
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_zero_v8i32: ; LMULMAX1-LABEL: splat_zero_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, 0 ; LMULMAX1-NEXT: vmv.v.i v8, 0
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> poison, i32 0, i32 0 %a = insertelement <8 x i32> poison, i32 0, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> zeroinitializer %b = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> zeroinitializer
store <8 x i32> %b, ptr %x store <8 x i32> %b, ptr %x
ret void ret void
} }
Show All 11 Lines
; LMULMAX2-NEXT: vmv.v.i v8, 0 ; LMULMAX2-NEXT: vmv.v.i v8, 0
; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: splat_zero_v4i64: ; LMULMAX1-RV32-LABEL: splat_zero_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0 ; LMULMAX1-RV32-NEXT: vmv.v.i v8, 0
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a0, a0, 16
; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: splat_zero_v4i64: ; LMULMAX1-RV64-LABEL: splat_zero_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0 ; LMULMAX1-RV64-NEXT: vmv.v.i v8, 0
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a0, a0, 16
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = insertelement <4 x i64> poison, i64 0, i32 0 %a = insertelement <4 x i64> poison, i64 0, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> zeroinitializer %b = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> zeroinitializer
store <4 x i64> %b, ptr %x store <4 x i64> %b, ptr %x
ret void ret void
} }
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
; LMULMAX2-NEXT: vmv.v.i v8, -1 ; LMULMAX2-NEXT: vmv.v.i v8, -1
; LMULMAX2-NEXT: vse8.v v8, (a0) ; LMULMAX2-NEXT: vse8.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_allones_v32i8: ; LMULMAX1-LABEL: splat_allones_v32i8:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, -1 ; LMULMAX1-NEXT: vmv.v.i v8, -1
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: vse8.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vse8.v v8, (a0) ; LMULMAX1-NEXT: vse8.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <32 x i8> poison, i8 -1, i32 0 %a = insertelement <32 x i8> poison, i8 -1, i32 0
%b = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> zeroinitializer %b = shufflevector <32 x i8> %a, <32 x i8> poison, <32 x i32> zeroinitializer
store <32 x i8> %b, ptr %x store <32 x i8> %b, ptr %x
ret void ret void
} }
Show All 11 Lines
; LMULMAX2-NEXT: vmv.v.i v8, -1 ; LMULMAX2-NEXT: vmv.v.i v8, -1
; LMULMAX2-NEXT: vse16.v v8, (a0) ; LMULMAX2-NEXT: vse16.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_allones_v16i16: ; LMULMAX1-LABEL: splat_allones_v16i16:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, -1 ; LMULMAX1-NEXT: vmv.v.i v8, -1
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: vse16.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vse16.v v8, (a0) ; LMULMAX1-NEXT: vse16.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <16 x i16> poison, i16 -1, i32 0 %a = insertelement <16 x i16> poison, i16 -1, i32 0
%b = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> zeroinitializer %b = shufflevector <16 x i16> %a, <16 x i16> poison, <16 x i32> zeroinitializer
store <16 x i16> %b, ptr %x store <16 x i16> %b, ptr %x
ret void ret void
} }
Show All 11 Lines
; LMULMAX2-NEXT: vmv.v.i v8, -1 ; LMULMAX2-NEXT: vmv.v.i v8, -1
; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-LABEL: splat_allones_v8i32: ; LMULMAX1-LABEL: splat_allones_v8i32:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-NEXT: vmv.v.i v8, -1 ; LMULMAX1-NEXT: vmv.v.i v8, -1
; LMULMAX1-NEXT: addi a1, a0, 16 ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: vse32.v v8, (a1) ; LMULMAX1-NEXT: addi a0, a0, 16
; LMULMAX1-NEXT: vse32.v v8, (a0) ; LMULMAX1-NEXT: vse32.v v8, (a0)
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
%a = insertelement <8 x i32> poison, i32 -1, i32 0 %a = insertelement <8 x i32> poison, i32 -1, i32 0
%b = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> zeroinitializer %b = shufflevector <8 x i32> %a, <8 x i32> poison, <8 x i32> zeroinitializer
store <8 x i32> %b, ptr %x store <8 x i32> %b, ptr %x
ret void ret void
} }
Show All 11 Lines
; LMULMAX2-NEXT: vmv.v.i v8, -1 ; LMULMAX2-NEXT: vmv.v.i v8, -1
; LMULMAX2-NEXT: vse64.v v8, (a0) ; LMULMAX2-NEXT: vse64.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: splat_allones_v4i64: ; LMULMAX1-RV32-LABEL: splat_allones_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmv.v.i v8, -1 ; LMULMAX1-RV32-NEXT: vmv.v.i v8, -1
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV32-NEXT: addi a0, a0, 16
; LMULMAX1-RV32-NEXT: vse32.v v8, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: splat_allones_v4i64: ; LMULMAX1-RV64-LABEL: splat_allones_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vmv.v.i v8, -1 ; LMULMAX1-RV64-NEXT: vmv.v.i v8, -1
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v8, (a1) ; LMULMAX1-RV64-NEXT: addi a0, a0, 16
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = insertelement <4 x i64> poison, i64 -1, i32 0 %a = insertelement <4 x i64> poison, i64 -1, i32 0
%b = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> zeroinitializer %b = shufflevector <4 x i64> %a, <4 x i64> poison, <4 x i32> zeroinitializer
store <4 x i64> %b, ptr %x store <4 x i64> %b, ptr %x
ret void ret void
} }
▲ Show 20 Lines • Show All 232 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,099 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @mulhu_v16i8(ptr %x) { define void @mulhu_v16i8(ptr %x) {
; RV32-LABEL: mulhu_v16i8: ; RV32-LABEL: mulhu_v16i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vle8.v v8, (a0) ; RV32-NEXT: vle8.v v8, (a0)
; RV32-NEXT: lui a1, 3
; RV32-NEXT: addi a1, a1, -2044
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a1
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: li a1, -128
; RV32-NEXT: vmerge.vxm v10, v9, a1, v0
; RV32-NEXT: lui a1, 1 ; RV32-NEXT: lui a1, 1
; RV32-NEXT: addi a2, a1, 32 ; RV32-NEXT: addi a2, a1, 32
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: lui a2, %hi(.LCPI65_0) ; RV32-NEXT: lui a2, %hi(.LCPI65_0)
; RV32-NEXT: addi a2, a2, %lo(.LCPI65_0) ; RV32-NEXT: addi a2, a2, %lo(.LCPI65_0)
; RV32-NEXT: vle8.v v9, (a2) ; RV32-NEXT: vle8.v v11, (a2)
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-NEXT: vmerge.vim v11, v10, 1, v0 ; RV32-NEXT: vsrl.vv v9, v8, v9
; RV32-NEXT: vsrl.vv v11, v8, v11 ; RV32-NEXT: vmulhu.vv v9, v9, v11
; RV32-NEXT: vmulhu.vv v9, v11, v9
; RV32-NEXT: vsub.vv v8, v8, v9 ; RV32-NEXT: vsub.vv v8, v8, v9
; RV32-NEXT: lui a2, 3
; RV32-NEXT: addi a2, a2, -2044
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: li a2, -128
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmerge.vxm v10, v10, a2, v0
; RV32-NEXT: vmulhu.vv v8, v8, v10 ; RV32-NEXT: vmulhu.vv v8, v8, v10
; RV32-NEXT: vadd.vv v8, v8, v9 ; RV32-NEXT: vadd.vv v8, v8, v9
; RV32-NEXT: li a2, 513 ; RV32-NEXT: li a2, 513
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a2 ; RV32-NEXT: vmv.v.x v0, a2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 4 ; RV32-NEXT: vmv.v.i v9, 4
; RV32-NEXT: vmerge.vim v9, v9, 1, v0 ; RV32-NEXT: vmerge.vim v9, v9, 1, v0
Show All 11 Lines
; RV32-NEXT: vsrl.vv v8, v8, v9 ; RV32-NEXT: vsrl.vv v8, v8, v9
; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: vse8.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mulhu_v16i8: ; RV64-LABEL: mulhu_v16i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vle8.v v8, (a0) ; RV64-NEXT: vle8.v v8, (a0)
; RV64-NEXT: lui a1, 3
; RV64-NEXT: addiw a1, a1, -2044
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.i v9, 0
; RV64-NEXT: li a1, -128
; RV64-NEXT: vmerge.vxm v10, v9, a1, v0
; RV64-NEXT: lui a1, 1 ; RV64-NEXT: lui a1, 1
; RV64-NEXT: addiw a2, a1, 32 ; RV64-NEXT: addiw a2, a1, 32
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a2 ; RV64-NEXT: vmv.v.x v0, a2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: lui a2, %hi(.LCPI65_0) ; RV64-NEXT: lui a2, %hi(.LCPI65_0)
; RV64-NEXT: addi a2, a2, %lo(.LCPI65_0) ; RV64-NEXT: addi a2, a2, %lo(.LCPI65_0)
; RV64-NEXT: vle8.v v9, (a2) ; RV64-NEXT: vle8.v v11, (a2)
; RV64-NEXT: vmv.v.i v10, 0 ; RV64-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-NEXT: vmerge.vim v11, v10, 1, v0 ; RV64-NEXT: vsrl.vv v9, v8, v9
; RV64-NEXT: vsrl.vv v11, v8, v11 ; RV64-NEXT: vmulhu.vv v9, v9, v11
; RV64-NEXT: vmulhu.vv v9, v11, v9
; RV64-NEXT: vsub.vv v8, v8, v9 ; RV64-NEXT: vsub.vv v8, v8, v9
; RV64-NEXT: lui a2, 3
; RV64-NEXT: addiw a2, a2, -2044
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a2
; RV64-NEXT: li a2, -128
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmerge.vxm v10, v10, a2, v0
; RV64-NEXT: vmulhu.vv v8, v8, v10 ; RV64-NEXT: vmulhu.vv v8, v8, v10
; RV64-NEXT: vadd.vv v8, v8, v9 ; RV64-NEXT: vadd.vv v8, v8, v9
; RV64-NEXT: li a2, 513 ; RV64-NEXT: li a2, 513
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a2 ; RV64-NEXT: vmv.v.x v0, a2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.i v9, 4 ; RV64-NEXT: vmv.v.i v9, 4
; RV64-NEXT: vmerge.vim v9, v9, 1, v0 ; RV64-NEXT: vmerge.vim v9, v9, 1, v0
Show All 17 Lines; RV64-NEXT: ret
ret void ret void
} }
define void @mulhu_v8i16(ptr %x) { define void @mulhu_v8i16(ptr %x) {
; CHECK-LABEL: mulhu_v8i16: ; CHECK-LABEL: mulhu_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vmv.v.i v9, 1 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv.s.x v10, a1
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.i v11, 1
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma ; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; CHECK-NEXT: vmv1r.v v11, v10 ; CHECK-NEXT: vslideup.vi v9, v11, 6
; CHECK-NEXT: vslideup.vi v11, v9, 6
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: lui a1, %hi(.LCPI66_0) ; CHECK-NEXT: lui a1, %hi(.LCPI66_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI66_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI66_0)
; CHECK-NEXT: vle16.v v12, (a1) ; CHECK-NEXT: vle16.v v12, (a1)
; CHECK-NEXT: vsrl.vv v11, v8, v11 ; CHECK-NEXT: vsrl.vv v9, v8, v9
; CHECK-NEXT: vmulhu.vv v11, v11, v12 ; CHECK-NEXT: vmulhu.vv v9, v9, v12
; CHECK-NEXT: vsub.vv v8, v8, v11 ; CHECK-NEXT: vsub.vv v8, v8, v9
; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma
; CHECK-NEXT: vmv.s.x v10, a1
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vmulhu.vv v8, v8, v10 ; CHECK-NEXT: vmulhu.vv v8, v8, v10
; CHECK-NEXT: vadd.vv v8, v8, v11 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: li a1, 33 ; CHECK-NEXT: li a1, 33
; CHECK-NEXT: vmv.v.x v0, a1 ; CHECK-NEXT: vmv.v.x v0, a1
; CHECK-NEXT: vmv.v.i v10, 3 ; CHECK-NEXT: vmv.v.i v9, 3
; CHECK-NEXT: vmerge.vim v10, v10, 2, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 2, v0
; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma ; CHECK-NEXT: vsetivli zero, 7, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vi v10, v9, 6 ; CHECK-NEXT: vslideup.vi v9, v11, 6
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsrl.vv v8, v8, v10 ; CHECK-NEXT: vsrl.vv v8, v8, v9
; CHECK-NEXT: vse16.v v8, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x i16>, ptr %x %a = load <8 x i16>, ptr %x
%b = udiv <8 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15> %b = udiv <8 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
store <8 x i16> %b, ptr %x store <8 x i16> %b, ptr %x
ret void ret void
} }
Show All 25 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @mulhu_v4i32(ptr %x) { define void @mulhu_v4i32(ptr %x) {
; CHECK-LABEL: mulhu_v4i32: ; CHECK-LABEL: mulhu_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, 524288
; CHECK-NEXT: vmv.s.x v9, a1
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma
; CHECK-NEXT: vslideup.vi v10, v9, 2
; CHECK-NEXT: lui a1, %hi(.LCPI68_0) ; CHECK-NEXT: lui a1, %hi(.LCPI68_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI68_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI68_0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v9, (a1) ; CHECK-NEXT: vle32.v v9, (a1)
; CHECK-NEXT: vmulhu.vv v9, v8, v9 ; CHECK-NEXT: vmulhu.vv v9, v8, v9
; CHECK-NEXT: vsub.vv v8, v8, v9 ; CHECK-NEXT: vsub.vv v8, v8, v9
; CHECK-NEXT: lui a1, 524288 ; CHECK-NEXT: vmulhu.vv v8, v8, v10
; CHECK-NEXT: vmv.s.x v10, a1
; CHECK-NEXT: vmv.v.i v11, 0
; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma
; CHECK-NEXT: vslideup.vi v11, v10, 2
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmulhu.vv v8, v8, v11
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vmv.v.i v9, 2 ; CHECK-NEXT: vmv.v.i v9, 2
; CHECK-NEXT: li a1, 1 ; CHECK-NEXT: li a1, 1
; CHECK-NEXT: vslide1down.vx v9, v9, a1 ; CHECK-NEXT: vslide1down.vx v9, v9, a1
; CHECK-NEXT: vsrl.vv v8, v8, v9 ; CHECK-NEXT: vsrl.vv v8, v8, v9
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x i32>, ptr %x %a = load <4 x i32>, ptr %x
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
ret void ret void
} }
define void @mulhs_v6i16(ptr %x) { define void @mulhs_v6i16(ptr %x) {
; CHECK-LABEL: mulhs_v6i16: ; CHECK-LABEL: mulhs_v6i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v0, 6
; CHECK-NEXT: vmv.v.i v9, -7
; CHECK-NEXT: vmerge.vim v9, v9, 7, v0
; CHECK-NEXT: vdiv.vv v9, v8, v9
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v10, 7 ; CHECK-NEXT: vmv.v.i v9, 7
; CHECK-NEXT: vid.v v11 ; CHECK-NEXT: vid.v v10
; CHECK-NEXT: li a1, -14 ; CHECK-NEXT: li a1, -14
; CHECK-NEXT: vmadd.vx v11, a1, v10 ; CHECK-NEXT: vmadd.vx v10, a1, v9
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 4 ; CHECK-NEXT: vslidedown.vi v9, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vdiv.vv v8, v8, v11 ; CHECK-NEXT: vdiv.vv v9, v9, v10
; CHECK-NEXT: vmv.v.i v0, 6
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v10, -7
; CHECK-NEXT: vmerge.vim v10, v10, 7, v0
; CHECK-NEXT: vdiv.vv v8, v8, v10
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 4 ; CHECK-NEXT: vslideup.vi v8, v9, 4
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vse16.v v9, (a0) ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <6 x i16>, ptr %x %a = load <6 x i16>, ptr %x
%b = sdiv <6 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7> %b = sdiv <6 x i16> %a, <i16 -7, i16 7, i16 7, i16 -7, i16 7, i16 -7>
store <6 x i16> %b, ptr %x store <6 x i16> %b, ptr %x
ret void ret void
} }
define void @mulhs_v4i32(ptr %x) { define void @mulhs_v4i32(ptr %x) {
▲ Show 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vmulh.vv v9, v8, v9 ; RV32-NEXT: vmulh.vv v9, v8, v9
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vid.v v10 ; RV32-NEXT: vid.v v10
; RV32-NEXT: vsrl.vi v10, v10, 1 ; RV32-NEXT: vsrl.vi v10, v10, 1
; RV32-NEXT: vrsub.vi v10, v10, 0 ; RV32-NEXT: vrsub.vi v10, v10, 0
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vmadd.vv v10, v8, v9 ; RV32-NEXT: vmadd.vv v10, v8, v9
; RV32-NEXT: li a1, 63
; RV32-NEXT: vsrl.vx v8, v10, a1
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 1 ; RV32-NEXT: vmv.v.i v8, 1
; RV32-NEXT: vmv.v.i v11, 0 ; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, ma ; RV32-NEXT: vsetivli zero, 3, e32, m1, tu, ma
; RV32-NEXT: vslideup.vi v11, v9, 2 ; RV32-NEXT: vslideup.vi v9, v8, 2
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vsra.vv v9, v10, v11 ; RV32-NEXT: vsra.vv v8, v10, v9
; RV32-NEXT: vadd.vv v8, v9, v8 ; RV32-NEXT: li a1, 63
; RV32-NEXT: vsrl.vx v9, v10, a1
; RV32-NEXT: vadd.vv v8, v8, v9
; RV32-NEXT: vse64.v v8, (a0) ; RV32-NEXT: vse64.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mulhs_v2i64: ; RV64-LABEL: mulhs_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: lui a1, 349525 ; RV64-NEXT: lui a1, 349525
; RV64-NEXT: addiw a1, a1, 1365 ; RV64-NEXT: addiw a1, a1, 1365
▲ Show 20 Lines • Show All 3,404 Lines • ▼ Show 20 Lines
define void @mulhu_v32i8(ptr %x) { define void @mulhu_v32i8(ptr %x) {
; LMULMAX2-RV32-LABEL: mulhu_v32i8: ; LMULMAX2-RV32-LABEL: mulhu_v32i8:
; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: li a1, 32 ; LMULMAX2-RV32-NEXT: li a1, 32
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX2-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX2-RV32-NEXT: vmv.v.i v10, 0 ; LMULMAX2-RV32-NEXT: vmv.v.i v10, 0
; LMULMAX2-RV32-NEXT: lui a2, 163907
; LMULMAX2-RV32-NEXT: addi a2, a2, -2044
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
; LMULMAX2-RV32-NEXT: li a2, -128
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vxm v12, v10, a2, v0
; LMULMAX2-RV32-NEXT: lui a2, 66049 ; LMULMAX2-RV32-NEXT: lui a2, 66049
; LMULMAX2-RV32-NEXT: addi a2, a2, 32 ; LMULMAX2-RV32-NEXT: addi a2, a2, 32
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2 ; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: lui a2, %hi(.LCPI181_0) ; LMULMAX2-RV32-NEXT: lui a2, %hi(.LCPI181_0)
; LMULMAX2-RV32-NEXT: addi a2, a2, %lo(.LCPI181_0) ; LMULMAX2-RV32-NEXT: addi a2, a2, %lo(.LCPI181_0)
; LMULMAX2-RV32-NEXT: vle8.v v12, (a2) ; LMULMAX2-RV32-NEXT: vle8.v v14, (a2)
; LMULMAX2-RV32-NEXT: vmerge.vim v14, v10, 1, v0 ; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV32-NEXT: vsrl.vv v14, v8, v14 ; LMULMAX2-RV32-NEXT: vsrl.vv v10, v8, v10
; LMULMAX2-RV32-NEXT: vmulhu.vv v12, v14, v12 ; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v10, v14
; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v12 ; LMULMAX2-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: lui a2, 163907 ; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: addi a2, a2, -2044 ; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
; LMULMAX2-RV32-NEXT: li a2, -128
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a2, v0
; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vadd.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vmv.v.i v10, 4 ; LMULMAX2-RV32-NEXT: vmv.v.i v10, 4
; LMULMAX2-RV32-NEXT: lui a2, 8208 ; LMULMAX2-RV32-NEXT: lui a2, 8208
; LMULMAX2-RV32-NEXT: addi a2, a2, 513 ; LMULMAX2-RV32-NEXT: addi a2, a2, 513
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2 ; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV32-NEXT: lui a2, 66785 ; LMULMAX2-RV32-NEXT: lui a2, 66785
Show All 13 Lines
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: mulhu_v32i8: ; LMULMAX2-RV64-LABEL: mulhu_v32i8:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: li a1, 32 ; LMULMAX2-RV64-NEXT: li a1, 32
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX2-RV64-NEXT: vmv.v.i v10, 0 ; LMULMAX2-RV64-NEXT: vmv.v.i v10, 0
; LMULMAX2-RV64-NEXT: lui a2, 163907
; LMULMAX2-RV64-NEXT: addiw a2, a2, -2044
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2
; LMULMAX2-RV64-NEXT: li a2, -128
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmerge.vxm v12, v10, a2, v0
; LMULMAX2-RV64-NEXT: lui a2, 66049 ; LMULMAX2-RV64-NEXT: lui a2, 66049
; LMULMAX2-RV64-NEXT: addiw a2, a2, 32 ; LMULMAX2-RV64-NEXT: addiw a2, a2, 32
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2 ; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: lui a2, %hi(.LCPI181_0) ; LMULMAX2-RV64-NEXT: lui a2, %hi(.LCPI181_0)
; LMULMAX2-RV64-NEXT: addi a2, a2, %lo(.LCPI181_0) ; LMULMAX2-RV64-NEXT: addi a2, a2, %lo(.LCPI181_0)
; LMULMAX2-RV64-NEXT: vle8.v v12, (a2) ; LMULMAX2-RV64-NEXT: vle8.v v14, (a2)
; LMULMAX2-RV64-NEXT: vmerge.vim v14, v10, 1, v0 ; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV64-NEXT: vsrl.vv v14, v8, v14 ; LMULMAX2-RV64-NEXT: vsrl.vv v10, v8, v10
; LMULMAX2-RV64-NEXT: vmulhu.vv v12, v14, v12 ; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v10, v14
; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v12 ; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: lui a2, 163907 ; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: addiw a2, a2, -2044 ; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2
; LMULMAX2-RV64-NEXT: li a2, -128
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmerge.vxm v10, v10, a2, v0
; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: vmv.v.i v10, 4 ; LMULMAX2-RV64-NEXT: vmv.v.i v10, 4
; LMULMAX2-RV64-NEXT: lui a2, 8208 ; LMULMAX2-RV64-NEXT: lui a2, 8208
; LMULMAX2-RV64-NEXT: addiw a2, a2, 513 ; LMULMAX2-RV64-NEXT: addiw a2, a2, 513
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2 ; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV64-NEXT: lui a2, 66785 ; LMULMAX2-RV64-NEXT: lui a2, 66785
Show All 32 Lines; LMULMAX1-NEXT: ret
ret void ret void
} }
define void @mulhu_v16i16(ptr %x) { define void @mulhu_v16i16(ptr %x) {
; LMULMAX2-RV32-LABEL: mulhu_v16i16: ; LMULMAX2-RV32-LABEL: mulhu_v16i16:
; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle16.v v10, (a0) ; LMULMAX2-RV32-NEXT: vle16.v v10, (a0)
; LMULMAX2-RV32-NEXT: li a1, 257
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v12, 0
; LMULMAX2-RV32-NEXT: lui a1, 1048568
; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v12, a1, v0
; LMULMAX2-RV32-NEXT: lui a1, 4 ; LMULMAX2-RV32-NEXT: lui a1, 4
; LMULMAX2-RV32-NEXT: addi a1, a1, 64 ; LMULMAX2-RV32-NEXT: addi a1, a1, 64
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v8, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v8, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI182_0) ; LMULMAX2-RV32-NEXT: lui a1, %hi(.LCPI182_0)
; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI182_0) ; LMULMAX2-RV32-NEXT: addi a1, a1, %lo(.LCPI182_0)
; LMULMAX2-RV32-NEXT: vle16.v v12, (a1) ; LMULMAX2-RV32-NEXT: vle16.v v16, (a1)
; LMULMAX2-RV32-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8 ; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8
; LMULMAX2-RV32-NEXT: vmerge.vim v16, v14, 1, v0 ; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX2-RV32-NEXT: vsrl.vv v16, v10, v16 ; LMULMAX2-RV32-NEXT: vsrl.vv v12, v10, v12
; LMULMAX2-RV32-NEXT: vmulhu.vv v12, v16, v12 ; LMULMAX2-RV32-NEXT: vmulhu.vv v12, v12, v16
; LMULMAX2-RV32-NEXT: vsub.vv v10, v10, v12 ; LMULMAX2-RV32-NEXT: vsub.vv v10, v10, v12
; LMULMAX2-RV32-NEXT: li a1, 257
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1
; LMULMAX2-RV32-NEXT: lui a1, 1048568
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vxm v14, v14, a1, v0
; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v10, v14 ; LMULMAX2-RV32-NEXT: vmulhu.vv v10, v10, v14
; LMULMAX2-RV32-NEXT: vadd.vv v10, v10, v12 ; LMULMAX2-RV32-NEXT: vadd.vv v10, v10, v12
; LMULMAX2-RV32-NEXT: lui a1, 2 ; LMULMAX2-RV32-NEXT: lui a1, 2
; LMULMAX2-RV32-NEXT: addi a1, a1, 289 ; LMULMAX2-RV32-NEXT: addi a1, a1, 289
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1 ; LMULMAX2-RV32-NEXT: vmv.v.x v0, a1
; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.i v12, 3 ; LMULMAX2-RV32-NEXT: vmv.v.i v12, 3
; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 2, v0 ; LMULMAX2-RV32-NEXT: vmerge.vim v12, v12, 2, v0
; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8 ; LMULMAX2-RV32-NEXT: vmv1r.v v0, v8
; LMULMAX2-RV32-NEXT: vmerge.vim v8, v12, 1, v0 ; LMULMAX2-RV32-NEXT: vmerge.vim v8, v12, 1, v0
; LMULMAX2-RV32-NEXT: vsrl.vv v8, v10, v8 ; LMULMAX2-RV32-NEXT: vsrl.vv v8, v10, v8
; LMULMAX2-RV32-NEXT: vse16.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse16.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: mulhu_v16i16: ; LMULMAX2-RV64-LABEL: mulhu_v16i16:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle16.v v10, (a0) ; LMULMAX2-RV64-NEXT: vle16.v v10, (a0)
; LMULMAX2-RV64-NEXT: li a1, 257
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v0, a1
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.i v12, 0
; LMULMAX2-RV64-NEXT: lui a1, 1048568
; LMULMAX2-RV64-NEXT: vmerge.vxm v14, v12, a1, v0
; LMULMAX2-RV64-NEXT: lui a1, 4 ; LMULMAX2-RV64-NEXT: lui a1, 4
; LMULMAX2-RV64-NEXT: addiw a1, a1, 64 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 64
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v8, a1 ; LMULMAX2-RV64-NEXT: vmv.v.x v8, a1
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI182_0) ; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI182_0)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI182_0) ; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI182_0)
; LMULMAX2-RV64-NEXT: vle16.v v12, (a1) ; LMULMAX2-RV64-NEXT: vle16.v v16, (a1)
; LMULMAX2-RV64-NEXT: vmv.v.i v14, 0
; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8 ; LMULMAX2-RV64-NEXT: vmv1r.v v0, v8
; LMULMAX2-RV64-NEXT: vmerge.vim v16, v14, 1, v0 ; LMULMAX2-RV64-NEXT: vmerge.vim v12, v12, 1, v0
; LMULMAX2-RV64-NEXT: vsrl.vv v16, v10, v16 ; LMULMAX2-RV64-NEXT: vsrl.vv v12, v10, v12
; LMULMAX2-RV64-NEXT: vmulhu.vv v12, v16, v12 ; LMULMAX2-RV64-NEXT: vmulhu.vv v12, v12, v16
; LMULMAX2-RV64-NEXT: vsub.vv v10, v10, v12 ; LMULMAX2-RV64-NEXT: vsub.vv v10, v10, v12
; LMULMAX2-RV64-NEXT: li a1, 257
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v0, a1
; LMULMAX2-RV64-NEXT: lui a1, 1048568
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmerge.vxm v14, v14, a1, v0
; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v10, v14 ; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v10, v14
; LMULMAX2-RV64-NEXT: vadd.vv v10, v10, v12 ; LMULMAX2-RV64-NEXT: vadd.vv v10, v10, v12
; LMULMAX2-RV64-NEXT: lui a1, 2 ; LMULMAX2-RV64-NEXT: lui a1, 2
; LMULMAX2-RV64-NEXT: addiw a1, a1, 289 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 289
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v0, a1 ; LMULMAX2-RV64-NEXT: vmv.v.x v0, a1
; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.i v12, 3 ; LMULMAX2-RV64-NEXT: vmv.v.i v12, 3
Show All 24 Lines; LMULMAX1-NEXT: ret
ret void ret void
} }
define void @mulhu_v8i32(ptr %x) { define void @mulhu_v8i32(ptr %x) {
; LMULMAX2-LABEL: mulhu_v8i32: ; LMULMAX2-LABEL: mulhu_v8i32:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-NEXT: vle32.v v8, (a0) ; LMULMAX2-NEXT: vle32.v v8, (a0)
; LMULMAX2-NEXT: lui a1, %hi(.LCPI183_0)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI183_0)
; LMULMAX2-NEXT: vle32.v v10, (a1)
; LMULMAX2-NEXT: vmulhu.vv v10, v8, v10
; LMULMAX2-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-NEXT: li a1, 68 ; LMULMAX2-NEXT: li a1, 68
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; LMULMAX2-NEXT: vmv.v.x v0, a1 ; LMULMAX2-NEXT: vmv.v.x v0, a1
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-NEXT: lui a1, %hi(.LCPI183_0)
; LMULMAX2-NEXT: addi a1, a1, %lo(.LCPI183_0)
; LMULMAX2-NEXT: vle32.v v10, (a1)
; LMULMAX2-NEXT: vmv.v.i v12, 0 ; LMULMAX2-NEXT: vmv.v.i v12, 0
; LMULMAX2-NEXT: lui a1, 524288 ; LMULMAX2-NEXT: lui a1, 524288
; LMULMAX2-NEXT: vmerge.vxm v12, v12, a1, v0 ; LMULMAX2-NEXT: vmerge.vxm v12, v12, a1, v0
; LMULMAX2-NEXT: vmulhu.vv v10, v8, v10
; LMULMAX2-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-NEXT: vmulhu.vv v8, v8, v12 ; LMULMAX2-NEXT: vmulhu.vv v8, v8, v12
; LMULMAX2-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-NEXT: li a1, 136 ; LMULMAX2-NEXT: li a1, 136
; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; LMULMAX2-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; LMULMAX2-NEXT: vmv.v.x v0, a1 ; LMULMAX2-NEXT: vmv.v.x v0, a1
; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; LMULMAX2-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-NEXT: vmv.v.i v10, 2 ; LMULMAX2-NEXT: vmv.v.i v10, 2
; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX2-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-NEXT: vsrl.vv v8, v8, v10 ; LMULMAX2-NEXT: vsrl.vv v8, v8, v10
; LMULMAX2-NEXT: vse32.v v8, (a0) ; LMULMAX2-NEXT: vse32.v v8, (a0)
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: mulhu_v8i32: ; LMULMAX1-RV32-LABEL: mulhu_v8i32:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vle32.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
; LMULMAX1-RV32-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vle32.v v9, (a1)
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI183_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI183_0)
; LMULMAX1-RV32-NEXT: vle32.v v9, (a2)
; LMULMAX1-RV32-NEXT: vle32.v v10, (a0)
; LMULMAX1-RV32-NEXT: vmulhu.vv v11, v8, v9
; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: lui a2, 524288 ; LMULMAX1-RV32-NEXT: lui a2, 524288
; LMULMAX1-RV32-NEXT: vmv.s.x v12, a2 ; LMULMAX1-RV32-NEXT: vmv.s.x v10, a2
; LMULMAX1-RV32-NEXT: vmv.v.i v13, 0 ; LMULMAX1-RV32-NEXT: vmv.v.i v11, 0
; LMULMAX1-RV32-NEXT: vsetivli zero, 3, e32, m1, tu, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 3, e32, m1, tu, ma
; LMULMAX1-RV32-NEXT: vslideup.vi v13, v12, 2 ; LMULMAX1-RV32-NEXT: vslideup.vi v11, v10, 2
; LMULMAX1-RV32-NEXT: lui a2, %hi(.LCPI183_0)
; LMULMAX1-RV32-NEXT: addi a2, a2, %lo(.LCPI183_0)
; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV32-NEXT: vmulhu.vv v8, v8, v13 ; LMULMAX1-RV32-NEXT: vle32.v v10, (a2)
; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v11 ; LMULMAX1-RV32-NEXT: vmulhu.vv v12, v9, v10
; LMULMAX1-RV32-NEXT: vmv.v.i v11, 2 ; LMULMAX1-RV32-NEXT: vsub.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: vmulhu.vv v9, v9, v11
; LMULMAX1-RV32-NEXT: vadd.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: vmv.v.i v12, 2
; LMULMAX1-RV32-NEXT: li a2, 1 ; LMULMAX1-RV32-NEXT: li a2, 1
; LMULMAX1-RV32-NEXT: vslide1down.vx v11, v11, a2 ; LMULMAX1-RV32-NEXT: vslide1down.vx v12, v12, a2
; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v11 ; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v12
; LMULMAX1-RV32-NEXT: vmulhu.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: vmulhu.vv v10, v8, v10
; LMULMAX1-RV32-NEXT: vsub.vv v10, v10, v9 ; LMULMAX1-RV32-NEXT: vsub.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vmulhu.vv v10, v10, v13 ; LMULMAX1-RV32-NEXT: vmulhu.vv v8, v8, v11
; LMULMAX1-RV32-NEXT: vadd.vv v9, v10, v9 ; LMULMAX1-RV32-NEXT: vadd.vv v8, v8, v10
; LMULMAX1-RV32-NEXT: vsrl.vv v9, v9, v11 ; LMULMAX1-RV32-NEXT: vsrl.vv v8, v8, v12
; LMULMAX1-RV32-NEXT: vse32.v v9, (a0) ; LMULMAX1-RV32-NEXT: vse32.v v8, (a0)
; LMULMAX1-RV32-NEXT: vse32.v v8, (a1) ; LMULMAX1-RV32-NEXT: vse32.v v9, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: mulhu_v8i32: ; LMULMAX1-RV64-LABEL: mulhu_v8i32:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle32.v v8, (a1) ; LMULMAX1-RV64-NEXT: vle32.v v8, (a1)
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI183_0) ; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI183_0)
Show All 40 Lines
; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: mulhu_v4i64: ; LMULMAX2-RV64-LABEL: mulhu_v4i64:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI184_0)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI184_0)
; LMULMAX2-RV64-NEXT: vle64.v v10, (a1)
; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v8, v10
; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: li a1, -1 ; LMULMAX2-RV64-NEXT: li a1, -1
; LMULMAX2-RV64-NEXT: slli a1, a1, 63 ; LMULMAX2-RV64-NEXT: slli a1, a1, 63
; LMULMAX2-RV64-NEXT: vmv.s.x v12, a1 ; LMULMAX2-RV64-NEXT: vmv.s.x v10, a1
; LMULMAX2-RV64-NEXT: vmv.v.i v14, 0 ; LMULMAX2-RV64-NEXT: vmv.v.i v12, 0
; LMULMAX2-RV64-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 3, e64, m2, tu, ma
; LMULMAX2-RV64-NEXT: vslideup.vi v14, v12, 2 ; LMULMAX2-RV64-NEXT: vslideup.vi v12, v10, 2
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI184_0)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI184_0)
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle64.v v10, (a1)
; LMULMAX2-RV64-NEXT: vmulhu.vv v10, v8, v10
; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI184_1) ; LMULMAX2-RV64-NEXT: lui a1, %hi(.LCPI184_1)
; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI184_1) ; LMULMAX2-RV64-NEXT: addi a1, a1, %lo(.LCPI184_1)
; LMULMAX2-RV64-NEXT: vle64.v v12, (a1) ; LMULMAX2-RV64-NEXT: vle64.v v14, (a1)
; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v14 ; LMULMAX2-RV64-NEXT: vsub.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: vadd.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v12 ; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v14
; LMULMAX2-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: mulhu_v4i64: ; LMULMAX1-RV32-LABEL: mulhu_v4i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV32-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV32-NEXT: addi a1, a0, 16 ; LMULMAX1-RV32-NEXT: addi a1, a0, 16
Show All 13 Lines
; LMULMAX1-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v9, (a1) ; LMULMAX1-RV32-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: mulhu_v4i64: ; LMULMAX1-RV64-LABEL: mulhu_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX1-RV64-NEXT: lui a1, %hi(.LCPI184_0) ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: addi a1, a1, %lo(.LCPI184_0) ; LMULMAX1-RV64-NEXT: vle64.v v9, (a1)
; LMULMAX1-RV64-NEXT: vlse64.v v9, (a1), zero ; LMULMAX1-RV64-NEXT: vmv.v.i v10, 0
; LMULMAX1-RV64-NEXT: lui a1, %hi(.LCPI184_1) ; LMULMAX1-RV64-NEXT: li a2, -1
; LMULMAX1-RV64-NEXT: ld a1, %lo(.LCPI184_1)(a1) ; LMULMAX1-RV64-NEXT: slli a2, a2, 63
; LMULMAX1-RV64-NEXT: addi a2, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v10, (a2)
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma
; LMULMAX1-RV64-NEXT: vmv.s.x v9, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v10, a2
; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI184_0)
; LMULMAX1-RV64-NEXT: addi a2, a2, %lo(.LCPI184_0)
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vmulhu.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vlse64.v v11, (a2), zero
; LMULMAX1-RV64-NEXT: vsub.vv v10, v10, v9 ; LMULMAX1-RV64-NEXT: lui a2, %hi(.LCPI184_1)
; LMULMAX1-RV64-NEXT: vmv.v.i v11, 0 ; LMULMAX1-RV64-NEXT: ld a2, %lo(.LCPI184_1)(a2)
; LMULMAX1-RV64-NEXT: li a1, -1
; LMULMAX1-RV64-NEXT: slli a1, a1, 63
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma
; LMULMAX1-RV64-NEXT: vmv.s.x v11, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v11, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vmulhu.vv v10, v10, v11 ; LMULMAX1-RV64-NEXT: vmulhu.vv v11, v9, v11
; LMULMAX1-RV64-NEXT: vadd.vv v9, v10, v9 ; LMULMAX1-RV64-NEXT: vsub.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vmulhu.vv v9, v9, v10
; LMULMAX1-RV64-NEXT: vadd.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: vid.v v10 ; LMULMAX1-RV64-NEXT: vid.v v10
; LMULMAX1-RV64-NEXT: vadd.vi v11, v10, 2 ; LMULMAX1-RV64-NEXT: vadd.vi v11, v10, 2
; LMULMAX1-RV64-NEXT: vsrl.vv v9, v9, v11 ; LMULMAX1-RV64-NEXT: vsrl.vv v9, v9, v11
; LMULMAX1-RV64-NEXT: lui a1, 838861 ; LMULMAX1-RV64-NEXT: lui a2, 838861
; LMULMAX1-RV64-NEXT: addiw a1, a1, -819 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -819
; LMULMAX1-RV64-NEXT: slli a3, a1, 32 ; LMULMAX1-RV64-NEXT: slli a3, a2, 32
; LMULMAX1-RV64-NEXT: add a1, a1, a3 ; LMULMAX1-RV64-NEXT: add a2, a2, a3
; LMULMAX1-RV64-NEXT: vmv.v.x v11, a1 ; LMULMAX1-RV64-NEXT: vmv.v.x v11, a2
; LMULMAX1-RV64-NEXT: lui a1, 699051 ; LMULMAX1-RV64-NEXT: lui a2, 699051
; LMULMAX1-RV64-NEXT: addiw a1, a1, -1365 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -1365
; LMULMAX1-RV64-NEXT: slli a3, a1, 32 ; LMULMAX1-RV64-NEXT: slli a3, a2, 32
; LMULMAX1-RV64-NEXT: add a1, a1, a3 ; LMULMAX1-RV64-NEXT: add a2, a2, a3
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, tu, ma
; LMULMAX1-RV64-NEXT: vmv.s.x v11, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v11, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX1-RV64-NEXT: vmulhu.vv v8, v8, v11 ; LMULMAX1-RV64-NEXT: vmulhu.vv v8, v8, v11
; LMULMAX1-RV64-NEXT: vadd.vi v10, v10, 1 ; LMULMAX1-RV64-NEXT: vadd.vi v10, v10, 1
; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v10 ; LMULMAX1-RV64-NEXT: vsrl.vv v8, v8, v10
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v9, (a2) ; LMULMAX1-RV64-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, ptr %x %a = load <4 x i64>, ptr %x
%b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9> %b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9>
store <4 x i64> %b, ptr %x store <4 x i64> %b, ptr %x
ret void ret void
} }
define void @mulhs_v32i8(ptr %x) { define void @mulhs_v32i8(ptr %x) {
; LMULMAX2-RV32-LABEL: mulhs_v32i8: ; LMULMAX2-RV32-LABEL: mulhs_v32i8:
; LMULMAX2-RV32: # %bb.0: ; LMULMAX2-RV32: # %bb.0:
; LMULMAX2-RV32-NEXT: li a1, 32 ; LMULMAX2-RV32-NEXT: li a1, 32
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX2-RV32-NEXT: vle8.v v8, (a0)
; LMULMAX2-RV32-NEXT: li a2, -123 ; LMULMAX2-RV32-NEXT: vmv.v.i v10, 7
; LMULMAX2-RV32-NEXT: vmv.v.x v10, a2
; LMULMAX2-RV32-NEXT: lui a2, 304453 ; LMULMAX2-RV32-NEXT: lui a2, 304453
; LMULMAX2-RV32-NEXT: addi a2, a2, -1452 ; LMULMAX2-RV32-NEXT: addi a2, a2, -1452
; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; LMULMAX2-RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2 ; LMULMAX2-RV32-NEXT: vmv.v.x v0, a2
; LMULMAX2-RV32-NEXT: li a2, 57
; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; LMULMAX2-RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV32-NEXT: vmerge.vxm v10, v10, a2, v0
; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vmv.v.i v10, 7
; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX2-RV32-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV32-NEXT: li a1, -123
; LMULMAX2-RV32-NEXT: vmv.v.x v12, a1
; LMULMAX2-RV32-NEXT: li a1, 57
; LMULMAX2-RV32-NEXT: vmerge.vxm v12, v12, a1, v0
; LMULMAX2-RV32-NEXT: vmulhu.vv v8, v8, v12
; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10 ; LMULMAX2-RV32-NEXT: vsrl.vv v8, v8, v10
; LMULMAX2-RV32-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: mulhs_v32i8: ; LMULMAX2-RV64-LABEL: mulhs_v32i8:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: li a1, 32 ; LMULMAX2-RV64-NEXT: li a1, 32
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle8.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle8.v v8, (a0)
; LMULMAX2-RV64-NEXT: li a2, -123 ; LMULMAX2-RV64-NEXT: vmv.v.i v10, 7
; LMULMAX2-RV64-NEXT: vmv.v.x v10, a2
; LMULMAX2-RV64-NEXT: lui a2, 304453 ; LMULMAX2-RV64-NEXT: lui a2, 304453
; LMULMAX2-RV64-NEXT: addiw a2, a2, -1452 ; LMULMAX2-RV64-NEXT: addiw a2, a2, -1452
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2 ; LMULMAX2-RV64-NEXT: vmv.v.x v0, a2
; LMULMAX2-RV64-NEXT: li a2, 57
; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; LMULMAX2-RV64-NEXT: vmerge.vxm v10, v10, a2, v0
; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vmv.v.i v10, 7
; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 1, v0 ; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 1, v0
; LMULMAX2-RV64-NEXT: li a1, -123
; LMULMAX2-RV64-NEXT: vmv.v.x v12, a1
; LMULMAX2-RV64-NEXT: li a1, 57
; LMULMAX2-RV64-NEXT: vmerge.vxm v12, v12, a1, v0
; LMULMAX2-RV64-NEXT: vmulhu.vv v8, v8, v12
; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v10 ; LMULMAX2-RV64-NEXT: vsrl.vv v8, v8, v10
; LMULMAX2-RV64-NEXT: vse8.v v8, (a0) ; LMULMAX2-RV64-NEXT: vse8.v v8, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: mulhs_v32i8: ; LMULMAX1-RV32-LABEL: mulhs_v32i8:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; LMULMAX1-RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; LMULMAX1-RV32-NEXT: vle8.v v8, (a0) ; LMULMAX1-RV32-NEXT: vle8.v v8, (a0)
▲ Show 20 Lines • Show All 226 Lines • ▼ Show 20 Lines
; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8 ; LMULMAX2-RV32-NEXT: vadd.vv v8, v10, v8
; LMULMAX2-RV32-NEXT: vse64.v v8, (a0) ; LMULMAX2-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32-NEXT: ret ; LMULMAX2-RV32-NEXT: ret
; ;
; LMULMAX2-RV64-LABEL: mulhs_v4i64: ; LMULMAX2-RV64-LABEL: mulhs_v4i64:
; LMULMAX2-RV64: # %bb.0: ; LMULMAX2-RV64: # %bb.0:
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64-NEXT: vle64.v v8, (a0) ; LMULMAX2-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64-NEXT: vmv.v.i v10, -1
; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; LMULMAX2-RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; LMULMAX2-RV64-NEXT: vmv.v.i v0, 5 ; LMULMAX2-RV64-NEXT: vmv.v.i v0, 5
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64-NEXT: lui a1, 349525 ; LMULMAX2-RV64-NEXT: lui a1, 349525
; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365 ; LMULMAX2-RV64-NEXT: addiw a1, a1, 1365
; LMULMAX2-RV64-NEXT: slli a2, a1, 32 ; LMULMAX2-RV64-NEXT: slli a2, a1, 32
; LMULMAX2-RV64-NEXT: add a1, a1, a2 ; LMULMAX2-RV64-NEXT: add a1, a1, a2
; LMULMAX2-RV64-NEXT: lui a2, %hi(.LCPI188_0) ; LMULMAX2-RV64-NEXT: lui a2, %hi(.LCPI188_0)
; LMULMAX2-RV64-NEXT: ld a2, %lo(.LCPI188_0)(a2) ; LMULMAX2-RV64-NEXT: ld a2, %lo(.LCPI188_0)(a2)
; LMULMAX2-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; LMULMAX2-RV64-NEXT: vmv.v.i v10, -1
; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 0, v0 ; LMULMAX2-RV64-NEXT: vmerge.vim v10, v10, 0, v0
; LMULMAX2-RV64-NEXT: vmv.v.x v12, a1 ; LMULMAX2-RV64-NEXT: vmv.v.x v12, a1
; LMULMAX2-RV64-NEXT: vmerge.vxm v12, v12, a2, v0 ; LMULMAX2-RV64-NEXT: vmerge.vxm v12, v12, a2, v0
; LMULMAX2-RV64-NEXT: vmulh.vv v12, v8, v12 ; LMULMAX2-RV64-NEXT: vmulh.vv v12, v8, v12
; LMULMAX2-RV64-NEXT: vmacc.vv v12, v8, v10 ; LMULMAX2-RV64-NEXT: vmacc.vv v12, v8, v10
; LMULMAX2-RV64-NEXT: li a1, 63 ; LMULMAX2-RV64-NEXT: li a1, 63
; LMULMAX2-RV64-NEXT: vsrl.vx v8, v12, a1 ; LMULMAX2-RV64-NEXT: vsrl.vx v8, v12, a1
; LMULMAX2-RV64-NEXT: vmv.v.i v10, 1 ; LMULMAX2-RV64-NEXT: vmv.v.i v10, 1
▲ Show 20 Lines • Show All 2,800 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck %s ; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck %s
; Integers ; Integers
define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr %p) { define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr %p) {
; CHECK-LABEL: vector_interleave_store_v32i1_v16i1: ; CHECK-LABEL: vector_interleave_store_v32i1_v16i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v8, 2 ; CHECK-NEXT: vslideup.vi v0, v8, 2
; CHECK-NEXT: li a1, 32
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 16 ; CHECK-NEXT: vslidedown.vi v10, v8, 16
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vwaddu.vv v12, v8, v10 ; CHECK-NEXT: vwaddu.vv v12, v8, v10
; CHECK-NEXT: li a2, -1 ; CHECK-NEXT: li a2, -1
; CHECK-NEXT: vwmaccu.vx v12, a2, v10 ; CHECK-NEXT: vwmaccu.vx v12, a2, v10
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v8, v12, 0 ; CHECK-NEXT: vmsne.vi v8, v12, 0
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

Show All 10 Lines
; CHECK-LABEL: load_factor2_v3: ; CHECK-LABEL: load_factor2_v3:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v10, (a0) ; CHECK-NEXT: vle32.v v10, (a0)
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vv v9, v8, v8 ; CHECK-NEXT: vadd.vv v9, v8, v8
; CHECK-NEXT: vrgather.vv v8, v10, v9 ; CHECK-NEXT: vrgather.vv v8, v10, v9
; CHECK-NEXT: vmv.v.i v0, 4
; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v10, 4 ; CHECK-NEXT: vslidedown.vi v12, v10, 4
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 4
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vrgather.vi v8, v12, 0, v0.t ; CHECK-NEXT: vrgather.vi v8, v12, 0, v0.t
; CHECK-NEXT: vadd.vi v11, v9, 1 ; CHECK-NEXT: vadd.vi v11, v9, 1
; CHECK-NEXT: vrgather.vv v9, v10, v11 ; CHECK-NEXT: vrgather.vv v9, v10, v11
; CHECK-NEXT: vrgather.vi v9, v12, 1, v0.t ; CHECK-NEXT: vrgather.vi v9, v12, 1, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%interleaved.vec = load <6 x i32>, ptr %ptr %interleaved.vec = load <6 x i32>, ptr %ptr
%v0 = shufflevector <6 x i32> %interleaved.vec, <6 x i32> poison, <3 x i32> <i32 0, i32 2, i32 4> %v0 = shufflevector <6 x i32> %interleaved.vec, <6 x i32> poison, <3 x i32> <i32 0, i32 2, i32 4>
▲ Show 20 Lines • Show All 620 Lines • ▼ Show 20 Lines
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: load_factor6_too_big: ; RV64-LABEL: load_factor6_too_big:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 92 ; RV64-NEXT: li a3, 90
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: sub sp, sp, a2 ; RV64-NEXT: sub sp, sp, a2
; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xdc, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 92 * vlenb ; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xda, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 90 * vlenb
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: addi a2, a1, 256 ; RV64-NEXT: addi a2, a1, 256
; RV64-NEXT: vle64.v v16, (a2) ; RV64-NEXT: vle64.v v16, (a2)
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 68 ; RV64-NEXT: li a3, 57
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV64-NEXT: addi a2, a1, 128 ; RV64-NEXT: addi a2, a1, 128
; RV64-NEXT: vle64.v v8, (a2) ; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 84 ; RV64-NEXT: slli a3, a2, 6
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: add a2, a3, a2
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vle64.v v24, (a1) ; RV64-NEXT: vle64.v v8, (a1)
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 73
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vrgather.vi v8, v16, 4 ; RV64-NEXT: vrgather.vi v8, v16, 4
; RV64-NEXT: li a1, 128 ; RV64-NEXT: li a1, 128
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.x v0, a1 ; RV64-NEXT: vmv.v.x v1, a1
; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma
; RV64-NEXT: vslidedown.vi v24, v16, 8
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 40 ; RV64-NEXT: li a2, 49
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vslidedown.vi v16, v16, 8 ; RV64-NEXT: vmv1r.v v0, v1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 52 ; RV64-NEXT: slli a2, a1, 5
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v1, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vrgather.vi v8, v24, 2, v0.t
; RV64-NEXT: vrgather.vi v8, v16, 2, v0.t
; RV64-NEXT: vmv.v.v v4, v8 ; RV64-NEXT: vmv.v.v v4, v8
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: li a1, 6 ; RV64-NEXT: li a1, 6
; RV64-NEXT: vid.v v8 ; RV64-NEXT: vid.v v8
; RV64-NEXT: vmul.vx v8, v8, a1 ; RV64-NEXT: vmul.vx v16, v8, a1
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 81
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: li a1, 56 ; RV64-NEXT: li a1, 56
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 60 ; RV64-NEXT: li a3, 73
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v24, v8 ; RV64-NEXT: vrgather.vv v24, v8, v16
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: vadd.vi v8, v16, -16
; RV64-NEXT: li a3, 76
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vadd.vi v8, v8, -16
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 44 ; RV64-NEXT: li a3, 41
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a1 ; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 5 ; RV64-NEXT: li a2, 25
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 84 ; RV64-NEXT: slli a2, a1, 6
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 44 ; RV64-NEXT: li a2, 41
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v24, v8, v0.t ; RV64-NEXT: vrgather.vv v24, v8, v16, v0.t
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: vmv.v.v v4, v16 ; RV64-NEXT: vmv.v.v v4, v24
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 36 ; RV64-NEXT: li a2, 29
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 68 ; RV64-NEXT: li a2, 57
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v16, v0, 5 ; RV64-NEXT: vrgather.vi v16, v8, 5
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: vmv1r.v v0, v1
; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 52 ; RV64-NEXT: li a2, 49
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v16, v24, 3, v0.t ; RV64-NEXT: vrgather.vi v16, v8, 3, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 44 ; RV64-NEXT: li a2, 41
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 76 ; RV64-NEXT: li a2, 81
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v0, v8, 1 ; RV64-NEXT: vadd.vi v0, v16, 1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 60 ; RV64-NEXT: li a2, 73
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v24, v0 ; RV64-NEXT: vrgather.vv v24, v8, v0
; RV64-NEXT: vadd.vi v24, v8, -15 ; RV64-NEXT: vadd.vi v8, v16, -15
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 24 ; RV64-NEXT: slli a2, a1, 4
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 5 ; RV64-NEXT: li a2, 25
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 84 ; RV64-NEXT: slli a2, a1, 6
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 24 ; RV64-NEXT: slli a2, a1, 4
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v24, v8, v0.t ; RV64-NEXT: vrgather.vv v24, v8, v16, v0.t
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 44 ; RV64-NEXT: li a2, 41
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v20, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vmv.v.v v20, v16 ; RV64-NEXT: vmv.v.v v8, v24
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 44 ; RV64-NEXT: li a2, 41
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v20, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 76 ; RV64-NEXT: li a2, 81
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v8, v24, 2 ; RV64-NEXT: vadd.vi v8, v24, 2
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 60 ; RV64-NEXT: li a2, 73
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v0, v8 ; RV64-NEXT: vrgather.vv v16, v0, v8
; RV64-NEXT: li a1, 24 ; RV64-NEXT: li a1, 24
; RV64-NEXT: vadd.vi v8, v24, -14 ; RV64-NEXT: vadd.vi v8, v24, -14
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a1 ; RV64-NEXT: vmv.v.x v2, a1
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 24
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: vmv1r.v v0, v2
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 84 ; RV64-NEXT: slli a2, a1, 6
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v24, v8, v0.t ; RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vmv.v.i v12, 6 ; RV64-NEXT: vmv.v.i v8, 6
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 4 ; RV64-NEXT: slli a2, a1, 2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vmv.s.x v8, zero
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vslideup.vi v12, v8, 5 ; RV64-NEXT: vmv.s.x v4, zero
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: vslideup.vi v8, v4, 5
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 68 ; RV64-NEXT: li a2, 57
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v20, v0, v12 ; RV64-NEXT: vrgather.vv v12, v24, v8
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 40 ; RV64-NEXT: slli a2, a1, 5
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl1r.v v1, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vmv1r.v v0, v1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 52 ; RV64-NEXT: li a2, 49
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v20, v8, 4, v0.t ; RV64-NEXT: vrgather.vi v12, v24, 4, v0.t
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: vmv.v.v v20, v16 ; RV64-NEXT: vmv.v.v v12, v16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 5 ; RV64-NEXT: li a2, 25
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v20, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 76 ; RV64-NEXT: li a2, 81
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v0, v8, 3 ; RV64-NEXT: vadd.vi v16, v8, 3
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 60 ; RV64-NEXT: li a2, 73
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v24, v0 ; RV64-NEXT: vrgather.vv v8, v24, v16
; RV64-NEXT: vmv.v.v v24, v16 ; RV64-NEXT: vmv.v.v v24, v8
; RV64-NEXT: vadd.vi v16, v8, -13
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 24 ; RV64-NEXT: li a2, 81
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v8, v8, -13
; RV64-NEXT: vmv1r.v v0, v2
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 84 ; RV64-NEXT: slli a2, a1, 6
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v24, v8, v16, v0.t ; RV64-NEXT: vrgather.vv v24, v16, v8, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 24 ; RV64-NEXT: slli a2, a1, 3
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: li a1, 1 ; RV64-NEXT: li a1, 1
; RV64-NEXT: vmv.v.i v20, 7 ; RV64-NEXT: vmv.v.i v12, 7
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 20 ; RV64-NEXT: slli a3, a2, 4
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: add a2, a3, a2
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs4r.v v20, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v12, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vmv.s.x v8, a1 ; RV64-NEXT: vmv.s.x v16, a1
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vslideup.vi v20, v8, 5 ; RV64-NEXT: vslideup.vi v12, v16, 5
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 68 ; RV64-NEXT: li a2, 57
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v24, v20 ; RV64-NEXT: vrgather.vv v16, v24, v12
; RV64-NEXT: vmv1r.v v0, v1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 40 ; RV64-NEXT: li a2, 49
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v16, v8, 5, v0.t
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 52 ; RV64-NEXT: slli a2, a1, 3
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v8, v24, 5, v0.t ; RV64-NEXT: vmv.v.v v16, v8
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 24 ; RV64-NEXT: slli a2, a1, 3
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vmv.v.v v8, v16 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 24 ; RV64-NEXT: li a2, 81
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vsetivli zero, 7, e64, m4, tu, ma ; RV64-NEXT: vadd.vi v8, v8, 4
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 12 ; RV64-NEXT: li a2, 73
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v24, v8
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 4 ; RV64-NEXT: slli a2, a1, 5
; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v20, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vslideup.vi v20, v8, 6 ; RV64-NEXT: li a1, 28
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: li a1, 192
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 68 ; RV64-NEXT: li a3, 81
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v8, v24, 2 ; RV64-NEXT: vadd.vi v16, v8, -12
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a1 ; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 52 ; RV64-NEXT: slli a2, a1, 6
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v24, v20, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 40 ; RV64-NEXT: slli a2, a1, 5
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 76 ; RV64-NEXT: slli a2, a1, 5
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vadd.vi v0, v24, 4 ; RV64-NEXT: vsetivli zero, 7, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 60 ; RV64-NEXT: slli a2, a1, 2
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v16, v0 ; RV64-NEXT: vslideup.vi v24, v4, 6
; RV64-NEXT: li a1, 28 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vadd.vi v16, v24, -12 ; RV64-NEXT: li a1, 192
; RV64-NEXT: addi a2, sp, 16 ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV64-NEXT: li a3, 57
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v28, v8, 2
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.x v0, a1 ; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 12 ; RV64-NEXT: slli a2, a1, 2
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 84 ; RV64-NEXT: li a2, 49
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: addi a1, sp, 16 ; RV64-NEXT: vmv4r.v v12, v28
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vrgather.vv v12, v8, v24, v0.t
; RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 40 ; RV64-NEXT: slli a2, a1, 5
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vmv.v.v v12, v8 ; RV64-NEXT: vmv.v.v v12, v24
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 40 ; RV64-NEXT: slli a2, a1, 5
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 7, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 20 ; RV64-NEXT: li a2, 81
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v4, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vslideup.vi v4, v8, 6 ; RV64-NEXT: vadd.vi v24, v0, 5
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 68 ; RV64-NEXT: li a2, 73
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v8, v16, 3 ; RV64-NEXT: vrgather.vv v16, v8, v24
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: vadd.vi v24, v0, -11
; RV64-NEXT: slli a1, a1, 4 ; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 52 ; RV64-NEXT: slli a2, a1, 6
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v16, v4, v0.t
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 20
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v0, v16, 5 ; RV64-NEXT: vrgather.vv v16, v8, v24, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 60 ; RV64-NEXT: li a2, 81
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vrgather.vv v8, v16, v0 ; RV64-NEXT: vsetivli zero, 7, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 76 ; RV64-NEXT: slli a2, a1, 4
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v24, v24, -11 ; RV64-NEXT: vslideup.vi v24, v8, 6
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 76 ; RV64-NEXT: li a2, 57
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v12, v8, 3
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 12 ; RV64-NEXT: slli a2, a1, 2
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 84 ; RV64-NEXT: li a2, 49
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: vrgather.vv v12, v16, v24, v0.t
; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 20 ; RV64-NEXT: li a2, 81
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vmv.v.v v12, v8 ; RV64-NEXT: vmv.v.v v12, v16
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 36
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v16, (a0)
; RV64-NEXT: addi a1, a0, 320 ; RV64-NEXT: addi a1, a0, 320
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vse64.v v12, (a1) ; RV64-NEXT: vse64.v v12, (a1)
; RV64-NEXT: addi a1, a0, 256 ; RV64-NEXT: addi a1, a0, 256
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 40 ; RV64-NEXT: slli a3, a2, 5
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: add a2, a3, a2
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: addi a1, a0, 192 ; RV64-NEXT: addi a1, a0, 192
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 24 ; RV64-NEXT: slli a3, a2, 3
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: add a2, a3, a2
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: addi a1, a0, 128 ; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 5 ; RV64-NEXT: li a3, 25
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: addi a1, a0, 64
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 41
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 44 ; RV64-NEXT: li a2, 29
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 92 ; RV64-NEXT: li a1, 90
; RV64-NEXT: mul a0, a0, a1 ; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%interleaved.vec = load <48 x i64>, ptr %ptr %interleaved.vec = load <48 x i64>, ptr %ptr
%v0 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 0, i32 6, i32 12, i32 18, i32 24, i32 30, i32 36, i32 42> %v0 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 0, i32 6, i32 12, i32 18, i32 24, i32 30, i32 36, i32 42>
%v1 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 1, i32 7, i32 13, i32 19, i32 25, i32 31, i32 37, i32 43> %v1 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 1, i32 7, i32 13, i32 19, i32 25, i32 31, i32 37, i32 43>
%v2 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 2, i32 8, i32 14, i32 20, i32 26, i32 32, i32 38, i32 44> %v2 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 2, i32 8, i32 14, i32 20, i32 26, i32 32, i32 38, i32 44>
▲ Show 20 Lines • Show All 83 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 355 Lines • ▼ Show 20 Lines
; RV64ZVE32F-NEXT: beqz a2, .LBB6_4 ; RV64ZVE32F-NEXT: beqz a2, .LBB6_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1 ; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lbu a0, 0(a1) ; RV64ZVE32F-NEXT: lbu a0, 0(a1)
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a0 ; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 ; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB6_4: # %else2 ; RV64ZVE32F-NEXT: .LBB6_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: ret
%v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru) %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
%ev = sext <2 x i8> %v to <2 x i64> %ev = sext <2 x i8> %v to <2 x i64>
ret <2 x i64> %ev ret <2 x i64> %ev
} }
define <2 x i64> @mgather_v2i8_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i8> %passthru) { define <2 x i64> @mgather_v2i8_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
; RV32V-LABEL: mgather_v2i8_zextload_v2i64: ; RV32V-LABEL: mgather_v2i8_zextload_v2i64:
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; RV64ZVE32F-NEXT: beqz a2, .LBB7_4 ; RV64ZVE32F-NEXT: beqz a2, .LBB7_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1 ; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lbu a0, 0(a1) ; RV64ZVE32F-NEXT: lbu a0, 0(a1)
; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a0 ; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 ; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB7_4: # %else2 ; RV64ZVE32F-NEXT: .LBB7_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: andi a1, a0, 255
; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: andi a0, a0, 255 ; RV64ZVE32F-NEXT: andi a0, a0, 255
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: andi a1, a1, 255
; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: ret
%v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru) %v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0(<2 x ptr> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
%ev = zext <2 x i8> %v to <2 x i64> %ev = zext <2 x i8> %v to <2 x i64>
ret <2 x i64> %ev ret <2 x i64> %ev
} }
declare <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr>, i32, <4 x i1>, <4 x i8>) declare <4 x i8> @llvm.masked.gather.v4i8.v4p0(<4 x ptr>, i32, <4 x i1>, <4 x i8>)
▲ Show 20 Lines • Show All 636 Lines • ▼ Show 20 Lines
; RV64ZVE32F-NEXT: beqz a2, .LBB17_4 ; RV64ZVE32F-NEXT: beqz a2, .LBB17_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1 ; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lh a0, 0(a1) ; RV64ZVE32F-NEXT: lh a0, 0(a1)
; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 2, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a0 ; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 ; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB17_4: # %else2 ; RV64ZVE32F-NEXT: .LBB17_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: ret
%v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru) %v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0(<2 x ptr> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)
%ev = sext <2 x i16> %v to <2 x i64> %ev = sext <2 x i16> %v to <2 x i64>
ret <2 x i64> %ev ret <2 x i64> %ev
} }
define <2 x i64> @mgather_v2i16_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> %passthru) { define <2 x i64> @mgather_v2i16_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {
; RV32V-LABEL: mgather_v2i16_zextload_v2i64: ; RV32V-LABEL: mgather_v2i16_zextload_v2i64:
▲ Show 20 Lines • Show All 1,047 Lines • ▼ Show 20 Lines
; RV64ZVE32F-NEXT: beqz a2, .LBB29_4 ; RV64ZVE32F-NEXT: beqz a2, .LBB29_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1 ; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lw a0, 0(a1) ; RV64ZVE32F-NEXT: lw a0, 0(a1)
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a0 ; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 ; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB29_4: # %else2 ; RV64ZVE32F-NEXT: .LBB29_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v9
; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: ret
%v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru) %v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru)
%ev = sext <2 x i32> %v to <2 x i64> %ev = sext <2 x i32> %v to <2 x i64>
ret <2 x i64> %ev ret <2 x i64> %ev
} }
define <2 x i64> @mgather_v2i32_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i32> %passthru) { define <2 x i64> @mgather_v2i32_zextload_v2i64(<2 x ptr> %ptrs, <2 x i1> %m, <2 x i32> %passthru) {
; RV32V-LABEL: mgather_v2i32_zextload_v2i64: ; RV32V-LABEL: mgather_v2i32_zextload_v2i64:
Show All 40 Lines
; RV64ZVE32F-NEXT: beqz a2, .LBB30_4 ; RV64ZVE32F-NEXT: beqz a2, .LBB30_4
; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1 ; RV64ZVE32F-NEXT: # %bb.3: # %cond.load1
; RV64ZVE32F-NEXT: lw a0, 0(a1) ; RV64ZVE32F-NEXT: lw a0, 0(a1)
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a0 ; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1 ; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: .LBB30_4: # %else2 ; RV64ZVE32F-NEXT: .LBB30_4: # %else2
; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vslidedown.vi v9, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a0, v9
; RV64ZVE32F-NEXT: slli a0, a0, 32
; RV64ZVE32F-NEXT: srli a1, a0, 32
; RV64ZVE32F-NEXT: vmv.x.s a0, v8 ; RV64ZVE32F-NEXT: vmv.x.s a0, v8
; RV64ZVE32F-NEXT: slli a0, a0, 32 ; RV64ZVE32F-NEXT: slli a0, a0, 32
; RV64ZVE32F-NEXT: srli a0, a0, 32 ; RV64ZVE32F-NEXT: srli a0, a0, 32
; RV64ZVE32F-NEXT: vslidedown.vi v8, v8, 1
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: slli a1, a1, 32
; RV64ZVE32F-NEXT: srli a1, a1, 32
; RV64ZVE32F-NEXT: ret ; RV64ZVE32F-NEXT: ret
%v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru) %v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru)
%ev = zext <2 x i32> %v to <2 x i64> %ev = zext <2 x i32> %v to <2 x i64>
ret <2 x i64> %ev ret <2 x i64> %ev
} }
declare <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr>, i32, <4 x i1>, <4 x i32>) declare <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr>, i32, <4 x i1>, <4 x i32>)
▲ Show 20 Lines • Show All 10,128 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64V-LABEL: mgather_baseidx_v32i8: ; RV64V-LABEL: mgather_baseidx_v32i8:
; RV64V: # %bb.0: ; RV64V: # %bb.0:
; RV64V-NEXT: vmv1r.v v12, v0
; RV64V-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64V-NEXT: vslidedown.vi v14, v8, 16
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64V-NEXT: vsext.vf8 v16, v14 ; RV64V-NEXT: vsext.vf8 v16, v8
; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64V-NEXT: vmv1r.v v12, v10
; RV64V-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64V-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; RV64V-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64V-NEXT: vslidedown.vi v14, v10, 16 ; RV64V-NEXT: vslidedown.vi v10, v10, 16
; RV64V-NEXT: vslidedown.vi v8, v8, 16
; RV64V-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64V-NEXT: vsext.vf8 v16, v8
; RV64V-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64V-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64V-NEXT: vslidedown.vi v0, v0, 2 ; RV64V-NEXT: vslidedown.vi v0, v0, 2
; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64V-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64V-NEXT: vluxei64.v v14, (a0), v16, v0.t
; RV64V-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64V-NEXT: vsext.vf8 v16, v8
; RV64V-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64V-NEXT: vmv1r.v v0, v12
; RV64V-NEXT: vluxei64.v v10, (a0), v16, v0.t ; RV64V-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64V-NEXT: li a0, 32 ; RV64V-NEXT: li a0, 32
; RV64V-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; RV64V-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; RV64V-NEXT: vslideup.vi v10, v14, 16 ; RV64V-NEXT: vslideup.vi v12, v10, 16
; RV64V-NEXT: vmv.v.v v8, v10 ; RV64V-NEXT: vmv.v.v v8, v12
; RV64V-NEXT: ret ; RV64V-NEXT: ret
; ;
; RV64ZVE32F-LABEL: mgather_baseidx_v32i8: ; RV64ZVE32F-LABEL: mgather_baseidx_v32i8:
; RV64ZVE32F: # %bb.0: ; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma ; RV64ZVE32F-NEXT: vsetivli zero, 0, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.x.s a1, v0 ; RV64ZVE32F-NEXT: vmv.x.s a1, v0
; RV64ZVE32F-NEXT: andi a2, a1, 1 ; RV64ZVE32F-NEXT: andi a2, a1, 1
; RV64ZVE32F-NEXT: beqz a2, .LBB98_2 ; RV64ZVE32F-NEXT: beqz a2, .LBB98_2
▲ Show 20 Lines • Show All 467 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 10,844 Lines • ▼ Show 20 Lines
; ;
; RV64-LABEL: mscatter_baseidx_v32i8: ; RV64-LABEL: mscatter_baseidx_v32i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10 ; RV64-NEXT: vsext.vf8 v16, v10
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, ma ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vslidedown.vi v10, v10, 16 ; RV64-NEXT: vslidedown.vi v10, v10, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10 ; RV64-NEXT: vsext.vf8 v16, v10
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vsoxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV64ZVE32F-LABEL: mscatter_baseidx_v32i8: ; RV64ZVE32F-LABEL: mscatter_baseidx_v32i8:
; RV64ZVE32F: # %bb.0: ; RV64ZVE32F: # %bb.0:
▲ Show 20 Lines • Show All 400 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll

Show First 20 Lines • Show All 1,787 Lines • ▼ Show 20 Lines
define signext i8 @vpreduce_mul_v64i8(i8 signext %s, <64 x i8> %v, <64 x i1> %m, i32 zeroext %evl) { define signext i8 @vpreduce_mul_v64i8(i8 signext %s, <64 x i8> %v, <64 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_mul_v64i8: ; RV32-LABEL: vpreduce_mul_v64i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: lui a2, %hi(.LCPI72_0)
; RV32-NEXT: addi a2, a2, %lo(.LCPI72_0)
; RV32-NEXT: li a3, 32 ; RV32-NEXT: li a3, 32
; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV32-NEXT: lui a2, %hi(.LCPI72_0)
; RV32-NEXT: addi a2, a2, %lo(.LCPI72_0)
; RV32-NEXT: vle32.v v16, (a2) ; RV32-NEXT: vle32.v v16, (a2)
; RV32-NEXT: mv a2, a0 ; RV32-NEXT: mv a2, a0
; RV32-NEXT: vmsltu.vx v12, v16, a1 ; RV32-NEXT: vid.v v24
; RV32-NEXT: vid.v v16 ; RV32-NEXT: vmsltu.vx v12, v24, a1
; RV32-NEXT: vmsltu.vx v13, v16, a1 ; RV32-NEXT: vmsltu.vx v13, v16, a1
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vslideup.vi v13, v12, 4 ; RV32-NEXT: vslideup.vi v12, v13, 4
; RV32-NEXT: li a0, 64 ; RV32-NEXT: li a0, 64
; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV32-NEXT: vmand.mm v0, v13, v0 ; RV32-NEXT: vmand.mm v0, v12, v0
; RV32-NEXT: vmv.v.i v12, 1 ; RV32-NEXT: vmv.v.i v12, 1
; RV32-NEXT: vmerge.vvm v8, v12, v8, v0 ; RV32-NEXT: vmerge.vvm v8, v12, v8, v0
; RV32-NEXT: vslidedown.vx v12, v8, a3 ; RV32-NEXT: vslidedown.vx v12, v8, a3
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: vslidedown.vi v12, v8, 16 ; RV32-NEXT: vslidedown.vi v12, v8, 16
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
; RV32-NEXT: vslidedown.vi v12, v8, 8 ; RV32-NEXT: vslidedown.vi v12, v8, 8
; RV32-NEXT: vmul.vv v8, v8, v12 ; RV32-NEXT: vmul.vv v8, v8, v12
Show All 13 Lines
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpreduce_mul_v64i8: ; RV64-LABEL: vpreduce_mul_v64i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8 ; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: lui a2, %hi(.LCPI72_0)
; RV64-NEXT: addi a2, a2, %lo(.LCPI72_0)
; RV64-NEXT: li a3, 32 ; RV64-NEXT: li a3, 32
; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; RV64-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; RV64-NEXT: lui a2, %hi(.LCPI72_0)
; RV64-NEXT: addi a2, a2, %lo(.LCPI72_0)
; RV64-NEXT: vle32.v v16, (a2) ; RV64-NEXT: vle32.v v16, (a2)
; RV64-NEXT: mv a2, a0 ; RV64-NEXT: mv a2, a0
; RV64-NEXT: vmsltu.vx v12, v16, a1 ; RV64-NEXT: vid.v v24
; RV64-NEXT: vid.v v16 ; RV64-NEXT: vmsltu.vx v12, v24, a1
; RV64-NEXT: vmsltu.vx v13, v16, a1 ; RV64-NEXT: vmsltu.vx v13, v16, a1
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-NEXT: vslideup.vi v13, v12, 4 ; RV64-NEXT: vslideup.vi v12, v13, 4
; RV64-NEXT: li a0, 64 ; RV64-NEXT: li a0, 64
; RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; RV64-NEXT: vmand.mm v0, v13, v0 ; RV64-NEXT: vmand.mm v0, v12, v0
; RV64-NEXT: vmv.v.i v12, 1 ; RV64-NEXT: vmv.v.i v12, 1
; RV64-NEXT: vmerge.vvm v8, v12, v8, v0 ; RV64-NEXT: vmerge.vvm v8, v12, v8, v0
; RV64-NEXT: vslidedown.vx v12, v8, a3 ; RV64-NEXT: vslidedown.vx v12, v8, a3
; RV64-NEXT: vmul.vv v8, v8, v12 ; RV64-NEXT: vmul.vv v8, v8, v12
; RV64-NEXT: vslidedown.vi v12, v8, 16 ; RV64-NEXT: vslidedown.vi v12, v8, 16
; RV64-NEXT: vmul.vv v8, v8, v12 ; RV64-NEXT: vmul.vv v8, v8, v12
; RV64-NEXT: vslidedown.vi v12, v8, 8 ; RV64-NEXT: vslidedown.vi v12, v8, 8
; RV64-NEXT: vmul.vv v8, v8, v12 ; RV64-NEXT: vmul.vv v8, v8, v12
▲ Show 20 Lines • Show All 46 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

Show First 20 Lines • Show All 939 Lines • ▼ Show 20 Lines
declare i64 @llvm.vector.reduce.add.v1i64(<1 x i64>) declare i64 @llvm.vector.reduce.add.v1i64(<1 x i64>)
define i64 @vreduce_add_v1i64(ptr %x) { define i64 @vreduce_add_v1i64(ptr %x) {
; RV32-LABEL: vreduce_add_v1i64: ; RV32-LABEL: vreduce_add_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_add_v1i64: ; RV64-LABEL: vreduce_add_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <1 x i64>, ptr %x %v = load <1 x i64>, ptr %x
%red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %v) %red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %v)
ret i64 %red ret i64 %red
} }
define i64 @vwreduce_add_v1i64(ptr %x) { define i64 @vwreduce_add_v1i64(ptr %x) {
; RV32-LABEL: vwreduce_add_v1i64: ; RV32-LABEL: vwreduce_add_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vsext.vf2 v9, v8 ; RV32-NEXT: vsext.vf2 v9, v8
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32 ; RV32-NEXT: vsrl.vx v8, v9, a0
; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vwreduce_add_v1i64: ; RV64-LABEL: vwreduce_add_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vsext.vf2 v9, v8 ; RV64-NEXT: vsext.vf2 v9, v8
; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: vmv.x.s a0, v9
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <1 x i32>, ptr %x %v = load <1 x i32>, ptr %x
%e = sext <1 x i32> %v to <1 x i64> %e = sext <1 x i32> %v to <1 x i64>
%red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %e) %red = call i64 @llvm.vector.reduce.add.v1i64(<1 x i64> %e)
ret i64 %red ret i64 %red
} }
define i64 @vwreduce_uadd_v1i64(ptr %x) { define i64 @vwreduce_uadd_v1i64(ptr %x) {
; RV32-LABEL: vwreduce_uadd_v1i64: ; RV32-LABEL: vwreduce_uadd_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle32.v v8, (a0) ; RV32-NEXT: vle32.v v8, (a0)
; RV32-NEXT: vzext.vf2 v9, v8 ; RV32-NEXT: vzext.vf2 v9, v8
; RV32-NEXT: vmv.x.s a0, v9 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32 ; RV32-NEXT: vsrl.vx v8, v9, a0
; RV32-NEXT: vsrl.vx v8, v9, a1
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: vmv.x.s a0, v9
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vwreduce_uadd_v1i64: ; RV64-LABEL: vwreduce_uadd_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle32.v v8, (a0) ; RV64-NEXT: vle32.v v8, (a0)
; RV64-NEXT: vzext.vf2 v9, v8 ; RV64-NEXT: vzext.vf2 v9, v8
; RV64-NEXT: vmv.x.s a0, v9 ; RV64-NEXT: vmv.x.s a0, v9
▲ Show 20 Lines • Show All 1,117 Lines • ▼ Show 20 Lines
declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64>) declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64>)
define i64 @vreduce_and_v1i64(ptr %x) { define i64 @vreduce_and_v1i64(ptr %x) {
; RV32-LABEL: vreduce_and_v1i64: ; RV32-LABEL: vreduce_and_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_and_v1i64: ; RV64-LABEL: vreduce_and_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <1 x i64>, ptr %x %v = load <1 x i64>, ptr %x
%red = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %v) %red = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>) declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)
define i64 @vreduce_and_v2i64(ptr %x) { define i64 @vreduce_and_v2i64(ptr %x) {
; RV32-LABEL: vreduce_and_v2i64: ; RV32-LABEL: vreduce_and_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vredand.vs v8, v8, v8 ; RV32-NEXT: vredand.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_and_v2i64: ; RV64-LABEL: vreduce_and_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vredand.vs v8, v8, v8 ; RV64-NEXT: vredand.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
▲ Show 20 Lines • Show All 539 Lines • ▼ Show 20 Lines
declare i64 @llvm.vector.reduce.or.v1i64(<1 x i64>) declare i64 @llvm.vector.reduce.or.v1i64(<1 x i64>)
define i64 @vreduce_or_v1i64(ptr %x) { define i64 @vreduce_or_v1i64(ptr %x) {
; RV32-LABEL: vreduce_or_v1i64: ; RV32-LABEL: vreduce_or_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_or_v1i64: ; RV64-LABEL: vreduce_or_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <1 x i64>, ptr %x %v = load <1 x i64>, ptr %x
%red = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %v) %red = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>) declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
define i64 @vreduce_or_v2i64(ptr %x) { define i64 @vreduce_or_v2i64(ptr %x) {
; RV32-LABEL: vreduce_or_v2i64: ; RV32-LABEL: vreduce_or_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vredor.vs v8, v8, v8 ; RV32-NEXT: vredor.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_or_v2i64: ; RV64-LABEL: vreduce_or_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vredor.vs v8, v8, v8 ; RV64-NEXT: vredor.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
▲ Show 20 Lines • Show All 560 Lines • ▼ Show 20 Lines
declare i64 @llvm.vector.reduce.xor.v1i64(<1 x i64>) declare i64 @llvm.vector.reduce.xor.v1i64(<1 x i64>)
define i64 @vreduce_xor_v1i64(ptr %x) { define i64 @vreduce_xor_v1i64(ptr %x) {
; RV32-LABEL: vreduce_xor_v1i64: ; RV32-LABEL: vreduce_xor_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_xor_v1i64: ; RV64-LABEL: vreduce_xor_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
▲ Show 20 Lines • Show All 577 Lines • ▼ Show 20 Lines
declare i64 @llvm.vector.reduce.smin.v1i64(<1 x i64>) declare i64 @llvm.vector.reduce.smin.v1i64(<1 x i64>)
define i64 @vreduce_smin_v1i64(ptr %x) { define i64 @vreduce_smin_v1i64(ptr %x) {
; RV32-LABEL: vreduce_smin_v1i64: ; RV32-LABEL: vreduce_smin_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_smin_v1i64: ; RV64-LABEL: vreduce_smin_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <1 x i64>, ptr %x %v = load <1 x i64>, ptr %x
%red = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> %v) %red = call i64 @llvm.vector.reduce.smin.v1i64(<1 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>) declare i64 @llvm.vector.reduce.smin.v2i64(<2 x i64>)
define i64 @vreduce_smin_v2i64(ptr %x) { define i64 @vreduce_smin_v2i64(ptr %x) {
; RV32-LABEL: vreduce_smin_v2i64: ; RV32-LABEL: vreduce_smin_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vredmin.vs v8, v8, v8 ; RV32-NEXT: vredmin.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_smin_v2i64: ; RV64-LABEL: vreduce_smin_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vredmin.vs v8, v8, v8 ; RV64-NEXT: vredmin.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
▲ Show 20 Lines • Show All 539 Lines • ▼ Show 20 Lines
declare i64 @llvm.vector.reduce.smax.v1i64(<1 x i64>) declare i64 @llvm.vector.reduce.smax.v1i64(<1 x i64>)
define i64 @vreduce_smax_v1i64(ptr %x) { define i64 @vreduce_smax_v1i64(ptr %x) {
; RV32-LABEL: vreduce_smax_v1i64: ; RV32-LABEL: vreduce_smax_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_smax_v1i64: ; RV64-LABEL: vreduce_smax_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <1 x i64>, ptr %x %v = load <1 x i64>, ptr %x
%red = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> %v) %red = call i64 @llvm.vector.reduce.smax.v1i64(<1 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>) declare i64 @llvm.vector.reduce.smax.v2i64(<2 x i64>)
define i64 @vreduce_smax_v2i64(ptr %x) { define i64 @vreduce_smax_v2i64(ptr %x) {
; RV32-LABEL: vreduce_smax_v2i64: ; RV32-LABEL: vreduce_smax_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vredmax.vs v8, v8, v8 ; RV32-NEXT: vredmax.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_smax_v2i64: ; RV64-LABEL: vreduce_smax_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vredmax.vs v8, v8, v8 ; RV64-NEXT: vredmax.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
▲ Show 20 Lines • Show All 539 Lines • ▼ Show 20 Lines
declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>) declare i64 @llvm.vector.reduce.umin.v1i64(<1 x i64>)
define i64 @vreduce_umin_v1i64(ptr %x) { define i64 @vreduce_umin_v1i64(ptr %x) {
; RV32-LABEL: vreduce_umin_v1i64: ; RV32-LABEL: vreduce_umin_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_umin_v1i64: ; RV64-LABEL: vreduce_umin_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <1 x i64>, ptr %x %v = load <1 x i64>, ptr %x
%red = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> %v) %red = call i64 @llvm.vector.reduce.umin.v1i64(<1 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>) declare i64 @llvm.vector.reduce.umin.v2i64(<2 x i64>)
define i64 @vreduce_umin_v2i64(ptr %x) { define i64 @vreduce_umin_v2i64(ptr %x) {
; RV32-LABEL: vreduce_umin_v2i64: ; RV32-LABEL: vreduce_umin_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vredminu.vs v8, v8, v8 ; RV32-NEXT: vredminu.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_umin_v2i64: ; RV64-LABEL: vreduce_umin_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vredminu.vs v8, v8, v8 ; RV64-NEXT: vredminu.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
▲ Show 20 Lines • Show All 539 Lines • ▼ Show 20 Lines
declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64>) declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64>)
define i64 @vreduce_umax_v1i64(ptr %x) { define i64 @vreduce_umax_v1i64(ptr %x) {
; RV32-LABEL: vreduce_umax_v1i64: ; RV32-LABEL: vreduce_umax_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_umax_v1i64: ; RV64-LABEL: vreduce_umax_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = load <1 x i64>, ptr %x %v = load <1 x i64>, ptr %x
%red = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %v) %red = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>) declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64>)
define i64 @vreduce_umax_v2i64(ptr %x) { define i64 @vreduce_umax_v2i64(ptr %x) {
; RV32-LABEL: vreduce_umax_v2i64: ; RV32-LABEL: vreduce_umax_v2i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: vredmaxu.vs v8, v8, v8 ; RV32-NEXT: vredmaxu.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_umax_v2i64: ; RV64-LABEL: vreduce_umax_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vredmaxu.vs v8, v8, v8 ; RV64-NEXT: vredmaxu.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
▲ Show 20 Lines • Show All 689 Lines • ▼ Show 20 Lines
declare i64 @llvm.vector.reduce.mul.v1i64(<1 x i64>) declare i64 @llvm.vector.reduce.mul.v1i64(<1 x i64>)
define i64 @vreduce_mul_v1i64(ptr %x) { define i64 @vreduce_mul_v1i64(ptr %x) {
; RV32-LABEL: vreduce_mul_v1i64: ; RV32-LABEL: vreduce_mul_v1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vle64.v v8, (a0) ; RV32-NEXT: vle64.v v8, (a0)
; RV32-NEXT: li a0, 32
; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsrl.vx v8, v8, a1
; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_mul_v1i64: ; RV64-LABEL: vreduce_mul_v1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV64-NEXT: vle64.v v8, (a0) ; RV64-NEXT: vle64.v v8, (a0)
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
▲ Show 20 Lines • Show All 249 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-setcc-fp-vp.ll

Show First 20 Lines • Show All 240 Lines • ▼ Show 20 Lines
} }
define <8 x i1> @fcmp_ord_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ord_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_v8f16: ; CHECK-LABEL: fcmp_ord_vf_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v8, v9 ; CHECK-NEXT: vmand.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ord", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"ord", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ord_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ord_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_v8f16: ; CHECK-LABEL: fcmp_ord_vf_swap_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v9, v8 ; CHECK-NEXT: vmand.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ord", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"ord", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
▲ Show 20 Lines • Show All 232 Lines • ▼ Show 20 Lines
} }
define <8 x i1> @fcmp_uno_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uno_vf_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_v8f16: ; CHECK-LABEL: fcmp_uno_vf_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v8, v9 ; CHECK-NEXT: vmor.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uno", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %va, <8 x half> %vb, metadata !"uno", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_uno_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uno_vf_swap_v8f16(<8 x half> %va, half %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_v8f16: ; CHECK-LABEL: fcmp_uno_vf_swap_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %b, i32 0 %elt.head = insertelement <8 x half> poison, half %b, i32 0
%vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"uno", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f16(<8 x half> %vb, <8 x half> %va, metadata !"uno", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
▲ Show 20 Lines • Show All 308 Lines • ▼ Show 20 Lines
} }
define <8 x i1> @fcmp_ord_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ord_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_v8f64: ; CHECK-LABEL: fcmp_ord_vf_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v16, v12, fa0, v0.t
; CHECK-NEXT: vmfeq.vf v8, v12, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v16, v8 ; CHECK-NEXT: vmand.mm v0, v12, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ord", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"ord", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ord_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ord_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_v8f64: ; CHECK-LABEL: fcmp_ord_vf_swap_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v16, v12, fa0, v0.t
; CHECK-NEXT: vmfeq.vf v8, v12, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v8, v16 ; CHECK-NEXT: vmand.mm v0, v16, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"ord", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"ord", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_ueq_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_ueq_vv_v8f64(<8 x double> %va, <8 x double> %vb, <8 x i1> %m, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 234 Lines • ▼ Show 20 Lines
} }
define <8 x i1> @fcmp_uno_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uno_vf_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_v8f64: ; CHECK-LABEL: fcmp_uno_vf_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfne.vv v16, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v16, v12, fa0, v0.t
; CHECK-NEXT: vmfne.vf v8, v12, fa0, v0.t ; CHECK-NEXT: vmfne.vv v12, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v16, v8 ; CHECK-NEXT: vmor.mm v0, v12, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"uno", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %va, <8 x double> %vb, metadata !"uno", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
define <8 x i1> @fcmp_uno_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) { define <8 x i1> @fcmp_uno_vf_swap_v8f64(<8 x double> %va, double %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_v8f64: ; CHECK-LABEL: fcmp_uno_vf_swap_v8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; CHECK-NEXT: vmfne.vv v16, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v16, v12, fa0, v0.t
; CHECK-NEXT: vmfne.vf v8, v12, fa0, v0.t ; CHECK-NEXT: vmfne.vv v12, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v8, v16 ; CHECK-NEXT: vmor.mm v0, v16, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <8 x double> poison, double %b, i32 0 %elt.head = insertelement <8 x double> poison, double %b, i32 0
%vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer %vb = shufflevector <8 x double> %elt.head, <8 x double> poison, <8 x i32> zeroinitializer
%v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"uno", <8 x i1> %m, i32 %evl) %v = call <8 x i1> @llvm.vp.fcmp.v8f64(<8 x double> %vb, <8 x double> %va, metadata !"uno", <8 x i1> %m, i32 %evl)
ret <8 x i1> %v ret <8 x i1> %v
} }
declare <32 x i1> @llvm.vp.fcmp.v32f64(<32 x double>, <32 x double>, metadata, <32 x i1>, i32) declare <32 x i1> @llvm.vp.fcmp.v32f64(<32 x double>, <32 x double>, metadata, <32 x i1>, i32)
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sext-vp.ll

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <4 x i64> %v ret <4 x i64> %v
} }
declare <32 x i64> @llvm.vp.sext.v32i64.v32i32(<32 x i32>, <32 x i1>, i32) declare <32 x i64> @llvm.vp.sext.v32i64.v32i32(<32 x i32>, <32 x i1>, i32)
define <32 x i64> @vsext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vsext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsext_v32i64_v32i32: ; CHECK-LABEL: vsext_v32i64_v32i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v16, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB12_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v8, 16
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vsext.vf2 v16, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB12_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB12_2: ; CHECK-NEXT: .LBB12_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vsext.vf2 v24, v8, v0.t ; CHECK-NEXT: vsext.vf2 v24, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vsext.vf2 v16, v8, v0.t
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.sext.v32i64.v32i32(<32 x i32> %va, <32 x i1> %m, i32 %evl) %v = call <32 x i64> @llvm.vp.sext.v32i64.v32i32(<32 x i32> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vsext_v32i64_v32i32_unmasked(<32 x i32> %va, i32 zeroext %evl) { define <32 x i64> @vsext_v32i64_v32i32_unmasked(<32 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsext_v32i64_v32i32_unmasked: ; CHECK-LABEL: vsext_v32i64_v32i32_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB13_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v8, 16
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vsext.vf2 v16, v24
; CHECK-NEXT: bltu a0, a1, .LBB13_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB13_2: ; CHECK-NEXT: .LBB13_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vsext.vf2 v24, v8 ; CHECK-NEXT: vsext.vf2 v24, v8
; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vsext.vf2 v16, v8
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.sext.v32i64.v32i32(<32 x i32> %va, <32 x i1> shufflevector (<32 x i1> insertelement (<32 x i1> undef, i1 true, i32 0), <32 x i1> undef, <32 x i32> zeroinitializer), i32 %evl) %v = call <32 x i64> @llvm.vp.sext.v32i64.v32i32(<32 x i32> %va, <32 x i1> shufflevector (<32 x i1> insertelement (<32 x i1> undef, i1 true, i32 0), <32 x i1> undef, <32 x i32> zeroinitializer), i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
declare <4 x i16> @llvm.vp.sext.v4i16.v4i7(<4 x i7>, <4 x i1>, i32) declare <4 x i16> @llvm.vp.sext.v4i16.v4i7(<4 x i7>, <4 x i1>, i32)
define <4 x i16> @vsext_v4i16_v4i7(<4 x i7> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i16> @vsext_v4i16_v4i7(<4 x i7> %va, <4 x i1> %m, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll

Show First 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; ZVBB-NEXT: ret ; ZVBB-NEXT: ret
%res = call <16 x i1> @llvm.experimental.vector.reverse.v16i1(<16 x i1> %a) %res = call <16 x i1> @llvm.experimental.vector.reverse.v16i1(<16 x i1> %a)
ret <16 x i1> %res ret <16 x i1> %res
} }
define <32 x i1> @reverse_v32i1(<32 x i1> %a) { define <32 x i1> @reverse_v32i1(<32 x i1> %a) {
; NO-ZVBB-LABEL: reverse_v32i1: ; NO-ZVBB-LABEL: reverse_v32i1:
; NO-ZVBB: # %bb.0: ; NO-ZVBB: # %bb.0:
; NO-ZVBB-NEXT: li a0, 32
; NO-ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; NO-ZVBB-NEXT: lui a0, %hi(.LCPI4_0) ; NO-ZVBB-NEXT: lui a0, %hi(.LCPI4_0)
; NO-ZVBB-NEXT: addi a0, a0, %lo(.LCPI4_0) ; NO-ZVBB-NEXT: addi a0, a0, %lo(.LCPI4_0)
; NO-ZVBB-NEXT: li a1, 32
; NO-ZVBB-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; NO-ZVBB-NEXT: vle8.v v8, (a0) ; NO-ZVBB-NEXT: vle8.v v8, (a0)
; NO-ZVBB-NEXT: vmv.v.i v10, 0 ; NO-ZVBB-NEXT: vmv.v.i v10, 0
; NO-ZVBB-NEXT: vmerge.vim v10, v10, 1, v0 ; NO-ZVBB-NEXT: vmerge.vim v10, v10, 1, v0
; NO-ZVBB-NEXT: vrgather.vv v12, v10, v8 ; NO-ZVBB-NEXT: vrgather.vv v12, v10, v8
; NO-ZVBB-NEXT: vmsne.vi v0, v12, 0 ; NO-ZVBB-NEXT: vmsne.vi v0, v12, 0
; NO-ZVBB-NEXT: ret ; NO-ZVBB-NEXT: ret
; ;
; ZVBB-LABEL: reverse_v32i1: ; ZVBB-LABEL: reverse_v32i1:
; ZVBB: # %bb.0: ; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; ZVBB-NEXT: vbrev.v v0, v0 ; ZVBB-NEXT: vbrev.v v0, v0
; ZVBB-NEXT: ret ; ZVBB-NEXT: ret
%res = call <32 x i1> @llvm.experimental.vector.reverse.v32i1(<32 x i1> %a) %res = call <32 x i1> @llvm.experimental.vector.reverse.v32i1(<32 x i1> %a)
ret <32 x i1> %res ret <32 x i1> %res
} }
define <64 x i1> @reverse_v64i1(<64 x i1> %a) { define <64 x i1> @reverse_v64i1(<64 x i1> %a) {
; NO-ZVBB-LABEL: reverse_v64i1: ; NO-ZVBB-LABEL: reverse_v64i1:
; NO-ZVBB: # %bb.0: ; NO-ZVBB: # %bb.0:
; NO-ZVBB-NEXT: li a0, 64
; NO-ZVBB-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; NO-ZVBB-NEXT: lui a0, %hi(.LCPI5_0) ; NO-ZVBB-NEXT: lui a0, %hi(.LCPI5_0)
; NO-ZVBB-NEXT: addi a0, a0, %lo(.LCPI5_0) ; NO-ZVBB-NEXT: addi a0, a0, %lo(.LCPI5_0)
; NO-ZVBB-NEXT: li a1, 64
; NO-ZVBB-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; NO-ZVBB-NEXT: vle8.v v8, (a0) ; NO-ZVBB-NEXT: vle8.v v8, (a0)
; NO-ZVBB-NEXT: vmv.v.i v12, 0 ; NO-ZVBB-NEXT: vmv.v.i v12, 0
; NO-ZVBB-NEXT: vmerge.vim v12, v12, 1, v0 ; NO-ZVBB-NEXT: vmerge.vim v12, v12, 1, v0
; NO-ZVBB-NEXT: vrgather.vv v16, v12, v8 ; NO-ZVBB-NEXT: vrgather.vv v16, v12, v8
; NO-ZVBB-NEXT: vmsne.vi v0, v16, 0 ; NO-ZVBB-NEXT: vmsne.vi v0, v16, 0
; NO-ZVBB-NEXT: ret ; NO-ZVBB-NEXT: ret
; ;
; ZVBB-LABEL: reverse_v64i1: ; ZVBB-LABEL: reverse_v64i1:
; ZVBB: # %bb.0: ; ZVBB: # %bb.0:
; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; ZVBB-NEXT: vbrev.v v0, v0 ; ZVBB-NEXT: vbrev.v v0, v0
; ZVBB-NEXT: ret ; ZVBB-NEXT: ret
%res = call <64 x i1> @llvm.experimental.vector.reverse.v64i1(<64 x i1> %a) %res = call <64 x i1> @llvm.experimental.vector.reverse.v64i1(<64 x i1> %a)
ret <64 x i1> %res ret <64 x i1> %res
} }
define <128 x i1> @reverse_v128i1(<128 x i1> %a) { define <128 x i1> @reverse_v128i1(<128 x i1> %a) {
; CHECK-LABEL: reverse_v128i1: ; CHECK-LABEL: reverse_v128i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: lui a0, %hi(.LCPI6_0) ; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI6_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI6_0)
; CHECK-NEXT: li a1, 128
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
; CHECK-NEXT: vle8.v v8, (a0) ; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmerge.vim v16, v16, 1, v0 ; CHECK-NEXT: vmerge.vim v16, v16, 1, v0
; CHECK-NEXT: vrgather.vv v24, v16, v8 ; CHECK-NEXT: vrgather.vv v24, v16, v8
; CHECK-NEXT: vmsne.vi v0, v24, 0 ; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <128 x i1> @llvm.experimental.vector.reverse.v128i1(<128 x i1> %a) %res = call <128 x i1> @llvm.experimental.vector.reverse.v128i1(<128 x i1> %a)
ret <128 x i1> %res ret <128 x i1> %res
▲ Show 20 Lines • Show All 1,010 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-sitofp-vp.ll

Show First 20 Lines • Show All 302 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <4 x double> %v ret <4 x double> %v
} }
declare <32 x double> @llvm.vp.sitofp.v32f64.v32i64(<32 x i64>, <32 x i1>, i32) declare <32 x double> @llvm.vp.sitofp.v32f64.v32i64(<32 x i64>, <32 x i1>, i32)
define <32 x double> @vsitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vsitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_v32f64_v32i64: ; CHECK-LABEL: vsitofp_v32f64_v32i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB25_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB25_2: ; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t ; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.sitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.sitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vsitofp_v32f64_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { define <32 x double> @vsitofp_v32f64_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_v32f64_v32i64_unmasked: ; CHECK-LABEL: vsitofp_v32f64_v32i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 18 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll

Show First 20 Lines • Show All 464 Lines • ▼ Show 20 Lines
} }
declare <32 x double> @llvm.experimental.vp.strided.load.v32f64.p0.i32(ptr, i32, <32 x i1>, i32) declare <32 x double> @llvm.experimental.vp.strided.load.v32f64.p0.i32(ptr, i32, <32 x i1>, i32)
; Widening + splitting (with HiIsEmpty == true) ; Widening + splitting (with HiIsEmpty == true)
define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask, i32 zeroext %evl) { define <33 x double> @strided_load_v33f64(ptr %ptr, i64 %stride, <33 x i1> %mask, i32 zeroext %evl) {
; CHECK-RV32-LABEL: strided_load_v33f64: ; CHECK-RV32-LABEL: strided_load_v33f64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: li a5, 32 ; CHECK-RV32-NEXT: li a3, 32
; CHECK-RV32-NEXT: vmv1r.v v8, v0 ; CHECK-RV32-NEXT: vmv1r.v v8, v0
; CHECK-RV32-NEXT: mv a3, a4 ; CHECK-RV32-NEXT: mv a5, a4
; CHECK-RV32-NEXT: bltu a4, a5, .LBB35_2 ; CHECK-RV32-NEXT: bltu a4, a3, .LBB35_2
; CHECK-RV32-NEXT: # %bb.1: ; CHECK-RV32-NEXT: # %bb.1:
; CHECK-RV32-NEXT: li a3, 32 ; CHECK-RV32-NEXT: li a5, 32
; CHECK-RV32-NEXT: .LBB35_2: ; CHECK-RV32-NEXT: .LBB35_2:
; CHECK-RV32-NEXT: mul a5, a3, a2 ; CHECK-RV32-NEXT: addi a3, a5, -16
; CHECK-RV32-NEXT: addi a6, a4, -32 ; CHECK-RV32-NEXT: sltu a6, a5, a3
; CHECK-RV32-NEXT: sltu a4, a4, a6 ; CHECK-RV32-NEXT: addi a7, a6, -1
; CHECK-RV32-NEXT: addi a4, a4, -1
; CHECK-RV32-NEXT: and a6, a4, a6
; CHECK-RV32-NEXT: li a4, 16
; CHECK-RV32-NEXT: add a5, a1, a5
; CHECK-RV32-NEXT: bltu a6, a4, .LBB35_4
; CHECK-RV32-NEXT: # %bb.3:
; CHECK-RV32-NEXT: li a6, 16 ; CHECK-RV32-NEXT: li a6, 16
; CHECK-RV32-NEXT: .LBB35_4: ; CHECK-RV32-NEXT: and a7, a7, a3
; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; CHECK-RV32-NEXT: mv a3, a5
; CHECK-RV32-NEXT: vslidedown.vi v0, v8, 4 ; CHECK-RV32-NEXT: bltu a5, a6, .LBB35_4
; CHECK-RV32-NEXT: vsetvli zero, a6, e64, m8, ta, ma ; CHECK-RV32-NEXT: # %bb.3:
; CHECK-RV32-NEXT: vlse64.v v16, (a5), a2, v0.t
; CHECK-RV32-NEXT: addi a5, a3, -16
; CHECK-RV32-NEXT: sltu a6, a3, a5
; CHECK-RV32-NEXT: addi a6, a6, -1
; CHECK-RV32-NEXT: and a5, a6, a5
; CHECK-RV32-NEXT: bltu a3, a4, .LBB35_6
; CHECK-RV32-NEXT: # %bb.5:
; CHECK-RV32-NEXT: li a3, 16 ; CHECK-RV32-NEXT: li a3, 16
; CHECK-RV32-NEXT: .LBB35_6: ; CHECK-RV32-NEXT: .LBB35_4:
; CHECK-RV32-NEXT: mul a4, a3, a2 ; CHECK-RV32-NEXT: mul t0, a3, a2
; CHECK-RV32-NEXT: add a4, a1, a4 ; CHECK-RV32-NEXT: add t0, a1, t0
; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-RV32-NEXT: vslidedown.vi v0, v8, 2 ; CHECK-RV32-NEXT: vslidedown.vi v0, v8, 2
; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (t0), a2, v0.t
; CHECK-RV32-NEXT: mul a7, a5, a2
; CHECK-RV32-NEXT: addi a5, a4, -32
; CHECK-RV32-NEXT: sltu a4, a4, a5
; CHECK-RV32-NEXT: addi a4, a4, -1
; CHECK-RV32-NEXT: and a5, a4, a5
; CHECK-RV32-NEXT: add a4, a1, a7
; CHECK-RV32-NEXT: bltu a5, a6, .LBB35_6
; CHECK-RV32-NEXT: # %bb.5:
; CHECK-RV32-NEXT: li a5, 16
; CHECK-RV32-NEXT: .LBB35_6:
; CHECK-RV32-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-RV32-NEXT: vslidedown.vi v0, v8, 4
; CHECK-RV32-NEXT: vsetvli zero, a5, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v24, (a4), a2, v0.t ; CHECK-RV32-NEXT: vlse64.v v24, (a4), a2, v0.t
; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv1r.v v0, v8 ; CHECK-RV32-NEXT: vmv1r.v v0, v8
; CHECK-RV32-NEXT: vlse64.v v8, (a1), a2, v0.t ; CHECK-RV32-NEXT: vlse64.v v8, (a1), a2, v0.t
; CHECK-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-RV32-NEXT: vse64.v v8, (a0) ; CHECK-RV32-NEXT: vse64.v v8, (a0)
; CHECK-RV32-NEXT: addi a1, a0, 256 ; CHECK-RV32-NEXT: addi a1, a0, 256
; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 1, e64, m8, ta, ma
; CHECK-RV32-NEXT: vse64.v v16, (a1) ; CHECK-RV32-NEXT: vse64.v v24, (a1)
; CHECK-RV32-NEXT: addi a0, a0, 128 ; CHECK-RV32-NEXT: addi a0, a0, 128
; CHECK-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-RV32-NEXT: vse64.v v24, (a0) ; CHECK-RV32-NEXT: vse64.v v16, (a0)
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: strided_load_v33f64: ; CHECK-RV64-LABEL: strided_load_v33f64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a5, 32 ; CHECK-RV64-NEXT: li a4, 32
; CHECK-RV64-NEXT: vmv1r.v v8, v0 ; CHECK-RV64-NEXT: vmv1r.v v8, v0
; CHECK-RV64-NEXT: mv a4, a3 ; CHECK-RV64-NEXT: mv a5, a3
; CHECK-RV64-NEXT: bltu a3, a5, .LBB35_2 ; CHECK-RV64-NEXT: bltu a3, a4, .LBB35_2
; CHECK-RV64-NEXT: # %bb.1: ; CHECK-RV64-NEXT: # %bb.1:
; CHECK-RV64-NEXT: li a4, 32 ; CHECK-RV64-NEXT: li a5, 32
; CHECK-RV64-NEXT: .LBB35_2: ; CHECK-RV64-NEXT: .LBB35_2:
; CHECK-RV64-NEXT: mul a5, a4, a2 ; CHECK-RV64-NEXT: addi a4, a5, -16
; CHECK-RV64-NEXT: addi a6, a3, -32 ; CHECK-RV64-NEXT: sltu a6, a5, a4
; CHECK-RV64-NEXT: sltu a3, a3, a6 ; CHECK-RV64-NEXT: addi a7, a6, -1
; CHECK-RV64-NEXT: addi a3, a3, -1
; CHECK-RV64-NEXT: and a6, a3, a6
; CHECK-RV64-NEXT: li a3, 16
; CHECK-RV64-NEXT: add a5, a1, a5
; CHECK-RV64-NEXT: bltu a6, a3, .LBB35_4
; CHECK-RV64-NEXT: # %bb.3:
; CHECK-RV64-NEXT: li a6, 16 ; CHECK-RV64-NEXT: li a6, 16
; CHECK-RV64-NEXT: .LBB35_4: ; CHECK-RV64-NEXT: and a7, a7, a4
; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; CHECK-RV64-NEXT: mv a4, a5
; CHECK-RV64-NEXT: vslidedown.vi v0, v8, 4 ; CHECK-RV64-NEXT: bltu a5, a6, .LBB35_4
; CHECK-RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma ; CHECK-RV64-NEXT: # %bb.3:
; CHECK-RV64-NEXT: vlse64.v v16, (a5), a2, v0.t
; CHECK-RV64-NEXT: addi a5, a4, -16
; CHECK-RV64-NEXT: sltu a6, a4, a5
; CHECK-RV64-NEXT: addi a6, a6, -1
; CHECK-RV64-NEXT: and a5, a6, a5
; CHECK-RV64-NEXT: bltu a4, a3, .LBB35_6
; CHECK-RV64-NEXT: # %bb.5:
; CHECK-RV64-NEXT: li a4, 16 ; CHECK-RV64-NEXT: li a4, 16
; CHECK-RV64-NEXT: .LBB35_6: ; CHECK-RV64-NEXT: .LBB35_4:
; CHECK-RV64-NEXT: mul a3, a4, a2 ; CHECK-RV64-NEXT: mul t0, a4, a2
; CHECK-RV64-NEXT: add a3, a1, a3 ; CHECK-RV64-NEXT: add t0, a1, t0
; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-RV64-NEXT: vslidedown.vi v0, v8, 2 ; CHECK-RV64-NEXT: vslidedown.vi v0, v8, 2
; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v16, (t0), a2, v0.t
; CHECK-RV64-NEXT: mul a7, a5, a2
; CHECK-RV64-NEXT: addi a5, a3, -32
; CHECK-RV64-NEXT: sltu a3, a3, a5
; CHECK-RV64-NEXT: addi a3, a3, -1
; CHECK-RV64-NEXT: and a5, a3, a5
; CHECK-RV64-NEXT: add a3, a1, a7
; CHECK-RV64-NEXT: bltu a5, a6, .LBB35_6
; CHECK-RV64-NEXT: # %bb.5:
; CHECK-RV64-NEXT: li a5, 16
; CHECK-RV64-NEXT: .LBB35_6:
; CHECK-RV64-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-RV64-NEXT: vslidedown.vi v0, v8, 4
; CHECK-RV64-NEXT: vsetvli zero, a5, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v24, (a3), a2, v0.t ; CHECK-RV64-NEXT: vlse64.v v24, (a3), a2, v0.t
; CHECK-RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-RV64-NEXT: vmv1r.v v0, v8 ; CHECK-RV64-NEXT: vmv1r.v v0, v8
; CHECK-RV64-NEXT: vlse64.v v8, (a1), a2, v0.t ; CHECK-RV64-NEXT: vlse64.v v8, (a1), a2, v0.t
; CHECK-RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-RV64-NEXT: vse64.v v8, (a0) ; CHECK-RV64-NEXT: vse64.v v8, (a0)
; CHECK-RV64-NEXT: addi a1, a0, 256 ; CHECK-RV64-NEXT: addi a1, a0, 256
; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 1, e64, m8, ta, ma
; CHECK-RV64-NEXT: vse64.v v16, (a1) ; CHECK-RV64-NEXT: vse64.v v24, (a1)
; CHECK-RV64-NEXT: addi a0, a0, 128 ; CHECK-RV64-NEXT: addi a0, a0, 128
; CHECK-RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-RV64-NEXT: vse64.v v24, (a0) ; CHECK-RV64-NEXT: vse64.v v16, (a0)
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
%v = call <33 x double> @llvm.experimental.vp.strided.load.v33f64.p0.i64(ptr %ptr, i64 %stride, <33 x i1> %mask, i32 %evl) %v = call <33 x double> @llvm.experimental.vp.strided.load.v33f64.p0.i64(ptr %ptr, i64 %stride, <33 x i1> %mask, i32 %evl)
ret <33 x double> %v ret <33 x double> %v
} }
declare <33 x double> @llvm.experimental.vp.strided.load.v33f64.p0.i64(ptr, i64, <33 x i1>, i32) declare <33 x double> @llvm.experimental.vp.strided.load.v33f64.p0.i64(ptr, i64, <33 x i1>, i32)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-trunc-vp.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <2 x i8> %v ret <2 x i8> %v
} }
declare <128 x i7> @llvm.vp.trunc.v128i7.v128i16(<128 x i16>, <128 x i1>, i32) declare <128 x i7> @llvm.vp.trunc.v128i7.v128i16(<128 x i16>, <128 x i1>, i32)
define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zeroext %vl) { define <128 x i7> @vtrunc_v128i7_v128i16(<128 x i16> %a, <128 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v128i7_v128i16: ; CHECK-LABEL: vtrunc_v128i7_v128i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v28, v0 ; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 8
; CHECK-NEXT: addi a1, a0, -64
; CHECK-NEXT: sltu a2, a0, a1
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
; CHECK-NEXT: li a1, 64 ; CHECK-NEXT: li a1, 64
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t ; CHECK-NEXT: vslidedown.vi v12, v0, 8
; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: bltu a0, a1, .LBB4_2 ; CHECK-NEXT: bltu a0, a1, .LBB4_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 64 ; CHECK-NEXT: li a2, 64
; CHECK-NEXT: .LBB4_2: ; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t
; CHECK-NEXT: addi a2, a0, -64
; CHECK-NEXT: sltu a0, a0, a2
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a2
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v28 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t ; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: li a0, 128 ; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vslideup.vx v16, v24, a1 ; CHECK-NEXT: vslideup.vx v8, v24, a1
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <128 x i7> @llvm.vp.trunc.v128i7.v128i16(<128 x i16> %a, <128 x i1> %m, i32 %vl) %v = call <128 x i7> @llvm.vp.trunc.v128i7.v128i16(<128 x i16> %a, <128 x i1> %m, i32 %vl)
ret <128 x i7> %v ret <128 x i7> %v
} }
declare <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32>, <2 x i1>, i32) declare <2 x i8> @llvm.vp.trunc.v2i8.v2i32(<2 x i32>, <2 x i1>, i32)
define <2 x i8> @vtrunc_v2i8_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) { define <2 x i8> @vtrunc_v2i8_v2i32(<2 x i32> %a, <2 x i1> %m, i32 zeroext %vl) {
▲ Show 20 Lines • Show All 137 Lines • ▼ Show 20 Lines
declare <128 x i32> @llvm.vp.trunc.v128i32.v128i64(<128 x i64>, <128 x i1>, i32) declare <128 x i32> @llvm.vp.trunc.v128i32.v128i64(<128 x i64>, <128 x i1>, i32)
define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 zeroext %vl) { define <128 x i32> @vtrunc_v128i32_v128i64(<128 x i64> %a, <128 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v128i32_v128i64: ; CHECK-LABEL: vtrunc_v128i32_v128i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 56 ; CHECK-NEXT: slli a2, a2, 6
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: sub sp, sp, a2 ; CHECK-NEXT: sub sp, sp, a2
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xc0, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 64 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4 ; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: slli a2, a2, 5
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v3, v0, 8 ; CHECK-NEXT: vslidedown.vi v3, v0, 8
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v2, v0, 4 ; CHECK-NEXT: vslidedown.vi v26, v0, 4
; CHECK-NEXT: addi a2, a1, 512 ; CHECK-NEXT: addi a2, a1, 512
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a2) ; CHECK-NEXT: vle64.v v8, (a2)
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 40 ; CHECK-NEXT: li a3, 48
; CHECK-NEXT: mul a2, a2, a3 ; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v27, v3, 4 ; CHECK-NEXT: vslidedown.vi v27, v3, 4
; CHECK-NEXT: addi a2, a1, 640 ; CHECK-NEXT: addi a2, a1, 640
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
Show All 10 Lines
; CHECK-NEXT: addi a2, a3, -16 ; CHECK-NEXT: addi a2, a3, -16
; CHECK-NEXT: sltu a5, a3, a2 ; CHECK-NEXT: sltu a5, a3, a2
; CHECK-NEXT: addi a5, a5, -1 ; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a2, a5, a2 ; CHECK-NEXT: and a2, a5, a2
; CHECK-NEXT: vslidedown.vi v0, v27, 2 ; CHECK-NEXT: vslidedown.vi v0, v27, 2
; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t ; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a5, a1, 128 ; CHECK-NEXT: addi a5, a1, 128
; CHECK-NEXT: bltu a3, a2, .LBB16_2 ; CHECK-NEXT: bltu a3, a2, .LBB16_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a3, 16 ; CHECK-NEXT: li a3, 16
; CHECK-NEXT: .LBB16_2: ; CHECK-NEXT: .LBB16_2:
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v4, v2, 2 ; CHECK-NEXT: vslidedown.vi v28, v26, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a5) ; CHECK-NEXT: vle64.v v8, (a5)
; CHECK-NEXT: addi a5, sp, 16
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m4, ta, ma
; CHECK-NEXT: li a3, 64 ; CHECK-NEXT: li a3, 64
; CHECK-NEXT: vmv1r.v v0, v27 ; CHECK-NEXT: vmv1r.v v0, v27
; CHECK-NEXT: csrr a5, vlenb ; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: li a6, 40 ; CHECK-NEXT: li a6, 48
; CHECK-NEXT: mul a5, a5, a6 ; CHECK-NEXT: mul a5, a5, a6
; CHECK-NEXT: add a5, sp, a5 ; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16 ; CHECK-NEXT: addi a5, a5, 16
; CHECK-NEXT: vl8r.v v8, (a5) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a5) # Unknown-size Folded Reload
; CHECK-NEXT: vnsrl.wi v24, v8, 0, v0.t ; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
; CHECK-NEXT: csrr a5, vlenb ; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: li a6, 48 ; CHECK-NEXT: li a6, 56
; CHECK-NEXT: mul a5, a5, a6 ; CHECK-NEXT: mul a5, a5, a6
; CHECK-NEXT: add a5, sp, a5 ; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16 ; CHECK-NEXT: addi a5, a5, 16
; CHECK-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; CHECK-NEXT: bltu a7, a3, .LBB16_4 ; CHECK-NEXT: bltu a7, a3, .LBB16_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: li a7, 64 ; CHECK-NEXT: li a7, 64
; CHECK-NEXT: .LBB16_4: ; CHECK-NEXT: .LBB16_4:
; CHECK-NEXT: addi a5, a1, 384
; CHECK-NEXT: li a3, 32 ; CHECK-NEXT: li a3, 32
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a1) ; CHECK-NEXT: vle64.v v8, (a1)
; CHECK-NEXT: addi a5, a7, -32 ; CHECK-NEXT: csrr a6, vlenb
; CHECK-NEXT: sltu a6, a7, a5 ; CHECK-NEXT: li t0, 40
; CHECK-NEXT: addi a6, a6, -1 ; CHECK-NEXT: mul a6, a6, t0
; CHECK-NEXT: and a5, a6, a5 ; CHECK-NEXT: add a6, sp, a6
; CHECK-NEXT: addi a6, a5, -16 ; CHECK-NEXT: addi a6, a6, 16
; CHECK-NEXT: sltu t0, a5, a6 ; CHECK-NEXT: vs8r.v v8, (a6) # Unknown-size Folded Spill
; CHECK-NEXT: addi a6, a7, -32
; CHECK-NEXT: sltu t0, a7, a6
; CHECK-NEXT: addi t0, t0, -1 ; CHECK-NEXT: addi t0, t0, -1
; CHECK-NEXT: and a6, t0, a6 ; CHECK-NEXT: and a6, t0, a6
; CHECK-NEXT: vsetvli zero, a6, e32, m4, ta, ma ; CHECK-NEXT: addi t0, a6, -16
; CHECK-NEXT: vmv1r.v v0, v4 ; CHECK-NEXT: sltu t1, a6, t0
; CHECK-NEXT: addi t1, t1, -1
; CHECK-NEXT: and t0, t1, t0
; CHECK-NEXT: vsetvli zero, t0, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v28
; CHECK-NEXT: addi t0, sp, 16
; CHECK-NEXT: vl8r.v v16, (t0) # Unknown-size Folded Reload
; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t ; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
; CHECK-NEXT: addi a6, sp, 16 ; CHECK-NEXT: csrr t0, vlenb
; CHECK-NEXT: vs8r.v v8, (a6) # Unknown-size Folded Spill ; CHECK-NEXT: slli t0, t0, 3
; CHECK-NEXT: bltu a5, a2, .LBB16_6 ; CHECK-NEXT: add t0, sp, t0
; CHECK-NEXT: addi t0, t0, 16
; CHECK-NEXT: vs8r.v v8, (t0) # Unknown-size Folded Spill
; CHECK-NEXT: bltu a6, a2, .LBB16_6
; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: li a5, 16 ; CHECK-NEXT: li a6, 16
; CHECK-NEXT: .LBB16_6: ; CHECK-NEXT: .LBB16_6:
; CHECK-NEXT: addi a6, a1, 384 ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v20, v3, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a5)
; CHECK-NEXT: addi a1, a1, 256 ; CHECK-NEXT: addi a1, a1, 256
; CHECK-NEXT: vsetvli zero, a5, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a6, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v2 ; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t
; CHECK-NEXT: csrr a5, vlenb ; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: li t0, 40 ; CHECK-NEXT: li a6, 40
; CHECK-NEXT: mul a5, a5, t0 ; CHECK-NEXT: mul a5, a5, a6
; CHECK-NEXT: add a5, sp, a5 ; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16 ; CHECK-NEXT: addi a5, a5, 16
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill ; CHECK-NEXT: vl8r.v v24, (a5) # Unknown-size Folded Reload
; CHECK-NEXT: vnsrl.wi v16, v24, 0, v0.t
; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: li a6, 48
; CHECK-NEXT: mul a5, a5, a6
; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16
; CHECK-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; CHECK-NEXT: bltu a4, a3, .LBB16_8 ; CHECK-NEXT: bltu a4, a3, .LBB16_8
; CHECK-NEXT: # %bb.7: ; CHECK-NEXT: # %bb.7:
; CHECK-NEXT: li a4, 32 ; CHECK-NEXT: li a4, 32
; CHECK-NEXT: .LBB16_8: ; CHECK-NEXT: .LBB16_8:
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v3, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a6)
; CHECK-NEXT: vle64.v v24, (a1) ; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: mv a1, a4 ; CHECK-NEXT: addi a1, a4, -16
; CHECK-NEXT: sltu a5, a4, a1
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a1, a5, a1
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v20
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t
; CHECK-NEXT: bltu a4, a2, .LBB16_10 ; CHECK-NEXT: bltu a4, a2, .LBB16_10
; CHECK-NEXT: # %bb.9: ; CHECK-NEXT: # %bb.9:
; CHECK-NEXT: li a1, 16 ; CHECK-NEXT: li a4, 16
; CHECK-NEXT: .LBB16_10: ; CHECK-NEXT: .LBB16_10:
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v2, v1, 2 ; CHECK-NEXT: vslidedown.vi v2, v1, 2
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a4, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v3 ; CHECK-NEXT: vmv1r.v v0, v3
; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t ; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: li a4, 40
; CHECK-NEXT: mul a1, a1, a4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a1, a4, -16
; CHECK-NEXT: sltu a4, a4, a1
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a1, a4, a1
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: bltu a7, a3, .LBB16_12 ; CHECK-NEXT: bltu a7, a3, .LBB16_12
; CHECK-NEXT: # %bb.11: ; CHECK-NEXT: # %bb.11:
; CHECK-NEXT: li a7, 32 ; CHECK-NEXT: li a7, 32
; CHECK-NEXT: .LBB16_12: ; CHECK-NEXT: .LBB16_12:
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a4, 48 ; CHECK-NEXT: li a4, 56
; CHECK-NEXT: mul a1, a1, a4 ; CHECK-NEXT: mul a1, a1, a4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vslideup.vi v16, v8, 16 ; CHECK-NEXT: vslideup.vi v8, v24, 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a4, 48 ; CHECK-NEXT: li a4, 56
; CHECK-NEXT: mul a1, a1, a4 ; CHECK-NEXT: mul a1, a1, a4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vmv4r.v v16, v8 ; CHECK-NEXT: vmv4r.v v24, v8
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a4, 40 ; CHECK-NEXT: li a4, 48
; CHECK-NEXT: mul a1, a1, a4 ; CHECK-NEXT: mul a1, a1, a4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vslideup.vi v8, v16, 16 ; CHECK-NEXT: vslideup.vi v8, v24, 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a4, 40 ; CHECK-NEXT: li a4, 48
; CHECK-NEXT: mul a1, a1, a4 ; CHECK-NEXT: mul a1, a1, a4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: li a4, 40
; CHECK-NEXT: mul a1, a1, a4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vslideup.vi v8, v24, 16 ; CHECK-NEXT: vslideup.vi v8, v16, 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: li a4, 40
; CHECK-NEXT: mul a1, a1, a4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a1, a7, -16 ; CHECK-NEXT: addi a1, a7, -16
; CHECK-NEXT: sltu a4, a7, a1 ; CHECK-NEXT: sltu a4, a7, a1
; CHECK-NEXT: addi a4, a4, -1 ; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a1, a4, a1 ; CHECK-NEXT: and a1, a4, a1
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v2 ; CHECK-NEXT: vmv1r.v v0, v2
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: li a4, 24
; CHECK-NEXT: mul a1, a1, a4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t ; CHECK-NEXT: vnsrl.wi v8, v16, 0, v0.t
; CHECK-NEXT: bltu a7, a2, .LBB16_14 ; CHECK-NEXT: bltu a7, a2, .LBB16_14
; CHECK-NEXT: # %bb.13: ; CHECK-NEXT: # %bb.13:
; CHECK-NEXT: li a7, 16 ; CHECK-NEXT: li a7, 16
; CHECK-NEXT: .LBB16_14: ; CHECK-NEXT: .LBB16_14:
; CHECK-NEXT: vsetvli zero, a7, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a7, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a2, 24 ; CHECK-NEXT: slli a1, a1, 5
; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t ; CHECK-NEXT: vnsrl.wi v16, v24, 0, v0.t
; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e32, m8, ta, ma
; CHECK-NEXT: vslideup.vi v24, v8, 16 ; CHECK-NEXT: vslideup.vi v16, v8, 16
; CHECK-NEXT: vse32.v v24, (a0) ; CHECK-NEXT: vse32.v v16, (a0)
; CHECK-NEXT: addi a1, a0, 256 ; CHECK-NEXT: addi a1, a0, 256
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 5 ; CHECK-NEXT: li a3, 40
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: addi a1, a0, 128 ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 40 ; CHECK-NEXT: li a3, 48
; CHECK-NEXT: mul a2, a2, a3 ; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vse32.v v8, (a1) ; CHECK-NEXT: vse32.v v8, (a1)
; CHECK-NEXT: addi a0, a0, 384 ; CHECK-NEXT: addi a0, a0, 384
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a2, 48 ; CHECK-NEXT: li a2, 56
; CHECK-NEXT: mul a1, a1, a2 ; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vse32.v v8, (a0) ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 56 ; CHECK-NEXT: slli a0, a0, 6
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <128 x i32> @llvm.vp.trunc.v128i32.v128i64(<128 x i64> %a, <128 x i1> %m, i32 %vl) %v = call <128 x i32> @llvm.vp.trunc.v128i32.v128i64(<128 x i64> %a, <128 x i1> %m, i32 %vl)
ret <128 x i32> %v ret <128 x i32> %v
} }
declare <32 x i32> @llvm.vp.trunc.v32i32.v32i64(<32 x i64>, <32 x i1>, i32) declare <32 x i32> @llvm.vp.trunc.v32i32.v32i64(<32 x i64>, <32 x i1>, i32)
define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext %vl) { define <32 x i32> @vtrunc_v32i32_v32i64(<32 x i64> %a, <32 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v32i32_v32i64: ; CHECK-LABEL: vtrunc_v32i32_v32i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v28, v0 ; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v12, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB17_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB17_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB17_2: ; CHECK-NEXT: .LBB17_2:
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v24, 0, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v28 ; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t ; CHECK-NEXT: vnsrl.wi v24, v16, 0, v0.t
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; CHECK-NEXT: vslideup.vi v16, v24, 16 ; CHECK-NEXT: vslideup.vi v8, v24, 16
; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x i32> @llvm.vp.trunc.v32i32.v32i64(<32 x i64> %a, <32 x i1> %m, i32 %vl) %v = call <32 x i32> @llvm.vp.trunc.v32i32.v32i64(<32 x i64> %a, <32 x i1> %m, i32 %vl)
ret <32 x i32> %v ret <32 x i32> %v
} }
declare <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8>, <2 x i1>, i32) declare <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8>, <2 x i1>, i32)
define <2 x i7> @vtrunc_v2i7_v2i8(<2 x i8> %a, <2 x i1> %m, i32 zeroext %vl) { define <2 x i7> @vtrunc_v2i7_v2i8(<2 x i8> %a, <2 x i1> %m, i32 zeroext %vl) {
; CHECK-LABEL: vtrunc_v2i7_v2i8: ; CHECK-LABEL: vtrunc_v2i7_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8> %a, <2 x i1> %m, i32 %vl) %v = call <2 x i7> @llvm.vp.trunc.v2i7.v2i8(<2 x i8> %a, <2 x i1> %m, i32 %vl)
ret <2 x i7> %v ret <2 x i7> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-uitofp-vp.ll

Show First 20 Lines • Show All 302 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <4 x double> %v ret <4 x double> %v
} }
declare <32 x double> @llvm.vp.uitofp.v32f64.v32i64(<32 x i64>, <32 x i1>, i32) declare <32 x double> @llvm.vp.uitofp.v32f64.v32i64(<32 x i64>, <32 x i1>, i32)
define <32 x double> @vuitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vuitofp_v32f64_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_v32f64_v32i64: ; CHECK-LABEL: vuitofp_v32f64_v32i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB25_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB25_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB25_2: ; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t ; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.uitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.uitofp.v32f64.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vuitofp_v32f64_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { define <32 x double> @vuitofp_v32f64_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_v32f64_v32i64_unmasked: ; CHECK-LABEL: vuitofp_v32f64_v32i64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 18 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll

Show First 20 Lines • Show All 1,522 Lines • ▼ Show 20 Lines
; Test that split-legalization works as expected. ; Test that split-legalization works as expected.
declare <32 x i64> @llvm.vp.add.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32) declare <32 x i64> @llvm.vp.add.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32)
define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vadd_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vadd_vx_v32i64: ; RV32-LABEL: vadd_vx_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v1, v0, 2
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: li a2, 16
; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vmv.v.i v24, -1
; RV32-NEXT: addi a1, a0, -16 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: sltu a2, a0, a1 ; RV32-NEXT: bltu a0, a2, .LBB108_2
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a1, a2, a1
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: li a1, 16
; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
; RV32-NEXT: bltu a0, a1, .LBB108_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a0, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB108_2: ; RV32-NEXT: .LBB108_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
; RV32-NEXT: addi a1, a0, -16
; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vadd.vv v8, v8, v24, v0.t ; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_v32i64: ; RV64-LABEL: vadd_vx_v32i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: li a2, 16
; RV64-NEXT: addi a1, a0, -16 ; RV64-NEXT: vslidedown.vi v24, v0, 2
; RV64-NEXT: sltu a2, a0, a1 ; RV64-NEXT: mv a1, a0
; RV64-NEXT: addi a2, a2, -1 ; RV64-NEXT: bltu a0, a2, .LBB108_2
; RV64-NEXT: and a1, a2, a1
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: li a1, 16
; RV64-NEXT: vadd.vi v16, v16, -1, v0.t
; RV64-NEXT: bltu a0, a1, .LBB108_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a0, 16 ; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB108_2: ; RV64-NEXT: .LBB108_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v8, v8, -1, v0.t
; RV64-NEXT: addi a1, a0, -16
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vadd.vi v8, v8, -1, v0.t ; RV64-NEXT: vadd.vi v16, v16, -1, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { define <32 x i64> @vadd_vi_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 12) %v = call <32 x i64> @llvm.vp.add.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 12)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) { define <32 x i64> @vadd_vx_v32i64_evl27(<32 x i64> %va, <32 x i1> %m) {
; RV32-LABEL: vadd_vx_v32i64_evl27: ; RV32-LABEL: vadd_vx_v32i64_evl27:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v1, v0, 2
; RV32-NEXT: li a0, 32 ; RV32-NEXT: li a0, 32
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vmv.v.i v24, -1
; RV32-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV32-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vadd.vv v8, v8, v24, v0.t ; RV32-NEXT: vadd.vv v8, v8, v24, v0.t
; RV32-NEXT: vsetivli zero, 11, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vadd.vv v16, v16, v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vadd_vx_v32i64_evl27: ; RV64-LABEL: vadd_vx_v32i64_evl27:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v24, v0, 2 ; RV64-NEXT: vslidedown.vi v24, v0, 2
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vadd.vi v8, v8, -1, v0.t ; RV64-NEXT: vadd.vi v8, v8, -1, v0.t
Show All 9 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vcopysign-vp.ll

Show First 20 Lines • Show All 318 Lines • ▼ Show 20 Lines
declare <32 x double> @llvm.vp.copysign.v32f64(<32 x double>, <32 x double>, <32 x i1>, i32) declare <32 x double> @llvm.vp.copysign.v32f64(<32 x double>, <32 x double>, <32 x i1>, i32)
define <32 x double> @vfsgnj_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfsgnj_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfsgnj_vv_v32f64: ; CHECK-LABEL: vfsgnj_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v1, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: bltu a2, a1, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfsgnj.vv v8, v8, v24, v0.t
; CHECK-NEXT: addi a0, a2, -16 ; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0 ; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1 ; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vfsgnj.vv v16, v16, v8, v0.t
; CHECK-NEXT: bltu a2, a0, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 16
; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfsgnj.vv v8, v8, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v16, v16, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.copysign.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.copysign.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vfsgnj_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %vb, i32 zeroext %evl) { define <32 x double> @vfsgnj_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %vb, i32 zeroext %evl) {
Show All 26 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfabs-vp.ll

Show First 20 Lines • Show All 315 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <16 x double> %v ret <16 x double> %v
} }
declare <32 x double> @llvm.vp.fabs.v32f64(<32 x double>, <32 x i1>, i32) declare <32 x double> @llvm.vp.fabs.v32f64(<32 x double>, <32 x i1>, i32)
define <32 x double> @vfabs_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfabs_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_v32f64: ; CHECK-LABEL: vfabs_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB26_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vfabs.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB26_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB26_2: ; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vfabs.v v8, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfabs.v v8, v8, v0.t ; CHECK-NEXT: vfabs.v v16, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.fabs.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.fabs.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vfabs_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) { define <32 x double> @vfabs_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_v32f64_unmasked: ; CHECK-LABEL: vfabs_vv_v32f64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfcmps-constrained-sdnode.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,221 Lines • ▼ Show 20 Lines
} }
define <32 x i1> @fcmps_uno_fv_v32f16(<32 x half> %va, half %b) nounwind strictfp { define <32 x i1> @fcmps_uno_fv_v32f16(<32 x half> %va, half %b) nounwind strictfp {
; CHECK-LABEL: fcmps_uno_fv_v32f16: ; CHECK-LABEL: fcmps_uno_fv_v32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT: vfmv.v.f v12, fa0 ; CHECK-NEXT: vfmv.v.f v12, fa0
; CHECK-NEXT: vmfle.vf v16, v12, fa0 ; CHECK-NEXT: vmfle.vv v16, v8, v8
; CHECK-NEXT: vmnot.m v12, v16 ; CHECK-NEXT: vmfle.vf v8, v12, fa0
; CHECK-NEXT: vmfle.vv v13, v8, v8 ; CHECK-NEXT: vmnot.m v8, v8
; CHECK-NEXT: vmorn.mm v0, v12, v13 ; CHECK-NEXT: vmorn.mm v0, v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <32 x half> poison, half %b, i32 0 %head = insertelement <32 x half> poison, half %b, i32 0
%splat = shufflevector <32 x half> %head, <32 x half> poison, <32 x i32> zeroinitializer %splat = shufflevector <32 x half> %head, <32 x half> poison, <32 x i32> zeroinitializer
%1 = call <32 x i1> @llvm.experimental.constrained.fcmps.v32f16(<32 x half> %splat, <32 x half> %va, metadata !"uno", metadata !"fpexcept.strict") strictfp %1 = call <32 x i1> @llvm.experimental.constrained.fcmps.v32f16(<32 x half> %splat, <32 x half> %va, metadata !"uno", metadata !"fpexcept.strict") strictfp
ret <32 x i1> %1 ret <32 x i1> %1
} }
declare <1 x i1> @llvm.experimental.constrained.fcmps.v1f32(<1 x float>, <1 x float>, metadata, metadata) declare <1 x i1> @llvm.experimental.constrained.fcmps.v1f32(<1 x float>, <1 x float>, metadata, metadata)
▲ Show 20 Lines • Show All 4,786 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll

Show First 20 Lines • Show All 651 Lines • ▼ Show 20 Lines
declare <32 x double> @llvm.vp.fma.v32f64(<32 x double>, <32 x double>, <32 x double>, <32 x i1>, i32) declare <32 x double> @llvm.vp.fma.v32f64(<32 x double>, <32 x double>, <32 x double>, <32 x i1>, i32)
define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfma_vv_v32f64: ; CHECK-LABEL: vfma_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 40 ; CHECK-NEXT: slli a1, a1, 5
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: addi a1, a2, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v1, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a2) ; CHECK-NEXT: vle64.v v24, (a2)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a1, a2, 128
; CHECK-NEXT: addi a2, a0, 128
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle64.v v8, (a2) ; CHECK-NEXT: mv a0, a4
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: bltu a4, a1, .LBB50_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfmadd.vv v24, v8, v16, v0.t
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, a4, -16 ; CHECK-NEXT: addi a0, a4, -16
; CHECK-NEXT: sltu a1, a4, a0 ; CHECK-NEXT: sltu a1, a4, a0
; CHECK-NEXT: addi a1, a1, -1 ; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vfmadd.vv v8, v24, v16, v0.t
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: bltu a4, a0, .LBB50_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a4, 16
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24 ; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfmadd.vv v8, v24, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 40 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfmadd.vv v16, v24, v8, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.fma.v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.fma.v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vfma_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %b, <32 x double> %c, i32 zeroext %evl) { define <32 x double> @vfma_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %b, <32 x double> %c, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax-vp.ll

Show First 20 Lines • Show All 318 Lines • ▼ Show 20 Lines
declare <32 x double> @llvm.vp.maxnum.v32f64(<32 x double>, <32 x double>, <32 x i1>, i32) declare <32 x double> @llvm.vp.maxnum.v32f64(<32 x double>, <32 x double>, <32 x i1>, i32)
define <32 x double> @vfmax_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfmax_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfmax_vv_v32f64: ; CHECK-LABEL: vfmax_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v1, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: bltu a2, a1, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfmax.vv v8, v8, v24, v0.t
; CHECK-NEXT: addi a0, a2, -16 ; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0 ; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1 ; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vfmax.vv v16, v16, v8, v0.t
; CHECK-NEXT: bltu a2, a0, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 16
; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfmax.vv v8, v8, v24, v0.t ; CHECK-NEXT: vfmax.vv v16, v16, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.maxnum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.maxnum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %vb, i32 zeroext %evl) { define <32 x double> @vfmax_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %vb, i32 zeroext %evl) {
Show All 26 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin-vp.ll

Show First 20 Lines • Show All 318 Lines • ▼ Show 20 Lines
declare <32 x double> @llvm.vp.minnum.v32f64(<32 x double>, <32 x double>, <32 x i1>, i32) declare <32 x double> @llvm.vp.minnum.v32f64(<32 x double>, <32 x double>, <32 x i1>, i32)
define <32 x double> @vfmin_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfmin_vv_v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfmin_vv_v32f64: ; CHECK-LABEL: vfmin_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v1, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: bltu a2, a1, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vfmin.vv v8, v8, v24, v0.t
; CHECK-NEXT: addi a0, a2, -16 ; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0 ; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1 ; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vfmin.vv v16, v16, v8, v0.t
; CHECK-NEXT: bltu a2, a0, .LBB26_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 16
; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfmin.vv v8, v8, v24, v0.t ; CHECK-NEXT: vfmin.vv v16, v16, v24, v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.minnum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.minnum.v32f64(<32 x double> %va, <32 x double> %vb, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %vb, i32 zeroext %evl) { define <32 x double> @vfmin_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %vb, i32 zeroext %evl) {
Show All 26 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll

Show First 20 Lines • Show All 651 Lines • ▼ Show 20 Lines
declare <32 x double> @llvm.vp.fmuladd.v32f64(<32 x double>, <32 x double>, <32 x double>, <32 x i1>, i32) declare <32 x double> @llvm.vp.fmuladd.v32f64(<32 x double>, <32 x double>, <32 x double>, <32 x i1>, i32)
define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfma_vv_v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfma_vv_v32f64: ; CHECK-LABEL: vfma_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 40 ; CHECK-NEXT: slli a1, a1, 5
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x20, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 32 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: addi a1, a2, 128
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v1, v0, 2
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a2) ; CHECK-NEXT: vle64.v v24, (a2)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a1, a2, 128
; CHECK-NEXT: addi a2, a0, 128
; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle64.v v16, (a1)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vle64.v v8, (a2) ; CHECK-NEXT: mv a0, a4
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: bltu a4, a1, .LBB50_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfmadd.vv v24, v8, v16, v0.t
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, a4, -16 ; CHECK-NEXT: addi a0, a4, -16
; CHECK-NEXT: sltu a1, a4, a0 ; CHECK-NEXT: sltu a1, a4, a0
; CHECK-NEXT: addi a1, a1, -1 ; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vfmadd.vv v8, v24, v16, v0.t
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: bltu a4, a0, .LBB50_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a4, 16
; CHECK-NEXT: .LBB50_2:
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24 ; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfmadd.vv v8, v24, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 40 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vfmadd.vv v16, v24, v8, v0.t
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.fmuladd.v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.fmuladd.v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vfma_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %b, <32 x double> %c, i32 zeroext %evl) { define <32 x double> @vfma_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %b, <32 x double> %c, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 68 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll

Show First 20 Lines • Show All 315 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <16 x double> %v ret <16 x double> %v
} }
declare <32 x double> @llvm.vp.fneg.v32f64(<32 x double>, <32 x i1>, i32) declare <32 x double> @llvm.vp.fneg.v32f64(<32 x double>, <32 x i1>, i32)
define <32 x double> @vfneg_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfneg_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfneg_vv_v32f64: ; CHECK-LABEL: vfneg_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB26_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vfneg.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB26_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB26_2: ; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vfneg.v v8, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfneg.v v8, v8, v0.t ; CHECK-NEXT: vfneg.v v16, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.fneg.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.fneg.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vfneg_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) { define <32 x double> @vfneg_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfneg_vv_v32f64_unmasked: ; CHECK-LABEL: vfneg_vv_v32f64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfsqrt-vp.ll

Show First 20 Lines • Show All 315 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <16 x double> %v ret <16 x double> %v
} }
declare <32 x double> @llvm.vp.sqrt.v32f64(<32 x double>, <32 x i1>, i32) declare <32 x double> @llvm.vp.sqrt.v32f64(<32 x double>, <32 x i1>, i32)
define <32 x double> @vfsqrt_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vfsqrt_vv_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfsqrt_vv_v32f64: ; CHECK-LABEL: vfsqrt_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v24, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB26_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vfsqrt.v v16, v16, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB26_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB26_2: ; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vfsqrt.v v8, v8, v0.t
; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfsqrt.v v8, v8, v0.t ; CHECK-NEXT: vfsqrt.v v16, v16, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.sqrt.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.sqrt.v32f64(<32 x double> %va, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vfsqrt_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) { define <32 x double> @vfsqrt_vv_v32f64_unmasked(<32 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfsqrt_vv_v32f64_unmasked: ; CHECK-LABEL: vfsqrt_vv_v32f64_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
Show All 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmax-vp.ll

Show First 20 Lines • Show All 1,085 Lines • ▼ Show 20 Lines
; Test that split-legalization works as expected. ; Test that split-legalization works as expected.
declare <32 x i64> @llvm.vp.smax.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32) declare <32 x i64> @llvm.vp.smax.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32)
define <32 x i64> @vmax_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vmax_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vmax_vx_v32i64: ; RV32-LABEL: vmax_vx_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v1, v0, 2
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: li a2, 16
; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vmv.v.i v24, -1
; RV32-NEXT: addi a1, a0, -16 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: sltu a2, a0, a1 ; RV32-NEXT: bltu a0, a2, .LBB74_2
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a1, a2, a1
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: li a1, 16
; RV32-NEXT: vmax.vv v16, v16, v24, v0.t
; RV32-NEXT: bltu a0, a1, .LBB74_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a0, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB74_2: ; RV32-NEXT: .LBB74_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmax.vv v8, v8, v24, v0.t
; RV32-NEXT: addi a1, a0, -16
; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vmax.vv v8, v8, v24, v0.t ; RV32-NEXT: vmax.vv v16, v16, v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmax_vx_v32i64: ; RV64-LABEL: vmax_vx_v32i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: addi a1, a0, -16
; RV64-NEXT: sltu a2, a0, a1
; RV64-NEXT: addi a2, a2, -1
; RV64-NEXT: and a2, a2, a1
; RV64-NEXT: li a1, -1
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: li a2, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: vmax.vx v16, v16, a1, v0.t ; RV64-NEXT: vslidedown.vi v24, v0, 2
; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB74_2 ; RV64-NEXT: bltu a0, a2, .LBB74_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a0, 16 ; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB74_2: ; RV64-NEXT: .LBB74_2:
; RV64-NEXT: li a2, -1
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmax.vx v8, v8, a2, v0.t
; RV64-NEXT: addi a1, a0, -16
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vmax.vx v8, v8, a1, v0.t ; RV64-NEXT: vmax.vx v16, v16, a2, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.smax.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) %v = call <32 x i64> @llvm.vp.smax.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmaxu-vp.ll

Show First 20 Lines • Show All 1,084 Lines • ▼ Show 20 Lines
; Test that split-legalization works as expected. ; Test that split-legalization works as expected.
declare <32 x i64> @llvm.vp.umax.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32) declare <32 x i64> @llvm.vp.umax.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32)
define <32 x i64> @vmaxu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vmaxu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vmaxu_vx_v32i64: ; RV32-LABEL: vmaxu_vx_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v1, v0, 2
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: li a2, 16
; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vmv.v.i v24, -1
; RV32-NEXT: addi a1, a0, -16 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: sltu a2, a0, a1 ; RV32-NEXT: bltu a0, a2, .LBB74_2
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a1, a2, a1
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: li a1, 16
; RV32-NEXT: vmaxu.vv v16, v16, v24, v0.t
; RV32-NEXT: bltu a0, a1, .LBB74_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a0, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB74_2: ; RV32-NEXT: .LBB74_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmaxu.vv v8, v8, v24, v0.t
; RV32-NEXT: addi a1, a0, -16
; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vmaxu.vv v8, v8, v24, v0.t ; RV32-NEXT: vmaxu.vv v16, v16, v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmaxu_vx_v32i64: ; RV64-LABEL: vmaxu_vx_v32i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: addi a1, a0, -16
; RV64-NEXT: sltu a2, a0, a1
; RV64-NEXT: addi a2, a2, -1
; RV64-NEXT: and a2, a2, a1
; RV64-NEXT: li a1, -1
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: li a2, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: vmaxu.vx v16, v16, a1, v0.t ; RV64-NEXT: vslidedown.vi v24, v0, 2
; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB74_2 ; RV64-NEXT: bltu a0, a2, .LBB74_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a0, 16 ; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB74_2: ; RV64-NEXT: .LBB74_2:
; RV64-NEXT: li a2, -1
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmaxu.vx v8, v8, a2, v0.t
; RV64-NEXT: addi a1, a0, -16
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vmaxu.vx v8, v8, a1, v0.t ; RV64-NEXT: vmaxu.vx v16, v16, a2, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.umax.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) %v = call <32 x i64> @llvm.vp.umax.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmin-vp.ll

Show First 20 Lines • Show All 1,085 Lines • ▼ Show 20 Lines
; Test that split-legalization works as expected. ; Test that split-legalization works as expected.
declare <32 x i64> @llvm.vp.smin.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32) declare <32 x i64> @llvm.vp.smin.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32)
define <32 x i64> @vmin_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vmin_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vmin_vx_v32i64: ; RV32-LABEL: vmin_vx_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v1, v0, 2
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: li a2, 16
; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vmv.v.i v24, -1
; RV32-NEXT: addi a1, a0, -16 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: sltu a2, a0, a1 ; RV32-NEXT: bltu a0, a2, .LBB74_2
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a1, a2, a1
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: li a1, 16
; RV32-NEXT: vmin.vv v16, v16, v24, v0.t
; RV32-NEXT: bltu a0, a1, .LBB74_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a0, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB74_2: ; RV32-NEXT: .LBB74_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmin.vv v8, v8, v24, v0.t
; RV32-NEXT: addi a1, a0, -16
; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vmin.vv v8, v8, v24, v0.t ; RV32-NEXT: vmin.vv v16, v16, v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vmin_vx_v32i64: ; RV64-LABEL: vmin_vx_v32i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: addi a1, a0, -16
; RV64-NEXT: sltu a2, a0, a1
; RV64-NEXT: addi a2, a2, -1
; RV64-NEXT: and a2, a2, a1
; RV64-NEXT: li a1, -1
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: li a2, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: vmin.vx v16, v16, a1, v0.t ; RV64-NEXT: vslidedown.vi v24, v0, 2
; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB74_2 ; RV64-NEXT: bltu a0, a2, .LBB74_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a0, 16 ; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB74_2: ; RV64-NEXT: .LBB74_2:
; RV64-NEXT: li a2, -1
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmin.vx v8, v8, a2, v0.t
; RV64-NEXT: addi a1, a0, -16
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vmin.vx v8, v8, a1, v0.t ; RV64-NEXT: vmin.vx v16, v16, a2, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.smin.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) %v = call <32 x i64> @llvm.vp.smin.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vminu-vp.ll

Show First 20 Lines • Show All 1,084 Lines • ▼ Show 20 Lines
; Test that split-legalization works as expected. ; Test that split-legalization works as expected.
declare <32 x i64> @llvm.vp.umin.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32) declare <32 x i64> @llvm.vp.umin.v32i64(<32 x i64>, <32 x i64>, <32 x i1>, i32)
define <32 x i64> @vminu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vminu_vx_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vminu_vx_v32i64: ; RV32-LABEL: vminu_vx_v32i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v1, v0, 2
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: li a2, 16
; RV32-NEXT: vmv.v.i v24, -1 ; RV32-NEXT: vmv.v.i v24, -1
; RV32-NEXT: addi a1, a0, -16 ; RV32-NEXT: mv a1, a0
; RV32-NEXT: sltu a2, a0, a1 ; RV32-NEXT: bltu a0, a2, .LBB74_2
; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a1, a2, a1
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: li a1, 16
; RV32-NEXT: vminu.vv v16, v16, v24, v0.t
; RV32-NEXT: bltu a0, a1, .LBB74_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a0, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB74_2: ; RV32-NEXT: .LBB74_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vminu.vv v8, v8, v24, v0.t
; RV32-NEXT: addi a1, a0, -16
; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vmv1r.v v0, v1
; RV32-NEXT: vminu.vv v8, v8, v24, v0.t ; RV32-NEXT: vminu.vv v16, v16, v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vminu_vx_v32i64: ; RV64-LABEL: vminu_vx_v32i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: addi a1, a0, -16
; RV64-NEXT: sltu a2, a0, a1
; RV64-NEXT: addi a2, a2, -1
; RV64-NEXT: and a2, a2, a1
; RV64-NEXT: li a1, -1
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: li a2, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: vminu.vx v16, v16, a1, v0.t ; RV64-NEXT: vslidedown.vi v24, v0, 2
; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB74_2 ; RV64-NEXT: bltu a0, a2, .LBB74_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a0, 16 ; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB74_2: ; RV64-NEXT: .LBB74_2:
; RV64-NEXT: li a2, -1
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vminu.vx v8, v8, a2, v0.t
; RV64-NEXT: addi a1, a0, -16
; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vminu.vx v8, v8, a1, v0.t ; RV64-NEXT: vminu.vx v16, v16, a2, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%elt.head = insertelement <32 x i64> poison, i64 -1, i32 0 %elt.head = insertelement <32 x i64> poison, i64 -1, i32 0
%vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer %vb = shufflevector <32 x i64> %elt.head, <32 x i64> poison, <32 x i32> zeroinitializer
%v = call <32 x i64> @llvm.vp.umin.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl) %v = call <32 x i64> @llvm.vp.umin.v32i64(<32 x i64> %va, <32 x i64> %vb, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

Show First 20 Lines • Show All 279 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v32i8: ; RV64-LABEL: vpgather_baseidx_v32i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v10, v0 ; RV64-NEXT: li a3, 16
; RV64-NEXT: mv a2, a1
; RV64-NEXT: bltu a1, a3, .LBB13_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a2, 16
; RV64-NEXT: .LBB13_2:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetvli zero, a2, e8, m1, ta, ma
; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v12, v8, 16 ; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v12 ; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e8, m1, ta, ma
; RV64-NEXT: vluxei64.v v12, (a0), v16, v0.t
; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB13_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB13_2:
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; RV64-NEXT: vmv1r.v v0, v10
; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: li a0, 32 ; RV64-NEXT: li a0, 32
; RV64-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; RV64-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; RV64-NEXT: vslideup.vi v8, v12, 16 ; RV64-NEXT: vslideup.vi v10, v8, 16
; RV64-NEXT: vmv.v.v v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, ptr %base, <32 x i8> %idxs %ptrs = getelementptr inbounds i8, ptr %base, <32 x i8> %idxs
%v = call <32 x i8> @llvm.vp.gather.v32i8.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x i8> @llvm.vp.gather.v32i8.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x i8> %v ret <32 x i8> %v
} }
declare <2 x i16> @llvm.vp.gather.v2i16.v2p0(<2 x ptr>, <2 x i1>, i32) declare <2 x i16> @llvm.vp.gather.v2i16.v2p0(<2 x ptr>, <2 x i1>, i32)
▲ Show 20 Lines • Show All 1,563 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
ret <8 x double> %v ret <8 x double> %v
} }
declare <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr>, <32 x i1>, i32) declare <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr>, <32 x i1>, i32)
define <32 x double> @vpgather_v32f64(<32 x ptr> %ptrs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_v32f64(<32 x ptr> %ptrs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_v32f64: ; RV32-LABEL: vpgather_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0 ; RV32-NEXT: li a2, 16
; RV32-NEXT: mv a1, a0
; RV32-NEXT: bltu a0, a2, .LBB86_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB86_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v24, (zero), v8, v0.t
; RV32-NEXT: addi a1, a0, -16 ; RV32-NEXT: addi a1, a0, -16
; RV32-NEXT: sltu a2, a0, a1 ; RV32-NEXT: sltu a0, a0, a1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: and a1, a2, a1 ; RV32-NEXT: and a0, a0, a1
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v8, 16 ; RV32-NEXT: vslidedown.vi v8, v8, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (zero), v24, v0.t
; RV32-NEXT: li a1, 16
; RV32-NEXT: bltu a0, a1, .LBB86_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a0, 16
; RV32-NEXT: .LBB86_2:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vluxei32.v v16, (zero), v8, v0.t
; RV32-NEXT: vluxei32.v v24, (zero), v8, v0.t ; RV32-NEXT: vmv8r.v v8, v24
; RV32-NEXT: vmv.v.v v8, v24
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_v32f64: ; RV64-LABEL: vpgather_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v24, v0 ; RV64-NEXT: li a2, 16
; RV64-NEXT: mv a1, a0
; RV64-NEXT: bltu a0, a2, .LBB86_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB86_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: addi a1, a0, -16 ; RV64-NEXT: addi a1, a0, -16
; RV64-NEXT: sltu a2, a0, a1 ; RV64-NEXT: sltu a0, a0, a1
; RV64-NEXT: addi a2, a2, -1 ; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: and a1, a2, a1 ; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (zero), v16, v0.t
; RV64-NEXT: li a1, 16
; RV64-NEXT: bltu a0, a1, .LBB86_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a0, 16
; RV64-NEXT: .LBB86_2:
; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vluxei64.v v16, (zero), v16, v0.t
; RV64-NEXT: vluxei64.v v8, (zero), v8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_v32i8_v32f64: ; RV32-LABEL: vpgather_baseidx_v32i8_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: li a3, 16 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB87_2 ; RV32-NEXT: bltu a1, a3, .LBB87_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB87_2: ; RV32-NEXT: .LBB87_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v32i8_v32f64: ; RV64-LABEL: vpgather_baseidx_v32i8_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsll.vi v24, v16, 3
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 16 ; RV64-NEXT: vslidedown.vi v10, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v8 ; RV64-NEXT: vsext.vf8 v16, v10
; RV64-NEXT: vsll.vi v16, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: vsext.vf8 v24, v8
; RV64-NEXT: li a3, 16
; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: mv a2, a1
; RV64-NEXT: bltu a1, a3, .LBB87_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a2, 16
; RV64-NEXT: .LBB87_2:
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB87_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB87_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v10 ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: vluxei64.v v8, (a0), v24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i8> %idxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i8> %idxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_sext_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_sext_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v32i8_v32f64: ; RV32-LABEL: vpgather_baseidx_sext_v32i8_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: li a3, 16 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB88_2 ; RV32-NEXT: bltu a1, a3, .LBB88_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB88_2: ; RV32-NEXT: .LBB88_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v32i8_v32f64: ; RV64-LABEL: vpgather_baseidx_sext_v32i8_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v12, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v12
; RV64-NEXT: vsext.vf8 v24, v8 ; RV64-NEXT: vsext.vf8 v24, v8
; RV64-NEXT: vsll.vi v24, v24, 3 ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsll.vi v16, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: li a3, 16
; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: mv a2, a1
; RV64-NEXT: bltu a1, a3, .LBB88_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a2, 16
; RV64-NEXT: .LBB88_2:
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB88_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB88_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v10 ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: vluxei64.v v8, (a0), v24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <32 x i8> %idxs to <32 x i64> %eidxs = sext <32 x i8> %idxs to <32 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_zext_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_zext_v32i8_v32f64(ptr %base, <32 x i8> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v32i8_v32f64: ; RV32-LABEL: vpgather_baseidx_zext_v32i8_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vzext.vf4 v16, v8 ; RV32-NEXT: vzext.vf4 v16, v8
; RV32-NEXT: li a3, 16 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB89_2 ; RV32-NEXT: bltu a1, a3, .LBB89_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB89_2: ; RV32-NEXT: .LBB89_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v32i8_v32f64: ; RV64-LABEL: vpgather_baseidx_zext_v32i8_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v10, v0
; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v12, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vzext.vf8 v16, v12
; RV64-NEXT: vzext.vf8 v24, v8 ; RV64-NEXT: vzext.vf8 v24, v8
; RV64-NEXT: vsll.vi v24, v24, 3 ; RV64-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vzext.vf8 v16, v8
; RV64-NEXT: vsll.vi v16, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: li a3, 16
; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: mv a2, a1
; RV64-NEXT: bltu a1, a3, .LBB89_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a2, 16
; RV64-NEXT: .LBB89_2:
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB89_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB89_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v10 ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: vluxei64.v v8, (a0), v24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <32 x i8> %idxs to <32 x i64> %eidxs = zext <32 x i8> %idxs to <32 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_v32i16_v32f64: ; RV32-LABEL: vpgather_baseidx_v32i16_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsext.vf2 v16, v8 ; RV32-NEXT: vsext.vf2 v16, v8
; RV32-NEXT: li a3, 16 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB90_2 ; RV32-NEXT: bltu a1, a3, .LBB90_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB90_2: ; RV32-NEXT: .LBB90_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v32i16_v32f64: ; RV64-LABEL: vpgather_baseidx_v32i16_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v8
; RV64-NEXT: vsll.vi v24, v16, 3
; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma ; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 16 ; RV64-NEXT: vslidedown.vi v12, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v16, v8 ; RV64-NEXT: vsext.vf4 v16, v12
; RV64-NEXT: vsll.vi v16, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: vsext.vf4 v24, v8
; RV64-NEXT: li a3, 16
; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: mv a2, a1
; RV64-NEXT: bltu a1, a3, .LBB90_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a2, 16
; RV64-NEXT: .LBB90_2:
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB90_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB90_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v12 ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: vluxei64.v v8, (a0), v24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i16> %idxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i16> %idxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_sext_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_sext_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v32i16_v32f64: ; RV32-LABEL: vpgather_baseidx_sext_v32i16_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsext.vf2 v16, v8 ; RV32-NEXT: vsext.vf2 v16, v8
; RV32-NEXT: li a3, 16 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB91_2 ; RV32-NEXT: bltu a1, a3, .LBB91_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB91_2: ; RV32-NEXT: .LBB91_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v32i16_v32f64: ; RV64-LABEL: vpgather_baseidx_sext_v32i16_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v24, v8
; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma ; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf4 v0, v16
; RV64-NEXT: vsext.vf4 v16, v8 ; RV64-NEXT: vsext.vf4 v16, v8
; RV64-NEXT: vsll.vi v24, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: vsll.vi v16, v0, 3 ; RV64-NEXT: li a3, 16
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: mv a2, a1
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: bltu a1, a3, .LBB91_2
; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v12, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB91_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: .LBB91_2: ; RV64-NEXT: .LBB91_2:
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v12 ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: vluxei64.v v8, (a0), v24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <32 x i16> %idxs to <32 x i64> %eidxs = sext <32 x i16> %idxs to <32 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_zext_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_zext_v32i16_v32f64(ptr %base, <32 x i16> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v32i16_v32f64: ; RV32-LABEL: vpgather_baseidx_zext_v32i16_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vzext.vf2 v16, v8 ; RV32-NEXT: vzext.vf2 v16, v8
; RV32-NEXT: li a3, 16 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v16, 3 ; RV32-NEXT: vsll.vi v16, v16, 3
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB92_2 ; RV32-NEXT: bltu a1, a3, .LBB92_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB92_2: ; RV32-NEXT: .LBB92_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v32i16_v32f64: ; RV64-LABEL: vpgather_baseidx_zext_v32i16_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vzext.vf4 v24, v8
; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma ; RV64-NEXT: vsetivli zero, 16, e16, m4, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vzext.vf4 v0, v16
; RV64-NEXT: vzext.vf4 v16, v8 ; RV64-NEXT: vzext.vf4 v16, v8
; RV64-NEXT: vsll.vi v24, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: vsll.vi v16, v0, 3 ; RV64-NEXT: li a3, 16
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: mv a2, a1
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: bltu a1, a3, .LBB92_2
; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v12, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB92_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: .LBB92_2: ; RV64-NEXT: .LBB92_2:
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v12 ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: vluxei64.v v8, (a0), v24, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <32 x i16> %idxs to <32 x i64> %eidxs = zext <32 x i16> %idxs to <32 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_v32i32_v32f64: ; RV32-LABEL: vpgather_baseidx_v32i32_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: li a3, 16 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v8, 3 ; RV32-NEXT: vsll.vi v16, v8, 3
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB93_2 ; RV32-NEXT: bltu a1, a3, .LBB93_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB93_2: ; RV32-NEXT: .LBB93_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 3
; RV64-NEXT: sub sp, sp, a2
; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf2 v16, v8
; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV64-NEXT: vslidedown.vi v8, v8, 16 ; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf2 v16, v8 ; RV64-NEXT: vsext.vf2 v24, v16
; RV64-NEXT: vsll.vi v8, v16, 3 ; RV64-NEXT: vsll.vi v16, v24, 3
; RV64-NEXT: vsext.vf2 v24, v8
; RV64-NEXT: li a3, 16
; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: mv a2, a1
; RV64-NEXT: bltu a1, a3, .LBB93_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a2, 16
; RV64-NEXT: .LBB93_2:
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v8, v0.t
; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB93_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB93_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 3
; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i32> %idxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i32> %idxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_sext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_sext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v32i32_v32f64: ; RV32-LABEL: vpgather_baseidx_sext_v32i32_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: li a3, 16 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v8, 3 ; RV32-NEXT: vsll.vi v16, v8, 3
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB94_2 ; RV32-NEXT: bltu a1, a3, .LBB94_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB94_2: ; RV32-NEXT: .LBB94_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v24, v0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf2 v24, v8
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsext.vf2 v0, v16
; RV64-NEXT: vsext.vf2 v16, v8 ; RV64-NEXT: vsext.vf2 v16, v8
; RV64-NEXT: vsll.vi v8, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: vsll.vi v16, v0, 3 ; RV64-NEXT: li a3, 16
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: mv a2, a1
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: bltu a1, a3, .LBB94_2
; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v24, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB94_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: .LBB94_2: ; RV64-NEXT: .LBB94_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = sext <32 x i32> %idxs to <32 x i64> %eidxs = sext <32 x i32> %idxs to <32 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_zext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_zext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v32i32_v32f64: ; RV32-LABEL: vpgather_baseidx_zext_v32i32_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: li a3, 16 ; RV32-NEXT: li a3, 16
; RV32-NEXT: vsll.vi v16, v8, 3 ; RV32-NEXT: vsll.vi v16, v8, 3
; RV32-NEXT: mv a2, a1 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: bltu a1, a3, .LBB95_2 ; RV32-NEXT: bltu a1, a3, .LBB95_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB95_2: ; RV32-NEXT: .LBB95_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2 ; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v24, v0 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vzext.vf2 v24, v8
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v8, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vzext.vf2 v0, v16
; RV64-NEXT: vzext.vf2 v16, v8 ; RV64-NEXT: vzext.vf2 v16, v8
; RV64-NEXT: vsll.vi v8, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: vsll.vi v16, v0, 3 ; RV64-NEXT: li a3, 16
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: vsll.vi v8, v24, 3
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: mv a2, a1
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: bltu a1, a3, .LBB95_2
; RV64-NEXT: and a2, a3, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v24, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB95_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16 ; RV64-NEXT: li a2, 16
; RV64-NEXT: .LBB95_2: ; RV64-NEXT: .LBB95_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%eidxs = zext <32 x i32> %idxs to <32 x i64> %eidxs = zext <32 x i32> %idxs to <32 x i64>
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_v32f64(ptr %base, <32 x i64> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_v32f64(ptr %base, <32 x i64> %idxs, <32 x i1> %m, i32 zeroext %evl) {
Show All 23 Lines
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v32f64: ; RV64-LABEL: vpgather_baseidx_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsll.vi v8, v8, 3
; RV64-NEXT: vsll.vi v16, v16, 3 ; RV64-NEXT: vsll.vi v16, v16, 3
; RV64-NEXT: li a3, 16
; RV64-NEXT: vsll.vi v8, v8, 3
; RV64-NEXT: mv a2, a1
; RV64-NEXT: bltu a1, a3, .LBB96_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a2, 16
; RV64-NEXT: .LBB96_2:
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: addi a2, a1, -16 ; RV64-NEXT: addi a2, a1, -16
; RV64-NEXT: sltu a3, a1, a2 ; RV64-NEXT: sltu a1, a1, a2
; RV64-NEXT: addi a3, a3, -1 ; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a2, a3, a2 ; RV64-NEXT: and a1, a1, a2
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: li a2, 16
; RV64-NEXT: bltu a1, a2, .LBB96_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: li a1, 16
; RV64-NEXT: .LBB96_2:
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vluxei64.v v16, (a0), v16, v0.t
; RV64-NEXT: vluxei64.v v8, (a0), v8, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %idxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %idxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpload.ll

Show First 20 Lines • Show All 375 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <8 x double> %load ret <8 x double> %load
} }
declare <32 x double> @llvm.vp.load.v32f64.p0(ptr, <32 x i1>, i32) declare <32 x double> @llvm.vp.load.v32f64.p0(ptr, <32 x i1>, i32)
define <32 x double> @vpload_v32f64(ptr %ptr, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpload_v32f64(ptr %ptr, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpload_v32f64: ; CHECK-LABEL: vpload_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: li a3, 16
; CHECK-NEXT: mv a2, a1
; CHECK-NEXT: bltu a1, a3, .LBB31_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 16
; CHECK-NEXT: .LBB31_2:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0), v0.t
; CHECK-NEXT: addi a2, a1, -16 ; CHECK-NEXT: addi a2, a1, -16
; CHECK-NEXT: sltu a3, a1, a2 ; CHECK-NEXT: sltu a1, a1, a2
; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a2, a3, a2 ; CHECK-NEXT: and a1, a1, a2
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: addi a3, a0, 128
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a3), v0.t
; CHECK-NEXT: li a2, 16
; CHECK-NEXT: bltu a1, a2, .LBB31_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB31_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vle64.v v16, (a0), v0.t
; CHECK-NEXT: vle64.v v8, (a0), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%load = call <32 x double> @llvm.vp.load.v32f64.p0(ptr %ptr, <32 x i1> %m, i32 %evl) %load = call <32 x double> @llvm.vp.load.v32f64.p0(ptr %ptr, <32 x i1> %m, i32 %evl)
ret <32 x double> %load ret <32 x double> %load
} }
declare <33 x double> @llvm.vp.load.v33f64.p0(ptr, <33 x i1>, i32) declare <33 x double> @llvm.vp.load.v33f64.p0(ptr, <33 x i1>, i32)
; Widen to v64f64 then split into 4 x v16f64, of which 1 is empty. ; Widen to v64f64 then split into 4 x v16f64, of which 1 is empty.
define <33 x double> @vpload_v33f64(ptr %ptr, <33 x i1> %m, i32 zeroext %evl) { define <33 x double> @vpload_v33f64(ptr %ptr, <33 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpload_v33f64: ; CHECK-LABEL: vpload_v33f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a4, 32 ; CHECK-NEXT: li a4, 32
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: mv a3, a2 ; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: bltu a2, a4, .LBB32_2 ; CHECK-NEXT: bltu a2, a4, .LBB32_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a3, 32 ; CHECK-NEXT: li a3, 32
; CHECK-NEXT: .LBB32_2: ; CHECK-NEXT: .LBB32_2:
; CHECK-NEXT: addi a4, a3, -16 ; CHECK-NEXT: addi a4, a3, -16
; CHECK-NEXT: sltu a5, a3, a4 ; CHECK-NEXT: sltu a5, a3, a4
; CHECK-NEXT: addi a5, a5, -1 ; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a4, a5, a4 ; CHECK-NEXT: and a4, a5, a4
; CHECK-NEXT: addi a5, a1, 128
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v8, 2 ; CHECK-NEXT: vslidedown.vi v0, v8, 2
; CHECK-NEXT: addi a5, a1, 128
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a5), v0.t ; CHECK-NEXT: vle64.v v16, (a5), v0.t
; CHECK-NEXT: addi a4, a2, -32 ; CHECK-NEXT: addi a4, a2, -32
; CHECK-NEXT: sltu a2, a2, a4 ; CHECK-NEXT: sltu a2, a2, a4
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a4, a2, a4 ; CHECK-NEXT: and a4, a2, a4
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: bltu a4, a2, .LBB32_4 ; CHECK-NEXT: bltu a4, a2, .LBB32_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: li a4, 16 ; CHECK-NEXT: li a4, 16
; CHECK-NEXT: .LBB32_4: ; CHECK-NEXT: .LBB32_4:
; CHECK-NEXT: addi a5, a1, 256
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v8, 4 ; CHECK-NEXT: vslidedown.vi v0, v8, 4
; CHECK-NEXT: addi a5, a1, 256
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a5), v0.t ; CHECK-NEXT: vle64.v v24, (a5), v0.t
; CHECK-NEXT: bltu a3, a2, .LBB32_6 ; CHECK-NEXT: bltu a3, a2, .LBB32_6
; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: li a3, 16 ; CHECK-NEXT: li a3, 16
; CHECK-NEXT: .LBB32_6: ; CHECK-NEXT: .LBB32_6:
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
Show All 13 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll

Show First 20 Lines • Show All 1,059 Lines • ▼ Show 20 Lines
; CHECK-LABEL: vpmerge_vv_v32f64: ; CHECK-LABEL: vpmerge_vv_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a1, a2, -16 ; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: sltu a3, a2, a1 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: and a1, a3, a1 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: bltu a2, a1, .LBB79_2
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle64.v v16, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: bltu a2, a0, .LBB79_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB79_2: ; CHECK-NEXT: .LBB79_2:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmerge.vvm v24, v24, v8, v0
; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmerge.vvm v8, v8, v24, v0 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmerge.vvm v16, v16, v8, v0
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x double> @llvm.vp.merge.v32f64(<32 x i1> %m, <32 x double> %va, <32 x double> %vb, i32 %evl) %v = call <32 x double> @llvm.vp.merge.v32f64(<32 x i1> %m, <32 x double> %va, <32 x double> %vb, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpmerge_vf_v32f64(double %a, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpmerge_vf_v32f64(double %a, <32 x double> %vb, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpmerge_vf_v32f64: ; CHECK-LABEL: vpmerge_vf_v32f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: bltu a0, a2, .LBB80_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB80_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a1, a2, a1 ; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a1, e64, m8, tu, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0
; CHECK-NEXT: bltu a0, a1, .LBB80_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB80_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfmerge.vfm v16, v16, fa0, v0
; CHECK-NEXT: vfmerge.vfm v8, v8, fa0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <32 x double> poison, double %a, i32 0 %elt.head = insertelement <32 x double> poison, double %a, i32 0
%va = shufflevector <32 x double> %elt.head, <32 x double> poison, <32 x i32> zeroinitializer %va = shufflevector <32 x double> %elt.head, <32 x double> poison, <32 x i32> zeroinitializer
%v = call <32 x double> @llvm.vp.merge.v32f64(<32 x i1> %m, <32 x double> %va, <32 x double> %vb, i32 %evl) %v = call <32 x double> @llvm.vp.merge.v32f64(<32 x i1> %m, <32 x double> %va, <32 x double> %vb, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

Show First 20 Lines • Show All 1,695 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a2, 16 ; RV32-NEXT: li a2, 16
; RV32-NEXT: mv a0, a1 ; RV32-NEXT: mv a0, a1
; RV32-NEXT: bltu a1, a2, .LBB79_2 ; RV32-NEXT: bltu a1, a2, .LBB79_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a0, 16 ; RV32-NEXT: li a0, 16
; RV32-NEXT: .LBB79_2: ; RV32-NEXT: .LBB79_2:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v8, (zero), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (zero), v24, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: addi a0, a1, -16 ; RV32-NEXT: addi a0, a1, -16
; RV32-NEXT: sltu a1, a1, a0 ; RV32-NEXT: sltu a1, a1, a0
; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a0, a1, a0 ; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (zero), v8, v0.t ; RV32-NEXT: vsoxei32.v v16, (zero), v8, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_v32f64: ; RV64-LABEL: vpscatter_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsll.vi v24, v24, 3 ; RV32-NEXT: vsll.vi v24, v24, 3
; RV32-NEXT: mv a1, a2 ; RV32-NEXT: mv a1, a2
; RV32-NEXT: bltu a2, a3, .LBB80_2 ; RV32-NEXT: bltu a2, a3, .LBB80_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB80_2: ; RV32-NEXT: .LBB80_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: addi a1, a2, -16 ; RV32-NEXT: addi a1, a2, -16
; RV32-NEXT: sltu a2, a2, a1 ; RV32-NEXT: sltu a2, a2, a1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a1, a2, a1 ; RV32-NEXT: and a1, a2, a1
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (a0), v8, v0.t ; RV32-NEXT: vsoxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_v32i32_v32f64: ; RV64-LABEL: vpscatter_baseidx_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsll.vi v24, v24, 3 ; RV32-NEXT: vsll.vi v24, v24, 3
; RV32-NEXT: mv a1, a2 ; RV32-NEXT: mv a1, a2
; RV32-NEXT: bltu a2, a3, .LBB81_2 ; RV32-NEXT: bltu a2, a3, .LBB81_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB81_2: ; RV32-NEXT: .LBB81_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: addi a1, a2, -16 ; RV32-NEXT: addi a1, a2, -16
; RV32-NEXT: sltu a2, a2, a1 ; RV32-NEXT: sltu a2, a2, a1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a1, a2, a1 ; RV32-NEXT: and a1, a2, a1
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (a0), v8, v0.t ; RV32-NEXT: vsoxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_sext_v32i32_v32f64: ; RV64-LABEL: vpscatter_baseidx_sext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsll.vi v24, v24, 3 ; RV32-NEXT: vsll.vi v24, v24, 3
; RV32-NEXT: mv a1, a2 ; RV32-NEXT: mv a1, a2
; RV32-NEXT: bltu a2, a3, .LBB82_2 ; RV32-NEXT: bltu a2, a3, .LBB82_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16 ; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB82_2: ; RV32-NEXT: .LBB82_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t ; RV32-NEXT: vsoxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: addi a1, a2, -16 ; RV32-NEXT: addi a1, a2, -16
; RV32-NEXT: sltu a2, a2, a1 ; RV32-NEXT: sltu a2, a2, a1
; RV32-NEXT: addi a2, a2, -1 ; RV32-NEXT: addi a2, a2, -1
; RV32-NEXT: and a1, a2, a1 ; RV32-NEXT: and a1, a2, a1
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vsoxei32.v v16, (a0), v8, v0.t ; RV32-NEXT: vsoxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpscatter_baseidx_zext_v32i32_v32f64: ; RV64-LABEL: vpscatter_baseidx_zext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpstore.ll

Show First 20 Lines • Show All 291 Lines • ▼ Show 20 Lines
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: .LBB23_2: ; CHECK-NEXT: .LBB23_2:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v8, (a0), v0.t ; CHECK-NEXT: vse64.v v8, (a0), v0.t
; CHECK-NEXT: addi a2, a1, -16 ; CHECK-NEXT: addi a2, a1, -16
; CHECK-NEXT: sltu a1, a1, a2 ; CHECK-NEXT: sltu a1, a1, a2
; CHECK-NEXT: addi a1, a1, -1 ; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a1, a1, a2 ; CHECK-NEXT: and a1, a1, a2
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v16, (a0), v0.t ; CHECK-NEXT: vse64.v v16, (a0), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.vp.store.v32f64.p0(<32 x double> %val, ptr %ptr, <32 x i1> %m, i32 %evl) call void @llvm.vp.store.v32f64.p0(<32 x double> %val, ptr %ptr, <32 x i1> %m, i32 %evl)
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll

Show First 20 Lines • Show All 1,826 Lines • ▼ Show 20 Lines; CHECK-ZVBB64-NEXT: ret
%b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer %b.splat = shufflevector <2 x i64> %b.head, <2 x i64> poison, <2 x i32> zeroinitializer
%x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat) %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> %b.splat)
ret <2 x i64> %x ret <2 x i64> %x
} }
define <2 x i64> @vror_vi_v2i64(<2 x i64> %a) { define <2 x i64> @vror_vi_v2i64(<2 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_v2i64: ; CHECK-RV32-LABEL: vror_vi_v2i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v9, a0
; CHECK-RV32-NEXT: vand.vi v9, v9, 1
; CHECK-RV32-NEXT: vsrl.vv v9, v8, v9
; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v9, 0 ; CHECK-RV32-NEXT: vmv.v.i v10, 0
; CHECK-RV32-NEXT: li a0, 1 ; CHECK-RV32-NEXT: li a1, 1
; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vsub.vx v9, v9, a0 ; CHECK-RV32-NEXT: vsub.vx v10, v10, a1
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vand.vx v9, v9, a0 ; CHECK-RV32-NEXT: vsll.vv v8, v8, v10
; CHECK-RV32-NEXT: vsll.vv v9, v8, v9 ; CHECK-RV32-NEXT: vor.vv v8, v9, v8
; CHECK-RV32-NEXT: vmv.v.x v10, a0
; CHECK-RV32-NEXT: vand.vi v10, v10, 1
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v10
; CHECK-RV32-NEXT: vor.vv v8, v8, v9
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_v2i64: ; CHECK-RV64-LABEL: vror_vi_v2i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV64-NEXT: vsll.vx v9, v8, a0 ; CHECK-RV64-NEXT: vsll.vx v9, v8, a0
; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1 ; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1
; CHECK-RV64-NEXT: vor.vv v8, v8, v9 ; CHECK-RV64-NEXT: vor.vv v8, v8, v9
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: vror_vi_v2i64: ; CHECK-ZVBB-LABEL: vror_vi_v2i64:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-ZVBB-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> shufflevector(<2 x i64> insertelement(<2 x i64> poison, i64 1, i32 0), <2 x i64> poison, <2 x i32> zeroinitializer)) %x = call <2 x i64> @llvm.fshr.v2i64(<2 x i64> %a, <2 x i64> %a, <2 x i64> shufflevector(<2 x i64> insertelement(<2 x i64> poison, i64 1, i32 0), <2 x i64> poison, <2 x i32> zeroinitializer))
ret <2 x i64> %x ret <2 x i64> %x
} }
define <2 x i64> @vror_vi_rotl_v2i64(<2 x i64> %a) { define <2 x i64> @vror_vi_rotl_v2i64(<2 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_rotl_v2i64: ; CHECK-RV32-LABEL: vror_vi_rotl_v2i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v9, a0
; CHECK-RV32-NEXT: vand.vi v9, v9, 1
; CHECK-RV32-NEXT: vsll.vv v9, v8, v9
; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v9, 0 ; CHECK-RV32-NEXT: vmv.v.i v10, 0
; CHECK-RV32-NEXT: li a0, 1 ; CHECK-RV32-NEXT: li a1, 1
; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV32-NEXT: vsub.vx v9, v9, a0 ; CHECK-RV32-NEXT: vsub.vx v10, v10, a1
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vand.vx v9, v9, a0 ; CHECK-RV32-NEXT: vsrl.vv v8, v8, v10
; CHECK-RV32-NEXT: vsrl.vv v9, v8, v9 ; CHECK-RV32-NEXT: vor.vv v8, v9, v8
; CHECK-RV32-NEXT: vmv.v.x v10, a0
; CHECK-RV32-NEXT: vand.vi v10, v10, 1
; CHECK-RV32-NEXT: vsll.vv v8, v8, v10
; CHECK-RV32-NEXT: vor.vv v8, v8, v9
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_rotl_v2i64: ; CHECK-RV64-LABEL: vror_vi_rotl_v2i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-RV64-NEXT: vsrl.vx v9, v8, a0 ; CHECK-RV64-NEXT: vsrl.vx v9, v8, a0
; CHECK-RV64-NEXT: vadd.vv v8, v8, v8 ; CHECK-RV64-NEXT: vadd.vv v8, v8, v8
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines; CHECK-ZVBB64-NEXT: ret
%b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer %b.splat = shufflevector <4 x i64> %b.head, <4 x i64> poison, <4 x i32> zeroinitializer
%x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat) %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> %b.splat)
ret <4 x i64> %x ret <4 x i64> %x
} }
define <4 x i64> @vror_vi_v4i64(<4 x i64> %a) { define <4 x i64> @vror_vi_v4i64(<4 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_v4i64: ; CHECK-RV32-LABEL: vror_vi_v4i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v10, a0
; CHECK-RV32-NEXT: vand.vi v10, v10, 1
; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10
; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v10, 0 ; CHECK-RV32-NEXT: vmv.v.i v12, 0
; CHECK-RV32-NEXT: li a0, 1 ; CHECK-RV32-NEXT: li a1, 1
; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vsub.vx v10, v10, a0 ; CHECK-RV32-NEXT: vsub.vx v12, v12, a1
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: vand.vx v12, v12, a0
; CHECK-RV32-NEXT: vand.vx v10, v10, a0 ; CHECK-RV32-NEXT: vsll.vv v8, v8, v12
; CHECK-RV32-NEXT: vsll.vv v10, v8, v10 ; CHECK-RV32-NEXT: vor.vv v8, v10, v8
; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: vand.vi v12, v12, 1
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v12
; CHECK-RV32-NEXT: vor.vv v8, v8, v10
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_v4i64: ; CHECK-RV64-LABEL: vror_vi_v4i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV64-NEXT: vsll.vx v10, v8, a0 ; CHECK-RV64-NEXT: vsll.vx v10, v8, a0
; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1 ; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1
; CHECK-RV64-NEXT: vor.vv v8, v8, v10 ; CHECK-RV64-NEXT: vor.vv v8, v8, v10
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: vror_vi_v4i64: ; CHECK-ZVBB-LABEL: vror_vi_v4i64:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-ZVBB-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> shufflevector(<4 x i64> insertelement(<4 x i64> poison, i64 1, i32 0), <4 x i64> poison, <4 x i32> zeroinitializer)) %x = call <4 x i64> @llvm.fshr.v4i64(<4 x i64> %a, <4 x i64> %a, <4 x i64> shufflevector(<4 x i64> insertelement(<4 x i64> poison, i64 1, i32 0), <4 x i64> poison, <4 x i32> zeroinitializer))
ret <4 x i64> %x ret <4 x i64> %x
} }
define <4 x i64> @vror_vi_rotl_v4i64(<4 x i64> %a) { define <4 x i64> @vror_vi_rotl_v4i64(<4 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_rotl_v4i64: ; CHECK-RV32-LABEL: vror_vi_rotl_v4i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v10, a0
; CHECK-RV32-NEXT: vand.vi v10, v10, 1
; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v10, 0 ; CHECK-RV32-NEXT: vmv.v.i v12, 0
; CHECK-RV32-NEXT: li a0, 1 ; CHECK-RV32-NEXT: li a1, 1
; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV32-NEXT: vsub.vx v10, v10, a0 ; CHECK-RV32-NEXT: vsub.vx v12, v12, a1
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: vand.vx v12, v12, a0
; CHECK-RV32-NEXT: vand.vx v10, v10, a0 ; CHECK-RV32-NEXT: vsrl.vv v8, v8, v12
; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10 ; CHECK-RV32-NEXT: vor.vv v8, v10, v8
; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: vand.vi v12, v12, 1
; CHECK-RV32-NEXT: vsll.vv v8, v8, v12
; CHECK-RV32-NEXT: vor.vv v8, v8, v10
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_rotl_v4i64: ; CHECK-RV64-LABEL: vror_vi_rotl_v4i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-RV64-NEXT: vsrl.vx v10, v8, a0 ; CHECK-RV64-NEXT: vsrl.vx v10, v8, a0
; CHECK-RV64-NEXT: vadd.vv v8, v8, v8 ; CHECK-RV64-NEXT: vadd.vv v8, v8, v8
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines; CHECK-ZVBB64-NEXT: ret
%b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer %b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer
%x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat) %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat)
ret <8 x i64> %x ret <8 x i64> %x
} }
define <8 x i64> @vror_vi_v8i64(<8 x i64> %a) { define <8 x i64> @vror_vi_v8i64(<8 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_v8i64: ; CHECK-RV32-LABEL: vror_vi_v8i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: vand.vi v12, v12, 1
; CHECK-RV32-NEXT: vsrl.vv v12, v8, v12
; CHECK-RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v12, 0 ; CHECK-RV32-NEXT: vmv.v.i v16, 0
; CHECK-RV32-NEXT: li a0, 1 ; CHECK-RV32-NEXT: li a1, 1
; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vsub.vx v12, v12, a0 ; CHECK-RV32-NEXT: vsub.vx v16, v16, a1
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: vand.vx v16, v16, a0
; CHECK-RV32-NEXT: vand.vx v12, v12, a0 ; CHECK-RV32-NEXT: vsll.vv v8, v8, v16
; CHECK-RV32-NEXT: vsll.vv v12, v8, v12 ; CHECK-RV32-NEXT: vor.vv v8, v12, v8
; CHECK-RV32-NEXT: vmv.v.x v16, a0
; CHECK-RV32-NEXT: vand.vi v16, v16, 1
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v16
; CHECK-RV32-NEXT: vor.vv v8, v8, v12
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_v8i64: ; CHECK-RV64-LABEL: vror_vi_v8i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV64-NEXT: vsll.vx v12, v8, a0 ; CHECK-RV64-NEXT: vsll.vx v12, v8, a0
; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1 ; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1
; CHECK-RV64-NEXT: vor.vv v8, v8, v12 ; CHECK-RV64-NEXT: vor.vv v8, v8, v12
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: vror_vi_v8i64: ; CHECK-ZVBB-LABEL: vror_vi_v8i64:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-ZVBB-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> shufflevector(<8 x i64> insertelement(<8 x i64> poison, i64 1, i32 0), <8 x i64> poison, <8 x i32> zeroinitializer)) %x = call <8 x i64> @llvm.fshr.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> shufflevector(<8 x i64> insertelement(<8 x i64> poison, i64 1, i32 0), <8 x i64> poison, <8 x i32> zeroinitializer))
ret <8 x i64> %x ret <8 x i64> %x
} }
define <8 x i64> @vror_vi_rotl_v8i64(<8 x i64> %a) { define <8 x i64> @vror_vi_rotl_v8i64(<8 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_rotl_v8i64: ; CHECK-RV32-LABEL: vror_vi_rotl_v8i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: vand.vi v12, v12, 1
; CHECK-RV32-NEXT: vsll.vv v12, v8, v12
; CHECK-RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v12, 0 ; CHECK-RV32-NEXT: vmv.v.i v16, 0
; CHECK-RV32-NEXT: li a0, 1 ; CHECK-RV32-NEXT: li a1, 1
; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV32-NEXT: vsub.vx v12, v12, a0 ; CHECK-RV32-NEXT: vsub.vx v16, v16, a1
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: vand.vx v16, v16, a0
; CHECK-RV32-NEXT: vand.vx v12, v12, a0 ; CHECK-RV32-NEXT: vsrl.vv v8, v8, v16
; CHECK-RV32-NEXT: vsrl.vv v12, v8, v12 ; CHECK-RV32-NEXT: vor.vv v8, v12, v8
; CHECK-RV32-NEXT: vmv.v.x v16, a0
; CHECK-RV32-NEXT: vand.vi v16, v16, 1
; CHECK-RV32-NEXT: vsll.vv v8, v8, v16
; CHECK-RV32-NEXT: vor.vv v8, v8, v12
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_rotl_v8i64: ; CHECK-RV64-LABEL: vror_vi_rotl_v8i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; CHECK-RV64-NEXT: vsrl.vx v12, v8, a0 ; CHECK-RV64-NEXT: vsrl.vx v12, v8, a0
; CHECK-RV64-NEXT: vadd.vv v8, v8, v8 ; CHECK-RV64-NEXT: vadd.vv v8, v8, v8
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect-vp.ll

Show First 20 Lines • Show All 397 Lines • ▼ Show 20 Lines
declare <32 x i64> @llvm.vp.select.v32i64(<32 x i1>, <32 x i64>, <32 x i64>, i32) declare <32 x i64> @llvm.vp.select.v32i64(<32 x i1>, <32 x i64>, <32 x i64>, i32)
define <32 x i64> @select_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32 zeroext %evl) { define <32 x i64> @select_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32 zeroext %evl) {
; CHECK-LABEL: select_v32i64: ; CHECK-LABEL: select_v32i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: addi a1, a0, 128
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: addi a1, a2, -16
; CHECK-NEXT: sltu a3, a2, a1
; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a1, a3, a1
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v24, (a1)
; CHECK-NEXT: addi a3, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: bltu a2, a1, .LBB25_2
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a0, 16
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0
; CHECK-NEXT: bltu a2, a0, .LBB25_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a2, 16 ; CHECK-NEXT: li a0, 16
; CHECK-NEXT: .LBB25_2: ; CHECK-NEXT: .LBB25_2:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, a2, -16
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: sltu a1, a2, a0
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0 ; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.select.v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32 %evl) %v = call <32 x i64> @llvm.vp.select.v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @select_evl_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c) { define <32 x i64> @select_evl_v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c) {
; CHECK-LABEL: select_evl_v32i64: ; CHECK-LABEL: select_evl_v32i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, a0, 128 ; CHECK-NEXT: addi a0, a0, 128
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v24, (a0)
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: vslidedown.vi v0, v0, 2
; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e64, m8, ta, ma
; CHECK-NEXT: vmerge.vvm v16, v8, v16, v0 ; CHECK-NEXT: vmerge.vvm v16, v24, v16, v0
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmerge.vvm v8, v24, v8, v0
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.select.v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32 17) %v = call <32 x i64> @llvm.vp.select.v32i64(<32 x i1> %a, <32 x i64> %b, <32 x i64> %c, i32 17)
ret <32 x i64> %v ret <32 x i64> %v
} }
declare <2 x half> @llvm.vp.select.v2f16(<2 x i1>, <2 x half>, <2 x half>, i32) declare <2 x half> @llvm.vp.select.v2f16(<2 x i1>, <2 x half>, <2 x half>, i32)
define <2 x half> @select_v2f16(<2 x i1> %a, <2 x half> %b, <2 x half> %c, i32 zeroext %evl) { define <2 x half> @select_v2f16(<2 x i1> %a, <2 x half> %b, <2 x half> %c, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 184 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zext-vp.ll

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <4 x i64> %v ret <4 x i64> %v
} }
declare <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32>, <32 x i1>, i32) declare <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32>, <32 x i1>, i32)
define <32 x i64> @vzext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext %evl) { define <32 x i64> @vzext_v32i64_v32i32(<32 x i32> %va, <32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vzext_v32i64_v32i32: ; CHECK-LABEL: vzext_v32i64_v32i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vi v0, v0, 2 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: vslidedown.vi v16, v0, 2
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB12_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v8, 16
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vzext.vf2 v16, v24, v0.t
; CHECK-NEXT: bltu a0, a1, .LBB12_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB12_2: ; CHECK-NEXT: .LBB12_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: vzext.vf2 v24, v8, v0.t ; CHECK-NEXT: vzext.vf2 v24, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vzext.vf2 v16, v8, v0.t
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32> %va, <32 x i1> %m, i32 %evl) %v = call <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32> %va, <32 x i1> %m, i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
define <32 x i64> @vzext_v32i64_v32i32_unmasked(<32 x i32> %va, i32 zeroext %evl) { define <32 x i64> @vzext_v32i64_v32i32_unmasked(<32 x i32> %va, i32 zeroext %evl) {
; CHECK-LABEL: vzext_v32i64_v32i32_unmasked: ; CHECK-LABEL: vzext_v32i64_v32i32_unmasked:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, a0, -16 ; CHECK-NEXT: li a2, 16
; CHECK-NEXT: sltu a2, a0, a1 ; CHECK-NEXT: mv a1, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: bltu a0, a2, .LBB13_2
; CHECK-NEXT: and a1, a2, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v24, v8, 16
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: li a1, 16
; CHECK-NEXT: vzext.vf2 v16, v24
; CHECK-NEXT: bltu a0, a1, .LBB13_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: li a0, 16 ; CHECK-NEXT: li a1, 16
; CHECK-NEXT: .LBB13_2: ; CHECK-NEXT: .LBB13_2:
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vzext.vf2 v24, v8 ; CHECK-NEXT: vzext.vf2 v24, v8
; CHECK-NEXT: vmv.v.v v8, v24 ; CHECK-NEXT: addi a1, a0, -16
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 16
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vzext.vf2 v16, v8
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32> %va, <32 x i1> shufflevector (<32 x i1> insertelement (<32 x i1> undef, i1 true, i32 0), <32 x i1> undef, <32 x i32> zeroinitializer), i32 %evl) %v = call <32 x i64> @llvm.vp.zext.v32i64.v32i32(<32 x i32> %va, <32 x i1> shufflevector (<32 x i1> insertelement (<32 x i1> undef, i1 true, i32 0), <32 x i1> undef, <32 x i32> zeroinitializer), i32 %evl)
ret <32 x i64> %v ret <32 x i64> %v
} }
declare <4 x i16> @llvm.vp.zext.v4i16.v4i7(<4 x i7>, <4 x i1>, i32) declare <4 x i16> @llvm.vp.zext.v4i16.v4i7(<4 x i7>, <4 x i1>, i32)
define <4 x i16> @vzext_v4i16_v4i7(<4 x i7> %va, <4 x i1> %m, i32 zeroext %evl) { define <4 x i16> @vzext_v4i16_v4i7(<4 x i7> %va, <4 x i1> %m, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 450 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: .cfi_offset s2, -32
; CHECK-V-NEXT: csrr a1, vlenb ; CHECK-V-NEXT: csrr a1, vlenb
; CHECK-V-NEXT: slli a1, a1, 1 ; CHECK-V-NEXT: slli a1, a1, 2
; CHECK-V-NEXT: sub sp, sp, a1 ; CHECK-V-NEXT: sub sp, sp, a1
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 4 * vlenb
; CHECK-V-NEXT: lhu s0, 24(a0) ; CHECK-V-NEXT: lhu s0, 24(a0)
; CHECK-V-NEXT: lhu s1, 16(a0) ; CHECK-V-NEXT: lhu s1, 16(a0)
; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu s2, 0(a0)
; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: lhu a0, 8(a0)
; CHECK-V-NEXT: fmv.w.x fa0, a0 ; CHECK-V-NEXT: fmv.w.x fa0, a0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s2 ; CHECK-V-NEXT: fmv.w.x fa0, s2
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vslideup.vi v8, v10, 1
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s1 ; CHECK-V-NEXT: fmv.w.x fa0, s1
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vslideup.vi v10, v8, 2
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s0 ; CHECK-V-NEXT: fmv.w.x fa0, s0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vslideup.vi v10, v8, 3
; CHECK-V-NEXT: lui a0, 524288 ; CHECK-V-NEXT: lui a0, 524288
; CHECK-V-NEXT: addiw a1, a0, -1 ; CHECK-V-NEXT: addiw a1, a0, -1
; CHECK-V-NEXT: vmin.vx v8, v10, a1 ; CHECK-V-NEXT: vmin.vx v8, v10, a1
; CHECK-V-NEXT: vmax.vx v10, v8, a0 ; CHECK-V-NEXT: vmax.vx v10, v8, a0
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-V-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-V-NEXT: vnsrl.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 2
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 48 ; CHECK-V-NEXT: addi sp, sp, 48
; CHECK-V-NEXT: ret ; CHECK-V-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 94 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: .cfi_offset s2, -32
; CHECK-V-NEXT: csrr a1, vlenb ; CHECK-V-NEXT: csrr a1, vlenb
; CHECK-V-NEXT: slli a1, a1, 1 ; CHECK-V-NEXT: slli a1, a1, 2
; CHECK-V-NEXT: sub sp, sp, a1 ; CHECK-V-NEXT: sub sp, sp, a1
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 4 * vlenb
; CHECK-V-NEXT: lhu s0, 24(a0) ; CHECK-V-NEXT: lhu s0, 24(a0)
; CHECK-V-NEXT: lhu s1, 16(a0) ; CHECK-V-NEXT: lhu s1, 16(a0)
; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu s2, 0(a0)
; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: lhu a0, 8(a0)
; CHECK-V-NEXT: fmv.w.x fa0, a0 ; CHECK-V-NEXT: fmv.w.x fa0, a0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s2 ; CHECK-V-NEXT: fmv.w.x fa0, s2
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vslideup.vi v8, v10, 1
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s1 ; CHECK-V-NEXT: fmv.w.x fa0, s1
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vslideup.vi v10, v8, 2
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s0 ; CHECK-V-NEXT: fmv.w.x fa0, s0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vslideup.vi v10, v8, 3
; CHECK-V-NEXT: li a0, -1 ; CHECK-V-NEXT: li a0, -1
; CHECK-V-NEXT: srli a0, a0, 32 ; CHECK-V-NEXT: srli a0, a0, 32
; CHECK-V-NEXT: vminu.vx v10, v10, a0 ; CHECK-V-NEXT: vminu.vx v10, v10, a0
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-V-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-V-NEXT: vnsrl.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 2
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 48 ; CHECK-V-NEXT: addi sp, sp, 48
; CHECK-V-NEXT: ret ; CHECK-V-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 104 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: .cfi_offset s2, -32
; CHECK-V-NEXT: csrr a1, vlenb ; CHECK-V-NEXT: csrr a1, vlenb
; CHECK-V-NEXT: slli a1, a1, 1 ; CHECK-V-NEXT: slli a1, a1, 2
; CHECK-V-NEXT: sub sp, sp, a1 ; CHECK-V-NEXT: sub sp, sp, a1
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 4 * vlenb
; CHECK-V-NEXT: lhu s0, 24(a0) ; CHECK-V-NEXT: lhu s0, 24(a0)
; CHECK-V-NEXT: lhu s1, 16(a0) ; CHECK-V-NEXT: lhu s1, 16(a0)
; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu s2, 0(a0)
; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: lhu a0, 8(a0)
; CHECK-V-NEXT: fmv.w.x fa0, a0 ; CHECK-V-NEXT: fmv.w.x fa0, a0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s2 ; CHECK-V-NEXT: fmv.w.x fa0, s2
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vslideup.vi v8, v10, 1
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s1 ; CHECK-V-NEXT: fmv.w.x fa0, s1
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vslideup.vi v10, v8, 2
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s0 ; CHECK-V-NEXT: fmv.w.x fa0, s0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vslideup.vi v10, v8, 3
; CHECK-V-NEXT: li a0, -1 ; CHECK-V-NEXT: li a0, -1
; CHECK-V-NEXT: srli a0, a0, 32 ; CHECK-V-NEXT: srli a0, a0, 32
; CHECK-V-NEXT: vmin.vx v8, v10, a0 ; CHECK-V-NEXT: vmin.vx v8, v10, a0
; CHECK-V-NEXT: vmax.vx v10, v8, zero ; CHECK-V-NEXT: vmax.vx v10, v8, zero
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-V-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-V-NEXT: vnsrl.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 2
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 48 ; CHECK-V-NEXT: addi sp, sp, 48
; CHECK-V-NEXT: ret ; CHECK-V-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 1,364 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixdfti@plt ; CHECK-V-NEXT: call __fixdfti@plt
; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: li a2, -1
; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: srli a3, a2, 1
; CHECK-V-NEXT: beqz s1, .LBB18_3 ; CHECK-V-NEXT: beqz a1, .LBB18_3
; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: # %bb.1: # %entry
; CHECK-V-NEXT: slti a4, s1, 0 ; CHECK-V-NEXT: slti a4, a1, 0
; CHECK-V-NEXT: bnez a1, .LBB18_4 ; CHECK-V-NEXT: bnez s1, .LBB18_4
; CHECK-V-NEXT: .LBB18_2: ; CHECK-V-NEXT: .LBB18_2:
; CHECK-V-NEXT: sltu a5, a0, a3 ; CHECK-V-NEXT: sltu a5, s0, a3
; CHECK-V-NEXT: neg a6, a4 ; CHECK-V-NEXT: beqz a5, .LBB18_5
; CHECK-V-NEXT: beqz a4, .LBB18_5
; CHECK-V-NEXT: j .LBB18_6 ; CHECK-V-NEXT: j .LBB18_6
; CHECK-V-NEXT: .LBB18_3: ; CHECK-V-NEXT: .LBB18_3:
; CHECK-V-NEXT: sltu a4, s0, a3 ; CHECK-V-NEXT: sltu a4, a0, a3
; CHECK-V-NEXT: beqz a1, .LBB18_2 ; CHECK-V-NEXT: beqz s1, .LBB18_2
; CHECK-V-NEXT: .LBB18_4: # %entry ; CHECK-V-NEXT: .LBB18_4: # %entry
; CHECK-V-NEXT: slti a5, a1, 0 ; CHECK-V-NEXT: slti a5, s1, 0
; CHECK-V-NEXT: neg a6, a4 ; CHECK-V-NEXT: bnez a5, .LBB18_6
; CHECK-V-NEXT: bnez a4, .LBB18_6
; CHECK-V-NEXT: .LBB18_5: # %entry ; CHECK-V-NEXT: .LBB18_5: # %entry
; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: mv s0, a3
; CHECK-V-NEXT: .LBB18_6: # %entry ; CHECK-V-NEXT: .LBB18_6: # %entry
; CHECK-V-NEXT: and a6, a6, s1 ; CHECK-V-NEXT: neg a6, a5
; CHECK-V-NEXT: neg a4, a5 ; CHECK-V-NEXT: neg a5, a4
; CHECK-V-NEXT: bnez a5, .LBB18_8 ; CHECK-V-NEXT: and a5, a5, a1
; CHECK-V-NEXT: bnez a4, .LBB18_8
; CHECK-V-NEXT: # %bb.7: # %entry ; CHECK-V-NEXT: # %bb.7: # %entry
; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: mv a0, a3
; CHECK-V-NEXT: .LBB18_8: # %entry ; CHECK-V-NEXT: .LBB18_8: # %entry
; CHECK-V-NEXT: and a4, a4, a1 ; CHECK-V-NEXT: and a4, a6, s1
; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: slli a1, a2, 63
; CHECK-V-NEXT: beq a6, a2, .LBB18_11 ; CHECK-V-NEXT: beq a5, a2, .LBB18_11
; CHECK-V-NEXT: # %bb.9: # %entry ; CHECK-V-NEXT: # %bb.9: # %entry
; CHECK-V-NEXT: slti a3, a6, 0 ; CHECK-V-NEXT: slti a3, a5, 0
; CHECK-V-NEXT: xori a3, a3, 1 ; CHECK-V-NEXT: xori a3, a3, 1
; CHECK-V-NEXT: bne a4, a2, .LBB18_12 ; CHECK-V-NEXT: bne a4, a2, .LBB18_12
; CHECK-V-NEXT: .LBB18_10: ; CHECK-V-NEXT: .LBB18_10:
; CHECK-V-NEXT: sltu a2, a1, a0 ; CHECK-V-NEXT: sltu a2, a1, s0
; CHECK-V-NEXT: beqz a3, .LBB18_13 ; CHECK-V-NEXT: beqz a2, .LBB18_13
; CHECK-V-NEXT: j .LBB18_14 ; CHECK-V-NEXT: j .LBB18_14
; CHECK-V-NEXT: .LBB18_11: ; CHECK-V-NEXT: .LBB18_11:
; CHECK-V-NEXT: sltu a3, a1, s0 ; CHECK-V-NEXT: sltu a3, a1, a0
; CHECK-V-NEXT: beq a4, a2, .LBB18_10 ; CHECK-V-NEXT: beq a4, a2, .LBB18_10
; CHECK-V-NEXT: .LBB18_12: # %entry ; CHECK-V-NEXT: .LBB18_12: # %entry
; CHECK-V-NEXT: slti a2, a4, 0 ; CHECK-V-NEXT: slti a2, a4, 0
; CHECK-V-NEXT: xori a2, a2, 1 ; CHECK-V-NEXT: xori a2, a2, 1
; CHECK-V-NEXT: bnez a3, .LBB18_14 ; CHECK-V-NEXT: bnez a2, .LBB18_14
; CHECK-V-NEXT: .LBB18_13: # %entry ; CHECK-V-NEXT: .LBB18_13: # %entry
; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: mv s0, a1
; CHECK-V-NEXT: .LBB18_14: # %entry ; CHECK-V-NEXT: .LBB18_14: # %entry
; CHECK-V-NEXT: bnez a2, .LBB18_16 ; CHECK-V-NEXT: bnez a3, .LBB18_16
; CHECK-V-NEXT: # %bb.15: # %entry ; CHECK-V-NEXT: # %bb.15: # %entry
; CHECK-V-NEXT: mv a0, a1 ; CHECK-V-NEXT: mv a0, a1
; CHECK-V-NEXT: .LBB18_16: # %entry ; CHECK-V-NEXT: .LBB18_16: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v9, s0
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: vmv.s.x v9, s0
; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 64 ; CHECK-V-NEXT: addi sp, sp, 64
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: call __fixunsdfti@plt ; CHECK-V-NEXT: call __fixunsdfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixunsdfti@plt ; CHECK-V-NEXT: call __fixunsdfti@plt
; CHECK-V-NEXT: snez a2, s1
; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: snez a1, a1
; CHECK-V-NEXT: snez a2, s1
; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: addi a2, a2, -1
; CHECK-V-NEXT: and a2, a2, s0 ; CHECK-V-NEXT: and a2, a2, s0
; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: addi a1, a1, -1
; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: and a0, a1, a0
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v9, a2
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: vmv.s.x v9, a2
; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 64 ; CHECK-V-NEXT: addi sp, sp, 64
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixdfti@plt ; CHECK-V-NEXT: call __fixdfti@plt
; CHECK-V-NEXT: mv s1, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixdfti@plt ; CHECK-V-NEXT: call __fixdfti@plt
; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: mv a2, s1
; CHECK-V-NEXT: blez a1, .LBB20_2 ; CHECK-V-NEXT: blez s1, .LBB20_2
; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: # %bb.1: # %entry
; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: li a2, 1
; CHECK-V-NEXT: .LBB20_2: # %entry ; CHECK-V-NEXT: .LBB20_2: # %entry
; CHECK-V-NEXT: slti a3, s0, 1 ; CHECK-V-NEXT: slti a4, a1, 1
; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: slti a3, s1, 1
; CHECK-V-NEXT: blez s0, .LBB20_4 ; CHECK-V-NEXT: blez a1, .LBB20_4
; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: # %bb.3: # %entry
; CHECK-V-NEXT: li s0, 1 ; CHECK-V-NEXT: li a1, 1
; CHECK-V-NEXT: .LBB20_4: # %entry ; CHECK-V-NEXT: .LBB20_4: # %entry
; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: neg a3, a3
; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: neg a4, a4
; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: and a0, a4, a0
; CHECK-V-NEXT: beqz a2, .LBB20_7 ; CHECK-V-NEXT: beqz a1, .LBB20_7
; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: # %bb.5: # %entry
; CHECK-V-NEXT: sgtz a1, a2 ; CHECK-V-NEXT: sgtz a1, a1
; CHECK-V-NEXT: and a3, a3, s1 ; CHECK-V-NEXT: and a3, a3, s0
; CHECK-V-NEXT: bnez s0, .LBB20_8 ; CHECK-V-NEXT: bnez a2, .LBB20_8
; CHECK-V-NEXT: .LBB20_6: ; CHECK-V-NEXT: .LBB20_6:
; CHECK-V-NEXT: snez a2, a3 ; CHECK-V-NEXT: snez a2, a3
; CHECK-V-NEXT: j .LBB20_9 ; CHECK-V-NEXT: j .LBB20_9
; CHECK-V-NEXT: .LBB20_7: ; CHECK-V-NEXT: .LBB20_7:
; CHECK-V-NEXT: snez a1, a0 ; CHECK-V-NEXT: snez a1, a0
; CHECK-V-NEXT: and a3, a3, s1 ; CHECK-V-NEXT: and a3, a3, s0
; CHECK-V-NEXT: beqz s0, .LBB20_6 ; CHECK-V-NEXT: beqz a2, .LBB20_6
; CHECK-V-NEXT: .LBB20_8: # %entry ; CHECK-V-NEXT: .LBB20_8: # %entry
; CHECK-V-NEXT: sgtz a2, s0 ; CHECK-V-NEXT: sgtz a2, a2
; CHECK-V-NEXT: .LBB20_9: # %entry ; CHECK-V-NEXT: .LBB20_9: # %entry
; CHECK-V-NEXT: neg a2, a2 ; CHECK-V-NEXT: neg a2, a2
; CHECK-V-NEXT: and a2, a2, a3 ; CHECK-V-NEXT: and a2, a2, a3
; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: neg a1, a1
; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: and a0, a1, a0
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: vmv.s.x v9, a2 ; CHECK-V-NEXT: vmv.s.x v9, a2
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixsfti@plt ; CHECK-V-NEXT: call __fixsfti@plt
; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: li a2, -1
; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: srli a3, a2, 1
; CHECK-V-NEXT: beqz s1, .LBB21_3 ; CHECK-V-NEXT: beqz a1, .LBB21_3
; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: # %bb.1: # %entry
; CHECK-V-NEXT: slti a4, s1, 0 ; CHECK-V-NEXT: slti a4, a1, 0
; CHECK-V-NEXT: bnez a1, .LBB21_4 ; CHECK-V-NEXT: bnez s1, .LBB21_4
; CHECK-V-NEXT: .LBB21_2: ; CHECK-V-NEXT: .LBB21_2:
; CHECK-V-NEXT: sltu a5, a0, a3 ; CHECK-V-NEXT: sltu a5, s0, a3
; CHECK-V-NEXT: neg a6, a4 ; CHECK-V-NEXT: beqz a5, .LBB21_5
; CHECK-V-NEXT: beqz a4, .LBB21_5
; CHECK-V-NEXT: j .LBB21_6 ; CHECK-V-NEXT: j .LBB21_6
; CHECK-V-NEXT: .LBB21_3: ; CHECK-V-NEXT: .LBB21_3:
; CHECK-V-NEXT: sltu a4, s0, a3 ; CHECK-V-NEXT: sltu a4, a0, a3
; CHECK-V-NEXT: beqz a1, .LBB21_2 ; CHECK-V-NEXT: beqz s1, .LBB21_2
; CHECK-V-NEXT: .LBB21_4: # %entry ; CHECK-V-NEXT: .LBB21_4: # %entry
; CHECK-V-NEXT: slti a5, a1, 0 ; CHECK-V-NEXT: slti a5, s1, 0
; CHECK-V-NEXT: neg a6, a4 ; CHECK-V-NEXT: bnez a5, .LBB21_6
; CHECK-V-NEXT: bnez a4, .LBB21_6
; CHECK-V-NEXT: .LBB21_5: # %entry ; CHECK-V-NEXT: .LBB21_5: # %entry
; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: mv s0, a3
; CHECK-V-NEXT: .LBB21_6: # %entry ; CHECK-V-NEXT: .LBB21_6: # %entry
; CHECK-V-NEXT: and a6, a6, s1 ; CHECK-V-NEXT: neg a6, a5
; CHECK-V-NEXT: neg a4, a5 ; CHECK-V-NEXT: neg a5, a4
; CHECK-V-NEXT: bnez a5, .LBB21_8 ; CHECK-V-NEXT: and a5, a5, a1
; CHECK-V-NEXT: bnez a4, .LBB21_8
; CHECK-V-NEXT: # %bb.7: # %entry ; CHECK-V-NEXT: # %bb.7: # %entry
; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: mv a0, a3
; CHECK-V-NEXT: .LBB21_8: # %entry ; CHECK-V-NEXT: .LBB21_8: # %entry
; CHECK-V-NEXT: and a4, a4, a1 ; CHECK-V-NEXT: and a4, a6, s1
; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: slli a1, a2, 63
; CHECK-V-NEXT: beq a6, a2, .LBB21_11 ; CHECK-V-NEXT: beq a5, a2, .LBB21_11
; CHECK-V-NEXT: # %bb.9: # %entry ; CHECK-V-NEXT: # %bb.9: # %entry
; CHECK-V-NEXT: slti a3, a6, 0 ; CHECK-V-NEXT: slti a3, a5, 0
; CHECK-V-NEXT: xori a3, a3, 1 ; CHECK-V-NEXT: xori a3, a3, 1
; CHECK-V-NEXT: bne a4, a2, .LBB21_12 ; CHECK-V-NEXT: bne a4, a2, .LBB21_12
; CHECK-V-NEXT: .LBB21_10: ; CHECK-V-NEXT: .LBB21_10:
; CHECK-V-NEXT: sltu a2, a1, a0 ; CHECK-V-NEXT: sltu a2, a1, s0
; CHECK-V-NEXT: beqz a3, .LBB21_13 ; CHECK-V-NEXT: beqz a2, .LBB21_13
; CHECK-V-NEXT: j .LBB21_14 ; CHECK-V-NEXT: j .LBB21_14
; CHECK-V-NEXT: .LBB21_11: ; CHECK-V-NEXT: .LBB21_11:
; CHECK-V-NEXT: sltu a3, a1, s0 ; CHECK-V-NEXT: sltu a3, a1, a0
; CHECK-V-NEXT: beq a4, a2, .LBB21_10 ; CHECK-V-NEXT: beq a4, a2, .LBB21_10
; CHECK-V-NEXT: .LBB21_12: # %entry ; CHECK-V-NEXT: .LBB21_12: # %entry
; CHECK-V-NEXT: slti a2, a4, 0 ; CHECK-V-NEXT: slti a2, a4, 0
; CHECK-V-NEXT: xori a2, a2, 1 ; CHECK-V-NEXT: xori a2, a2, 1
; CHECK-V-NEXT: bnez a3, .LBB21_14 ; CHECK-V-NEXT: bnez a2, .LBB21_14
; CHECK-V-NEXT: .LBB21_13: # %entry ; CHECK-V-NEXT: .LBB21_13: # %entry
; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: mv s0, a1
; CHECK-V-NEXT: .LBB21_14: # %entry ; CHECK-V-NEXT: .LBB21_14: # %entry
; CHECK-V-NEXT: bnez a2, .LBB21_16 ; CHECK-V-NEXT: bnez a3, .LBB21_16
; CHECK-V-NEXT: # %bb.15: # %entry ; CHECK-V-NEXT: # %bb.15: # %entry
; CHECK-V-NEXT: mv a0, a1 ; CHECK-V-NEXT: mv a0, a1
; CHECK-V-NEXT: .LBB21_16: # %entry ; CHECK-V-NEXT: .LBB21_16: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v9, s0
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: vmv.s.x v9, s0
; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 64 ; CHECK-V-NEXT: addi sp, sp, 64
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: call __fixunssfti@plt ; CHECK-V-NEXT: call __fixunssfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixunssfti@plt ; CHECK-V-NEXT: call __fixunssfti@plt
; CHECK-V-NEXT: snez a2, s1
; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: snez a1, a1
; CHECK-V-NEXT: snez a2, s1
; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: addi a2, a2, -1
; CHECK-V-NEXT: and a2, a2, s0 ; CHECK-V-NEXT: and a2, a2, s0
; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: addi a1, a1, -1
; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: and a0, a1, a0
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v9, a2
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: vmv.s.x v9, a2
; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 64 ; CHECK-V-NEXT: addi sp, sp, 64
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixsfti@plt ; CHECK-V-NEXT: call __fixsfti@plt
; CHECK-V-NEXT: mv s1, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixsfti@plt ; CHECK-V-NEXT: call __fixsfti@plt
; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: mv a2, s1
; CHECK-V-NEXT: blez a1, .LBB23_2 ; CHECK-V-NEXT: blez s1, .LBB23_2
; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: # %bb.1: # %entry
; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: li a2, 1
; CHECK-V-NEXT: .LBB23_2: # %entry ; CHECK-V-NEXT: .LBB23_2: # %entry
; CHECK-V-NEXT: slti a3, s0, 1 ; CHECK-V-NEXT: slti a4, a1, 1
; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: slti a3, s1, 1
; CHECK-V-NEXT: blez s0, .LBB23_4 ; CHECK-V-NEXT: blez a1, .LBB23_4
; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: # %bb.3: # %entry
; CHECK-V-NEXT: li s0, 1 ; CHECK-V-NEXT: li a1, 1
; CHECK-V-NEXT: .LBB23_4: # %entry ; CHECK-V-NEXT: .LBB23_4: # %entry
; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: neg a3, a3
; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: neg a4, a4
; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: and a0, a4, a0
; CHECK-V-NEXT: beqz a2, .LBB23_7 ; CHECK-V-NEXT: beqz a1, .LBB23_7
; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: # %bb.5: # %entry
; CHECK-V-NEXT: sgtz a1, a2 ; CHECK-V-NEXT: sgtz a1, a1
; CHECK-V-NEXT: and a3, a3, s1 ; CHECK-V-NEXT: and a3, a3, s0
; CHECK-V-NEXT: bnez s0, .LBB23_8 ; CHECK-V-NEXT: bnez a2, .LBB23_8
; CHECK-V-NEXT: .LBB23_6: ; CHECK-V-NEXT: .LBB23_6:
; CHECK-V-NEXT: snez a2, a3 ; CHECK-V-NEXT: snez a2, a3
; CHECK-V-NEXT: j .LBB23_9 ; CHECK-V-NEXT: j .LBB23_9
; CHECK-V-NEXT: .LBB23_7: ; CHECK-V-NEXT: .LBB23_7:
; CHECK-V-NEXT: snez a1, a0 ; CHECK-V-NEXT: snez a1, a0
; CHECK-V-NEXT: and a3, a3, s1 ; CHECK-V-NEXT: and a3, a3, s0
; CHECK-V-NEXT: beqz s0, .LBB23_6 ; CHECK-V-NEXT: beqz a2, .LBB23_6
; CHECK-V-NEXT: .LBB23_8: # %entry ; CHECK-V-NEXT: .LBB23_8: # %entry
; CHECK-V-NEXT: sgtz a2, s0 ; CHECK-V-NEXT: sgtz a2, a2
; CHECK-V-NEXT: .LBB23_9: # %entry ; CHECK-V-NEXT: .LBB23_9: # %entry
; CHECK-V-NEXT: neg a2, a2 ; CHECK-V-NEXT: neg a2, a2
; CHECK-V-NEXT: and a2, a2, a3 ; CHECK-V-NEXT: and a2, a2, a3
; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: neg a1, a1
; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: and a0, a1, a0
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: vmv.s.x v9, a2 ; CHECK-V-NEXT: vmv.s.x v9, a2
▲ Show 20 Lines • Show All 847 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: .cfi_offset s2, -32
; CHECK-V-NEXT: csrr a1, vlenb ; CHECK-V-NEXT: csrr a1, vlenb
; CHECK-V-NEXT: slli a1, a1, 1 ; CHECK-V-NEXT: slli a1, a1, 2
; CHECK-V-NEXT: sub sp, sp, a1 ; CHECK-V-NEXT: sub sp, sp, a1
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 4 * vlenb
; CHECK-V-NEXT: lhu s0, 24(a0) ; CHECK-V-NEXT: lhu s0, 24(a0)
; CHECK-V-NEXT: lhu s1, 16(a0) ; CHECK-V-NEXT: lhu s1, 16(a0)
; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu s2, 0(a0)
; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: lhu a0, 8(a0)
; CHECK-V-NEXT: fmv.w.x fa0, a0 ; CHECK-V-NEXT: fmv.w.x fa0, a0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s2 ; CHECK-V-NEXT: fmv.w.x fa0, s2
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vslideup.vi v8, v10, 1
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s1 ; CHECK-V-NEXT: fmv.w.x fa0, s1
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vslideup.vi v10, v8, 2
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s0 ; CHECK-V-NEXT: fmv.w.x fa0, s0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vslideup.vi v10, v8, 3
; CHECK-V-NEXT: lui a0, 524288 ; CHECK-V-NEXT: lui a0, 524288
; CHECK-V-NEXT: addiw a1, a0, -1 ; CHECK-V-NEXT: addiw a1, a0, -1
; CHECK-V-NEXT: vmin.vx v8, v10, a1 ; CHECK-V-NEXT: vmin.vx v8, v10, a1
; CHECK-V-NEXT: vmax.vx v10, v8, a0 ; CHECK-V-NEXT: vmax.vx v10, v8, a0
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-V-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-V-NEXT: vnsrl.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 2
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 48 ; CHECK-V-NEXT: addi sp, sp, 48
; CHECK-V-NEXT: ret ; CHECK-V-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: .cfi_offset s2, -32
; CHECK-V-NEXT: csrr a1, vlenb ; CHECK-V-NEXT: csrr a1, vlenb
; CHECK-V-NEXT: slli a1, a1, 1 ; CHECK-V-NEXT: slli a1, a1, 2
; CHECK-V-NEXT: sub sp, sp, a1 ; CHECK-V-NEXT: sub sp, sp, a1
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 4 * vlenb
; CHECK-V-NEXT: lhu s0, 24(a0) ; CHECK-V-NEXT: lhu s0, 24(a0)
; CHECK-V-NEXT: lhu s1, 16(a0) ; CHECK-V-NEXT: lhu s1, 16(a0)
; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu s2, 0(a0)
; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: lhu a0, 8(a0)
; CHECK-V-NEXT: fmv.w.x fa0, a0 ; CHECK-V-NEXT: fmv.w.x fa0, a0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s2 ; CHECK-V-NEXT: fmv.w.x fa0, s2
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vslideup.vi v8, v10, 1
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s1 ; CHECK-V-NEXT: fmv.w.x fa0, s1
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vslideup.vi v10, v8, 2
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s0 ; CHECK-V-NEXT: fmv.w.x fa0, s0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.lu.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vslideup.vi v10, v8, 3
; CHECK-V-NEXT: li a0, -1 ; CHECK-V-NEXT: li a0, -1
; CHECK-V-NEXT: srli a0, a0, 32 ; CHECK-V-NEXT: srli a0, a0, 32
; CHECK-V-NEXT: vminu.vx v10, v10, a0 ; CHECK-V-NEXT: vminu.vx v10, v10, a0
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-V-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-V-NEXT: vnsrl.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 2
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 48 ; CHECK-V-NEXT: addi sp, sp, 48
; CHECK-V-NEXT: ret ; CHECK-V-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill ; CHECK-V-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; CHECK-V-NEXT: .cfi_offset ra, -8 ; CHECK-V-NEXT: .cfi_offset ra, -8
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: .cfi_offset s2, -32 ; CHECK-V-NEXT: .cfi_offset s2, -32
; CHECK-V-NEXT: csrr a1, vlenb ; CHECK-V-NEXT: csrr a1, vlenb
; CHECK-V-NEXT: slli a1, a1, 1 ; CHECK-V-NEXT: slli a1, a1, 2
; CHECK-V-NEXT: sub sp, sp, a1 ; CHECK-V-NEXT: sub sp, sp, a1
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x30, 0x22, 0x11, 0x04, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 48 + 4 * vlenb
; CHECK-V-NEXT: lhu s0, 24(a0) ; CHECK-V-NEXT: lhu s0, 24(a0)
; CHECK-V-NEXT: lhu s1, 16(a0) ; CHECK-V-NEXT: lhu s1, 16(a0)
; CHECK-V-NEXT: lhu s2, 0(a0) ; CHECK-V-NEXT: lhu s2, 0(a0)
; CHECK-V-NEXT: lhu a0, 8(a0) ; CHECK-V-NEXT: lhu a0, 8(a0)
; CHECK-V-NEXT: fmv.w.x fa0, a0 ; CHECK-V-NEXT: fmv.w.x fa0, a0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s2 ; CHECK-V-NEXT: fmv.w.x fa0, s2
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: addi a0, sp, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v8, v10, 1 ; CHECK-V-NEXT: vslideup.vi v8, v10, 1
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s1 ; CHECK-V-NEXT: fmv.w.x fa0, s1
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma ; CHECK-V-NEXT: vsetivli zero, 3, e64, m2, tu, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 2 ; CHECK-V-NEXT: vslideup.vi v10, v8, 2
; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs2r.v v10, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: fmv.w.x fa0, s0 ; CHECK-V-NEXT: fmv.w.x fa0, s0
; CHECK-V-NEXT: call __extendhfsf2@plt ; CHECK-V-NEXT: call __extendhfsf2@plt
; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz ; CHECK-V-NEXT: fcvt.l.s a0, fa0, rtz
; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: addi a0, sp, 16 ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add a0, sp, a0
; CHECK-V-NEXT: addi a0, a0, 16
; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl2r.v v10, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslideup.vi v10, v8, 3 ; CHECK-V-NEXT: vslideup.vi v10, v8, 3
; CHECK-V-NEXT: li a0, -1 ; CHECK-V-NEXT: li a0, -1
; CHECK-V-NEXT: srli a0, a0, 32 ; CHECK-V-NEXT: srli a0, a0, 32
; CHECK-V-NEXT: vmin.vx v8, v10, a0 ; CHECK-V-NEXT: vmin.vx v8, v10, a0
; CHECK-V-NEXT: vmax.vx v10, v8, zero ; CHECK-V-NEXT: vmax.vx v10, v8, zero
; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-V-NEXT: vnsrl.wi v8, v10, 0 ; CHECK-V-NEXT: vnsrl.wi v8, v10, 0
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 2
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 48 ; CHECK-V-NEXT: addi sp, sp, 48
; CHECK-V-NEXT: ret ; CHECK-V-NEXT: ret
entry: entry:
▲ Show 20 Lines • Show All 1,348 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixdfti@plt ; CHECK-V-NEXT: call __fixdfti@plt
; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: li a2, -1
; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: srli a3, a2, 1
; CHECK-V-NEXT: beqz s1, .LBB45_2 ; CHECK-V-NEXT: beqz a1, .LBB45_2
; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: # %bb.1: # %entry
; CHECK-V-NEXT: slti a4, s1, 0 ; CHECK-V-NEXT: slti a4, a1, 0
; CHECK-V-NEXT: beqz a4, .LBB45_3 ; CHECK-V-NEXT: beqz a4, .LBB45_3
; CHECK-V-NEXT: j .LBB45_4 ; CHECK-V-NEXT: j .LBB45_4
; CHECK-V-NEXT: .LBB45_2: ; CHECK-V-NEXT: .LBB45_2:
; CHECK-V-NEXT: sltu a4, s0, a3 ; CHECK-V-NEXT: sltu a4, a0, a3
; CHECK-V-NEXT: bnez a4, .LBB45_4 ; CHECK-V-NEXT: bnez a4, .LBB45_4
; CHECK-V-NEXT: .LBB45_3: # %entry ; CHECK-V-NEXT: .LBB45_3: # %entry
; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: mv a0, a3
; CHECK-V-NEXT: .LBB45_4: # %entry ; CHECK-V-NEXT: .LBB45_4: # %entry
; CHECK-V-NEXT: neg a5, a4 ; CHECK-V-NEXT: beqz s1, .LBB45_6
; CHECK-V-NEXT: beqz a1, .LBB45_6
; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: # %bb.5: # %entry
; CHECK-V-NEXT: slti a4, a1, 0 ; CHECK-V-NEXT: slti a6, s1, 0
; CHECK-V-NEXT: and a5, a5, s1 ; CHECK-V-NEXT: j .LBB45_7
; CHECK-V-NEXT: beqz a4, .LBB45_7
; CHECK-V-NEXT: j .LBB45_8
; CHECK-V-NEXT: .LBB45_6: ; CHECK-V-NEXT: .LBB45_6:
; CHECK-V-NEXT: sltu a4, a0, a3 ; CHECK-V-NEXT: sltu a6, s0, a3
; CHECK-V-NEXT: and a5, a5, s1
; CHECK-V-NEXT: bnez a4, .LBB45_8
; CHECK-V-NEXT: .LBB45_7: # %entry ; CHECK-V-NEXT: .LBB45_7: # %entry
; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: neg a5, a6
; CHECK-V-NEXT: .LBB45_8: # %entry ; CHECK-V-NEXT: and a5, a5, s1
; CHECK-V-NEXT: bnez a6, .LBB45_9
; CHECK-V-NEXT: # %bb.8: # %entry
; CHECK-V-NEXT: mv s0, a3
; CHECK-V-NEXT: .LBB45_9: # %entry
; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: neg a4, a4
; CHECK-V-NEXT: slli a3, a2, 63 ; CHECK-V-NEXT: slli a3, a2, 63
; CHECK-V-NEXT: beq a5, a2, .LBB45_10 ; CHECK-V-NEXT: beq a5, a2, .LBB45_11
; CHECK-V-NEXT: # %bb.9: # %entry ; CHECK-V-NEXT: # %bb.10: # %entry
; CHECK-V-NEXT: slti a5, a5, 0 ; CHECK-V-NEXT: slti a5, a5, 0
; CHECK-V-NEXT: xori a5, a5, 1 ; CHECK-V-NEXT: xori a5, a5, 1
; CHECK-V-NEXT: and a1, a4, a1 ; CHECK-V-NEXT: and a1, a4, a1
; CHECK-V-NEXT: beqz a5, .LBB45_11 ; CHECK-V-NEXT: beqz a5, .LBB45_12
; CHECK-V-NEXT: j .LBB45_12 ; CHECK-V-NEXT: j .LBB45_13
; CHECK-V-NEXT: .LBB45_10: ; CHECK-V-NEXT: .LBB45_11:
; CHECK-V-NEXT: sltu a5, a3, s0 ; CHECK-V-NEXT: sltu a5, a3, s0
; CHECK-V-NEXT: and a1, a4, a1 ; CHECK-V-NEXT: and a1, a4, a1
; CHECK-V-NEXT: bnez a5, .LBB45_12 ; CHECK-V-NEXT: bnez a5, .LBB45_13
; CHECK-V-NEXT: .LBB45_11: # %entry
; CHECK-V-NEXT: mv s0, a3
; CHECK-V-NEXT: .LBB45_12: # %entry ; CHECK-V-NEXT: .LBB45_12: # %entry
; CHECK-V-NEXT: beq a1, a2, .LBB45_14 ; CHECK-V-NEXT: mv s0, a3
; CHECK-V-NEXT: # %bb.13: # %entry ; CHECK-V-NEXT: .LBB45_13: # %entry
; CHECK-V-NEXT: beq a1, a2, .LBB45_15
; CHECK-V-NEXT: # %bb.14: # %entry
; CHECK-V-NEXT: slti a1, a1, 0 ; CHECK-V-NEXT: slti a1, a1, 0
; CHECK-V-NEXT: xori a1, a1, 1 ; CHECK-V-NEXT: xori a1, a1, 1
; CHECK-V-NEXT: beqz a1, .LBB45_15 ; CHECK-V-NEXT: beqz a1, .LBB45_16
; CHECK-V-NEXT: j .LBB45_16 ; CHECK-V-NEXT: j .LBB45_17
; CHECK-V-NEXT: .LBB45_14: ; CHECK-V-NEXT: .LBB45_15:
; CHECK-V-NEXT: sltu a1, a3, a0 ; CHECK-V-NEXT: sltu a1, a3, a0
; CHECK-V-NEXT: bnez a1, .LBB45_16 ; CHECK-V-NEXT: bnez a1, .LBB45_17
; CHECK-V-NEXT: .LBB45_15: # %entry
; CHECK-V-NEXT: mv a0, a3
; CHECK-V-NEXT: .LBB45_16: # %entry ; CHECK-V-NEXT: .LBB45_16: # %entry
; CHECK-V-NEXT: mv a0, a3
; CHECK-V-NEXT: .LBB45_17: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v9, s0
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: vmv.s.x v9, s0
; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 64 ; CHECK-V-NEXT: addi sp, sp, 64
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixunsdfti@plt ; CHECK-V-NEXT: call __fixunsdfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslidedown.vi v8, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixunsdfti@plt ; CHECK-V-NEXT: call __fixunsdfti@plt
; CHECK-V-NEXT: snez a2, s1
; CHECK-V-NEXT: addi a2, a2, -1
; CHECK-V-NEXT: and a2, a2, s0
; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: snez a1, a1
; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: addi a1, a1, -1
; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: and a0, a1, a0
; CHECK-V-NEXT: snez a1, s1
; CHECK-V-NEXT: addi a1, a1, -1
; CHECK-V-NEXT: and a1, a1, s0
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v9, a2 ; CHECK-V-NEXT: vmv.s.x v8, a1
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v9, a0
; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 64 ; CHECK-V-NEXT: addi sp, sp, 64
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixdfti@plt ; CHECK-V-NEXT: call __fixdfti@plt
; CHECK-V-NEXT: mv s1, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e64, m1, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixdfti@plt ; CHECK-V-NEXT: call __fixdfti@plt
; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: mv a2, a1
; CHECK-V-NEXT: blez a1, .LBB47_2 ; CHECK-V-NEXT: blez a1, .LBB47_2
; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: # %bb.1: # %entry
; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: li a2, 1
; CHECK-V-NEXT: .LBB47_2: # %entry ; CHECK-V-NEXT: .LBB47_2: # %entry
; CHECK-V-NEXT: slti a3, s0, 1 ; CHECK-V-NEXT: mv a3, s1
; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: blez s1, .LBB47_4
; CHECK-V-NEXT: and a3, a3, s1 ; CHECK-V-NEXT: # %bb.3: # %entry
; CHECK-V-NEXT: li a3, 1
; CHECK-V-NEXT: .LBB47_4: # %entry
; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: slti a1, a1, 1
; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: neg a1, a1
; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: and a0, a1, a0
; CHECK-V-NEXT: blez s0, .LBB47_4 ; CHECK-V-NEXT: slti a1, s1, 1
; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: neg a1, a1
; CHECK-V-NEXT: li s0, 1 ; CHECK-V-NEXT: and a1, a1, s0
; CHECK-V-NEXT: .LBB47_4: # %entry ; CHECK-V-NEXT: slti a3, a3, 0
; CHECK-V-NEXT: slti a1, s0, 0 ; CHECK-V-NEXT: addi a3, a3, -1
; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: and a1, a3, a1
; CHECK-V-NEXT: and a1, a1, a3
; CHECK-V-NEXT: slti a2, a2, 0 ; CHECK-V-NEXT: slti a2, a2, 0
; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: addi a2, a2, -1
; CHECK-V-NEXT: and a0, a2, a0 ; CHECK-V-NEXT: and a0, a2, a0
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: vmv.s.x v9, a1 ; CHECK-V-NEXT: vmv.s.x v9, a1
; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
▲ Show 20 Lines • Show All 119 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixsfti@plt ; CHECK-V-NEXT: call __fixsfti@plt
; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: li a2, -1
; CHECK-V-NEXT: srli a3, a2, 1 ; CHECK-V-NEXT: srli a3, a2, 1
; CHECK-V-NEXT: beqz s1, .LBB48_2 ; CHECK-V-NEXT: beqz a1, .LBB48_2
; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: # %bb.1: # %entry
; CHECK-V-NEXT: slti a4, s1, 0 ; CHECK-V-NEXT: slti a4, a1, 0
; CHECK-V-NEXT: beqz a4, .LBB48_3 ; CHECK-V-NEXT: beqz a4, .LBB48_3
; CHECK-V-NEXT: j .LBB48_4 ; CHECK-V-NEXT: j .LBB48_4
; CHECK-V-NEXT: .LBB48_2: ; CHECK-V-NEXT: .LBB48_2:
; CHECK-V-NEXT: sltu a4, s0, a3 ; CHECK-V-NEXT: sltu a4, a0, a3
; CHECK-V-NEXT: bnez a4, .LBB48_4 ; CHECK-V-NEXT: bnez a4, .LBB48_4
; CHECK-V-NEXT: .LBB48_3: # %entry ; CHECK-V-NEXT: .LBB48_3: # %entry
; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: mv a0, a3
; CHECK-V-NEXT: .LBB48_4: # %entry ; CHECK-V-NEXT: .LBB48_4: # %entry
; CHECK-V-NEXT: neg a5, a4 ; CHECK-V-NEXT: beqz s1, .LBB48_6
; CHECK-V-NEXT: beqz a1, .LBB48_6
; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: # %bb.5: # %entry
; CHECK-V-NEXT: slti a4, a1, 0 ; CHECK-V-NEXT: slti a6, s1, 0
; CHECK-V-NEXT: and a5, a5, s1 ; CHECK-V-NEXT: j .LBB48_7
; CHECK-V-NEXT: beqz a4, .LBB48_7
; CHECK-V-NEXT: j .LBB48_8
; CHECK-V-NEXT: .LBB48_6: ; CHECK-V-NEXT: .LBB48_6:
; CHECK-V-NEXT: sltu a4, a0, a3 ; CHECK-V-NEXT: sltu a6, s0, a3
; CHECK-V-NEXT: and a5, a5, s1
; CHECK-V-NEXT: bnez a4, .LBB48_8
; CHECK-V-NEXT: .LBB48_7: # %entry ; CHECK-V-NEXT: .LBB48_7: # %entry
; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: neg a5, a6
; CHECK-V-NEXT: .LBB48_8: # %entry ; CHECK-V-NEXT: and a5, a5, s1
; CHECK-V-NEXT: bnez a6, .LBB48_9
; CHECK-V-NEXT: # %bb.8: # %entry
; CHECK-V-NEXT: mv s0, a3
; CHECK-V-NEXT: .LBB48_9: # %entry
; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: neg a4, a4
; CHECK-V-NEXT: slli a3, a2, 63 ; CHECK-V-NEXT: slli a3, a2, 63
; CHECK-V-NEXT: beq a5, a2, .LBB48_10 ; CHECK-V-NEXT: beq a5, a2, .LBB48_11
; CHECK-V-NEXT: # %bb.9: # %entry ; CHECK-V-NEXT: # %bb.10: # %entry
; CHECK-V-NEXT: slti a5, a5, 0 ; CHECK-V-NEXT: slti a5, a5, 0
; CHECK-V-NEXT: xori a5, a5, 1 ; CHECK-V-NEXT: xori a5, a5, 1
; CHECK-V-NEXT: and a1, a4, a1 ; CHECK-V-NEXT: and a1, a4, a1
; CHECK-V-NEXT: beqz a5, .LBB48_11 ; CHECK-V-NEXT: beqz a5, .LBB48_12
; CHECK-V-NEXT: j .LBB48_12 ; CHECK-V-NEXT: j .LBB48_13
; CHECK-V-NEXT: .LBB48_10: ; CHECK-V-NEXT: .LBB48_11:
; CHECK-V-NEXT: sltu a5, a3, s0 ; CHECK-V-NEXT: sltu a5, a3, s0
; CHECK-V-NEXT: and a1, a4, a1 ; CHECK-V-NEXT: and a1, a4, a1
; CHECK-V-NEXT: bnez a5, .LBB48_12 ; CHECK-V-NEXT: bnez a5, .LBB48_13
; CHECK-V-NEXT: .LBB48_11: # %entry
; CHECK-V-NEXT: mv s0, a3
; CHECK-V-NEXT: .LBB48_12: # %entry ; CHECK-V-NEXT: .LBB48_12: # %entry
; CHECK-V-NEXT: beq a1, a2, .LBB48_14 ; CHECK-V-NEXT: mv s0, a3
; CHECK-V-NEXT: # %bb.13: # %entry ; CHECK-V-NEXT: .LBB48_13: # %entry
; CHECK-V-NEXT: beq a1, a2, .LBB48_15
; CHECK-V-NEXT: # %bb.14: # %entry
; CHECK-V-NEXT: slti a1, a1, 0 ; CHECK-V-NEXT: slti a1, a1, 0
; CHECK-V-NEXT: xori a1, a1, 1 ; CHECK-V-NEXT: xori a1, a1, 1
; CHECK-V-NEXT: beqz a1, .LBB48_15 ; CHECK-V-NEXT: beqz a1, .LBB48_16
; CHECK-V-NEXT: j .LBB48_16 ; CHECK-V-NEXT: j .LBB48_17
; CHECK-V-NEXT: .LBB48_14: ; CHECK-V-NEXT: .LBB48_15:
; CHECK-V-NEXT: sltu a1, a3, a0 ; CHECK-V-NEXT: sltu a1, a3, a0
; CHECK-V-NEXT: bnez a1, .LBB48_16 ; CHECK-V-NEXT: bnez a1, .LBB48_17
; CHECK-V-NEXT: .LBB48_15: # %entry
; CHECK-V-NEXT: mv a0, a3
; CHECK-V-NEXT: .LBB48_16: # %entry ; CHECK-V-NEXT: .LBB48_16: # %entry
; CHECK-V-NEXT: mv a0, a3
; CHECK-V-NEXT: .LBB48_17: # %entry
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v9, s0
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: vmv.s.x v9, s0
; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 64 ; CHECK-V-NEXT: addi sp, sp, 64
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s0, -16
; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s1, -24
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixunssfti@plt ; CHECK-V-NEXT: call __fixunssfti@plt
; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vslidedown.vi v8, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixunssfti@plt ; CHECK-V-NEXT: call __fixunssfti@plt
; CHECK-V-NEXT: snez a2, s1
; CHECK-V-NEXT: addi a2, a2, -1
; CHECK-V-NEXT: and a2, a2, s0
; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: snez a1, a1
; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: addi a1, a1, -1
; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: and a0, a1, a0
; CHECK-V-NEXT: snez a1, s1
; CHECK-V-NEXT: addi a1, a1, -1
; CHECK-V-NEXT: and a1, a1, s0
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v9, a2 ; CHECK-V-NEXT: vmv.s.x v8, a1
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v9, a0
; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
; CHECK-V-NEXT: slli a0, a0, 1 ; CHECK-V-NEXT: slli a0, a0, 1
; CHECK-V-NEXT: add sp, sp, a0 ; CHECK-V-NEXT: add sp, sp, a0
; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
; CHECK-V-NEXT: addi sp, sp, 64 ; CHECK-V-NEXT: addi sp, sp, 64
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; CHECK-V-NEXT: sub sp, sp, a0 ; CHECK-V-NEXT: sub sp, sp, a0
; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb ; CHECK-V-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 64 + 2 * vlenb
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 ; CHECK-V-NEXT: vslidedown.vi v9, v8, 1
; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: vfmv.f.s fa0, v9
; CHECK-V-NEXT: call __fixsfti@plt ; CHECK-V-NEXT: call __fixsfti@plt
; CHECK-V-NEXT: mv s1, a0 ; CHECK-V-NEXT: mv s0, a0
; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: mv s1, a1
; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma ; CHECK-V-NEXT: vsetivli zero, 0, e32, mf2, ta, ma
; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: addi a0, sp, 32
; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: vfmv.f.s fa0, v8
; CHECK-V-NEXT: call __fixsfti@plt ; CHECK-V-NEXT: call __fixsfti@plt
; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: mv a2, a1
; CHECK-V-NEXT: blez a1, .LBB50_2 ; CHECK-V-NEXT: blez a1, .LBB50_2
; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: # %bb.1: # %entry
; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: li a2, 1
; CHECK-V-NEXT: .LBB50_2: # %entry ; CHECK-V-NEXT: .LBB50_2: # %entry
; CHECK-V-NEXT: slti a3, s0, 1 ; CHECK-V-NEXT: mv a3, s1
; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: blez s1, .LBB50_4
; CHECK-V-NEXT: and a3, a3, s1 ; CHECK-V-NEXT: # %bb.3: # %entry
; CHECK-V-NEXT: li a3, 1
; CHECK-V-NEXT: .LBB50_4: # %entry
; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: slti a1, a1, 1
; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: neg a1, a1
; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: and a0, a1, a0
; CHECK-V-NEXT: blez s0, .LBB50_4 ; CHECK-V-NEXT: slti a1, s1, 1
; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: neg a1, a1
; CHECK-V-NEXT: li s0, 1 ; CHECK-V-NEXT: and a1, a1, s0
; CHECK-V-NEXT: .LBB50_4: # %entry ; CHECK-V-NEXT: slti a3, a3, 0
; CHECK-V-NEXT: slti a1, s0, 0 ; CHECK-V-NEXT: addi a3, a3, -1
; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: and a1, a3, a1
; CHECK-V-NEXT: and a1, a1, a3
; CHECK-V-NEXT: slti a2, a2, 0 ; CHECK-V-NEXT: slti a2, a2, 0
; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: addi a2, a2, -1
; CHECK-V-NEXT: and a0, a2, a0 ; CHECK-V-NEXT: and a0, a2, a0
; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vmv.s.x v8, a0
; CHECK-V-NEXT: vmv.s.x v9, a1 ; CHECK-V-NEXT: vmv.s.x v9, a1
; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1
; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: csrr a0, vlenb
▲ Show 20 Lines • Show All 403 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f) %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) { define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i16: ; CHECK-LABEL: test_signed_v4f32_v4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f) %x = call <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)
ret <vscale x 4 x i16> %x ret <vscale x 4 x i16> %x
} }
define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) { define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i16: ; CHECK-LABEL: test_signed_v8f32_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f) %x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)
ret <vscale x 8 x i16> %x ret <vscale x 8 x i16> %x
} }
define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) { define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i64: ; CHECK-LABEL: test_signed_v2f32_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f) %x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)
ret <vscale x 2 x i64> %x ret <vscale x 2 x i64> %x
} }
define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) { define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i64: ; CHECK-LABEL: test_signed_v4f32_v4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f) %x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)
ret <vscale x 4 x i64> %x ret <vscale x 4 x i64> %x
} }
; Double ; Double
declare <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double>) declare <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double>)
declare <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double>) declare <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double>)
declare <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double>) declare <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double>)
declare <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f64.nxv4i16(<vscale x 4 x double>) declare <vscale x 4 x i16> @llvm.fptosi.sat.nxv4f64.nxv4i16(<vscale x 4 x double>)
declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f64.nxv8i16(<vscale x 8 x double>) declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f64.nxv8i16(<vscale x 8 x double>)
declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f64.nxv2i64(<vscale x 2 x double>) declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f64.nxv2i64(<vscale x 2 x double>)
declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double>) declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f64.nxv4i64(<vscale x 4 x double>)
define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) { define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i32: ; CHECK-LABEL: test_signed_v2f64_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f) %x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)
ret <vscale x 2 x i32> %x ret <vscale x 2 x i32> %x
} }
define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) { define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i32: ; CHECK-LABEL: test_signed_v4f64_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v12, v8
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f) %x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }
define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) { define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i32: ; CHECK-LABEL: test_signed_v8f64_v8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.x.f.w v16, v8
; CHECK-NEXT: vmerge.vim v8, v16, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v16, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f) %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) { define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i16: ; CHECK-LABEL: test_signed_v4f64_v4i16:
▲ Show 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half>) declare <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half>)
declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half>) declare <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half>)
declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half>) declare <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)
define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) { define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i32: ; CHECK-LABEL: test_signed_v2f16_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f) %x = call <vscale x 2 x i32> @llvm.fptosi.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)
ret <vscale x 2 x i32> %x ret <vscale x 2 x i32> %x
} }
define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) { define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32: ; CHECK-LABEL: test_signed_v4f16_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f) %x = call <vscale x 4 x i32> @llvm.fptosi.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }
define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) { define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32: ; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f) %x = call <vscale x 8 x i32> @llvm.fptosi.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) { define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
Show All 19 Lines; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f) %x = call <vscale x 8 x i16> @llvm.fptosi.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)
ret <vscale x 8 x i16> %x ret <vscale x 8 x i16> %x
} }
define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) { define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i64: ; CHECK-LABEL: test_signed_v2f16_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v9 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f) %x = call <vscale x 2 x i64> @llvm.fptosi.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)
ret <vscale x 2 x i64> %x ret <vscale x 2 x i64> %x
} }
define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) { define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i64: ; CHECK-LABEL: test_signed_v4f16_v4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vfwcvt.f.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v10 ; CHECK-NEXT: vfwcvt.rtz.x.f.v v12, v10
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f) %x = call <vscale x 4 x i64> @llvm.fptosi.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)
ret <vscale x 4 x i64> %x ret <vscale x 4 x i64> %x
} }

llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll

Show First 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f) %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f32.nxv8i32(<vscale x 8 x float> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) { define <vscale x 4 x i16> @test_signed_v4f32_v4i16(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i16: ; CHECK-LABEL: test_signed_v4f32_v4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f) %x = call <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f32.nxv4i16(<vscale x 4 x float> %f)
ret <vscale x 4 x i16> %x ret <vscale x 4 x i16> %x
} }
define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) { define <vscale x 8 x i16> @test_signed_v8f32_v8i16(<vscale x 8 x float> %f) {
; CHECK-LABEL: test_signed_v8f32_v8i16: ; CHECK-LABEL: test_signed_v8f32_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f) %x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f32.nxv8i16(<vscale x 8 x float> %f)
ret <vscale x 8 x i16> %x ret <vscale x 8 x i16> %x
} }
define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) { define <vscale x 2 x i64> @test_signed_v2f32_v2i64(<vscale x 2 x float> %f) {
; CHECK-LABEL: test_signed_v2f32_v2i64: ; CHECK-LABEL: test_signed_v2f32_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f) %x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f32.nxv2i64(<vscale x 2 x float> %f)
ret <vscale x 2 x i64> %x ret <vscale x 2 x i64> %x
} }
define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) { define <vscale x 4 x i64> @test_signed_v4f32_v4i64(<vscale x 4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i64: ; CHECK-LABEL: test_signed_v4f32_v4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f) %x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f32.nxv4i64(<vscale x 4 x float> %f)
ret <vscale x 4 x i64> %x ret <vscale x 4 x i64> %x
} }
; Double ; Double
declare <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double>) declare <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double>)
declare <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double>) declare <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double>)
declare <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double>) declare <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double>)
declare <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f64.nxv4i16(<vscale x 4 x double>) declare <vscale x 4 x i16> @llvm.fptoui.sat.nxv4f64.nxv4i16(<vscale x 4 x double>)
declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f64.nxv8i16(<vscale x 8 x double>) declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f64.nxv8i16(<vscale x 8 x double>)
declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f64.nxv2i64(<vscale x 2 x double>) declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f64.nxv2i64(<vscale x 2 x double>)
declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f64.nxv4i64(<vscale x 4 x double>) declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f64.nxv4i64(<vscale x 4 x double>)
define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) { define <vscale x 2 x i32> @test_signed_v2f64_v2i32(<vscale x 2 x double> %f) {
; CHECK-LABEL: test_signed_v2f64_v2i32: ; CHECK-LABEL: test_signed_v2f64_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v10, v8
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f) %x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f64.nxv2i32(<vscale x 2 x double> %f)
ret <vscale x 2 x i32> %x ret <vscale x 2 x i32> %x
} }
define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) { define <vscale x 4 x i32> @test_signed_v4f64_v4i32(<vscale x 4 x double> %f) {
; CHECK-LABEL: test_signed_v4f64_v4i32: ; CHECK-LABEL: test_signed_v4f64_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v12, v8
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f) %x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f64.nxv4i32(<vscale x 4 x double> %f)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }
define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) { define <vscale x 8 x i32> @test_signed_v8f64_v8i32(<vscale x 8 x double> %f) {
; CHECK-LABEL: test_signed_v8f64_v8i32: ; CHECK-LABEL: test_signed_v8f64_v8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.rtz.xu.f.w v16, v8
; CHECK-NEXT: vmerge.vim v8, v16, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v16, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f) %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f64.nxv8i32(<vscale x 8 x double> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) { define <vscale x 4 x i16> @test_signed_v4f64_v4i16(<vscale x 4 x double> %f) {
; CHECK32-LABEL: test_signed_v4f64_v4i16: ; CHECK32-LABEL: test_signed_v4f64_v4i16:
▲ Show 20 Lines • Show All 93 Lines • ▼ Show 20 Lines
declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half>) declare <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half>)
declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half>) declare <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half>)
declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half>) declare <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half>)
define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) { define <vscale x 2 x i32> @test_signed_v2f16_v2i32(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i32: ; CHECK-LABEL: test_signed_v2f16_v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vmerge.vim v8, v9, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v9, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f) %x = call <vscale x 2 x i32> @llvm.fptoui.sat.nxv2f16.nxv2i32(<vscale x 2 x half> %f)
ret <vscale x 2 x i32> %x ret <vscale x 2 x i32> %x
} }
define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) { define <vscale x 4 x i32> @test_signed_v4f16_v4i32(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i32: ; CHECK-LABEL: test_signed_v4f16_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f) %x = call <vscale x 4 x i32> @llvm.fptoui.sat.nxv4f16.nxv4i32(<vscale x 4 x half> %f)
ret <vscale x 4 x i32> %x ret <vscale x 4 x i32> %x
} }
define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) { define <vscale x 8 x i32> @test_signed_v8f16_v8i32(<vscale x 8 x half> %f) {
; CHECK-LABEL: test_signed_v8f16_v8i32: ; CHECK-LABEL: test_signed_v8f16_v8i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; CHECK-NEXT: vmfne.vv v0, v8, v8 ; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f) %x = call <vscale x 8 x i32> @llvm.fptoui.sat.nxv8f16.nxv8i32(<vscale x 8 x half> %f)
ret <vscale x 8 x i32> %x ret <vscale x 8 x i32> %x
} }
define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) { define <vscale x 4 x i16> @test_signed_v4f16_v4i16(<vscale x 4 x half> %f) {
Show All 19 Lines; CHECK-NEXT: ret
%x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f) %x = call <vscale x 8 x i16> @llvm.fptoui.sat.nxv8f16.nxv8i16(<vscale x 8 x half> %f)
ret <vscale x 8 x i16> %x ret <vscale x 8 x i16> %x
} }
define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) { define <vscale x 2 x i64> @test_signed_v2f16_v2i64(<vscale x 2 x half> %f) {
; CHECK-LABEL: test_signed_v2f16_v2i64: ; CHECK-LABEL: test_signed_v2f16_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v9, v8 ; CHECK-NEXT: vfwcvt.f.f.v v9, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v9 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v10, v9
; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v10, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f) %x = call <vscale x 2 x i64> @llvm.fptoui.sat.nxv2f16.nxv2i64(<vscale x 2 x half> %f)
ret <vscale x 2 x i64> %x ret <vscale x 2 x i64> %x
} }
define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) { define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
; CHECK-LABEL: test_signed_v4f16_v4i64: ; CHECK-LABEL: test_signed_v4f16_v4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vfwcvt.f.f.v v10, v8 ; CHECK-NEXT: vfwcvt.f.f.v v10, v8
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v10 ; CHECK-NEXT: vfwcvt.rtz.xu.f.v v12, v10
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; CHECK-NEXT: vmfne.vv v0, v8, v8
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vmerge.vim v8, v12, 0, v0 ; CHECK-NEXT: vmerge.vim v8, v12, 0, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f) %x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)
ret <vscale x 4 x i64> %x ret <vscale x 4 x i64> %x
} }

llvm/test/CodeGen/RISCV/rvv/fshr-fshl-vp.ll

Show First 20 Lines • Show All 960 Lines • ▼ Show 20 Lines
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 56 ; CHECK-NEXT: li a3, 56
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: slli a1, a1, 5
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 40 ; CHECK-NEXT: li a3, 40
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: slli a3, a1, 3 ; CHECK-NEXT: slli a3, a1, 3
; CHECK-NEXT: add a5, a0, a3 ; CHECK-NEXT: add a5, a0, a3
; CHECK-NEXT: vl8re64.v v8, (a5) ; CHECK-NEXT: vl8re64.v v8, (a5)
; CHECK-NEXT: csrr a5, vlenb ; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: slli a5, a5, 4 ; CHECK-NEXT: slli a5, a5, 4
; CHECK-NEXT: add a5, sp, a5 ; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16 ; CHECK-NEXT: addi a5, a5, 16
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
; CHECK-NEXT: sub a5, a4, a1 ; CHECK-NEXT: srli a5, a1, 3
; CHECK-NEXT: sltu a6, a4, a5 ; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a5
; CHECK-NEXT: add a5, a2, a3
; CHECK-NEXT: sub a3, a4, a1
; CHECK-NEXT: sltu a6, a4, a3
; CHECK-NEXT: addi a6, a6, -1 ; CHECK-NEXT: addi a6, a6, -1
; CHECK-NEXT: and a5, a6, a5 ; CHECK-NEXT: and a6, a6, a3
; CHECK-NEXT: add a3, a2, a3 ; CHECK-NEXT: li a3, 63
; CHECK-NEXT: vl8re64.v v8, (a3) ; CHECK-NEXT: vl8re64.v v8, (a5)
; CHECK-NEXT: addi a3, sp, 16 ; CHECK-NEXT: addi a5, sp, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
; CHECK-NEXT: vl8re64.v v16, (a0) ; CHECK-NEXT: vl8re64.v v16, (a0)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5 ; CHECK-NEXT: li a5, 24
; CHECK-NEXT: mul a0, a0, a5
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vl8re64.v v16, (a2) ; CHECK-NEXT: vl8re64.v v16, (a2)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a2, 48 ; CHECK-NEXT: li a2, 48
; CHECK-NEXT: mul a0, a0, a2 ; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: li a0, 63 ; CHECK-NEXT: vand.vx v16, v8, a3, v0.t
; CHECK-NEXT: vnot.v v16, v8, v0.t ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: mul a2, a2, a3 ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vsrl.vv v16, v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t ; CHECK-NEXT: vsll.vi v16, v16, 1, v0.t
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: mul a2, a2, a3 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vsll.vv v16, v8, v16, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: bltu a4, a1, .LBB46_2 ; CHECK-NEXT: bltu a4, a1, .LBB46_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a4, a1 ; CHECK-NEXT: mv a4, a1
; CHECK-NEXT: .LBB46_2: ; CHECK-NEXT: .LBB46_2:
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: li a2, 48 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: mul a1, a1, a2 ; CHECK-NEXT: li a1, 48
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: li a1, 24
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a1, a1, 5 ; CHECK-NEXT: li a1, 24
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: li a2, 48 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: mul a1, a1, a2 ; CHECK-NEXT: li a1, 48
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vnot.v v16, v8, v0.t ; CHECK-NEXT: vnot.v v16, v8, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t ; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 40 ; CHECK-NEXT: li a1, 40
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t ; CHECK-NEXT: vsll.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t ; CHECK-NEXT: vsll.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5 ; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t ; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24 ; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 56 ; CHECK-NEXT: li a1, 56
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
Show All 10 Lines
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 56 ; CHECK-NEXT: li a3, 56
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb
; CHECK-NEXT: vmv1r.v v24, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 24 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 40 ; CHECK-NEXT: li a3, 40
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a3
; CHECK-NEXT: slli a3, a1, 3 ; CHECK-NEXT: slli a3, a1, 3
; CHECK-NEXT: add a5, a0, a3 ; CHECK-NEXT: add a5, a0, a3
; CHECK-NEXT: vl8re64.v v8, (a5) ; CHECK-NEXT: vl8re64.v v8, (a5)
; CHECK-NEXT: csrr a5, vlenb ; CHECK-NEXT: csrr a5, vlenb
; CHECK-NEXT: slli a5, a5, 4 ; CHECK-NEXT: li a6, 24
; CHECK-NEXT: mul a5, a5, a6
; CHECK-NEXT: add a5, sp, a5 ; CHECK-NEXT: add a5, sp, a5
; CHECK-NEXT: addi a5, a5, 16 ; CHECK-NEXT: addi a5, a5, 16
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
; CHECK-NEXT: sub a5, a4, a1 ; CHECK-NEXT: srli a5, a1, 3
; CHECK-NEXT: sltu a6, a4, a5 ; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a5
; CHECK-NEXT: add a5, a2, a3
; CHECK-NEXT: sub a3, a4, a1
; CHECK-NEXT: sltu a6, a4, a3
; CHECK-NEXT: addi a6, a6, -1 ; CHECK-NEXT: addi a6, a6, -1
; CHECK-NEXT: and a5, a6, a5 ; CHECK-NEXT: and a6, a6, a3
; CHECK-NEXT: add a3, a2, a3 ; CHECK-NEXT: li a3, 63
; CHECK-NEXT: vl8re64.v v8, (a3) ; CHECK-NEXT: vl8re64.v v8, (a5)
; CHECK-NEXT: addi a3, sp, 16 ; CHECK-NEXT: addi a5, sp, 16
; CHECK-NEXT: vs8r.v v8, (a3) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
; CHECK-NEXT: vl8re64.v v16, (a0) ; CHECK-NEXT: vl8re64.v v16, (a0)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5 ; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vl8re64.v v16, (a2) ; CHECK-NEXT: vl8re64.v v16, (a2)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a2, 48 ; CHECK-NEXT: li a2, 48
; CHECK-NEXT: mul a0, a0, a2 ; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli zero, a5, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: li a0, 63 ; CHECK-NEXT: vand.vx v16, v8, a3, v0.t
; CHECK-NEXT: vnot.v v16, v8, v0.t ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: slli a2, a2, 4 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vsll.vv v16, v16, v8, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vnot.v v8, v8, v0.t
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a2, 24
; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t ; CHECK-NEXT: vsrl.vi v16, v16, 1, v0.t
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: vsrl.vv v8, v16, v8, v0.t
; CHECK-NEXT: slli a2, a2, 4 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: li a2, 24
; CHECK-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: slli a2, a2, 4 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vsrl.vv v16, v8, v16, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vsll.vv v8, v16, v8, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li a3, 24
; CHECK-NEXT: mul a2, a2, a3
; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: bltu a4, a1, .LBB47_2 ; CHECK-NEXT: bltu a4, a1, .LBB47_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a4, a1 ; CHECK-NEXT: mv a4, a1
; CHECK-NEXT: .LBB47_2: ; CHECK-NEXT: .LBB47_2:
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: li a2, 48 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: mul a1, a1, a2 ; CHECK-NEXT: li a1, 48
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vand.vx v16, v8, a0, v0.t ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: vand.vx v16, v8, a3, v0.t
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: li a2, 40 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: mul a1, a1, a2 ; CHECK-NEXT: li a1, 40
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vsll.vv v16, v16, v8, v0.t ; CHECK-NEXT: vsll.vv v16, v16, v8, v0.t
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a2, 40 ; CHECK-NEXT: li a1, 40
; CHECK-NEXT: mul a1, a1, a2 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a2, 48 ; CHECK-NEXT: li a1, 48
; CHECK-NEXT: mul a1, a1, a2 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vnot.v v16, v8, v0.t ; CHECK-NEXT: vnot.v v16, v8, v0.t
; CHECK-NEXT: vand.vx v16, v16, a0, v0.t ; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5 ; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vsrl.vi v8, v8, 1, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 1, v0.t
; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: vsrl.vv v8, v8, v16, v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
▲ Show 20 Lines • Show All 69 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel | FileCheck %s
; Make sure we don't create a COPY instruction for IMPLICIT_DEF. ; Make sure we don't create a COPY instruction for IMPLICIT_DEF.
define <vscale x 8 x i64> @vpload_nxv8i64(<vscale x 8 x i64>* %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) #1 { define <vscale x 8 x i64> @vpload_nxv8i64(<vscale x 8 x i64>* %ptr, <vscale x 8 x i1> %m, i32 zeroext %evl) #1 {
; CHECK-LABEL: name: vpload_nxv8i64 ; CHECK-LABEL: name: vpload_nxv8i64
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $x10, $v0, $x11 ; CHECK-NEXT: liveins: $x10, $v0, $x11
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: $v0 = COPY [[COPY1]] ; CHECK-NEXT: $v0 = COPY [[COPY1]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrm8nov0 = IMPLICIT_DEF ; CHECK-NEXT: [[PseudoVLE64_V_M8_MASK:%[0-9]+]]:vrm8nov0 = PseudoVLE64_V_M8_MASK $noreg, [[COPY2]], $v0, [[COPY]], 6 /* e64 */, 1 /* ta, mu */ :: (load unknown-size from %ir.ptr, align 64)
; CHECK-NEXT: [[PseudoVLE64_V_M8_MASK:%[0-9]+]]:vrm8nov0 = PseudoVLE64_V_M8_MASK [[DEF]], [[COPY2]], $v0, [[COPY]], 6 /* e64 */, 1 /* ta, mu */ :: (load unknown-size from %ir.ptr, align 64)
; CHECK-NEXT: $v8m8 = COPY [[PseudoVLE64_V_M8_MASK]] ; CHECK-NEXT: $v8m8 = COPY [[PseudoVLE64_V_M8_MASK]]
; CHECK-NEXT: PseudoRET implicit $v8m8 ; CHECK-NEXT: PseudoRET implicit $v8m8
%load = call <vscale x 8 x i64> @llvm.vp.load.nxv8i64.p0(<vscale x 8 x i64>* %ptr, <vscale x 8 x i1> %m, i32 %evl) %load = call <vscale x 8 x i64> @llvm.vp.load.nxv8i64.p0(<vscale x 8 x i64>* %ptr, <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i64> %load ret <vscale x 8 x i64> %load
} }
declare <vscale x 8 x i64> @llvm.vp.load.nxv8i64.p0(<vscale x 8 x i64>*, <vscale x 8 x i1>, i32) declare <vscale x 8 x i64> @llvm.vp.load.nxv8i64.p0(<vscale x 8 x i64>*, <vscale x 8 x i1>, i32)

llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll

Show First 20 Lines • Show All 432 Lines • ▼ Show 20 Lines
} }
define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) { define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) {
; CHECK-LABEL: insert_nxv4i1_nxv1i1_2: ; CHECK-LABEL: insert_nxv4i1_nxv1i1_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vmv.v.i v9, 0
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3 ; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v9, v8, a0 ; CHECK-NEXT: vslideup.vx v9, v8, a0
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = call <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 2) %vec = call <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 2)
ret <vscale x 4 x i1> %vec ret <vscale x 4 x i1> %vec
} }
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/insertelt-fp.ll

Show All 22 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 1 x half> %v, half %elt, i32 3
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 zeroext %idx) { define <vscale x 1 x half> @insertelt_nxv1f16_idx(<vscale x 1 x half> %v, half %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv1f16_idx: ; CHECK-LABEL: insertelt_nxv1f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e16, mf4, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) {
Show All 15 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 2 x half> %v, half %elt, i32 3
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 zeroext %idx) { define <vscale x 2 x half> @insertelt_nxv2f16_idx(<vscale x 2 x half> %v, half %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv2f16_idx: ; CHECK-LABEL: insertelt_nxv2f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) {
Show All 15 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 3 %r = insertelement <vscale x 4 x half> %v, half %elt, i32 3
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 zeroext %idx) { define <vscale x 4 x half> @insertelt_nxv4f16_idx(<vscale x 4 x half> %v, half %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv4f16_idx: ; CHECK-LABEL: insertelt_nxv4f16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) {
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 1 x float> %v, float %elt, i32 3
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 1 x float> @insertelt_nxv1f32_idx(<vscale x 1 x float> %v, float %elt, i32 zeroext %idx) { define <vscale x 1 x float> @insertelt_nxv1f32_idx(<vscale x 1 x float> %v, float %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv1f32_idx: ; CHECK-LABEL: insertelt_nxv1f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e32, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) { define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) {
Show All 15 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 3 %r = insertelement <vscale x 2 x float> %v, float %elt, i32 3
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_idx(<vscale x 2 x float> %v, float %elt, i32 zeroext %idx) { define <vscale x 2 x float> @insertelt_nxv2f32_idx(<vscale x 2 x float> %v, float %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv2f32_idx: ; CHECK-LABEL: insertelt_nxv2f32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) { define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) {
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 3 %r = insertelement <vscale x 1 x double> %v, double %elt, i32 3
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 1 x double> @insertelt_nxv1f64_idx(<vscale x 1 x double> %v, double %elt, i32 zeroext %idx) { define <vscale x 1 x double> @insertelt_nxv1f64_idx(<vscale x 1 x double> %v, double %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv1f64_idx: ; CHECK-LABEL: insertelt_nxv1f64_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: addi a1, a0, 1 ; CHECK-NEXT: addi a1, a0, 1
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: vslideup.vx v8, v9, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) { define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) {
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll

Show All 19 Lines
} }
define <vscale x 1 x i1> @insertelt_idx_nxv1i1(<vscale x 1 x i1> %x, i1 %elt, i64 %idx) { define <vscale x 1 x i1> @insertelt_idx_nxv1i1(<vscale x 1 x i1> %x, i1 %elt, i64 %idx) {
; CHECK-LABEL: insertelt_idx_nxv1i1: ; CHECK-LABEL: insertelt_idx_nxv1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf8, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 1 x i1> %x, i1 %elt, i64 %idx %y = insertelement <vscale x 1 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 1 x i1> %y ret <vscale x 1 x i1> %y
} }
Show All 16 Lines
} }
define <vscale x 2 x i1> @insertelt_idx_nxv2i1(<vscale x 2 x i1> %x, i1 %elt, i64 %idx) { define <vscale x 2 x i1> @insertelt_idx_nxv2i1(<vscale x 2 x i1> %x, i1 %elt, i64 %idx) {
; CHECK-LABEL: insertelt_idx_nxv2i1: ; CHECK-LABEL: insertelt_idx_nxv2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf4, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 2 x i1> %x, i1 %elt, i64 %idx %y = insertelement <vscale x 2 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 2 x i1> %y ret <vscale x 2 x i1> %y
} }
Show All 16 Lines
} }
define <vscale x 4 x i1> @insertelt_idx_nxv4i1(<vscale x 4 x i1> %x, i1 %elt, i64 %idx) { define <vscale x 4 x i1> @insertelt_idx_nxv4i1(<vscale x 4 x i1> %x, i1 %elt, i64 %idx) {
; CHECK-LABEL: insertelt_idx_nxv4i1: ; CHECK-LABEL: insertelt_idx_nxv4i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf2, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 4 x i1> %x, i1 %elt, i64 %idx %y = insertelement <vscale x 4 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 4 x i1> %y ret <vscale x 4 x i1> %y
} }
Show All 16 Lines
} }
define <vscale x 8 x i1> @insertelt_idx_nxv8i1(<vscale x 8 x i1> %x, i1 %elt, i64 %idx) { define <vscale x 8 x i1> @insertelt_idx_nxv8i1(<vscale x 8 x i1> %x, i1 %elt, i64 %idx) {
; CHECK-LABEL: insertelt_idx_nxv8i1: ; CHECK-LABEL: insertelt_idx_nxv8i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma ; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, m1, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vand.vi v8, v8, 1
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <vscale x 8 x i1> %x, i1 %elt, i64 %idx %y = insertelement <vscale x 8 x i1> %x, i1 %elt, i64 %idx
ret <vscale x 8 x i1> %y ret <vscale x 8 x i1> %y
} }
▲ Show 20 Lines • Show All 105 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

Show All 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv1i8_idx: ; CHECK-LABEL: insertelt_nxv1i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf8, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) { define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i8_0: ; CHECK-LABEL: insertelt_nxv2i8_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv2i8_idx: ; CHECK-LABEL: insertelt_nxv2i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf4, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) { define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i8_0: ; CHECK-LABEL: insertelt_nxv4i8_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv4i8_idx: ; CHECK-LABEL: insertelt_nxv4i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf2, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) { define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i8_0: ; CHECK-LABEL: insertelt_nxv8i8_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 signext %idx) { define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv8i8_idx: ; CHECK-LABEL: insertelt_nxv8i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, m1, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) { define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i8_0: ; CHECK-LABEL: insertelt_nxv16i8_0:
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv1i16_idx: ; CHECK-LABEL: insertelt_nxv1i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e16, mf4, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) { define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i16_0: ; CHECK-LABEL: insertelt_nxv2i16_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv2i16_idx: ; CHECK-LABEL: insertelt_nxv2i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e16, mf2, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) { define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i16_0: ; CHECK-LABEL: insertelt_nxv4i16_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 signext %idx) { define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 signext %idx) {
; CHECK-LABEL: insertelt_nxv4i16_idx: ; CHECK-LABEL: insertelt_nxv4i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e16, m1, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) { define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i16_0: ; CHECK-LABEL: insertelt_nxv8i16_0:
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %elt, i32 %idx) { define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv1i32_idx: ; CHECK-LABEL: insertelt_nxv1i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e32, mf2, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 %elt) { define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv2i32_0: ; CHECK-LABEL: insertelt_nxv2i32_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %elt, i32 %idx) { define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 %elt, i32 %idx) {
; CHECK-LABEL: insertelt_nxv2i32_idx: ; CHECK-LABEL: insertelt_nxv2i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e32, m1, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 %elt) { define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv4i32_0: ; CHECK-LABEL: insertelt_nxv4i32_0:
▲ Show 20 Lines • Show All 326 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll

Show All 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 3
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 zeroext %idx) { define <vscale x 1 x i8> @insertelt_nxv1i8_idx(<vscale x 1 x i8> %v, i8 signext %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv1i8_idx: ; CHECK-LABEL: insertelt_nxv1i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf8, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) { define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i8_0: ; CHECK-LABEL: insertelt_nxv2i8_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 3
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 zeroext %idx) { define <vscale x 2 x i8> @insertelt_nxv2i8_idx(<vscale x 2 x i8> %v, i8 signext %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv2i8_idx: ; CHECK-LABEL: insertelt_nxv2i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf4, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) { define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i8_0: ; CHECK-LABEL: insertelt_nxv4i8_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 3
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 zeroext %idx) { define <vscale x 4 x i8> @insertelt_nxv4i8_idx(<vscale x 4 x i8> %v, i8 signext %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv4i8_idx: ; CHECK-LABEL: insertelt_nxv4i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, mf2, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) { define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i8_0: ; CHECK-LABEL: insertelt_nxv8i8_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3 %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 3
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 zeroext %idx) { define <vscale x 8 x i8> @insertelt_nxv8i8_idx(<vscale x 8 x i8> %v, i8 signext %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv8i8_idx: ; CHECK-LABEL: insertelt_nxv8i8_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e8, m1, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e8, m1, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) { define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i8_0: ; CHECK-LABEL: insertelt_nxv16i8_0:
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 3
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 zeroext %idx) { define <vscale x 1 x i16> @insertelt_nxv1i16_idx(<vscale x 1 x i16> %v, i16 signext %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv1i16_idx: ; CHECK-LABEL: insertelt_nxv1i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e16, mf4, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) { define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i16_0: ; CHECK-LABEL: insertelt_nxv2i16_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 3
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 zeroext %idx) { define <vscale x 2 x i16> @insertelt_nxv2i16_idx(<vscale x 2 x i16> %v, i16 signext %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv2i16_idx: ; CHECK-LABEL: insertelt_nxv2i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e16, mf2, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) { define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i16_0: ; CHECK-LABEL: insertelt_nxv4i16_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3 %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 3
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 zeroext %idx) { define <vscale x 4 x i16> @insertelt_nxv4i16_idx(<vscale x 4 x i16> %v, i16 signext %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv4i16_idx: ; CHECK-LABEL: insertelt_nxv4i16_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e16, m1, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) { define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i16_0: ; CHECK-LABEL: insertelt_nxv8i16_0:
▲ Show 20 Lines • Show All 116 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 3
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 signext %elt, i32 zeroext %idx) { define <vscale x 1 x i32> @insertelt_nxv1i32_idx(<vscale x 1 x i32> %v, i32 signext %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv1i32_idx: ; CHECK-LABEL: insertelt_nxv1i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e32, mf2, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e32, mf2, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 signext %elt) { define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i32_0: ; CHECK-LABEL: insertelt_nxv2i32_0:
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3 %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 3
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 signext %elt, i32 zeroext %idx) { define <vscale x 2 x i32> @insertelt_nxv2i32_idx(<vscale x 2 x i32> %v, i32 signext %elt, i32 zeroext %idx) {
; CHECK-LABEL: insertelt_nxv2i32_idx: ; CHECK-LABEL: insertelt_nxv2i32_idx:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, ma ; CHECK-NEXT: addi a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v9, a0 ; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: addi a0, a1, 1 ; CHECK-NEXT: vsetvli zero, a2, e32, m1, tu, ma
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 signext %elt) { define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i32_0: ; CHECK-LABEL: insertelt_nxv4i32_0:
▲ Show 20 Lines • Show All 243 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/memset-inline.ll

Show First 20 Lines • Show All 163 Lines • ▼ Show 20 Lines
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 16, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 16, i1 0)
ret void ret void
} }
define void @memset_32(ptr %a, i8 %value) nounwind { define void @memset_32(ptr %a, i8 %value) nounwind {
; RV32-BOTH-LABEL: memset_32: ; RV32-BOTH-LABEL: memset_32:
; RV32-BOTH: # %bb.0: ; RV32-BOTH: # %bb.0:
; RV32-BOTH-NEXT: addi a2, a0, 16
; RV32-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-BOTH-NEXT: vmv.v.x v8, a1 ; RV32-BOTH-NEXT: vmv.v.x v8, a1
; RV32-BOTH-NEXT: addi a1, a0, 16 ; RV32-BOTH-NEXT: vse8.v v8, (a2)
; RV32-BOTH-NEXT: vse8.v v8, (a1)
; RV32-BOTH-NEXT: vse8.v v8, (a0) ; RV32-BOTH-NEXT: vse8.v v8, (a0)
; RV32-BOTH-NEXT: ret ; RV32-BOTH-NEXT: ret
; ;
; RV64-BOTH-LABEL: memset_32: ; RV64-BOTH-LABEL: memset_32:
; RV64-BOTH: # %bb.0: ; RV64-BOTH: # %bb.0:
; RV64-BOTH-NEXT: addi a2, a0, 16
; RV64-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-BOTH-NEXT: vmv.v.x v8, a1 ; RV64-BOTH-NEXT: vmv.v.x v8, a1
; RV64-BOTH-NEXT: addi a1, a0, 16 ; RV64-BOTH-NEXT: vse8.v v8, (a2)
; RV64-BOTH-NEXT: vse8.v v8, (a1)
; RV64-BOTH-NEXT: vse8.v v8, (a0) ; RV64-BOTH-NEXT: vse8.v v8, (a0)
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 32, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 32, i1 0)
ret void ret void
} }
define void @memset_64(ptr %a, i8 %value) nounwind { define void @memset_64(ptr %a, i8 %value) nounwind {
; RV32-BOTH-LABEL: memset_64: ; RV32-BOTH-LABEL: memset_64:
; RV32-BOTH: # %bb.0: ; RV32-BOTH: # %bb.0:
; RV32-BOTH-NEXT: addi a2, a0, 48
; RV32-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-BOTH-NEXT: vmv.v.x v8, a1 ; RV32-BOTH-NEXT: vmv.v.x v8, a1
; RV32-BOTH-NEXT: addi a1, a0, 48 ; RV32-BOTH-NEXT: vse8.v v8, (a2)
; RV32-BOTH-NEXT: vse8.v v8, (a1)
; RV32-BOTH-NEXT: addi a1, a0, 32 ; RV32-BOTH-NEXT: addi a1, a0, 32
; RV32-BOTH-NEXT: vse8.v v8, (a1) ; RV32-BOTH-NEXT: vse8.v v8, (a1)
; RV32-BOTH-NEXT: addi a1, a0, 16 ; RV32-BOTH-NEXT: addi a1, a0, 16
; RV32-BOTH-NEXT: vse8.v v8, (a1) ; RV32-BOTH-NEXT: vse8.v v8, (a1)
; RV32-BOTH-NEXT: vse8.v v8, (a0) ; RV32-BOTH-NEXT: vse8.v v8, (a0)
; RV32-BOTH-NEXT: ret ; RV32-BOTH-NEXT: ret
; ;
; RV64-BOTH-LABEL: memset_64: ; RV64-BOTH-LABEL: memset_64:
; RV64-BOTH: # %bb.0: ; RV64-BOTH: # %bb.0:
; RV64-BOTH-NEXT: addi a2, a0, 48
; RV64-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-BOTH-NEXT: vmv.v.x v8, a1 ; RV64-BOTH-NEXT: vmv.v.x v8, a1
; RV64-BOTH-NEXT: addi a1, a0, 48 ; RV64-BOTH-NEXT: vse8.v v8, (a2)
; RV64-BOTH-NEXT: vse8.v v8, (a1)
; RV64-BOTH-NEXT: addi a1, a0, 32 ; RV64-BOTH-NEXT: addi a1, a0, 32
; RV64-BOTH-NEXT: vse8.v v8, (a1) ; RV64-BOTH-NEXT: vse8.v v8, (a1)
; RV64-BOTH-NEXT: addi a1, a0, 16 ; RV64-BOTH-NEXT: addi a1, a0, 16
; RV64-BOTH-NEXT: vse8.v v8, (a1) ; RV64-BOTH-NEXT: vse8.v v8, (a1)
; RV64-BOTH-NEXT: vse8.v v8, (a0) ; RV64-BOTH-NEXT: vse8.v v8, (a0)
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 64, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 %value, i64 64, i1 0)
ret void ret void
▲ Show 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr align 16 %a, i8 %value, i64 16, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr align 16 %a, i8 %value, i64 16, i1 0)
ret void ret void
} }
define void @aligned_memset_32(ptr align 32 %a, i8 %value) nounwind { define void @aligned_memset_32(ptr align 32 %a, i8 %value) nounwind {
; RV32-BOTH-LABEL: aligned_memset_32: ; RV32-BOTH-LABEL: aligned_memset_32:
; RV32-BOTH: # %bb.0: ; RV32-BOTH: # %bb.0:
; RV32-BOTH-NEXT: addi a2, a0, 16
; RV32-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-BOTH-NEXT: vmv.v.x v8, a1 ; RV32-BOTH-NEXT: vmv.v.x v8, a1
; RV32-BOTH-NEXT: addi a1, a0, 16 ; RV32-BOTH-NEXT: vse8.v v8, (a2)
; RV32-BOTH-NEXT: vse8.v v8, (a1)
; RV32-BOTH-NEXT: vse8.v v8, (a0) ; RV32-BOTH-NEXT: vse8.v v8, (a0)
; RV32-BOTH-NEXT: ret ; RV32-BOTH-NEXT: ret
; ;
; RV64-BOTH-LABEL: aligned_memset_32: ; RV64-BOTH-LABEL: aligned_memset_32:
; RV64-BOTH: # %bb.0: ; RV64-BOTH: # %bb.0:
; RV64-BOTH-NEXT: addi a2, a0, 16
; RV64-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-BOTH-NEXT: vmv.v.x v8, a1 ; RV64-BOTH-NEXT: vmv.v.x v8, a1
; RV64-BOTH-NEXT: addi a1, a0, 16 ; RV64-BOTH-NEXT: vse8.v v8, (a2)
; RV64-BOTH-NEXT: vse8.v v8, (a1)
; RV64-BOTH-NEXT: vse8.v v8, (a0) ; RV64-BOTH-NEXT: vse8.v v8, (a0)
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr align 32 %a, i8 %value, i64 32, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr align 32 %a, i8 %value, i64 32, i1 0)
ret void ret void
} }
define void @aligned_memset_64(ptr align 64 %a, i8 %value) nounwind { define void @aligned_memset_64(ptr align 64 %a, i8 %value) nounwind {
; RV32-BOTH-LABEL: aligned_memset_64: ; RV32-BOTH-LABEL: aligned_memset_64:
; RV32-BOTH: # %bb.0: ; RV32-BOTH: # %bb.0:
; RV32-BOTH-NEXT: addi a2, a0, 48
; RV32-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-BOTH-NEXT: vmv.v.x v8, a1 ; RV32-BOTH-NEXT: vmv.v.x v8, a1
; RV32-BOTH-NEXT: addi a1, a0, 48 ; RV32-BOTH-NEXT: vse8.v v8, (a2)
; RV32-BOTH-NEXT: vse8.v v8, (a1)
; RV32-BOTH-NEXT: addi a1, a0, 32 ; RV32-BOTH-NEXT: addi a1, a0, 32
; RV32-BOTH-NEXT: vse8.v v8, (a1) ; RV32-BOTH-NEXT: vse8.v v8, (a1)
; RV32-BOTH-NEXT: addi a1, a0, 16 ; RV32-BOTH-NEXT: addi a1, a0, 16
; RV32-BOTH-NEXT: vse8.v v8, (a1) ; RV32-BOTH-NEXT: vse8.v v8, (a1)
; RV32-BOTH-NEXT: vse8.v v8, (a0) ; RV32-BOTH-NEXT: vse8.v v8, (a0)
; RV32-BOTH-NEXT: ret ; RV32-BOTH-NEXT: ret
; ;
; RV64-BOTH-LABEL: aligned_memset_64: ; RV64-BOTH-LABEL: aligned_memset_64:
; RV64-BOTH: # %bb.0: ; RV64-BOTH: # %bb.0:
; RV64-BOTH-NEXT: addi a2, a0, 48
; RV64-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-BOTH-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-BOTH-NEXT: vmv.v.x v8, a1 ; RV64-BOTH-NEXT: vmv.v.x v8, a1
; RV64-BOTH-NEXT: addi a1, a0, 48 ; RV64-BOTH-NEXT: vse8.v v8, (a2)
; RV64-BOTH-NEXT: vse8.v v8, (a1)
; RV64-BOTH-NEXT: addi a1, a0, 32 ; RV64-BOTH-NEXT: addi a1, a0, 32
; RV64-BOTH-NEXT: vse8.v v8, (a1) ; RV64-BOTH-NEXT: vse8.v v8, (a1)
; RV64-BOTH-NEXT: addi a1, a0, 16 ; RV64-BOTH-NEXT: addi a1, a0, 16
; RV64-BOTH-NEXT: vse8.v v8, (a1) ; RV64-BOTH-NEXT: vse8.v v8, (a1)
; RV64-BOTH-NEXT: vse8.v v8, (a0) ; RV64-BOTH-NEXT: vse8.v v8, (a0)
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 %value, i64 64, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 %value, i64 64, i1 0)
ret void ret void
▲ Show 20 Lines • Show All 140 Lines • ▼ Show 20 Lines
; RV64-FAST-NEXT: ret ; RV64-FAST-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 16, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 16, i1 0)
ret void ret void
} }
define void @bzero_32(ptr %a) nounwind { define void @bzero_32(ptr %a) nounwind {
; RV32-LABEL: bzero_32: ; RV32-LABEL: bzero_32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: addi a1, a0, 16
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.i v8, 0 ; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vse8.v v8, (a1) ; RV32-NEXT: vse8.v v8, (a0)
; RV32-NEXT: addi a0, a0, 16
; RV32-NEXT: vse8.v v8, (a0) ; RV32-NEXT: vse8.v v8, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: bzero_32: ; RV64-LABEL: bzero_32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi a1, a0, 16
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: vse8.v v8, (a1) ; RV64-NEXT: vse8.v v8, (a0)
; RV64-NEXT: addi a0, a0, 16
; RV64-NEXT: vse8.v v8, (a0) ; RV64-NEXT: vse8.v v8, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
; ;
; RV32-FAST-LABEL: bzero_32: ; RV32-FAST-LABEL: bzero_32:
; RV32-FAST: # %bb.0: ; RV32-FAST: # %bb.0:
; RV32-FAST-NEXT: addi a1, a0, 16
; RV32-FAST-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-FAST-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-FAST-NEXT: vmv.v.i v8, 0 ; RV32-FAST-NEXT: vmv.v.i v8, 0
; RV32-FAST-NEXT: vse64.v v8, (a1) ; RV32-FAST-NEXT: vse64.v v8, (a0)
; RV32-FAST-NEXT: addi a0, a0, 16
; RV32-FAST-NEXT: vse64.v v8, (a0) ; RV32-FAST-NEXT: vse64.v v8, (a0)
; RV32-FAST-NEXT: ret ; RV32-FAST-NEXT: ret
; ;
; RV64-FAST-LABEL: bzero_32: ; RV64-FAST-LABEL: bzero_32:
; RV64-FAST: # %bb.0: ; RV64-FAST: # %bb.0:
; RV64-FAST-NEXT: addi a1, a0, 16
; RV64-FAST-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-FAST-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-FAST-NEXT: vmv.v.i v8, 0 ; RV64-FAST-NEXT: vmv.v.i v8, 0
; RV64-FAST-NEXT: vse64.v v8, (a1) ; RV64-FAST-NEXT: vse64.v v8, (a0)
; RV64-FAST-NEXT: addi a0, a0, 16
; RV64-FAST-NEXT: vse64.v v8, (a0) ; RV64-FAST-NEXT: vse64.v v8, (a0)
; RV64-FAST-NEXT: ret ; RV64-FAST-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 32, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr %a, i8 0, i64 32, i1 0)
ret void ret void
} }
define void @bzero_64(ptr %a) nounwind { define void @bzero_64(ptr %a) nounwind {
; RV32-LABEL: bzero_64: ; RV32-LABEL: bzero_64:
▲ Show 20 Lines • Show All 91 Lines • ▼ Show 20 Lines
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr align 16 %a, i8 0, i64 16, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr align 16 %a, i8 0, i64 16, i1 0)
ret void ret void
} }
define void @aligned_bzero_32(ptr %a) nounwind { define void @aligned_bzero_32(ptr %a) nounwind {
; RV32-BOTH-LABEL: aligned_bzero_32: ; RV32-BOTH-LABEL: aligned_bzero_32:
; RV32-BOTH: # %bb.0: ; RV32-BOTH: # %bb.0:
; RV32-BOTH-NEXT: addi a1, a0, 16
; RV32-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-BOTH-NEXT: vmv.v.i v8, 0 ; RV32-BOTH-NEXT: vmv.v.i v8, 0
; RV32-BOTH-NEXT: vse64.v v8, (a1) ; RV32-BOTH-NEXT: vse64.v v8, (a0)
; RV32-BOTH-NEXT: addi a0, a0, 16
; RV32-BOTH-NEXT: vse64.v v8, (a0) ; RV32-BOTH-NEXT: vse64.v v8, (a0)
; RV32-BOTH-NEXT: ret ; RV32-BOTH-NEXT: ret
; ;
; RV64-BOTH-LABEL: aligned_bzero_32: ; RV64-BOTH-LABEL: aligned_bzero_32:
; RV64-BOTH: # %bb.0: ; RV64-BOTH: # %bb.0:
; RV64-BOTH-NEXT: addi a1, a0, 16
; RV64-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-BOTH-NEXT: vmv.v.i v8, 0 ; RV64-BOTH-NEXT: vmv.v.i v8, 0
; RV64-BOTH-NEXT: vse64.v v8, (a1) ; RV64-BOTH-NEXT: vse64.v v8, (a0)
; RV64-BOTH-NEXT: addi a0, a0, 16
; RV64-BOTH-NEXT: vse64.v v8, (a0) ; RV64-BOTH-NEXT: vse64.v v8, (a0)
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr align 32 %a, i8 0, i64 32, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr align 32 %a, i8 0, i64 32, i1 0)
ret void ret void
} }
define void @aligned_bzero_64(ptr %a) nounwind { define void @aligned_bzero_64(ptr %a) nounwind {
; RV32-BOTH-LABEL: aligned_bzero_64: ; RV32-BOTH-LABEL: aligned_bzero_64:
Show All 31 Lines
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 0, i64 66, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 0, i64 66, i1 0)
ret void ret void
} }
define void @aligned_bzero_96(ptr %a) nounwind { define void @aligned_bzero_96(ptr %a) nounwind {
; RV32-BOTH-LABEL: aligned_bzero_96: ; RV32-BOTH-LABEL: aligned_bzero_96:
; RV32-BOTH: # %bb.0: ; RV32-BOTH: # %bb.0:
; RV32-BOTH-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-BOTH-NEXT: vmv.v.i v8, 0
; RV32-BOTH-NEXT: vse64.v v8, (a0)
; RV32-BOTH-NEXT: addi a1, a0, 80 ; RV32-BOTH-NEXT: addi a1, a0, 80
; RV32-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV32-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV32-BOTH-NEXT: vmv.v.i v8, 0 ; RV32-BOTH-NEXT: vmv.v.i v8, 0
; RV32-BOTH-NEXT: vse64.v v8, (a1) ; RV32-BOTH-NEXT: vse64.v v8, (a1)
; RV32-BOTH-NEXT: addi a1, a0, 64 ; RV32-BOTH-NEXT: addi a0, a0, 64
; RV32-BOTH-NEXT: vse64.v v8, (a1)
; RV32-BOTH-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-BOTH-NEXT: vmv.v.i v8, 0
; RV32-BOTH-NEXT: vse64.v v8, (a0) ; RV32-BOTH-NEXT: vse64.v v8, (a0)
; RV32-BOTH-NEXT: ret ; RV32-BOTH-NEXT: ret
; ;
; RV64-BOTH-LABEL: aligned_bzero_96: ; RV64-BOTH-LABEL: aligned_bzero_96:
; RV64-BOTH: # %bb.0: ; RV64-BOTH: # %bb.0:
; RV64-BOTH-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-BOTH-NEXT: vmv.v.i v8, 0
; RV64-BOTH-NEXT: vse64.v v8, (a0)
; RV64-BOTH-NEXT: addi a1, a0, 80 ; RV64-BOTH-NEXT: addi a1, a0, 80
; RV64-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; RV64-BOTH-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RV64-BOTH-NEXT: vmv.v.i v8, 0 ; RV64-BOTH-NEXT: vmv.v.i v8, 0
; RV64-BOTH-NEXT: vse64.v v8, (a1) ; RV64-BOTH-NEXT: vse64.v v8, (a1)
; RV64-BOTH-NEXT: addi a1, a0, 64 ; RV64-BOTH-NEXT: addi a0, a0, 64
; RV64-BOTH-NEXT: vse64.v v8, (a1)
; RV64-BOTH-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-BOTH-NEXT: vmv.v.i v8, 0
; RV64-BOTH-NEXT: vse64.v v8, (a0) ; RV64-BOTH-NEXT: vse64.v v8, (a0)
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 0, i64 96, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 0, i64 96, i1 0)
ret void ret void
} }
define void @aligned_bzero_128(ptr %a) nounwind { define void @aligned_bzero_128(ptr %a) nounwind {
; RV32-BOTH-LABEL: aligned_bzero_128: ; RV32-BOTH-LABEL: aligned_bzero_128:
Show All 11 Lines
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 0, i64 128, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 0, i64 128, i1 0)
ret void ret void
} }
define void @aligned_bzero_256(ptr %a) nounwind { define void @aligned_bzero_256(ptr %a) nounwind {
; RV32-BOTH-LABEL: aligned_bzero_256: ; RV32-BOTH-LABEL: aligned_bzero_256:
; RV32-BOTH: # %bb.0: ; RV32-BOTH: # %bb.0:
; RV32-BOTH-NEXT: addi a1, a0, 128
; RV32-BOTH-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV32-BOTH-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV32-BOTH-NEXT: vmv.v.i v8, 0 ; RV32-BOTH-NEXT: vmv.v.i v8, 0
; RV32-BOTH-NEXT: vse64.v v8, (a1) ; RV32-BOTH-NEXT: vse64.v v8, (a0)
; RV32-BOTH-NEXT: addi a0, a0, 128
; RV32-BOTH-NEXT: vse64.v v8, (a0) ; RV32-BOTH-NEXT: vse64.v v8, (a0)
; RV32-BOTH-NEXT: ret ; RV32-BOTH-NEXT: ret
; ;
; RV64-BOTH-LABEL: aligned_bzero_256: ; RV64-BOTH-LABEL: aligned_bzero_256:
; RV64-BOTH: # %bb.0: ; RV64-BOTH: # %bb.0:
; RV64-BOTH-NEXT: addi a1, a0, 128
; RV64-BOTH-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-BOTH-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-BOTH-NEXT: vmv.v.i v8, 0 ; RV64-BOTH-NEXT: vmv.v.i v8, 0
; RV64-BOTH-NEXT: vse64.v v8, (a1) ; RV64-BOTH-NEXT: vse64.v v8, (a0)
; RV64-BOTH-NEXT: addi a0, a0, 128
; RV64-BOTH-NEXT: vse64.v v8, (a0) ; RV64-BOTH-NEXT: vse64.v v8, (a0)
; RV64-BOTH-NEXT: ret ; RV64-BOTH-NEXT: ret
tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 0, i64 256, i1 0) tail call void @llvm.memset.inline.p0.i64(ptr align 64 %a, i8 0, i64 256, i1 0)
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

Show First 20 Lines • Show All 2,074 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v10, (a0), v16, v0.t
; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_nxv16i8: ; RV64-LABEL: mgather_baseidx_nxv16i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0 ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a1, a1, 3 ; RV64-NEXT: srli a1, a1, 3
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma ; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v0, a1 ; RV64-NEXT: vslidedown.vx v0, v0, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v9 ; RV64-NEXT: vsext.vf8 v16, v9
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v11, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v11, (a0), v16, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vmv1r.v v0, v12
; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64-NEXT: vmv2r.v v8, v10 ; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, ptr %base, <vscale x 16 x i8> %idxs %ptrs = getelementptr inbounds i8, ptr %base, <vscale x 16 x i8> %idxs
%v = call <vscale x 16 x i8> @llvm.masked.gather.nxv16i8.nxv16p0(<vscale x 16 x ptr> %ptrs, i32 2, <vscale x 16 x i1> %m, <vscale x 16 x i8> %passthru) %v = call <vscale x 16 x i8> @llvm.masked.gather.nxv16i8.nxv16p0(<vscale x 16 x ptr> %ptrs, i32 2, <vscale x 16 x i1> %m, <vscale x 16 x i8> %passthru)
ret <vscale x 16 x i8> %v ret <vscale x 16 x i8> %v
} }
declare <vscale x 32 x i8> @llvm.masked.gather.nxv32i8.nxv32p0(<vscale x 32 x ptr>, i32, <vscale x 32 x i1>, <vscale x 32 x i8>) declare <vscale x 32 x i8> @llvm.masked.gather.nxv32i8.nxv32p0(<vscale x 32 x ptr>, i32, <vscale x 32 x i1>, <vscale x 32 x i8>)
define <vscale x 32 x i8> @mgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8> %idxs, <vscale x 32 x i1> %m, <vscale x 32 x i8> %passthru) { define <vscale x 32 x i8> @mgather_baseidx_nxv32i8(ptr %base, <vscale x 32 x i8> %idxs, <vscale x 32 x i1> %m, <vscale x 32 x i8> %passthru) {
; RV32-LABEL: mgather_baseidx_nxv32i8: ; RV32-LABEL: mgather_baseidx_nxv32i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v16, v0 ; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-NEXT: vluxei32.v v12, (a0), v16, v0.t
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: srli a1, a1, 2 ; RV32-NEXT: srli a1, a1, 2
; RV32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma ; RV32-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vx v0, v0, a1 ; RV32-NEXT: vslidedown.vx v0, v0, a1
; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; RV32-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v24, v10 ; RV32-NEXT: vsext.vf4 v16, v10
; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-NEXT: vluxei32.v v14, (a0), v24, v0.t
; RV32-NEXT: vsetvli zero, zero, e32, m8, ta, ma
; RV32-NEXT: vsext.vf4 v24, v8
; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e8, m2, ta, mu
; RV32-NEXT: vmv1r.v v0, v16 ; RV32-NEXT: vluxei32.v v14, (a0), v16, v0.t
; RV32-NEXT: vluxei32.v v12, (a0), v24, v0.t
; RV32-NEXT: vmv4r.v v8, v12 ; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mgather_baseidx_nxv32i8: ; RV64-LABEL: mgather_baseidx_nxv32i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v16, v0 ; RV64-NEXT: vmv1r.v v16, v0
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: srli a2, a1, 2 ; RV64-NEXT: vsext.vf8 v24, v8
; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vx v17, v0, a2
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v24, v10
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vmv1r.v v0, v17 ; RV64-NEXT: vluxei64.v v12, (a0), v24, v0.t
; RV64-NEXT: vluxei64.v v14, (a0), v24, v0.t ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a1, a1, 3 ; RV64-NEXT: srli a2, a1, 3
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma ; RV64-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v16, a1 ; RV64-NEXT: vslidedown.vx v0, v0, a2
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a3, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v24, v9 ; RV64-NEXT: vsext.vf8 v24, v9
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v13, (a0), v24, v0.t ; RV64-NEXT: vluxei64.v v13, (a0), v24, v0.t
; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; RV64-NEXT: srli a1, a1, 2
; RV64-NEXT: vsext.vf8 v24, v8 ; RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vx v0, v16, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vmv1r.v v0, v16 ; RV64-NEXT: vluxei64.v v14, (a0), v16, v0.t
; RV64-NEXT: vluxei64.v v12, (a0), v24, v0.t ; RV64-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma ; RV64-NEXT: vslidedown.vx v0, v0, a2
; RV64-NEXT: vslidedown.vx v0, v17, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v11 ; RV64-NEXT: vsext.vf8 v16, v11
; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu ; RV64-NEXT: vsetvli zero, zero, e8, m1, ta, mu
; RV64-NEXT: vluxei64.v v15, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v15, (a0), v16, v0.t
; RV64-NEXT: vmv4r.v v8, v12 ; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, ptr %base, <vscale x 32 x i8> %idxs %ptrs = getelementptr inbounds i8, ptr %base, <vscale x 32 x i8> %idxs
%v = call <vscale x 32 x i8> @llvm.masked.gather.nxv32i8.nxv32p0(<vscale x 32 x ptr> %ptrs, i32 2, <vscale x 32 x i1> %m, <vscale x 32 x i8> %passthru) %v = call <vscale x 32 x i8> @llvm.masked.gather.nxv32i8.nxv32p0(<vscale x 32 x ptr> %ptrs, i32 2, <vscale x 32 x i1> %m, <vscale x 32 x i8> %passthru)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

Show All 10 Lines
; ;
define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) { define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv2i1: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv2i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2 ; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1 ; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv2i1: ; RV32-BITS-256-LABEL: reverse_nxv2i1:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0 ; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: srli a0, a0, 2 ; RV32-BITS-256-NEXT: srli a0, a0, 2
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0 ; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9 ; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1 ; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv2i1: ; RV32-BITS-512-LABEL: reverse_nxv2i1:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0 ; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 2 ; RV32-BITS-512-NEXT: srli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0 ; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9 ; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1 ; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i1: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i1:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2 ; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv2i1: ; RV64-BITS-256-LABEL: reverse_nxv2i1:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0 ; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 2 ; RV64-BITS-256-NEXT: srli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0 ; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9 ; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv2i1: ; RV64-BITS-512-LABEL: reverse_nxv2i1:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0 ; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 2 ; RV64-BITS-512-NEXT: srli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0 ; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9 ; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 2 x i1> @llvm.experimental.vector.reverse.nxv2i1(<vscale x 2 x i1> %a) %res = call <vscale x 2 x i1> @llvm.experimental.vector.reverse.nxv2i1(<vscale x 2 x i1> %a)
ret <vscale x 2 x i1> %res ret <vscale x 2 x i1> %res
} }
define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) { define <vscale x 4 x i1> @reverse_nxv4i1(<vscale x 4 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv4i1: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv4i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1 ; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1 ; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv4i1: ; RV32-BITS-256-LABEL: reverse_nxv4i1:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0 ; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: srli a0, a0, 1 ; RV32-BITS-256-NEXT: srli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0 ; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9 ; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1 ; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv4i1: ; RV32-BITS-512-LABEL: reverse_nxv4i1:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0 ; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 1 ; RV32-BITS-512-NEXT: srli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0 ; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9 ; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1 ; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i1: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i1:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1 ; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v9
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv4i1: ; RV64-BITS-256-LABEL: reverse_nxv4i1:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0 ; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 1 ; RV64-BITS-256-NEXT: srli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0 ; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9 ; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv4i1: ; RV64-BITS-512-LABEL: reverse_nxv4i1:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0 ; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 1 ; RV64-BITS-512-NEXT: srli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0 ; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9 ; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1> %a) %res = call <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1> %a)
ret <vscale x 4 x i1> %res ret <vscale x 4 x i1> %res
} }
define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) { define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv8i1: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv8i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v8 ; RV32-BITS-UNKNOWN-NEXT: vid.v v10
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v10, 0 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v10, v10, 1, v0 ; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v9, 1
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v10, v8
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v11, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv8i1: ; RV32-BITS-256-LABEL: reverse_nxv8i1:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vid.v v8 ; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-256-NEXT: vrsub.vx v8, v8, a0 ; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-256-NEXT: vmv.v.i v9, 0
; RV32-BITS-256-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-BITS-256-NEXT: vrgather.vv v10, v9, v8
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1 ; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv8i1: ; RV32-BITS-512-LABEL: reverse_nxv8i1:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vid.v v8 ; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV32-BITS-512-NEXT: vrsub.vx v8, v8, a0 ; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV32-BITS-512-NEXT: vmv.v.i v9, 0
; RV32-BITS-512-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-BITS-512-NEXT: vrgather.vv v10, v9, v8
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1 ; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i1: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i1:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v8 ; RV64-BITS-UNKNOWN-NEXT: vid.v v10
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v10, 0 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v10, v10, 1, v0 ; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v9, 1
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v10, v8
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v11, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv8i1: ; RV64-BITS-256-LABEL: reverse_nxv8i1:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vid.v v8 ; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-256-NEXT: vrsub.vx v8, v8, a0 ; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-256-NEXT: vmv.v.i v9, 0
; RV64-BITS-256-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-BITS-256-NEXT: vrgather.vv v10, v9, v8
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv8i1: ; RV64-BITS-512-LABEL: reverse_nxv8i1:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vid.v v8 ; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0
; RV64-BITS-512-NEXT: vrsub.vx v8, v8, a0 ; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9
; RV64-BITS-512-NEXT: vmv.v.i v9, 0
; RV64-BITS-512-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-BITS-512-NEXT: vrgather.vv v10, v9, v8
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1> %a) %res = call <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1> %a)
ret <vscale x 8 x i1> %res ret <vscale x 8 x i1> %res
} }
define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) { define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv16i1: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv16i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v12
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 1 ; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v12
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1 ; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv16i1: ; RV32-BITS-256-LABEL: reverse_nxv16i1:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0 ; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: vid.v v10
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 1 ; RV32-BITS-256-NEXT: slli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vid.v v10
; RV32-BITS-256-NEXT: vrsub.vx v10, v10, a0 ; RV32-BITS-256-NEXT: vrsub.vx v10, v10, a0
; RV32-BITS-256-NEXT: vrgather.vv v12, v8, v10 ; RV32-BITS-256-NEXT: vrgather.vv v12, v8, v10
; RV32-BITS-256-NEXT: vand.vi v8, v12, 1 ; RV32-BITS-256-NEXT: vand.vi v8, v12, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv16i1: ; RV32-BITS-512-LABEL: reverse_nxv16i1:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0 ; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: vid.v v10
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 1 ; RV32-BITS-512-NEXT: slli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vid.v v10
; RV32-BITS-512-NEXT: vrsub.vx v10, v10, a0 ; RV32-BITS-512-NEXT: vrsub.vx v10, v10, a0
; RV32-BITS-512-NEXT: vrgather.vv v12, v8, v10 ; RV32-BITS-512-NEXT: vrgather.vv v12, v8, v10
; RV32-BITS-512-NEXT: vand.vi v8, v12, 1 ; RV32-BITS-512-NEXT: vand.vi v8, v12, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i1: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i1:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v12
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 1 ; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v12
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v10, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv16i1: ; RV64-BITS-256-LABEL: reverse_nxv16i1:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0 ; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: vid.v v10
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 1 ; RV64-BITS-256-NEXT: slli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v10
; RV64-BITS-256-NEXT: vrsub.vx v10, v10, a0 ; RV64-BITS-256-NEXT: vrsub.vx v10, v10, a0
; RV64-BITS-256-NEXT: vrgather.vv v12, v8, v10 ; RV64-BITS-256-NEXT: vrgather.vv v12, v8, v10
; RV64-BITS-256-NEXT: vand.vi v8, v12, 1 ; RV64-BITS-256-NEXT: vand.vi v8, v12, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv16i1: ; RV64-BITS-512-LABEL: reverse_nxv16i1:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0 ; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: vid.v v10
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 1 ; RV64-BITS-512-NEXT: slli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vid.v v10
; RV64-BITS-512-NEXT: vrsub.vx v10, v10, a0 ; RV64-BITS-512-NEXT: vrsub.vx v10, v10, a0
; RV64-BITS-512-NEXT: vrgather.vv v12, v8, v10 ; RV64-BITS-512-NEXT: vrgather.vv v12, v8, v10
; RV64-BITS-512-NEXT: vand.vi v8, v12, 1 ; RV64-BITS-512-NEXT: vand.vi v8, v12, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 16 x i1> @llvm.experimental.vector.reverse.nxv16i1(<vscale x 16 x i1> %a) %res = call <vscale x 16 x i1> @llvm.experimental.vector.reverse.nxv16i1(<vscale x 16 x i1> %a)
ret <vscale x 16 x i1> %res ret <vscale x 16 x i1> %res
} }
define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) { define <vscale x 32 x i1> @reverse_nxv32i1(<vscale x 32 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv32i1: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv32i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2 ; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v12, 1 ; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v12, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv32i1: ; RV32-BITS-256-LABEL: reverse_nxv32i1:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0 ; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: vid.v v12
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 2 ; RV32-BITS-256-NEXT: slli a0, a0, 2
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vid.v v12
; RV32-BITS-256-NEXT: vrsub.vx v12, v12, a0 ; RV32-BITS-256-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-256-NEXT: vrgather.vv v16, v8, v12 ; RV32-BITS-256-NEXT: vrgather.vv v16, v8, v12
; RV32-BITS-256-NEXT: vand.vi v8, v16, 1 ; RV32-BITS-256-NEXT: vand.vi v8, v16, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv32i1: ; RV32-BITS-512-LABEL: reverse_nxv32i1:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0 ; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: vid.v v12
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 2 ; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vid.v v12
; RV32-BITS-512-NEXT: vrsub.vx v12, v12, a0 ; RV32-BITS-512-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-512-NEXT: vrgather.vv v16, v8, v12 ; RV32-BITS-512-NEXT: vrgather.vv v16, v8, v12
; RV32-BITS-512-NEXT: vand.vi v8, v16, 1 ; RV32-BITS-512-NEXT: vand.vi v8, v16, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i1: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i1:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2 ; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v12, 1 ; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v12, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv32i1: ; RV64-BITS-256-LABEL: reverse_nxv32i1:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0 ; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: vid.v v12
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 2 ; RV64-BITS-256-NEXT: slli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v12
; RV64-BITS-256-NEXT: vrsub.vx v12, v12, a0 ; RV64-BITS-256-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-256-NEXT: vrgather.vv v16, v8, v12 ; RV64-BITS-256-NEXT: vrgather.vv v16, v8, v12
; RV64-BITS-256-NEXT: vand.vi v8, v16, 1 ; RV64-BITS-256-NEXT: vand.vi v8, v16, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv32i1: ; RV64-BITS-512-LABEL: reverse_nxv32i1:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0 ; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: vid.v v12
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 2 ; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vid.v v12
; RV64-BITS-512-NEXT: vrsub.vx v12, v12, a0 ; RV64-BITS-512-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-512-NEXT: vrgather.vv v16, v8, v12 ; RV64-BITS-512-NEXT: vrgather.vv v16, v8, v12
; RV64-BITS-512-NEXT: vand.vi v8, v16, 1 ; RV64-BITS-512-NEXT: vand.vi v8, v16, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1> %a) %res = call <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1> %a)
ret <vscale x 32 x i1> %res ret <vscale x 32 x i1> %res
} }
define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) { define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i1: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v8
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2 ; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v8
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v16, 0 ; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v16, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v16, v16, 1, v0 ; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v16, v16, 1, v0
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v16, v8 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v16, v8
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v24, v20, v8 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v24, v20, v8
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v24, 1 ; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v24, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv64i1: ; RV32-BITS-256-LABEL: reverse_nxv64i1:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0 ; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: vid.v v16
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 3 ; RV32-BITS-256-NEXT: slli a0, a0, 3
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vid.v v16
; RV32-BITS-256-NEXT: vrsub.vx v16, v16, a0 ; RV32-BITS-256-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-256-NEXT: vrgather.vv v24, v8, v16 ; RV32-BITS-256-NEXT: vrgather.vv v24, v8, v16
; RV32-BITS-256-NEXT: vand.vi v8, v24, 1 ; RV32-BITS-256-NEXT: vand.vi v8, v24, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv64i1: ; RV32-BITS-512-LABEL: reverse_nxv64i1:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vid.v v8
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 2 ; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vid.v v8
; RV32-BITS-512-NEXT: vrsub.vx v8, v8, a0 ; RV32-BITS-512-NEXT: vrsub.vx v8, v8, a0
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v16, 0 ; RV32-BITS-512-NEXT: vmv.v.i v16, 0
; RV32-BITS-512-NEXT: vmerge.vim v16, v16, 1, v0 ; RV32-BITS-512-NEXT: vmerge.vim v16, v16, 1, v0
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vrgather.vv v28, v16, v8 ; RV32-BITS-512-NEXT: vrgather.vv v28, v16, v8
; RV32-BITS-512-NEXT: vrgather.vv v24, v20, v8 ; RV32-BITS-512-NEXT: vrgather.vv v24, v20, v8
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-512-NEXT: vand.vi v8, v24, 1 ; RV32-BITS-512-NEXT: vand.vi v8, v24, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i1: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i1:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v8
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2 ; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v8
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v16, 0 ; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v16, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v16, v16, 1, v0 ; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v16, v16, 1, v0
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v16, v8 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v16, v8
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v24, v20, v8 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v24, v20, v8
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v24, 1 ; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v24, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv64i1: ; RV64-BITS-256-LABEL: reverse_nxv64i1:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0 ; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: vid.v v16
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 3 ; RV64-BITS-256-NEXT: slli a0, a0, 3
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v16
; RV64-BITS-256-NEXT: vrsub.vx v16, v16, a0 ; RV64-BITS-256-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-256-NEXT: vrgather.vv v24, v8, v16 ; RV64-BITS-256-NEXT: vrgather.vv v24, v8, v16
; RV64-BITS-256-NEXT: vand.vi v8, v24, 1 ; RV64-BITS-256-NEXT: vand.vi v8, v24, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv64i1: ; RV64-BITS-512-LABEL: reverse_nxv64i1:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vid.v v8
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 2 ; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vid.v v8
; RV64-BITS-512-NEXT: vrsub.vx v8, v8, a0 ; RV64-BITS-512-NEXT: vrsub.vx v8, v8, a0
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v16, 0 ; RV64-BITS-512-NEXT: vmv.v.i v16, 0
; RV64-BITS-512-NEXT: vmerge.vim v16, v16, 1, v0 ; RV64-BITS-512-NEXT: vmerge.vim v16, v16, 1, v0
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vrgather.vv v28, v16, v8 ; RV64-BITS-512-NEXT: vrgather.vv v28, v16, v8
; RV64-BITS-512-NEXT: vrgather.vv v24, v20, v8 ; RV64-BITS-512-NEXT: vrgather.vv v24, v20, v8
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-512-NEXT: vand.vi v8, v24, 1 ; RV64-BITS-512-NEXT: vand.vi v8, v24, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 64 x i1> @llvm.experimental.vector.reverse.nxv64i1(<vscale x 64 x i1> %a) %res = call <vscale x 64 x i1> @llvm.experimental.vector.reverse.nxv64i1(<vscale x 64 x i1> %a)
ret <vscale x 64 x i1> %res ret <vscale x 64 x i1> %res
} }
; ;
; VECTOR_REVERSE - integer ; VECTOR_REVERSE - integer
; ;
define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) { define <vscale x 1 x i8> @reverse_nxv1i8(<vscale x 1 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv1i8: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv1i8:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 3 ; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 3
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv1i8: ; RV32-BITS-256-LABEL: reverse_nxv1i8:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: srli a0, a0, 3 ; RV32-BITS-256-NEXT: srli a0, a0, 3
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10 ; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-256-NEXT: vmv1r.v v8, v9 ; RV32-BITS-256-NEXT: vmv1r.v v8, v9
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv1i8: ; RV32-BITS-512-LABEL: reverse_nxv1i8:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 3 ; RV32-BITS-512-NEXT: srli a0, a0, 3
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10 ; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-512-NEXT: vmv1r.v v8, v9 ; RV32-BITS-512-NEXT: vmv1r.v v8, v9
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv1i8: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv1i8:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 3 ; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 3
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv1i8: ; RV64-BITS-256-LABEL: reverse_nxv1i8:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 3 ; RV64-BITS-256-NEXT: srli a0, a0, 3
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10 ; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-256-NEXT: vmv1r.v v8, v9 ; RV64-BITS-256-NEXT: vmv1r.v v8, v9
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv1i8: ; RV64-BITS-512-LABEL: reverse_nxv1i8:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 3 ; RV64-BITS-512-NEXT: srli a0, a0, 3
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 ; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-512-NEXT: vmv1r.v v8, v9 ; RV64-BITS-512-NEXT: vmv1r.v v8, v9
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 1 x i8> @llvm.experimental.vector.reverse.nxv1i8(<vscale x 1 x i8> %a) %res = call <vscale x 1 x i8> @llvm.experimental.vector.reverse.nxv1i8(<vscale x 1 x i8> %a)
ret <vscale x 1 x i8> %res ret <vscale x 1 x i8> %res
} }
define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) { define <vscale x 2 x i8> @reverse_nxv2i8(<vscale x 2 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv2i8: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv2i8:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2 ; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv2i8: ; RV32-BITS-256-LABEL: reverse_nxv2i8:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: srli a0, a0, 2 ; RV32-BITS-256-NEXT: srli a0, a0, 2
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10 ; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-256-NEXT: vmv1r.v v8, v9 ; RV32-BITS-256-NEXT: vmv1r.v v8, v9
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv2i8: ; RV32-BITS-512-LABEL: reverse_nxv2i8:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 2 ; RV32-BITS-512-NEXT: srli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10 ; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-512-NEXT: vmv1r.v v8, v9 ; RV32-BITS-512-NEXT: vmv1r.v v8, v9
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i8: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv2i8:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2 ; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv2i8: ; RV64-BITS-256-LABEL: reverse_nxv2i8:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 2 ; RV64-BITS-256-NEXT: srli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10 ; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-256-NEXT: vmv1r.v v8, v9 ; RV64-BITS-256-NEXT: vmv1r.v v8, v9
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv2i8: ; RV64-BITS-512-LABEL: reverse_nxv2i8:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 2 ; RV64-BITS-512-NEXT: srli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 ; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-512-NEXT: vmv1r.v v8, v9 ; RV64-BITS-512-NEXT: vmv1r.v v8, v9
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 2 x i8> @llvm.experimental.vector.reverse.nxv2i8(<vscale x 2 x i8> %a) %res = call <vscale x 2 x i8> @llvm.experimental.vector.reverse.nxv2i8(<vscale x 2 x i8> %a)
ret <vscale x 2 x i8> %res ret <vscale x 2 x i8> %res
} }
define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) { define <vscale x 4 x i8> @reverse_nxv4i8(<vscale x 4 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv4i8: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv4i8:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1 ; RV32-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v9
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV32-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv4i8: ; RV32-BITS-256-LABEL: reverse_nxv4i8:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: srli a0, a0, 1 ; RV32-BITS-256-NEXT: srli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; RV32-BITS-256-NEXT: vid.v v9
; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10 ; RV32-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-256-NEXT: vmv1r.v v8, v9 ; RV32-BITS-256-NEXT: vmv1r.v v8, v9
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv4i8: ; RV32-BITS-512-LABEL: reverse_nxv4i8:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: srli a0, a0, 1 ; RV32-BITS-512-NEXT: srli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; RV32-BITS-512-NEXT: vid.v v9
; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0 ; RV32-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10 ; RV32-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV32-BITS-512-NEXT: vmv1r.v v8, v9 ; RV32-BITS-512-NEXT: vmv1r.v v8, v9
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i8: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv4i8:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1 ; RV64-BITS-UNKNOWN-NEXT: srli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v9
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, mf2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10
; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9 ; RV64-BITS-UNKNOWN-NEXT: vmv1r.v v8, v9
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv4i8: ; RV64-BITS-256-LABEL: reverse_nxv4i8:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: srli a0, a0, 1 ; RV64-BITS-256-NEXT: srli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; RV64-BITS-256-NEXT: vid.v v9
; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-256-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10 ; RV64-BITS-256-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-256-NEXT: vmv1r.v v8, v9 ; RV64-BITS-256-NEXT: vmv1r.v v8, v9
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv4i8: ; RV64-BITS-512-LABEL: reverse_nxv4i8:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: srli a0, a0, 1 ; RV64-BITS-512-NEXT: srli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; RV64-BITS-512-NEXT: vid.v v9
; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0 ; RV64-BITS-512-NEXT: vrsub.vx v10, v9, a0
; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 ; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10
; RV64-BITS-512-NEXT: vmv1r.v v8, v9 ; RV64-BITS-512-NEXT: vmv1r.v v8, v9
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 4 x i8> @llvm.experimental.vector.reverse.nxv4i8(<vscale x 4 x i8> %a) %res = call <vscale x 4 x i8> @llvm.experimental.vector.reverse.nxv4i8(<vscale x 4 x i8> %a)
ret <vscale x 4 x i8> %res ret <vscale x 4 x i8> %res
} }
▲ Show 20 Lines • Show All 67 Lines • ▼ Show 20 Lines
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 8 x i8> @llvm.experimental.vector.reverse.nxv8i8(<vscale x 8 x i8> %a) %res = call <vscale x 8 x i8> @llvm.experimental.vector.reverse.nxv8i8(<vscale x 8 x i8> %a)
ret <vscale x 8 x i8> %res ret <vscale x 8 x i8> %res
} }
define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) { define <vscale x 16 x i8> @reverse_nxv16i8(<vscale x 16 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv16i8: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv16i8:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v12
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 1 ; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v12
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
; RV32-BITS-UNKNOWN-NEXT: vmv.v.v v8, v10 ; RV32-BITS-UNKNOWN-NEXT: vmv.v.v v8, v10
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv16i8: ; RV32-BITS-256-LABEL: reverse_nxv16i8:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV32-BITS-256-NEXT: vid.v v10
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 1 ; RV32-BITS-256-NEXT: slli a0, a0, 1
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; RV32-BITS-256-NEXT: vid.v v10
; RV32-BITS-256-NEXT: vrsub.vx v12, v10, a0 ; RV32-BITS-256-NEXT: vrsub.vx v12, v10, a0
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v12 ; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v12
; RV32-BITS-256-NEXT: vmv.v.v v8, v10 ; RV32-BITS-256-NEXT: vmv.v.v v8, v10
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv16i8: ; RV32-BITS-512-LABEL: reverse_nxv16i8:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV32-BITS-512-NEXT: vid.v v10
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 1 ; RV32-BITS-512-NEXT: slli a0, a0, 1
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; RV32-BITS-512-NEXT: vid.v v10
; RV32-BITS-512-NEXT: vrsub.vx v12, v10, a0 ; RV32-BITS-512-NEXT: vrsub.vx v12, v10, a0
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v12 ; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v12
; RV32-BITS-512-NEXT: vmv.v.v v8, v10 ; RV32-BITS-512-NEXT: vmv.v.v v8, v10
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i8: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv16i8:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v12
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 1 ; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 1
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v12
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v12, v12, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v10, v8, v12
; RV64-BITS-UNKNOWN-NEXT: vmv.v.v v8, v10 ; RV64-BITS-UNKNOWN-NEXT: vmv.v.v v8, v10
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv16i8: ; RV64-BITS-256-LABEL: reverse_nxv16i8:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV64-BITS-256-NEXT: vid.v v10
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 1 ; RV64-BITS-256-NEXT: slli a0, a0, 1
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; RV64-BITS-256-NEXT: vid.v v10
; RV64-BITS-256-NEXT: vrsub.vx v12, v10, a0 ; RV64-BITS-256-NEXT: vrsub.vx v12, v10, a0
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v12 ; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v12
; RV64-BITS-256-NEXT: vmv.v.v v8, v10 ; RV64-BITS-256-NEXT: vmv.v.v v8, v10
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv16i8: ; RV64-BITS-512-LABEL: reverse_nxv16i8:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; RV64-BITS-512-NEXT: vid.v v10
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 1 ; RV64-BITS-512-NEXT: slli a0, a0, 1
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m2, ta, ma
; RV64-BITS-512-NEXT: vid.v v10
; RV64-BITS-512-NEXT: vrsub.vx v12, v10, a0 ; RV64-BITS-512-NEXT: vrsub.vx v12, v10, a0
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v12 ; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v12
; RV64-BITS-512-NEXT: vmv.v.v v8, v10 ; RV64-BITS-512-NEXT: vmv.v.v v8, v10
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.experimental.vector.reverse.nxv16i8(<vscale x 16 x i8> %a) %res = call <vscale x 16 x i8> @llvm.experimental.vector.reverse.nxv16i8(<vscale x 16 x i8> %a)
ret <vscale x 16 x i8> %res ret <vscale x 16 x i8> %res
} }
define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) { define <vscale x 32 x i8> @reverse_nxv32i8(<vscale x 32 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv32i8: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv32i8:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2 ; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
; RV32-BITS-UNKNOWN-NEXT: vmv.v.v v8, v12 ; RV32-BITS-UNKNOWN-NEXT: vmv.v.v v8, v12
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv32i8: ; RV32-BITS-256-LABEL: reverse_nxv32i8:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-256-NEXT: vid.v v12
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 2 ; RV32-BITS-256-NEXT: slli a0, a0, 2
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; RV32-BITS-256-NEXT: vid.v v12
; RV32-BITS-256-NEXT: vrsub.vx v16, v12, a0 ; RV32-BITS-256-NEXT: vrsub.vx v16, v12, a0
; RV32-BITS-256-NEXT: vrgather.vv v12, v8, v16 ; RV32-BITS-256-NEXT: vrgather.vv v12, v8, v16
; RV32-BITS-256-NEXT: vmv.v.v v8, v12 ; RV32-BITS-256-NEXT: vmv.v.v v8, v12
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv32i8: ; RV32-BITS-512-LABEL: reverse_nxv32i8:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vid.v v12
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 2 ; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vid.v v12
; RV32-BITS-512-NEXT: vrsub.vx v16, v12, a0 ; RV32-BITS-512-NEXT: vrsub.vx v16, v12, a0
; RV32-BITS-512-NEXT: vrgather.vv v12, v8, v16 ; RV32-BITS-512-NEXT: vrgather.vv v12, v8, v16
; RV32-BITS-512-NEXT: vmv.v.v v8, v12 ; RV32-BITS-512-NEXT: vmv.v.v v8, v12
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i8: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv32i8:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2 ; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v12, v8, v16
; RV64-BITS-UNKNOWN-NEXT: vmv.v.v v8, v12 ; RV64-BITS-UNKNOWN-NEXT: vmv.v.v v8, v12
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv32i8: ; RV64-BITS-256-LABEL: reverse_nxv32i8:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-256-NEXT: vid.v v12
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 2 ; RV64-BITS-256-NEXT: slli a0, a0, 2
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; RV64-BITS-256-NEXT: vid.v v12
; RV64-BITS-256-NEXT: vrsub.vx v16, v12, a0 ; RV64-BITS-256-NEXT: vrsub.vx v16, v12, a0
; RV64-BITS-256-NEXT: vrgather.vv v12, v8, v16 ; RV64-BITS-256-NEXT: vrgather.vv v12, v8, v16
; RV64-BITS-256-NEXT: vmv.v.v v8, v12 ; RV64-BITS-256-NEXT: vmv.v.v v8, v12
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv32i8: ; RV64-BITS-512-LABEL: reverse_nxv32i8:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vid.v v12
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 2 ; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vid.v v12
; RV64-BITS-512-NEXT: vrsub.vx v16, v12, a0 ; RV64-BITS-512-NEXT: vrsub.vx v16, v12, a0
; RV64-BITS-512-NEXT: vrgather.vv v12, v8, v16 ; RV64-BITS-512-NEXT: vrgather.vv v12, v8, v16
; RV64-BITS-512-NEXT: vmv.v.v v8, v12 ; RV64-BITS-512-NEXT: vmv.v.v v8, v12
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 32 x i8> @llvm.experimental.vector.reverse.nxv32i8(<vscale x 32 x i8> %a) %res = call <vscale x 32 x i8> @llvm.experimental.vector.reverse.nxv32i8(<vscale x 32 x i8> %a)
ret <vscale x 32 x i8> %res ret <vscale x 32 x i8> %res
} }
define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) { define <vscale x 64 x i8> @reverse_nxv64i8(<vscale x 64 x i8> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i8: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i8:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2 ; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v16
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v24, v16, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v24, v16, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v20, v8, v24 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v20, v8, v24
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v16, v12, v24 ; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v16, v12, v24
; RV32-BITS-UNKNOWN-NEXT: vmv8r.v v8, v16 ; RV32-BITS-UNKNOWN-NEXT: vmv8r.v v8, v16
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv64i8: ; RV32-BITS-256-LABEL: reverse_nxv64i8:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-256-NEXT: vid.v v16
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 3 ; RV32-BITS-256-NEXT: slli a0, a0, 3
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; RV32-BITS-256-NEXT: vid.v v16
; RV32-BITS-256-NEXT: vrsub.vx v24, v16, a0 ; RV32-BITS-256-NEXT: vrsub.vx v24, v16, a0
; RV32-BITS-256-NEXT: vrgather.vv v16, v8, v24 ; RV32-BITS-256-NEXT: vrgather.vv v16, v8, v24
; RV32-BITS-256-NEXT: vmv.v.v v8, v16 ; RV32-BITS-256-NEXT: vmv.v.v v8, v16
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv64i8: ; RV32-BITS-512-LABEL: reverse_nxv64i8:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vid.v v16
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 2 ; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vid.v v16
; RV32-BITS-512-NEXT: vrsub.vx v24, v16, a0 ; RV32-BITS-512-NEXT: vrsub.vx v24, v16, a0
; RV32-BITS-512-NEXT: vrgather.vv v20, v8, v24 ; RV32-BITS-512-NEXT: vrgather.vv v20, v8, v24
; RV32-BITS-512-NEXT: vrgather.vv v16, v12, v24 ; RV32-BITS-512-NEXT: vrgather.vv v16, v12, v24
; RV32-BITS-512-NEXT: vmv8r.v v8, v16 ; RV32-BITS-512-NEXT: vmv8r.v v8, v16
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i8: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i8:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2 ; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v16
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v24, v16, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v24, v16, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v20, v8, v24 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v20, v8, v24
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v16, v12, v24 ; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v16, v12, v24
; RV64-BITS-UNKNOWN-NEXT: vmv8r.v v8, v16 ; RV64-BITS-UNKNOWN-NEXT: vmv8r.v v8, v16
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv64i8: ; RV64-BITS-256-LABEL: reverse_nxv64i8:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-256-NEXT: vid.v v16
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 3 ; RV64-BITS-256-NEXT: slli a0, a0, 3
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; RV64-BITS-256-NEXT: vid.v v16
; RV64-BITS-256-NEXT: vrsub.vx v24, v16, a0 ; RV64-BITS-256-NEXT: vrsub.vx v24, v16, a0
; RV64-BITS-256-NEXT: vrgather.vv v16, v8, v24 ; RV64-BITS-256-NEXT: vrgather.vv v16, v8, v24
; RV64-BITS-256-NEXT: vmv.v.v v8, v16 ; RV64-BITS-256-NEXT: vmv.v.v v8, v16
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv64i8: ; RV64-BITS-512-LABEL: reverse_nxv64i8:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vid.v v16
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 2 ; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vid.v v16
; RV64-BITS-512-NEXT: vrsub.vx v24, v16, a0 ; RV64-BITS-512-NEXT: vrsub.vx v24, v16, a0
; RV64-BITS-512-NEXT: vrgather.vv v20, v8, v24 ; RV64-BITS-512-NEXT: vrgather.vv v20, v8, v24
; RV64-BITS-512-NEXT: vrgather.vv v16, v12, v24 ; RV64-BITS-512-NEXT: vrgather.vv v16, v12, v24
; RV64-BITS-512-NEXT: vmv8r.v v8, v16 ; RV64-BITS-512-NEXT: vmv8r.v v8, v16
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 64 x i8> @llvm.experimental.vector.reverse.nxv64i8(<vscale x 64 x i8> %a) %res = call <vscale x 64 x i8> @llvm.experimental.vector.reverse.nxv64i8(<vscale x 64 x i8> %a)
ret <vscale x 64 x i8> %res ret <vscale x 64 x i8> %res
} }
define <vscale x 1 x i16> @reverse_nxv1i16(<vscale x 1 x i16> %a) { define <vscale x 1 x i16> @reverse_nxv1i16(<vscale x 1 x i16> %a) {
; CHECK-LABEL: reverse_nxv1i16: ; CHECK-LABEL: reverse_nxv1i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i16> @llvm.experimental.vector.reverse.nxv1i16(<vscale x 1 x i16> %a) %res = call <vscale x 1 x i16> @llvm.experimental.vector.reverse.nxv1i16(<vscale x 1 x i16> %a)
ret <vscale x 1 x i16> %res ret <vscale x 1 x i16> %res
} }
define <vscale x 2 x i16> @reverse_nxv2i16(<vscale x 2 x i16> %a) { define <vscale x 2 x i16> @reverse_nxv2i16(<vscale x 2 x i16> %a) {
; CHECK-LABEL: reverse_nxv2i16: ; CHECK-LABEL: reverse_nxv2i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i16> @llvm.experimental.vector.reverse.nxv2i16(<vscale x 2 x i16> %a) %res = call <vscale x 2 x i16> @llvm.experimental.vector.reverse.nxv2i16(<vscale x 2 x i16> %a)
ret <vscale x 2 x i16> %res ret <vscale x 2 x i16> %res
} }
define <vscale x 4 x i16> @reverse_nxv4i16(<vscale x 4 x i16> %a) { define <vscale x 4 x i16> @reverse_nxv4i16(<vscale x 4 x i16> %a) {
; CHECK-LABEL: reverse_nxv4i16: ; CHECK-LABEL: reverse_nxv4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i16> @llvm.experimental.vector.reverse.nxv4i16(<vscale x 4 x i16> %a) %res = call <vscale x 4 x i16> @llvm.experimental.vector.reverse.nxv4i16(<vscale x 4 x i16> %a)
ret <vscale x 4 x i16> %res ret <vscale x 4 x i16> %res
} }
Show All 10 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.experimental.vector.reverse.nxv8i16(<vscale x 8 x i16> %a) %res = call <vscale x 8 x i16> @llvm.experimental.vector.reverse.nxv8i16(<vscale x 8 x i16> %a)
ret <vscale x 8 x i16> %res ret <vscale x 8 x i16> %res
} }
define <vscale x 16 x i16> @reverse_nxv16i16(<vscale x 16 x i16> %a) { define <vscale x 16 x i16> @reverse_nxv16i16(<vscale x 16 x i16> %a) {
; CHECK-LABEL: reverse_nxv16i16: ; CHECK-LABEL: reverse_nxv16i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vrsub.vx v16, v12, a0 ; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i16> @llvm.experimental.vector.reverse.nxv16i16(<vscale x 16 x i16> %a) %res = call <vscale x 16 x i16> @llvm.experimental.vector.reverse.nxv16i16(<vscale x 16 x i16> %a)
ret <vscale x 16 x i16> %res ret <vscale x 16 x i16> %res
} }
define <vscale x 32 x i16> @reverse_nxv32i16(<vscale x 32 x i16> %a) { define <vscale x 32 x i16> @reverse_nxv32i16(<vscale x 32 x i16> %a) {
; CHECK-LABEL: reverse_nxv32i16: ; CHECK-LABEL: reverse_nxv32i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vrsub.vx v24, v16, a0 ; CHECK-NEXT: vrsub.vx v24, v16, a0
; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vrgather.vv v16, v8, v24
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x i16> @llvm.experimental.vector.reverse.nxv32i16(<vscale x 32 x i16> %a) %res = call <vscale x 32 x i16> @llvm.experimental.vector.reverse.nxv32i16(<vscale x 32 x i16> %a)
ret <vscale x 32 x i16> %res ret <vscale x 32 x i16> %res
} }
define <vscale x 1 x i32> @reverse_nxv1i32(<vscale x 1 x i32> %a) { define <vscale x 1 x i32> @reverse_nxv1i32(<vscale x 1 x i32> %a) {
; CHECK-LABEL: reverse_nxv1i32: ; CHECK-LABEL: reverse_nxv1i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i32> @llvm.experimental.vector.reverse.nxv1i32(<vscale x 1 x i32> %a) %res = call <vscale x 1 x i32> @llvm.experimental.vector.reverse.nxv1i32(<vscale x 1 x i32> %a)
ret <vscale x 1 x i32> %res ret <vscale x 1 x i32> %res
} }
define <vscale x 2 x i32> @reverse_nxv2i32(<vscale x 2 x i32> %a) { define <vscale x 2 x i32> @reverse_nxv2i32(<vscale x 2 x i32> %a) {
; CHECK-LABEL: reverse_nxv2i32: ; CHECK-LABEL: reverse_nxv2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i32> @llvm.experimental.vector.reverse.nxv2i32(<vscale x 2 x i32> %a) %res = call <vscale x 2 x i32> @llvm.experimental.vector.reverse.nxv2i32(<vscale x 2 x i32> %a)
ret <vscale x 2 x i32> %res ret <vscale x 2 x i32> %res
} }
define <vscale x 4 x i32> @reverse_nxv4i32(<vscale x 4 x i32> %a) { define <vscale x 4 x i32> @reverse_nxv4i32(<vscale x 4 x i32> %a) {
; CHECK-LABEL: reverse_nxv4i32: ; CHECK-LABEL: reverse_nxv4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vrsub.vx v12, v10, a0 ; CHECK-NEXT: vrsub.vx v12, v10, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a) %res = call <vscale x 4 x i32> @llvm.experimental.vector.reverse.nxv4i32(<vscale x 4 x i32> %a)
ret <vscale x 4 x i32> %res ret <vscale x 4 x i32> %res
} }
Show All 10 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.experimental.vector.reverse.nxv8i32(<vscale x 8 x i32> %a) %res = call <vscale x 8 x i32> @llvm.experimental.vector.reverse.nxv8i32(<vscale x 8 x i32> %a)
ret <vscale x 8 x i32> %res ret <vscale x 8 x i32> %res
} }
define <vscale x 16 x i32> @reverse_nxv16i32(<vscale x 16 x i32> %a) { define <vscale x 16 x i32> @reverse_nxv16i32(<vscale x 16 x i32> %a) {
; CHECK-LABEL: reverse_nxv16i32: ; CHECK-LABEL: reverse_nxv16i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vrsub.vx v24, v16, a0 ; CHECK-NEXT: vrsub.vx v24, v16, a0
; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vrgather.vv v16, v8, v24
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x i32> @llvm.experimental.vector.reverse.nxv16i32(<vscale x 16 x i32> %a) %res = call <vscale x 16 x i32> @llvm.experimental.vector.reverse.nxv16i32(<vscale x 16 x i32> %a)
ret <vscale x 16 x i32> %res ret <vscale x 16 x i32> %res
} }
define <vscale x 1 x i64> @reverse_nxv1i64(<vscale x 1 x i64> %a) { define <vscale x 1 x i64> @reverse_nxv1i64(<vscale x 1 x i64> %a) {
; CHECK-LABEL: reverse_nxv1i64: ; CHECK-LABEL: reverse_nxv1i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x i64> @llvm.experimental.vector.reverse.nxv1i64(<vscale x 1 x i64> %a) %res = call <vscale x 1 x i64> @llvm.experimental.vector.reverse.nxv1i64(<vscale x 1 x i64> %a)
ret <vscale x 1 x i64> %res ret <vscale x 1 x i64> %res
} }
define <vscale x 2 x i64> @reverse_nxv2i64(<vscale x 2 x i64> %a) { define <vscale x 2 x i64> @reverse_nxv2i64(<vscale x 2 x i64> %a) {
; CHECK-LABEL: reverse_nxv2i64: ; CHECK-LABEL: reverse_nxv2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vrsub.vx v12, v10, a0 ; CHECK-NEXT: vrsub.vx v12, v10, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.experimental.vector.reverse.nxv2i64(<vscale x 2 x i64> %a) %res = call <vscale x 2 x i64> @llvm.experimental.vector.reverse.nxv2i64(<vscale x 2 x i64> %a)
ret <vscale x 2 x i64> %res ret <vscale x 2 x i64> %res
} }
define <vscale x 4 x i64> @reverse_nxv4i64(<vscale x 4 x i64> %a) { define <vscale x 4 x i64> @reverse_nxv4i64(<vscale x 4 x i64> %a) {
; CHECK-LABEL: reverse_nxv4i64: ; CHECK-LABEL: reverse_nxv4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vrsub.vx v16, v12, a0 ; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.experimental.vector.reverse.nxv4i64(<vscale x 4 x i64> %a) %res = call <vscale x 4 x i64> @llvm.experimental.vector.reverse.nxv4i64(<vscale x 4 x i64> %a)
ret <vscale x 4 x i64> %res ret <vscale x 4 x i64> %res
} }
Show All 14 Lines
; ;
; VECTOR_REVERSE - floating point ; VECTOR_REVERSE - floating point
; ;
define <vscale x 1 x half> @reverse_nxv1f16(<vscale x 1 x half> %a) { define <vscale x 1 x half> @reverse_nxv1f16(<vscale x 1 x half> %a) {
; CHECK-LABEL: reverse_nxv1f16: ; CHECK-LABEL: reverse_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x half> @llvm.experimental.vector.reverse.nxv1f16(<vscale x 1 x half> %a) %res = call <vscale x 1 x half> @llvm.experimental.vector.reverse.nxv1f16(<vscale x 1 x half> %a)
ret <vscale x 1 x half> %res ret <vscale x 1 x half> %res
} }
define <vscale x 2 x half> @reverse_nxv2f16(<vscale x 2 x half> %a) { define <vscale x 2 x half> @reverse_nxv2f16(<vscale x 2 x half> %a) {
; CHECK-LABEL: reverse_nxv2f16: ; CHECK-LABEL: reverse_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x half> @llvm.experimental.vector.reverse.nxv2f16(<vscale x 2 x half> %a) %res = call <vscale x 2 x half> @llvm.experimental.vector.reverse.nxv2f16(<vscale x 2 x half> %a)
ret <vscale x 2 x half> %res ret <vscale x 2 x half> %res
} }
define <vscale x 4 x half> @reverse_nxv4f16(<vscale x 4 x half> %a) { define <vscale x 4 x half> @reverse_nxv4f16(<vscale x 4 x half> %a) {
; CHECK-LABEL: reverse_nxv4f16: ; CHECK-LABEL: reverse_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x half> @llvm.experimental.vector.reverse.nxv4f16(<vscale x 4 x half> %a) %res = call <vscale x 4 x half> @llvm.experimental.vector.reverse.nxv4f16(<vscale x 4 x half> %a)
ret <vscale x 4 x half> %res ret <vscale x 4 x half> %res
} }
Show All 10 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x half> @llvm.experimental.vector.reverse.nxv8f16(<vscale x 8 x half> %a) %res = call <vscale x 8 x half> @llvm.experimental.vector.reverse.nxv8f16(<vscale x 8 x half> %a)
ret <vscale x 8 x half> %res ret <vscale x 8 x half> %res
} }
define <vscale x 16 x half> @reverse_nxv16f16(<vscale x 16 x half> %a) { define <vscale x 16 x half> @reverse_nxv16f16(<vscale x 16 x half> %a) {
; CHECK-LABEL: reverse_nxv16f16: ; CHECK-LABEL: reverse_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vrsub.vx v16, v12, a0 ; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x half> @llvm.experimental.vector.reverse.nxv16f16(<vscale x 16 x half> %a) %res = call <vscale x 16 x half> @llvm.experimental.vector.reverse.nxv16f16(<vscale x 16 x half> %a)
ret <vscale x 16 x half> %res ret <vscale x 16 x half> %res
} }
define <vscale x 32 x half> @reverse_nxv32f16(<vscale x 32 x half> %a) { define <vscale x 32 x half> @reverse_nxv32f16(<vscale x 32 x half> %a) {
; CHECK-LABEL: reverse_nxv32f16: ; CHECK-LABEL: reverse_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: slli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vrsub.vx v24, v16, a0 ; CHECK-NEXT: vrsub.vx v24, v16, a0
; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vrgather.vv v16, v8, v24
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 32 x half> @llvm.experimental.vector.reverse.nxv32f16(<vscale x 32 x half> %a) %res = call <vscale x 32 x half> @llvm.experimental.vector.reverse.nxv32f16(<vscale x 32 x half> %a)
ret <vscale x 32 x half> %res ret <vscale x 32 x half> %res
} }
define <vscale x 1 x float> @reverse_nxv1f32(<vscale x 1 x float> %a) { define <vscale x 1 x float> @reverse_nxv1f32(<vscale x 1 x float> %a) {
; CHECK-LABEL: reverse_nxv1f32: ; CHECK-LABEL: reverse_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x float> @llvm.experimental.vector.reverse.nxv1f32(<vscale x 1 x float> %a) %res = call <vscale x 1 x float> @llvm.experimental.vector.reverse.nxv1f32(<vscale x 1 x float> %a)
ret <vscale x 1 x float> %res ret <vscale x 1 x float> %res
} }
define <vscale x 2 x float> @reverse_nxv2f32(<vscale x 2 x float> %a) { define <vscale x 2 x float> @reverse_nxv2f32(<vscale x 2 x float> %a) {
; CHECK-LABEL: reverse_nxv2f32: ; CHECK-LABEL: reverse_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x float> @llvm.experimental.vector.reverse.nxv2f32(<vscale x 2 x float> %a) %res = call <vscale x 2 x float> @llvm.experimental.vector.reverse.nxv2f32(<vscale x 2 x float> %a)
ret <vscale x 2 x float> %res ret <vscale x 2 x float> %res
} }
define <vscale x 4 x float> @reverse_nxv4f32(<vscale x 4 x float> %a) { define <vscale x 4 x float> @reverse_nxv4f32(<vscale x 4 x float> %a) {
; CHECK-LABEL: reverse_nxv4f32: ; CHECK-LABEL: reverse_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vrsub.vx v12, v10, a0 ; CHECK-NEXT: vrsub.vx v12, v10, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float> %a) %res = call <vscale x 4 x float> @llvm.experimental.vector.reverse.nxv4f32(<vscale x 4 x float> %a)
ret <vscale x 4 x float> %res ret <vscale x 4 x float> %res
} }
Show All 10 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x float> @llvm.experimental.vector.reverse.nxv8f32(<vscale x 8 x float> %a) %res = call <vscale x 8 x float> @llvm.experimental.vector.reverse.nxv8f32(<vscale x 8 x float> %a)
ret <vscale x 8 x float> %res ret <vscale x 8 x float> %res
} }
define <vscale x 16 x float> @reverse_nxv16f32(<vscale x 16 x float> %a) { define <vscale x 16 x float> @reverse_nxv16f32(<vscale x 16 x float> %a) {
; CHECK-LABEL: reverse_nxv16f32: ; CHECK-LABEL: reverse_nxv16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1 ; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vrsub.vx v24, v16, a0 ; CHECK-NEXT: vrsub.vx v24, v16, a0
; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vrgather.vv v16, v8, v24
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 16 x float> @llvm.experimental.vector.reverse.nxv16f32(<vscale x 16 x float> %a) %res = call <vscale x 16 x float> @llvm.experimental.vector.reverse.nxv16f32(<vscale x 16 x float> %a)
ret <vscale x 16 x float> %res ret <vscale x 16 x float> %res
} }
define <vscale x 1 x double> @reverse_nxv1f64(<vscale x 1 x double> %a) { define <vscale x 1 x double> @reverse_nxv1f64(<vscale x 1 x double> %a) {
; CHECK-LABEL: reverse_nxv1f64: ; CHECK-LABEL: reverse_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vrsub.vx v10, v9, a0 ; CHECK-NEXT: vrsub.vx v10, v9, a0
; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vrgather.vv v9, v8, v10
; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: vmv.v.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 1 x double> @llvm.experimental.vector.reverse.nxv1f64(<vscale x 1 x double> %a) %res = call <vscale x 1 x double> @llvm.experimental.vector.reverse.nxv1f64(<vscale x 1 x double> %a)
ret <vscale x 1 x double> %res ret <vscale x 1 x double> %res
} }
define <vscale x 2 x double> @reverse_nxv2f64(<vscale x 2 x double> %a) { define <vscale x 2 x double> @reverse_nxv2f64(<vscale x 2 x double> %a) {
; CHECK-LABEL: reverse_nxv2f64: ; CHECK-LABEL: reverse_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vrsub.vx v12, v10, a0 ; CHECK-NEXT: vrsub.vx v12, v10, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 2 x double> @llvm.experimental.vector.reverse.nxv2f64(<vscale x 2 x double> %a) %res = call <vscale x 2 x double> @llvm.experimental.vector.reverse.nxv2f64(<vscale x 2 x double> %a)
ret <vscale x 2 x double> %res ret <vscale x 2 x double> %res
} }
define <vscale x 4 x double> @reverse_nxv4f64(<vscale x 4 x double> %a) { define <vscale x 4 x double> @reverse_nxv4f64(<vscale x 4 x double> %a) {
; CHECK-LABEL: reverse_nxv4f64: ; CHECK-LABEL: reverse_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vrsub.vx v16, v12, a0 ; CHECK-NEXT: vrsub.vx v16, v12, a0
; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vrgather.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x double> @llvm.experimental.vector.reverse.nxv4f64(<vscale x 4 x double> %a) %res = call <vscale x 4 x double> @llvm.experimental.vector.reverse.nxv4f64(<vscale x 4 x double> %a)
ret <vscale x 4 x double> %res ret <vscale x 4 x double> %res
} }
Show All 12 Lines; CHECK-NEXT: ret
ret <vscale x 8 x double> %res ret <vscale x 8 x double> %res
} }
; Test widen reverse vector ; Test widen reverse vector
define <vscale x 3 x i64> @reverse_nxv3i64(<vscale x 3 x i64> %a) { define <vscale x 3 x i64> @reverse_nxv3i64(<vscale x 3 x i64> %a) {
; CHECK-LABEL: reverse_nxv3i64: ; CHECK-LABEL: reverse_nxv3i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vrsub.vx v12, v12, a0 ; CHECK-NEXT: vrsub.vx v12, v12, a0
; CHECK-NEXT: vrgather.vv v16, v8, v12 ; CHECK-NEXT: vrgather.vv v16, v8, v12
; CHECK-NEXT: vmv1r.v v8, v17 ; CHECK-NEXT: vmv1r.v v8, v17
; CHECK-NEXT: vmv1r.v v9, v18 ; CHECK-NEXT: vmv1r.v v9, v18
; CHECK-NEXT: vmv1r.v v10, v19 ; CHECK-NEXT: vmv1r.v v10, v19
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 3 x i64> @llvm.experimental.vector.reverse.nxv3i64(<vscale x 3 x i64> %a) %res = call <vscale x 3 x i64> @llvm.experimental.vector.reverse.nxv3i64(<vscale x 3 x i64> %a)
ret <vscale x 3 x i64> %res ret <vscale x 3 x i64> %res
▲ Show 20 Lines • Show All 285 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll

Show All 9 Linesdefine <vscale x 1 x double> @foo(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x double> %z, <vscale x 1 x i1> %m, i32 %vl) {
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v9 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v9
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 32 ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 32
; CHECK-NEXT: [[SRLI:%[0-9]+]]:gprnox0 = SRLI killed [[SLLI]], 32 ; CHECK-NEXT: [[SRLI:%[0-9]+]]:gprnox0 = SRLI killed [[SLLI]], 32
; CHECK-NEXT: $v0 = COPY [[COPY1]] ; CHECK-NEXT: $v0 = COPY [[COPY1]]
; CHECK-NEXT: [[DEF:%[0-9]+]]:vrnov0 = IMPLICIT_DEF ; CHECK-NEXT: [[PseudoVFMUL_VV_M1_MASK:%[0-9]+]]:vrnov0 = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFMUL_VV_M1_MASK $noreg, [[COPY3]], [[COPY2]], $v0, 7, killed [[SRLI]], 6 /* e64 */, 1 /* ta, mu */, implicit $frm
; CHECK-NEXT: [[PseudoVFMUL_VV_M1_MASK:%[0-9]+]]:vrnov0 = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFMUL_VV_M1_MASK [[DEF]], [[COPY3]], [[COPY2]], $v0, 7, killed [[SRLI]], 6 /* e64 */, 1 /* ta, mu */
; CHECK-NEXT: $v8 = COPY [[PseudoVFMUL_VV_M1_MASK]] ; CHECK-NEXT: $v8 = COPY [[PseudoVFMUL_VV_M1_MASK]]
; CHECK-NEXT: PseudoRET implicit $v8 ; CHECK-NEXT: PseudoRET implicit $v8
%1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl) %1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl)
ret <vscale x 1 x double> %1 ret <vscale x 1 x double> %1
} }

llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll

Show All 15 Lines
; SPILL-O0-NEXT: sub sp, sp, a1 ; SPILL-O0-NEXT: sub sp, sp, a1
; SPILL-O0-NEXT: sw a0, 8(sp) # 4-byte Folded Spill ; SPILL-O0-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
; SPILL-O0-NEXT: vmv1r.v v10, v9 ; SPILL-O0-NEXT: vmv1r.v v10, v9
; SPILL-O0-NEXT: vmv1r.v v9, v8 ; SPILL-O0-NEXT: vmv1r.v v9, v8
; SPILL-O0-NEXT: csrr a1, vlenb ; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1 ; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 16 ; SPILL-O0-NEXT: addi a1, a1, 16
; SPILL-O0-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill ; SPILL-O0-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vfadd.vv v8, v9, v10 ; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
; SPILL-O0-NEXT: addi a0, sp, 16 ; SPILL-O0-NEXT: addi a0, sp, 16
; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: lui a0, %hi(.L.str) ; SPILL-O0-NEXT: lui a0, %hi(.L.str)
; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str) ; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str)
; SPILL-O0-NEXT: call puts@plt ; SPILL-O0-NEXT: call puts@plt
; SPILL-O0-NEXT: addi a1, sp, 16 ; SPILL-O0-NEXT: addi a1, sp, 16
; SPILL-O0-NEXT: vl1r.v v10, (a1) # Unknown-size Folded Reload ; SPILL-O0-NEXT: vl1r.v v10, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: csrr a1, vlenb ; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1 ; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 16 ; SPILL-O0-NEXT: addi a1, a1, 16
; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload ; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: # kill: def $x11 killed $x10 ; SPILL-O0-NEXT: # kill: def $x11 killed $x10
; SPILL-O0-NEXT: lw a0, 8(sp) # 4-byte Folded Reload ; SPILL-O0-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vfadd.vv v8, v9, v10 ; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
; SPILL-O0-NEXT: csrr a0, vlenb ; SPILL-O0-NEXT: csrr a0, vlenb
; SPILL-O0-NEXT: slli a0, a0, 1 ; SPILL-O0-NEXT: slli a0, a0, 1
; SPILL-O0-NEXT: add sp, sp, a0 ; SPILL-O0-NEXT: add sp, sp, a0
; SPILL-O0-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; SPILL-O0-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; SPILL-O0-NEXT: addi sp, sp, 32 ; SPILL-O0-NEXT: addi sp, sp, 32
; SPILL-O0-NEXT: ret ; SPILL-O0-NEXT: ret
; ;
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll

Show All 18 Lines
; SPILL-O0-NEXT: sub sp, sp, a1 ; SPILL-O0-NEXT: sub sp, sp, a1
; SPILL-O0-NEXT: sd a0, 16(sp) # 8-byte Folded Spill ; SPILL-O0-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
; SPILL-O0-NEXT: vmv1r.v v10, v9 ; SPILL-O0-NEXT: vmv1r.v v10, v9
; SPILL-O0-NEXT: vmv1r.v v9, v8 ; SPILL-O0-NEXT: vmv1r.v v9, v8
; SPILL-O0-NEXT: csrr a1, vlenb ; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1 ; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 32 ; SPILL-O0-NEXT: addi a1, a1, 32
; SPILL-O0-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill ; SPILL-O0-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vfadd.vv v8, v9, v10 ; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
; SPILL-O0-NEXT: addi a0, sp, 32 ; SPILL-O0-NEXT: addi a0, sp, 32
; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: lui a0, %hi(.L.str) ; SPILL-O0-NEXT: lui a0, %hi(.L.str)
; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str) ; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str)
; SPILL-O0-NEXT: call puts@plt ; SPILL-O0-NEXT: call puts@plt
; SPILL-O0-NEXT: addi a1, sp, 32 ; SPILL-O0-NEXT: addi a1, sp, 32
; SPILL-O0-NEXT: vl1r.v v10, (a1) # Unknown-size Folded Reload ; SPILL-O0-NEXT: vl1r.v v10, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: csrr a1, vlenb ; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1 ; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 32 ; SPILL-O0-NEXT: addi a1, a1, 32
; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload ; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: # kill: def $x11 killed $x10 ; SPILL-O0-NEXT: # kill: def $x11 killed $x10
; SPILL-O0-NEXT: ld a0, 16(sp) # 8-byte Folded Reload ; SPILL-O0-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vfadd.vv v8, v9, v10 ; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
; SPILL-O0-NEXT: csrr a0, vlenb ; SPILL-O0-NEXT: csrr a0, vlenb
; SPILL-O0-NEXT: slli a0, a0, 1 ; SPILL-O0-NEXT: slli a0, a0, 1
; SPILL-O0-NEXT: add sp, sp, a0 ; SPILL-O0-NEXT: add sp, sp, a0
; SPILL-O0-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; SPILL-O0-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; SPILL-O0-NEXT: addi sp, sp, 48 ; SPILL-O0-NEXT: addi sp, sp, 48
; SPILL-O0-NEXT: ret ; SPILL-O0-NEXT: ret
; ;
▲ Show 20 Lines • Show All 72 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll

Show First 20 Lines • Show All 931 Lines • ▼ Show 20 Lines
; Folding this would create a loop in the DAG becuase the chain from the VLE is ; Folding this would create a loop in the DAG becuase the chain from the VLE is
; used by the vssubu. ; used by the vssubu.
define void @test_dag_loop() { define void @test_dag_loop() {
; CHECK-LABEL: test_dag_loop: ; CHECK-LABEL: test_dag_loop:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, m8, ta, ma
; CHECK-NEXT: vle16.v v8, (zero) ; CHECK-NEXT: vle16.v v8, (zero)
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vmclr.m v0 ; CHECK-NEXT: vmclr.m v0
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetivli zero, 0, e8, m4, tu, mu ; CHECK-NEXT: vsetivli zero, 0, e8, m4, tu, mu
; CHECK-NEXT: vmv4r.v v20, v16 ; CHECK-NEXT: vmv4r.v v20, v16
; CHECK-NEXT: vssubu.vx v20, v16, zero, v0.t ; CHECK-NEXT: vssubu.vx v20, v16, zero, v0.t
; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e8, m4, ta, ma
; CHECK-NEXT: vmseq.vv v0, v20, v16 ; CHECK-NEXT: vmseq.vv v0, v20, v16
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0 ; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: vsetivli zero, 1, e16, m8, tu, ma ; CHECK-NEXT: vsetivli zero, 1, e16, m8, tu, ma
▲ Show 20 Lines • Show All 118 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/setcc-fp-vp.ll

Show First 20 Lines • Show All 228 Lines • ▼ Show 20 Lines
} }
define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_nxv1f16: ; CHECK-LABEL: fcmp_ord_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v8, v9 ; CHECK-NEXT: vmand.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f16: ; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v9, v8 ; CHECK-NEXT: vmand.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
▲ Show 20 Lines • Show All 232 Lines • ▼ Show 20 Lines
} }
define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_nxv1f16: ; CHECK-LABEL: fcmp_uno_vf_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v8, v9 ; CHECK-NEXT: vmor.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f16(<vscale x 1 x half> %va, half %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f16: ; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f16(<vscale x 1 x half> %vb, <vscale x 1 x half> %va, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
▲ Show 20 Lines • Show All 249 Lines • ▼ Show 20 Lines
} }
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_nxv8f16: ; CHECK-LABEL: fcmp_ord_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v12, v10, fa0, v0.t
; CHECK-NEXT: vmfeq.vf v8, v10, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v10, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v12, v8 ; CHECK-NEXT: vmand.mm v0, v10, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f16: ; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfeq.vv v12, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v12, v10, fa0, v0.t
; CHECK-NEXT: vmfeq.vf v8, v10, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v10, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v8, v12 ; CHECK-NEXT: vmand.mm v0, v12, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 234 Lines • ▼ Show 20 Lines
} }
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_nxv8f16: ; CHECK-LABEL: fcmp_uno_vf_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfne.vv v12, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v12, v10, fa0, v0.t
; CHECK-NEXT: vmfne.vf v8, v10, fa0, v0.t ; CHECK-NEXT: vmfne.vv v10, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v12, v8 ; CHECK-NEXT: vmor.mm v0, v10, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f16(<vscale x 8 x half> %va, half %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f16: ; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.v.f v10, fa0 ; CHECK-NEXT: vfmv.v.f v10, fa0
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vmfne.vv v12, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v12, v10, fa0, v0.t
; CHECK-NEXT: vmfne.vf v8, v10, fa0, v0.t ; CHECK-NEXT: vmfne.vv v10, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v8, v12 ; CHECK-NEXT: vmor.mm v0, v12, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0 %elt.head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %va, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
declare <vscale x 64 x i1> @llvm.vp.fcmp.nxv64f16(<vscale x 64 x half>, <vscale x 64 x half>, metadata, <vscale x 64 x i1>, i32) declare <vscale x 64 x i1> @llvm.vp.fcmp.nxv64f16(<vscale x 64 x half>, <vscale x 64 x half>, metadata, <vscale x 64 x i1>, i32)
▲ Show 20 Lines • Show All 282 Lines • ▼ Show 20 Lines
} }
define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ord_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_nxv1f64: ; CHECK-LABEL: fcmp_ord_vf_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v8, v9 ; CHECK-NEXT: vmand.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_ord_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f64: ; CHECK-LABEL: fcmp_ord_vf_swap_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfeq.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfeq.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v9, v8 ; CHECK-NEXT: vmand.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"ord", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
▲ Show 20 Lines • Show All 232 Lines • ▼ Show 20 Lines
} }
define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uno_vf_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_nxv1f64: ; CHECK-LABEL: fcmp_uno_vf_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v8, v9 ; CHECK-NEXT: vmor.mm v0, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) { define <vscale x 1 x i1> @fcmp_uno_vf_swap_nxv1f64(<vscale x 1 x double> %va, double %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f64: ; CHECK-LABEL: fcmp_uno_vf_swap_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vfmv.v.f v9, fa0 ; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t ; CHECK-NEXT: vmfne.vf v9, v9, fa0, v0.t
; CHECK-NEXT: vmfne.vv v8, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v9, v8 ; CHECK-NEXT: vmor.mm v0, v9, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 1 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer %vb = shufflevector <vscale x 1 x double> %elt.head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl) %v = call <vscale x 1 x i1> @llvm.vp.fcmp.nxv1f64(<vscale x 1 x double> %vb, <vscale x 1 x double> %va, metadata !"uno", <vscale x 1 x i1> %m, i32 %evl)
ret <vscale x 1 x i1> %v ret <vscale x 1 x i1> %v
} }
▲ Show 20 Lines • Show All 250 Lines • ▼ Show 20 Lines
} }
define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ord_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_nxv8f64: ; CHECK-LABEL: fcmp_ord_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmv.v.f v16, fa0 ; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v24, v16, fa0, v0.t
; CHECK-NEXT: vmfeq.vf v8, v16, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v24, v8 ; CHECK-NEXT: vmand.mm v0, v16, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ord_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f64: ; CHECK-LABEL: fcmp_ord_vf_swap_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmv.v.f v16, fa0 ; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfeq.vv v24, v8, v8, v0.t ; CHECK-NEXT: vmfeq.vf v24, v16, fa0, v0.t
; CHECK-NEXT: vmfeq.vf v8, v16, fa0, v0.t ; CHECK-NEXT: vmfeq.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmand.mm v0, v8, v24 ; CHECK-NEXT: vmand.mm v0, v24, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"ord", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_ueq_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x i1> %m, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 234 Lines • ▼ Show 20 Lines
} }
define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uno_vf_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_nxv8f64: ; CHECK-LABEL: fcmp_uno_vf_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmv.v.f v16, fa0 ; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfne.vv v24, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v24, v16, fa0, v0.t
; CHECK-NEXT: vmfne.vf v8, v16, fa0, v0.t ; CHECK-NEXT: vmfne.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v24, v8 ; CHECK-NEXT: vmor.mm v0, v16, v24
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) { define <vscale x 8 x i1> @fcmp_uno_vf_swap_nxv8f64(<vscale x 8 x double> %va, double %b, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f64: ; CHECK-LABEL: fcmp_uno_vf_swap_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-NEXT: vfmv.v.f v16, fa0 ; CHECK-NEXT: vfmv.v.f v16, fa0
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmfne.vv v24, v8, v8, v0.t ; CHECK-NEXT: vmfne.vf v24, v16, fa0, v0.t
; CHECK-NEXT: vmfne.vf v8, v16, fa0, v0.t ; CHECK-NEXT: vmfne.vv v16, v8, v8, v0.t
; CHECK-NEXT: vmor.mm v0, v8, v24 ; CHECK-NEXT: vmor.mm v0, v24, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0 %elt.head = insertelement <vscale x 8 x double> poison, double %b, i32 0
%vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer %vb = shufflevector <vscale x 8 x double> %elt.head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl) %v = call <vscale x 8 x i1> @llvm.vp.fcmp.nxv8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %va, metadata !"uno", <vscale x 8 x i1> %m, i32 %evl)
ret <vscale x 8 x i1> %v ret <vscale x 8 x i1> %v
} }
declare <vscale x 32 x i1> @llvm.vp.fcmp.nxv32f64(<vscale x 32 x double>, <vscale x 32 x double>, metadata, <vscale x 32 x i1>, i32) declare <vscale x 32 x i1> @llvm.vp.fcmp.nxv32f64(<vscale x 32 x double>, <vscale x 32 x double>, metadata, <vscale x 32 x i1>, i32)
Show All 16 Lines
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a3, 40 ; CHECK-NEXT: li a3, 40
; CHECK-NEXT: mul a1, a1, a3 ; CHECK-NEXT: mul a1, a1, a3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul t0, a3, a1
; CHECK-NEXT: slli t2, a3, 3
; CHECK-NEXT: srli a4, a3, 2 ; CHECK-NEXT: srli a4, a3, 2
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v1, v0, a4 ; CHECK-NEXT: vslidedown.vx v1, v0, a4
; CHECK-NEXT: srli a1, a3, 3 ; CHECK-NEXT: srli a1, a3, 3
; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a1 ; CHECK-NEXT: add a5, a2, t2
; CHECK-NEXT: li a5, 24 ; CHECK-NEXT: vl8re64.v v8, (a5)
; CHECK-NEXT: slli t1, a3, 3 ; CHECK-NEXT: slli t3, a3, 4
; CHECK-NEXT: add a7, a2, t1
; CHECK-NEXT: vl8re64.v v8, (a7)
; CHECK-NEXT: mul t0, a3, a5
; CHECK-NEXT: slli a5, a3, 1 ; CHECK-NEXT: slli a5, a3, 1
; CHECK-NEXT: slli t2, a3, 4 ; CHECK-NEXT: vslidedown.vx v0, v0, a1
; CHECK-NEXT: mv a7, a6 ; CHECK-NEXT: mv a7, a6
; CHECK-NEXT: bltu a6, a5, .LBB171_2 ; CHECK-NEXT: bltu a6, a5, .LBB171_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a7, a5 ; CHECK-NEXT: mv a7, a5
; CHECK-NEXT: .LBB171_2: ; CHECK-NEXT: .LBB171_2:
; CHECK-NEXT: add t0, a2, t0 ; CHECK-NEXT: add t1, a2, t0
; CHECK-NEXT: add t1, a0, t1 ; CHECK-NEXT: add t2, a0, t2
; CHECK-NEXT: add t2, a2, t2 ; CHECK-NEXT: add t0, a2, t3
; CHECK-NEXT: vl8re64.v v16, (a2) ; CHECK-NEXT: vl8re64.v v16, (a2)
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 4 ; CHECK-NEXT: slli a2, a2, 4
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: sub a2, a7, a3 ; CHECK-NEXT: sub a2, a7, a3
; CHECK-NEXT: sltu t3, a7, a2 ; CHECK-NEXT: sltu t3, a7, a2
; CHECK-NEXT: addi t3, t3, -1 ; CHECK-NEXT: addi t3, t3, -1
; CHECK-NEXT: and a2, t3, a2 ; CHECK-NEXT: and a2, t3, a2
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 5 ; CHECK-NEXT: slli a2, a2, 5
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vmfeq.vv v2, v16, v8, v0.t ; CHECK-NEXT: vmfeq.vv v2, v16, v8, v0.t
; CHECK-NEXT: bltu a7, a3, .LBB171_4 ; CHECK-NEXT: bltu a7, a3, .LBB171_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a7, a3 ; CHECK-NEXT: mv a7, a3
; CHECK-NEXT: .LBB171_4: ; CHECK-NEXT: .LBB171_4:
; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, ma ; CHECK-NEXT: vl8re64.v v8, (t1)
; CHECK-NEXT: vslidedown.vx v17, v1, a1
; CHECK-NEXT: vl8re64.v v8, (t0)
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 5 ; CHECK-NEXT: slli a2, a2, 5
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: vl8re64.v v8, (t1) ; CHECK-NEXT: vl8re64.v v8, (t2)
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: li t0, 24 ; CHECK-NEXT: li t1, 24
; CHECK-NEXT: mul a2, a2, t0 ; CHECK-NEXT: mul a2, a2, t1
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: vl8re64.v v8, (t2) ; CHECK-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v18, v1, a1
; CHECK-NEXT: vl8re64.v v8, (t0)
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; CHECK-NEXT: vl8re64.v v8, (a0) ; CHECK-NEXT: vl8re64.v v8, (a0)
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli zero, a7, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a2, 40 ; CHECK-NEXT: li a2, 40
; CHECK-NEXT: mul a0, a0, a2 ; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmfeq.vv v18, v24, v8, v0.t ; CHECK-NEXT: vmfeq.vv v17, v24, v8, v0.t
; CHECK-NEXT: add a0, a1, a1 ; CHECK-NEXT: add a0, a1, a1
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
; CHECK-NEXT: sub a0, a6, a5 ; CHECK-NEXT: sub a0, a6, a5
; CHECK-NEXT: sltu a2, a6, a0 ; CHECK-NEXT: sltu a2, a6, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a0, a2, a0 ; CHECK-NEXT: and a0, a2, a0
; CHECK-NEXT: vslideup.vx v18, v2, a1 ; CHECK-NEXT: vslideup.vx v17, v2, a1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: mv a2, a0
; CHECK-NEXT: bltu a0, a3, .LBB171_6 ; CHECK-NEXT: bltu a0, a3, .LBB171_6
; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB171_6: ; CHECK-NEXT: .LBB171_6:
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: slli a2, a2, 3
; CHECK-NEXT: add a2, sp, a2 ; CHECK-NEXT: add a2, sp, a2
; CHECK-NEXT: addi a2, a2, 16 ; CHECK-NEXT: addi a2, a2, 16
; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: addi a2, sp, 16 ; CHECK-NEXT: addi a2, sp, 16
; CHECK-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload
; CHECK-NEXT: vmfeq.vv v16, v24, v8, v0.t ; CHECK-NEXT: vmfeq.vv v16, v24, v8, v0.t
; CHECK-NEXT: add a2, a4, a1 ; CHECK-NEXT: add a2, a4, a1
; CHECK-NEXT: vsetvli zero, a2, e8, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a2, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v18, v16, a4 ; CHECK-NEXT: vslideup.vx v17, v16, a4
; CHECK-NEXT: sub a2, a0, a3 ; CHECK-NEXT: sub a2, a0, a3
; CHECK-NEXT: sltu a0, a0, a2 ; CHECK-NEXT: sltu a0, a0, a2
; CHECK-NEXT: addi a0, a0, -1 ; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a2 ; CHECK-NEXT: and a0, a0, a2
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v17 ; CHECK-NEXT: vmv1r.v v0, v18
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5 ; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a2, 24 ; CHECK-NEXT: li a2, 24
; CHECK-NEXT: mul a0, a0, a2 ; CHECK-NEXT: mul a0, a0, a2
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmfeq.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmfeq.vv v16, v8, v24, v0.t
; CHECK-NEXT: slli a0, a1, 1 ; CHECK-NEXT: slli a0, a1, 1
; CHECK-NEXT: add a0, a0, a1 ; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vx v18, v16, a0 ; CHECK-NEXT: vslideup.vx v17, v16, a0
; CHECK-NEXT: vmv1r.v v0, v18 ; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 48 ; CHECK-NEXT: li a1, 48
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = call <vscale x 32 x i1> @llvm.vp.fcmp.nxv32f64(<vscale x 32 x double> %va, <vscale x 32 x double> %vb, metadata !"oeq", <vscale x 32 x i1> %m, i32 %evl) %v = call <vscale x 32 x i1> @llvm.vp.fcmp.nxv32f64(<vscale x 32 x double> %va, <vscale x 32 x double> %vb, metadata !"oeq", <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i1> %v ret <vscale x 32 x i1> %v
} }

llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll

Show First 20 Lines • Show All 1,158 Lines • ▼ Show 20 Lines
; CHECK-LABEL: icmp_eq_vv_nxv128i8: ; CHECK-LABEL: icmp_eq_vv_nxv128i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: vmv1r.v v2, v0 ; CHECK-NEXT: vmv1r.v v24, v0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a2, a0, a1 ; CHECK-NEXT: add a4, a0, a1
; CHECK-NEXT: vl8r.v v8, (a2) ; CHECK-NEXT: vl8r.v v8, (a4)
; CHECK-NEXT: sub a2, a3, a1 ; CHECK-NEXT: vl8r.v v0, (a0)
; CHECK-NEXT: sltu a4, a3, a2
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: vl8r.v v24, (a0)
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: and a2, a4, a2 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, ma ; CHECK-NEXT: sub a0, a3, a1
; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: sltu a2, a3, a0
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a0, a2, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma
; CHECK-NEXT: vmseq.vv v1, v16, v8, v0.t ; CHECK-NEXT: vmseq.vv v1, v16, v8, v0.t
; CHECK-NEXT: bltu a3, a1, .LBB96_2 ; CHECK-NEXT: bltu a3, a1, .LBB96_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: .LBB96_2: ; CHECK-NEXT: .LBB96_2:
; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v2 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmseq.vv v16, v8, v24, v0.t ; CHECK-NEXT: vmseq.vv v16, v8, v24, v0.t
▲ Show 20 Lines • Show All 2,929 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll

Show First 20 Lines • Show All 250 Lines • ▼ Show 20 Lines
define <32 x i16> @v16i16_2(<16 x i16> %a, <16 x i16> %b) { define <32 x i16> @v16i16_2(<16 x i16> %a, <16 x i16> %b) {
; RV32-LABEL: v16i16_2: ; RV32-LABEL: v16i16_2:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: lui a0, %hi(.LCPI15_0) ; RV32-NEXT: lui a0, %hi(.LCPI15_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI15_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI15_0)
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; RV32-NEXT: vle16.v v20, (a0) ; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vmv2r.v v16, v10 ; RV32-NEXT: vmv2r.v v20, v10
; RV32-NEXT: vmv2r.v v12, v8 ; RV32-NEXT: vrgather.vv v12, v8, v16
; RV32-NEXT: vrgather.vv v8, v12, v20 ; RV32-NEXT: vid.v v8
; RV32-NEXT: vid.v v12 ; RV32-NEXT: vrsub.vi v8, v8, 15
; RV32-NEXT: vrsub.vi v12, v12, 15
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -1 ; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; RV32-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; RV32-NEXT: vrgather.vv v8, v16, v12, v0.t ; RV32-NEXT: vrgather.vv v12, v20, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: v16i16_2: ; RV64-LABEL: v16i16_2:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, %hi(.LCPI15_0) ; RV64-NEXT: lui a0, %hi(.LCPI15_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI15_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI15_0)
; RV64-NEXT: li a1, 32 ; RV64-NEXT: li a1, 32
; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, ma
; RV64-NEXT: vle16.v v20, (a0) ; RV64-NEXT: vle16.v v16, (a0)
; RV64-NEXT: vmv2r.v v16, v10 ; RV64-NEXT: vmv2r.v v20, v10
; RV64-NEXT: vmv2r.v v12, v8 ; RV64-NEXT: vrgather.vv v12, v8, v16
; RV64-NEXT: vrgather.vv v8, v12, v20 ; RV64-NEXT: vid.v v8
; RV64-NEXT: vid.v v12 ; RV64-NEXT: vrsub.vi v8, v8, 15
; RV64-NEXT: vrsub.vi v12, v12, 15
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -1 ; RV64-NEXT: addiw a0, a0, -1
; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV64-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; RV64-NEXT: vsetvli zero, a1, e16, m4, ta, mu
; RV64-NEXT: vrgather.vv v8, v16, v12, v0.t ; RV64-NEXT: vrgather.vv v12, v20, v8, v0.t
; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%v32i16 = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v32i16 = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 31, i32 30, i32 29, i32 28, i32 27, i32 26, i32 25, i32 24, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <32 x i16> %v32i16 ret <32 x i16> %v32i16
} }
define <2 x i32> @v2i32(<2 x i32> %a) { define <2 x i32> @v2i32(<2 x i32> %a) {
; CHECK-LABEL: v2i32: ; CHECK-LABEL: v2i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
▲ Show 20 Lines • Show All 193 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
ret <4 x i64> %v4i64 ret <4 x i64> %v4i64
} }
define <8 x i64> @v4i64_2(<4 x i64> %a, <4 x i64> %b) { define <8 x i64> @v4i64_2(<4 x i64> %a, <4 x i64> %b) {
; RV32-LABEL: v4i64_2: ; RV32-LABEL: v4i64_2:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv2r.v v16, v10 ; RV32-NEXT: vmv2r.v v16, v10
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vid.v v18 ; RV32-NEXT: vid.v v10
; RV32-NEXT: vrsub.vi v19, v18, 7 ; RV32-NEXT: vrsub.vi v11, v10, 7
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vrgatherei16.vv v12, v8, v19 ; RV32-NEXT: vrgatherei16.vv v12, v8, v11
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV32-NEXT: vrsub.vi v8, v18, 3 ; RV32-NEXT: vrsub.vi v8, v10, 3
; RV32-NEXT: vmv.v.i v0, 15 ; RV32-NEXT: vmv.v.i v0, 15
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t ; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: v4i64_2: ; RV64-LABEL: v4i64_2:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 272 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
ret <4 x double> %v4f64 ret <4 x double> %v4f64
} }
define <8 x double> @v4f64_2(<4 x double> %a, <4 x double> %b) { define <8 x double> @v4f64_2(<4 x double> %a, <4 x double> %b) {
; RV32-LABEL: v4f64_2: ; RV32-LABEL: v4f64_2:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv2r.v v16, v10 ; RV32-NEXT: vmv2r.v v16, v10
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vid.v v18 ; RV32-NEXT: vid.v v10
; RV32-NEXT: vrsub.vi v19, v18, 7 ; RV32-NEXT: vrsub.vi v11, v10, 7
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vrgatherei16.vv v12, v8, v19 ; RV32-NEXT: vrgatherei16.vv v12, v8, v11
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV32-NEXT: vrsub.vi v8, v18, 3 ; RV32-NEXT: vrsub.vi v8, v10, 3
; RV32-NEXT: vmv.v.i v0, 15 ; RV32-NEXT: vmv.v.i v0, 15
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t ; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: v4f64_2: ; RV64-LABEL: v4f64_2:
; RV64: # %bb.0: ; RV64: # %bb.0:
Show All 31 Lines

llvm/test/CodeGen/RISCV/rvv/splat-vector-split-i64-vl-sdnode.ll

Show All 30 Lines
; CHECK-NEXT: sw a0, 8(sp) ; CHECK-NEXT: sw a0, 8(sp)
; CHECK-NEXT: li a0, 56 ; CHECK-NEXT: li a0, 56
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-NEXT: vsrl.vx v10, v8, a0 ; CHECK-NEXT: vsrl.vx v10, v8, a0
; CHECK-NEXT: li a1, 40 ; CHECK-NEXT: li a1, 40
; CHECK-NEXT: vsrl.vx v12, v8, a1 ; CHECK-NEXT: vsrl.vx v12, v8, a1
; CHECK-NEXT: lui a2, 16 ; CHECK-NEXT: lui a2, 16
; CHECK-NEXT: addi a2, a2, -256 ; CHECK-NEXT: addi a2, a2, -256
; CHECK-NEXT: mv a3, sp
; CHECK-NEXT: vlse64.v v14, (a3), zero
; CHECK-NEXT: vand.vx v12, v12, a2 ; CHECK-NEXT: vand.vx v12, v12, a2
; CHECK-NEXT: vor.vv v10, v12, v10 ; CHECK-NEXT: vor.vv v10, v12, v10
; CHECK-NEXT: vsrl.vi v12, v8, 8 ; CHECK-NEXT: vsrl.vi v12, v8, 24
; CHECK-NEXT: vand.vv v12, v12, v14 ; CHECK-NEXT: mv a3, sp
; CHECK-NEXT: vsrl.vi v16, v8, 24 ; CHECK-NEXT: vlse64.v v14, (a3), zero
; CHECK-NEXT: lui a3, 4080 ; CHECK-NEXT: lui a3, 4080
; CHECK-NEXT: vand.vx v16, v16, a3 ; CHECK-NEXT: vand.vx v12, v12, a3
; CHECK-NEXT: vor.vv v12, v12, v16 ; CHECK-NEXT: vsrl.vi v16, v8, 8
; CHECK-NEXT: vand.vv v16, v16, v14
; CHECK-NEXT: vor.vv v12, v16, v12
; CHECK-NEXT: vor.vv v10, v12, v10 ; CHECK-NEXT: vor.vv v10, v12, v10
; CHECK-NEXT: vand.vv v12, v8, v14 ; CHECK-NEXT: vand.vv v12, v8, v14
; CHECK-NEXT: vsll.vi v12, v12, 8 ; CHECK-NEXT: vsll.vi v12, v12, 8
; CHECK-NEXT: vand.vx v14, v8, a3 ; CHECK-NEXT: vand.vx v14, v8, a3
; CHECK-NEXT: vsll.vi v14, v14, 24 ; CHECK-NEXT: vsll.vi v14, v14, 24
; CHECK-NEXT: vor.vv v12, v14, v12 ; CHECK-NEXT: vor.vv v12, v14, v12
; CHECK-NEXT: vsll.vx v14, v8, a0 ; CHECK-NEXT: vsll.vx v14, v8, a0
; CHECK-NEXT: vand.vx v8, v8, a2 ; CHECK-NEXT: vand.vx v8, v8, a2
Show All 36 Lines

llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
declare <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64>, <2 x i64>) declare <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64>, <2 x i64>)
declare <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>) declare <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>)
declare <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16>, <8 x i16>) declare <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16>, <8 x i16>)
declare <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8>, <16 x i8>) declare <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8>, <16 x i8>)
define <2 x i64> @vec_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { define <2 x i64> @vec_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; CHECK-LABEL: vec_v2i64: ; CHECK-LABEL: vec_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vsll.vv v10, v8, v9 ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vmsne.vv v9, v8, v9
; CHECK-NEXT: li a0, -1 ; CHECK-NEXT: li a0, -1
; CHECK-NEXT: srli a1, a0, 1 ; CHECK-NEXT: srli a1, a0, 1
; CHECK-NEXT: vmv.v.x v11, a1 ; CHECK-NEXT: vsll.vv v10, v8, v9
; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: slli a0, a0, 63 ; CHECK-NEXT: slli a0, a0, 63
; CHECK-NEXT: vmerge.vxm v8, v11, a0, v0 ; CHECK-NEXT: vmerge.vxm v9, v9, a0, v0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64> %x, <2 x i64> %y) %tmp = call <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %tmp ret <2 x i64> %tmp
} }
define <4 x i32> @vec_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @vec_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec_v4i32: ; CHECK-LABEL: vec_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vsll.vv v10, v8, v9 ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vmsne.vv v9, v8, v9
; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addiw a0, a0, -1 ; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vmv.v.x v11, a0 ; CHECK-NEXT: vsll.vv v10, v8, v9
; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: li a0, 1 ; CHECK-NEXT: li a0, 1
; CHECK-NEXT: slli a0, a0, 31 ; CHECK-NEXT: slli a0, a0, 31
; CHECK-NEXT: vmerge.vxm v8, v11, a0, v0 ; CHECK-NEXT: vmerge.vxm v9, v9, a0, v0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32> %x, <4 x i32> %y) %tmp = call <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
ret <4 x i32> %tmp ret <4 x i32> %tmp
} }
define <8 x i16> @vec_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind { define <8 x i16> @vec_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; CHECK-LABEL: vec_v8i16: ; CHECK-LABEL: vec_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vsll.vv v10, v8, v9 ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vmsne.vv v9, v8, v9
; CHECK-NEXT: lui a0, 8 ; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a1, a0, -1 ; CHECK-NEXT: addiw a1, a0, -1
; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: vsll.vv v10, v8, v9
; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vmerge.vxm v9, v9, a0, v0
; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16> %x, <8 x i16> %y) %tmp = call <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
ret <8 x i16> %tmp ret <8 x i16> %tmp
} }
define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind { define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: vec_v16i8: ; CHECK-LABEL: vec_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsll.vv v10, v8, v9 ; CHECK-NEXT: vsll.vv v10, v8, v9
; CHECK-NEXT: vsra.vv v9, v10, v9 ; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vmsne.vv v9, v8, v9 ; CHECK-NEXT: vmsne.vv v8, v8, v9
; CHECK-NEXT: li a0, 127 ; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vmv.v.x v11, a0
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 128 ; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vmerge.vxm v8, v11, a0, v0 ; CHECK-NEXT: vmerge.vxm v9, v9, a0, v0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8> %x, <16 x i8> %y) %tmp = call <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
ret <16 x i8> %tmp ret <16 x i8> %tmp
} }
declare <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) declare <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
declare <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) declare <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
declare <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) declare <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>) declare <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
define <vscale x 2 x i64> @vec_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) nounwind { define <vscale x 2 x i64> @vec_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) nounwind {
; CHECK-LABEL: vec_nxv2i64: ; CHECK-LABEL: vec_nxv2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: srli a1, a0, 1
; CHECK-NEXT: vsll.vv v12, v8, v10 ; CHECK-NEXT: vsll.vv v12, v8, v10
; CHECK-NEXT: vsra.vv v14, v12, v10 ; CHECK-NEXT: vsra.vv v14, v12, v10
; CHECK-NEXT: vmsne.vv v10, v8, v14 ; CHECK-NEXT: vmsne.vv v10, v8, v14
; CHECK-NEXT: li a0, -1 ; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: srli a1, a0, 1
; CHECK-NEXT: vmv.v.x v14, a1
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: slli a0, a0, 63 ; CHECK-NEXT: slli a0, a0, 63
; CHECK-NEXT: vmerge.vxm v8, v14, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) %tmp = call <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y)
ret <vscale x 2 x i64> %tmp ret <vscale x 2 x i64> %tmp
} }
define <vscale x 4 x i32> @vec_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) nounwind { define <vscale x 4 x i32> @vec_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) nounwind {
; CHECK-LABEL: vec_nxv4i32: ; CHECK-LABEL: vec_nxv4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vsll.vv v12, v8, v10 ; CHECK-NEXT: vsll.vv v12, v8, v10
; CHECK-NEXT: vsra.vv v14, v12, v10 ; CHECK-NEXT: vsra.vv v14, v12, v10
; CHECK-NEXT: vmsne.vv v10, v8, v14 ; CHECK-NEXT: vmsne.vv v10, v8, v14
; CHECK-NEXT: lui a0, 524288 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vmv.v.x v14, a0
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 1 ; CHECK-NEXT: li a0, 1
; CHECK-NEXT: slli a0, a0, 31 ; CHECK-NEXT: slli a0, a0, 31
; CHECK-NEXT: vmerge.vxm v8, v14, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y) %tmp = call <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y)
ret <vscale x 4 x i32> %tmp ret <vscale x 4 x i32> %tmp
} }
define <vscale x 8 x i16> @vec_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) nounwind { define <vscale x 8 x i16> @vec_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) nounwind {
; CHECK-LABEL: vec_nxv8i16: ; CHECK-LABEL: vec_nxv8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a1, a0, -1
; CHECK-NEXT: vsll.vv v12, v8, v10 ; CHECK-NEXT: vsll.vv v12, v8, v10
; CHECK-NEXT: vsra.vv v14, v12, v10 ; CHECK-NEXT: vsra.vv v14, v12, v10
; CHECK-NEXT: vmsne.vv v10, v8, v14 ; CHECK-NEXT: vmsne.vv v10, v8, v14
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a1, a0, -1
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmv.v.x v8, a1 ; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) %tmp = call <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y)
ret <vscale x 8 x i16> %tmp ret <vscale x 8 x i16> %tmp
} }
define <vscale x 16 x i8> @vec_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) nounwind { define <vscale x 16 x i8> @vec_nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) nounwind {
; CHECK-LABEL: vec_nxv16i8: ; CHECK-LABEL: vec_nxv16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsll.vv v12, v8, v10 ; CHECK-NEXT: vsll.vv v12, v8, v10
; CHECK-NEXT: vsra.vv v14, v12, v10 ; CHECK-NEXT: vsra.vv v14, v12, v10
; CHECK-NEXT: vmsne.vv v10, v8, v14 ; CHECK-NEXT: vmsne.vv v10, v8, v14
; CHECK-NEXT: li a0, 127 ; CHECK-NEXT: vmv.v.x v8, a0
; CHECK-NEXT: vmv.v.x v14, a0
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 128 ; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vmerge.vxm v8, v14, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v12, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y) %tmp = call <vscale x 16 x i8> @llvm.sshl.sat.nxv16i8(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y)
ret <vscale x 16 x i8> %tmp ret <vscale x 16 x i8> %tmp
} }

llvm/test/CodeGen/RISCV/rvv/stepvector.ll

Show First 20 Lines • Show All 556 Lines • ▼ Show 20 Lines
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vid.v v8 ; RV32-NEXT: vid.v v8
; RV32-NEXT: vadd.vv v16, v8, v16 ; RV32-NEXT: vadd.vv v16, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: stepvector_nxv16i64: ; RV64-LABEL: stepvector_nxv16i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64-NEXT: vid.v v8
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vid.v v8
; RV64-NEXT: vadd.vx v16, v8, a0 ; RV64-NEXT: vadd.vx v16, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() %v = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
ret <vscale x 16 x i64> %v ret <vscale x 16 x i64> %v
} }
define <vscale x 16 x i64> @add_stepvector_nxv16i64() { define <vscale x 16 x i64> @add_stepvector_nxv16i64() {
; RV32-LABEL: add_stepvector_nxv16i64: ; RV32-LABEL: add_stepvector_nxv16i64:
Show All 10 Lines
; RV32-NEXT: vid.v v8 ; RV32-NEXT: vid.v v8
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vadd.vv v16, v8, v16 ; RV32-NEXT: vadd.vv v16, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: add_stepvector_nxv16i64: ; RV64-LABEL: add_stepvector_nxv16i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64-NEXT: vid.v v8
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 1 ; RV64-NEXT: slli a0, a0, 1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vid.v v8
; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: vadd.vx v16, v8, a0 ; RV64-NEXT: vadd.vx v16, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%0 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() %0 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
%1 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() %1 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
%2 = add <vscale x 16 x i64> %0, %1 %2 = add <vscale x 16 x i64> %0, %1
ret <vscale x 16 x i64> %2 ret <vscale x 16 x i64> %2
} }
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; RV32-NEXT: vid.v v24 ; RV32-NEXT: vid.v v24
; RV32-NEXT: vmul.vv v8, v24, v8 ; RV32-NEXT: vmul.vv v8, v24, v8
; RV32-NEXT: vadd.vv v16, v8, v16 ; RV32-NEXT: vadd.vv v16, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mul_bigimm_stepvector_nxv16i64: ; RV64-LABEL: mul_bigimm_stepvector_nxv16i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: lui a1, 1987
; RV64-NEXT: addiw a1, a1, -731
; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -683
; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV64-NEXT: vid.v v8 ; RV64-NEXT: vid.v v8
; RV64-NEXT: lui a0, 1987 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: addiw a0, a0, -731
; RV64-NEXT: slli a0, a0, 12
; RV64-NEXT: addi a0, a0, -683
; RV64-NEXT: vmul.vx v8, v8, a0
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: mul a0, a1, a0
; RV64-NEXT: vadd.vx v16, v8, a0 ; RV64-NEXT: vadd.vx v16, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%0 = insertelement <vscale x 16 x i64> poison, i64 33333333333, i32 0 %0 = insertelement <vscale x 16 x i64> poison, i64 33333333333, i32 0
%1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer %1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer
%2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() %2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
%3 = mul <vscale x 16 x i64> %2, %1 %3 = mul <vscale x 16 x i64> %2, %1
ret <vscale x 16 x i64> %3 ret <vscale x 16 x i64> %3
Show All 14 Lines
; RV32-NEXT: vid.v v8 ; RV32-NEXT: vid.v v8
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vadd.vv v16, v8, v16 ; RV32-NEXT: vadd.vv v16, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: shl_stepvector_nxv16i64: ; RV64-LABEL: shl_stepvector_nxv16i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64-NEXT: vid.v v8
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 2 ; RV64-NEXT: slli a0, a0, 2
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vid.v v8
; RV64-NEXT: vsll.vi v8, v8, 2
; RV64-NEXT: vadd.vx v16, v8, a0 ; RV64-NEXT: vadd.vx v16, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%0 = insertelement <vscale x 16 x i64> poison, i64 2, i32 0 %0 = insertelement <vscale x 16 x i64> poison, i64 2, i32 0
%1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer %1 = shufflevector <vscale x 16 x i64> %0, <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer
%2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() %2 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
%3 = shl <vscale x 16 x i64> %2, %1 %3 = shl <vscale x 16 x i64> %2, %1
ret <vscale x 16 x i64> %3 ret <vscale x 16 x i64> %3
} }

llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll

Show First 20 Lines • Show All 765 Lines • ▼ Show 20 Lines
; CHECK-RV32-LABEL: strided_load_nxv16f64: ; CHECK-RV32-LABEL: strided_load_nxv16f64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vmv1r.v v8, v0 ; CHECK-RV32-NEXT: vmv1r.v v8, v0
; CHECK-RV32-NEXT: csrr a4, vlenb ; CHECK-RV32-NEXT: csrr a4, vlenb
; CHECK-RV32-NEXT: sub a2, a3, a4 ; CHECK-RV32-NEXT: sub a2, a3, a4
; CHECK-RV32-NEXT: sltu a5, a3, a2 ; CHECK-RV32-NEXT: sltu a5, a3, a2
; CHECK-RV32-NEXT: addi a5, a5, -1 ; CHECK-RV32-NEXT: addi a5, a5, -1
; CHECK-RV32-NEXT: and a2, a5, a2 ; CHECK-RV32-NEXT: and a2, a5, a2
; CHECK-RV32-NEXT: srli a5, a4, 3
; CHECK-RV32-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK-RV32-NEXT: vslidedown.vx v0, v0, a5
; CHECK-RV32-NEXT: bltu a3, a4, .LBB42_2 ; CHECK-RV32-NEXT: bltu a3, a4, .LBB42_2
; CHECK-RV32-NEXT: # %bb.1: ; CHECK-RV32-NEXT: # %bb.1:
; CHECK-RV32-NEXT: mv a3, a4 ; CHECK-RV32-NEXT: mv a3, a4
; CHECK-RV32-NEXT: .LBB42_2: ; CHECK-RV32-NEXT: .LBB42_2:
; CHECK-RV32-NEXT: mul a4, a3, a1 ; CHECK-RV32-NEXT: mul a5, a3, a1
; CHECK-RV32-NEXT: add a4, a0, a4 ; CHECK-RV32-NEXT: add a5, a0, a5
; CHECK-RV32-NEXT: srli a4, a4, 3
; CHECK-RV32-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK-RV32-NEXT: vslidedown.vx v0, v8, a4
; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (a4), a1, v0.t ; CHECK-RV32-NEXT: vlse64.v v16, (a5), a1, v0.t
; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv1r.v v0, v8 ; CHECK-RV32-NEXT: vmv1r.v v0, v8
; CHECK-RV32-NEXT: vlse64.v v8, (a0), a1, v0.t ; CHECK-RV32-NEXT: vlse64.v v8, (a0), a1, v0.t
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: strided_load_nxv16f64: ; CHECK-RV64-LABEL: strided_load_nxv16f64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: vmv1r.v v8, v0 ; CHECK-RV64-NEXT: vmv1r.v v8, v0
; CHECK-RV64-NEXT: csrr a4, vlenb ; CHECK-RV64-NEXT: csrr a4, vlenb
; CHECK-RV64-NEXT: sub a3, a2, a4 ; CHECK-RV64-NEXT: sub a3, a2, a4
; CHECK-RV64-NEXT: sltu a5, a2, a3 ; CHECK-RV64-NEXT: sltu a5, a2, a3
; CHECK-RV64-NEXT: addi a5, a5, -1 ; CHECK-RV64-NEXT: addi a5, a5, -1
; CHECK-RV64-NEXT: and a3, a5, a3 ; CHECK-RV64-NEXT: and a3, a5, a3
; CHECK-RV64-NEXT: srli a5, a4, 3
; CHECK-RV64-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK-RV64-NEXT: vslidedown.vx v0, v0, a5
; CHECK-RV64-NEXT: bltu a2, a4, .LBB42_2 ; CHECK-RV64-NEXT: bltu a2, a4, .LBB42_2
; CHECK-RV64-NEXT: # %bb.1: ; CHECK-RV64-NEXT: # %bb.1:
; CHECK-RV64-NEXT: mv a2, a4 ; CHECK-RV64-NEXT: mv a2, a4
; CHECK-RV64-NEXT: .LBB42_2: ; CHECK-RV64-NEXT: .LBB42_2:
; CHECK-RV64-NEXT: mul a4, a2, a1 ; CHECK-RV64-NEXT: mul a5, a2, a1
; CHECK-RV64-NEXT: add a4, a0, a4 ; CHECK-RV64-NEXT: add a5, a0, a5
; CHECK-RV64-NEXT: srli a4, a4, 3
; CHECK-RV64-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK-RV64-NEXT: vslidedown.vx v0, v8, a4
; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v16, (a4), a1, v0.t ; CHECK-RV64-NEXT: vlse64.v v16, (a5), a1, v0.t
; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-RV64-NEXT: vmv1r.v v0, v8 ; CHECK-RV64-NEXT: vmv1r.v v0, v8
; CHECK-RV64-NEXT: vlse64.v v8, (a0), a1, v0.t ; CHECK-RV64-NEXT: vlse64.v v8, (a0), a1, v0.t
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
%v = call <vscale x 16 x double> @llvm.experimental.vp.strided.load.nxv16f64.p0.i64(ptr %ptr, i64 %stride, <vscale x 16 x i1> %mask, i32 %evl) %v = call <vscale x 16 x double> @llvm.experimental.vp.strided.load.nxv16f64.p0.i64(ptr %ptr, i64 %stride, <vscale x 16 x i1> %mask, i32 %evl)
ret <vscale x 16 x double> %v ret <vscale x 16 x double> %v
} }
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; Widening + splitting (with HiIsEmpty == true) ; Widening + splitting (with HiIsEmpty == true)
; NOTE: We can't return <vscale x 17 x double> as that introduces a vector ; NOTE: We can't return <vscale x 17 x double> as that introduces a vector
; store that can't yet be legalized through widening. In order to test purely ; store that can't yet be legalized through widening. In order to test purely
; the vp.strided.load legalization, we manually split it. ; the vp.strided.load legalization, we manually split it.
define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vscale x 17 x i1> %mask, i32 zeroext %evl, <vscale x 1 x double>* %hi_ptr) { define <vscale x 16 x double> @strided_load_nxv17f64(ptr %ptr, i64 %stride, <vscale x 17 x i1> %mask, i32 zeroext %evl, <vscale x 1 x double>* %hi_ptr) {
; CHECK-RV32-LABEL: strided_load_nxv17f64: ; CHECK-RV32-LABEL: strided_load_nxv17f64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: csrr a5, vlenb ; CHECK-RV32-NEXT: csrr a2, vlenb
; CHECK-RV32-NEXT: slli a7, a5, 1 ; CHECK-RV32-NEXT: slli a7, a2, 1
; CHECK-RV32-NEXT: vmv1r.v v8, v0 ; CHECK-RV32-NEXT: vmv1r.v v8, v0
; CHECK-RV32-NEXT: mv a2, a3 ; CHECK-RV32-NEXT: mv a6, a3
; CHECK-RV32-NEXT: bltu a3, a7, .LBB44_2 ; CHECK-RV32-NEXT: bltu a3, a7, .LBB44_2
; CHECK-RV32-NEXT: # %bb.1: ; CHECK-RV32-NEXT: # %bb.1:
; CHECK-RV32-NEXT: mv a2, a7 ; CHECK-RV32-NEXT: mv a6, a7
; CHECK-RV32-NEXT: .LBB44_2: ; CHECK-RV32-NEXT: .LBB44_2:
; CHECK-RV32-NEXT: sub a6, a2, a5 ; CHECK-RV32-NEXT: sub a5, a6, a2
; CHECK-RV32-NEXT: sltu t0, a2, a6 ; CHECK-RV32-NEXT: sltu t0, a6, a5
; CHECK-RV32-NEXT: addi t0, t0, -1 ; CHECK-RV32-NEXT: addi t0, t0, -1
; CHECK-RV32-NEXT: and t0, t0, a6 ; CHECK-RV32-NEXT: and t0, t0, a5
; CHECK-RV32-NEXT: srli a6, a5, 3 ; CHECK-RV32-NEXT: mv a5, a6
; CHECK-RV32-NEXT: vsetvli t1, zero, e8, mf4, ta, ma ; CHECK-RV32-NEXT: bltu a6, a2, .LBB44_4
; CHECK-RV32-NEXT: vslidedown.vx v0, v8, a6
; CHECK-RV32-NEXT: mv a6, a2
; CHECK-RV32-NEXT: bltu a2, a5, .LBB44_4
; CHECK-RV32-NEXT: # %bb.3: ; CHECK-RV32-NEXT: # %bb.3:
; CHECK-RV32-NEXT: mv a6, a5 ; CHECK-RV32-NEXT: mv a5, a2
; CHECK-RV32-NEXT: .LBB44_4: ; CHECK-RV32-NEXT: .LBB44_4:
; CHECK-RV32-NEXT: mul t1, a6, a1 ; CHECK-RV32-NEXT: mul t1, a5, a1
; CHECK-RV32-NEXT: add t1, a0, t1 ; CHECK-RV32-NEXT: add t1, a0, t1
; CHECK-RV32-NEXT: srli t2, a2, 3
; CHECK-RV32-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
; CHECK-RV32-NEXT: vslidedown.vx v0, v8, t2
; CHECK-RV32-NEXT: vsetvli zero, t0, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, t0, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v16, (t1), a1, v0.t ; CHECK-RV32-NEXT: vlse64.v v16, (t1), a1, v0.t
; CHECK-RV32-NEXT: sub a7, a3, a7 ; CHECK-RV32-NEXT: sub a7, a3, a7
; CHECK-RV32-NEXT: sltu a3, a3, a7 ; CHECK-RV32-NEXT: sltu a3, a3, a7
; CHECK-RV32-NEXT: addi a3, a3, -1 ; CHECK-RV32-NEXT: addi a3, a3, -1
; CHECK-RV32-NEXT: and a3, a3, a7 ; CHECK-RV32-NEXT: and a3, a3, a7
; CHECK-RV32-NEXT: bltu a3, a5, .LBB44_6 ; CHECK-RV32-NEXT: bltu a3, a2, .LBB44_6
; CHECK-RV32-NEXT: # %bb.5: ; CHECK-RV32-NEXT: # %bb.5:
; CHECK-RV32-NEXT: mv a3, a5 ; CHECK-RV32-NEXT: mv a3, a2
; CHECK-RV32-NEXT: .LBB44_6: ; CHECK-RV32-NEXT: .LBB44_6:
; CHECK-RV32-NEXT: srli a5, a5, 2 ; CHECK-RV32-NEXT: mul a6, a6, a1
; CHECK-RV32-NEXT: add a6, a0, a6
; CHECK-RV32-NEXT: srli a2, a2, 2
; CHECK-RV32-NEXT: vsetvli a7, zero, e8, mf2, ta, ma ; CHECK-RV32-NEXT: vsetvli a7, zero, e8, mf2, ta, ma
; CHECK-RV32-NEXT: vslidedown.vx v0, v8, a5 ; CHECK-RV32-NEXT: vslidedown.vx v0, v8, a2
; CHECK-RV32-NEXT: mul a2, a2, a1
; CHECK-RV32-NEXT: add a2, a0, a2
; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-RV32-NEXT: vlse64.v v24, (a2), a1, v0.t ; CHECK-RV32-NEXT: vlse64.v v24, (a6), a1, v0.t
; CHECK-RV32-NEXT: vsetvli zero, a6, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv1r.v v0, v8 ; CHECK-RV32-NEXT: vmv1r.v v0, v8
; CHECK-RV32-NEXT: vlse64.v v8, (a0), a1, v0.t ; CHECK-RV32-NEXT: vlse64.v v8, (a0), a1, v0.t
; CHECK-RV32-NEXT: vs1r.v v24, (a4) ; CHECK-RV32-NEXT: vs1r.v v24, (a4)
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: strided_load_nxv17f64: ; CHECK-RV64-LABEL: strided_load_nxv17f64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: csrr a5, vlenb ; CHECK-RV64-NEXT: csrr a4, vlenb
; CHECK-RV64-NEXT: slli a7, a5, 1 ; CHECK-RV64-NEXT: slli a7, a4, 1
; CHECK-RV64-NEXT: vmv1r.v v8, v0 ; CHECK-RV64-NEXT: vmv1r.v v8, v0
; CHECK-RV64-NEXT: mv a4, a2 ; CHECK-RV64-NEXT: mv a6, a2
; CHECK-RV64-NEXT: bltu a2, a7, .LBB44_2 ; CHECK-RV64-NEXT: bltu a2, a7, .LBB44_2
; CHECK-RV64-NEXT: # %bb.1: ; CHECK-RV64-NEXT: # %bb.1:
; CHECK-RV64-NEXT: mv a4, a7 ; CHECK-RV64-NEXT: mv a6, a7
; CHECK-RV64-NEXT: .LBB44_2: ; CHECK-RV64-NEXT: .LBB44_2:
; CHECK-RV64-NEXT: sub a6, a4, a5 ; CHECK-RV64-NEXT: sub a5, a6, a4
; CHECK-RV64-NEXT: sltu t0, a4, a6 ; CHECK-RV64-NEXT: sltu t0, a6, a5
; CHECK-RV64-NEXT: addi t0, t0, -1 ; CHECK-RV64-NEXT: addi t0, t0, -1
; CHECK-RV64-NEXT: and t0, t0, a6 ; CHECK-RV64-NEXT: and t0, t0, a5
; CHECK-RV64-NEXT: srli a6, a5, 3 ; CHECK-RV64-NEXT: mv a5, a6
; CHECK-RV64-NEXT: vsetvli t1, zero, e8, mf4, ta, ma ; CHECK-RV64-NEXT: bltu a6, a4, .LBB44_4
; CHECK-RV64-NEXT: vslidedown.vx v0, v8, a6
; CHECK-RV64-NEXT: mv a6, a4
; CHECK-RV64-NEXT: bltu a4, a5, .LBB44_4
; CHECK-RV64-NEXT: # %bb.3: ; CHECK-RV64-NEXT: # %bb.3:
; CHECK-RV64-NEXT: mv a6, a5 ; CHECK-RV64-NEXT: mv a5, a4
; CHECK-RV64-NEXT: .LBB44_4: ; CHECK-RV64-NEXT: .LBB44_4:
; CHECK-RV64-NEXT: mul t1, a6, a1 ; CHECK-RV64-NEXT: mul t1, a5, a1
; CHECK-RV64-NEXT: add t1, a0, t1 ; CHECK-RV64-NEXT: add t1, a0, t1
; CHECK-RV64-NEXT: srli t2, a4, 3
; CHECK-RV64-NEXT: vsetvli t3, zero, e8, mf4, ta, ma
; CHECK-RV64-NEXT: vslidedown.vx v0, v8, t2
; CHECK-RV64-NEXT: vsetvli zero, t0, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, t0, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v16, (t1), a1, v0.t ; CHECK-RV64-NEXT: vlse64.v v16, (t1), a1, v0.t
; CHECK-RV64-NEXT: sub a7, a2, a7 ; CHECK-RV64-NEXT: sub a7, a2, a7
; CHECK-RV64-NEXT: sltu a2, a2, a7 ; CHECK-RV64-NEXT: sltu a2, a2, a7
; CHECK-RV64-NEXT: addi a2, a2, -1 ; CHECK-RV64-NEXT: addi a2, a2, -1
; CHECK-RV64-NEXT: and a2, a2, a7 ; CHECK-RV64-NEXT: and a2, a2, a7
; CHECK-RV64-NEXT: bltu a2, a5, .LBB44_6 ; CHECK-RV64-NEXT: bltu a2, a4, .LBB44_6
; CHECK-RV64-NEXT: # %bb.5: ; CHECK-RV64-NEXT: # %bb.5:
; CHECK-RV64-NEXT: mv a2, a5 ; CHECK-RV64-NEXT: mv a2, a4
; CHECK-RV64-NEXT: .LBB44_6: ; CHECK-RV64-NEXT: .LBB44_6:
; CHECK-RV64-NEXT: srli a5, a5, 2 ; CHECK-RV64-NEXT: mul a6, a6, a1
; CHECK-RV64-NEXT: add a6, a0, a6
; CHECK-RV64-NEXT: srli a4, a4, 2
; CHECK-RV64-NEXT: vsetvli a7, zero, e8, mf2, ta, ma ; CHECK-RV64-NEXT: vsetvli a7, zero, e8, mf2, ta, ma
; CHECK-RV64-NEXT: vslidedown.vx v0, v8, a5 ; CHECK-RV64-NEXT: vslidedown.vx v0, v8, a4
; CHECK-RV64-NEXT: mul a4, a4, a1
; CHECK-RV64-NEXT: add a4, a0, a4
; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-RV64-NEXT: vlse64.v v24, (a4), a1, v0.t ; CHECK-RV64-NEXT: vlse64.v v24, (a6), a1, v0.t
; CHECK-RV64-NEXT: vsetvli zero, a6, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a5, e64, m8, ta, ma
; CHECK-RV64-NEXT: vmv1r.v v0, v8 ; CHECK-RV64-NEXT: vmv1r.v v0, v8
; CHECK-RV64-NEXT: vlse64.v v8, (a0), a1, v0.t ; CHECK-RV64-NEXT: vlse64.v v8, (a0), a1, v0.t
; CHECK-RV64-NEXT: vs1r.v v24, (a3) ; CHECK-RV64-NEXT: vs1r.v v24, (a3)
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
%v = call <vscale x 17 x double> @llvm.experimental.vp.strided.load.nxv17f64.p0.i64(ptr %ptr, i64 %stride, <vscale x 17 x i1> %mask, i32 %evl) %v = call <vscale x 17 x double> @llvm.experimental.vp.strided.load.nxv17f64.p0.i64(ptr %ptr, i64 %stride, <vscale x 17 x i1> %mask, i32 %evl)
%lo = call <vscale x 16 x double> @llvm.experimental.vector.extract.nxv16f64(<vscale x 17 x double> %v, i64 0) %lo = call <vscale x 16 x double> @llvm.experimental.vector.extract.nxv16f64(<vscale x 17 x double> %v, i64 0)
%hi = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64(<vscale x 17 x double> %v, i64 16) %hi = call <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64(<vscale x 17 x double> %v, i64 16)
store <vscale x 1 x double> %hi, <vscale x 1 x double>* %hi_ptr store <vscale x 1 x double> %hi, <vscale x 1 x double>* %hi_ptr
ret <vscale x 16 x double> %lo ret <vscale x 16 x double> %lo
} }
declare <vscale x 17 x double> @llvm.experimental.vp.strided.load.nxv17f64.p0.i64(ptr, i64, <vscale x 17 x i1>, i32) declare <vscale x 17 x double> @llvm.experimental.vp.strided.load.nxv17f64.p0.i64(ptr, i64, <vscale x 17 x i1>, i32)
declare <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64(<vscale x 17 x double> %vec, i64 %idx) declare <vscale x 1 x double> @llvm.experimental.vector.extract.nxv1f64(<vscale x 17 x double> %vec, i64 %idx)
declare <vscale x 16 x double> @llvm.experimental.vector.extract.nxv16f64(<vscale x 17 x double> %vec, i64 %idx) declare <vscale x 16 x double> @llvm.experimental.vector.extract.nxv16f64(<vscale x 17 x double> %vec, i64 %idx)

llvm/test/CodeGen/RISCV/rvv/strided-vpstore.ll

Show First 20 Lines • Show All 615 Lines • ▼ Show 20 Lines
} }
declare void @llvm.experimental.vp.strided.store.nxv3f32.p0.i32(<vscale x 3 x float>, ptr , i32, <vscale x 3 x i1>, i32) declare void @llvm.experimental.vp.strided.store.nxv3f32.p0.i32(<vscale x 3 x float>, ptr , i32, <vscale x 3 x i1>, i32)
; Splitting ; Splitting
define void @strided_store_nxv16f64(<vscale x 16 x double> %v, ptr %ptr, i32 signext %stride, <vscale x 16 x i1> %mask, i32 zeroext %evl) { define void @strided_store_nxv16f64(<vscale x 16 x double> %v, ptr %ptr, i32 signext %stride, <vscale x 16 x i1> %mask, i32 zeroext %evl) {
; CHECK-RV32-LABEL: strided_store_nxv16f64: ; CHECK-RV32-LABEL: strided_store_nxv16f64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: csrr a4, vlenb ; CHECK-RV32-NEXT: csrr a3, vlenb
; CHECK-RV32-NEXT: mv a3, a2 ; CHECK-RV32-NEXT: mv a4, a2
; CHECK-RV32-NEXT: bltu a2, a4, .LBB34_2 ; CHECK-RV32-NEXT: bltu a2, a3, .LBB34_2
; CHECK-RV32-NEXT: # %bb.1: ; CHECK-RV32-NEXT: # %bb.1:
; CHECK-RV32-NEXT: mv a3, a4 ; CHECK-RV32-NEXT: mv a4, a3
; CHECK-RV32-NEXT: .LBB34_2: ; CHECK-RV32-NEXT: .LBB34_2:
; CHECK-RV32-NEXT: vsetvli zero, a3, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-RV32-NEXT: vsse64.v v8, (a0), a1, v0.t ; CHECK-RV32-NEXT: vsse64.v v8, (a0), a1, v0.t
; CHECK-RV32-NEXT: sub a5, a2, a4 ; CHECK-RV32-NEXT: sub a5, a2, a3
; CHECK-RV32-NEXT: sltu a2, a2, a5 ; CHECK-RV32-NEXT: sltu a2, a2, a5
; CHECK-RV32-NEXT: addi a2, a2, -1 ; CHECK-RV32-NEXT: addi a2, a2, -1
; CHECK-RV32-NEXT: and a2, a2, a5 ; CHECK-RV32-NEXT: and a2, a2, a5
; CHECK-RV32-NEXT: srli a4, a4, 3 ; CHECK-RV32-NEXT: mul a4, a4, a1
; CHECK-RV32-NEXT: vsetvli a5, zero, e8, mf4, ta, ma ; CHECK-RV32-NEXT: add a0, a0, a4
; CHECK-RV32-NEXT: vslidedown.vx v0, v0, a4 ; CHECK-RV32-NEXT: srli a3, a3, 3
; CHECK-RV32-NEXT: mul a3, a3, a1 ; CHECK-RV32-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-RV32-NEXT: add a0, a0, a3 ; CHECK-RV32-NEXT: vslidedown.vx v0, v0, a3
; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-RV32-NEXT: vsse64.v v16, (a0), a1, v0.t ; CHECK-RV32-NEXT: vsse64.v v16, (a0), a1, v0.t
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: strided_store_nxv16f64: ; CHECK-RV64-LABEL: strided_store_nxv16f64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: csrr a4, vlenb ; CHECK-RV64-NEXT: csrr a3, vlenb
; CHECK-RV64-NEXT: mv a3, a2 ; CHECK-RV64-NEXT: mv a4, a2
; CHECK-RV64-NEXT: bltu a2, a4, .LBB34_2 ; CHECK-RV64-NEXT: bltu a2, a3, .LBB34_2
; CHECK-RV64-NEXT: # %bb.1: ; CHECK-RV64-NEXT: # %bb.1:
; CHECK-RV64-NEXT: mv a3, a4 ; CHECK-RV64-NEXT: mv a4, a3
; CHECK-RV64-NEXT: .LBB34_2: ; CHECK-RV64-NEXT: .LBB34_2:
; CHECK-RV64-NEXT: vsetvli zero, a3, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-RV64-NEXT: vsse64.v v8, (a0), a1, v0.t ; CHECK-RV64-NEXT: vsse64.v v8, (a0), a1, v0.t
; CHECK-RV64-NEXT: sub a5, a2, a4 ; CHECK-RV64-NEXT: sub a5, a2, a3
; CHECK-RV64-NEXT: sltu a2, a2, a5 ; CHECK-RV64-NEXT: sltu a2, a2, a5
; CHECK-RV64-NEXT: addi a2, a2, -1 ; CHECK-RV64-NEXT: addi a2, a2, -1
; CHECK-RV64-NEXT: and a2, a2, a5 ; CHECK-RV64-NEXT: and a2, a2, a5
; CHECK-RV64-NEXT: srli a4, a4, 3 ; CHECK-RV64-NEXT: mul a4, a4, a1
; CHECK-RV64-NEXT: vsetvli a5, zero, e8, mf4, ta, ma ; CHECK-RV64-NEXT: add a0, a0, a4
; CHECK-RV64-NEXT: vslidedown.vx v0, v0, a4 ; CHECK-RV64-NEXT: srli a3, a3, 3
; CHECK-RV64-NEXT: mul a3, a3, a1 ; CHECK-RV64-NEXT: vsetvli a4, zero, e8, mf4, ta, ma
; CHECK-RV64-NEXT: add a0, a0, a3 ; CHECK-RV64-NEXT: vslidedown.vx v0, v0, a3
; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-RV64-NEXT: vsse64.v v16, (a0), a1, v0.t ; CHECK-RV64-NEXT: vsse64.v v16, (a0), a1, v0.t
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
call void @llvm.experimental.vp.strided.store.nxv16f64.p0.i32(<vscale x 16 x double> %v, ptr %ptr, i32 %stride, <vscale x 16 x i1> %mask, i32 %evl) call void @llvm.experimental.vp.strided.store.nxv16f64.p0.i32(<vscale x 16 x double> %v, ptr %ptr, i32 %stride, <vscale x 16 x i1> %mask, i32 %evl)
ret void ret void
} }
define void @strided_store_nxv16f64_allones_mask(<vscale x 16 x double> %v, ptr %ptr, i32 signext %stride, i32 zeroext %evl) { define void @strided_store_nxv16f64_allones_mask(<vscale x 16 x double> %v, ptr %ptr, i32 signext %stride, i32 zeroext %evl) {
▲ Show 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
; CHECK-RV32-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill ; CHECK-RV32-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv1r.v v0, v24 ; CHECK-RV32-NEXT: vmv1r.v v0, v24
; CHECK-RV32-NEXT: vsse64.v v8, (a1), a2, v0.t ; CHECK-RV32-NEXT: vsse64.v v8, (a1), a2, v0.t
; CHECK-RV32-NEXT: sub a0, a5, a4 ; CHECK-RV32-NEXT: sub a0, a5, a4
; CHECK-RV32-NEXT: sltu t0, a5, a0 ; CHECK-RV32-NEXT: sltu t0, a5, a0
; CHECK-RV32-NEXT: addi t0, t0, -1 ; CHECK-RV32-NEXT: addi t0, t0, -1
; CHECK-RV32-NEXT: and a0, t0, a0 ; CHECK-RV32-NEXT: and a0, t0, a0
; CHECK-RV32-NEXT: mul a7, a7, a2
; CHECK-RV32-NEXT: add a7, a1, a7
; CHECK-RV32-NEXT: srli t0, a4, 3 ; CHECK-RV32-NEXT: srli t0, a4, 3
; CHECK-RV32-NEXT: vsetvli t1, zero, e8, mf4, ta, ma ; CHECK-RV32-NEXT: vsetvli t1, zero, e8, mf4, ta, ma
; CHECK-RV32-NEXT: vslidedown.vx v0, v24, t0 ; CHECK-RV32-NEXT: vslidedown.vx v0, v24, t0
; CHECK-RV32-NEXT: mul a7, a7, a2
; CHECK-RV32-NEXT: add a7, a1, a7
; CHECK-RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-RV32-NEXT: sub a0, a3, a6 ; CHECK-RV32-NEXT: sub a0, a3, a6
; CHECK-RV32-NEXT: sltu a3, a3, a0 ; CHECK-RV32-NEXT: sltu a3, a3, a0
; CHECK-RV32-NEXT: addi a3, a3, -1 ; CHECK-RV32-NEXT: addi a3, a3, -1
; CHECK-RV32-NEXT: and a0, a3, a0 ; CHECK-RV32-NEXT: and a0, a3, a0
; CHECK-RV32-NEXT: vsse64.v v16, (a7), a2, v0.t ; CHECK-RV32-NEXT: vsse64.v v16, (a7), a2, v0.t
; CHECK-RV32-NEXT: bltu a0, a4, .LBB36_6 ; CHECK-RV32-NEXT: bltu a0, a4, .LBB36_6
; CHECK-RV32-NEXT: # %bb.5: ; CHECK-RV32-NEXT: # %bb.5:
; CHECK-RV32-NEXT: mv a0, a4 ; CHECK-RV32-NEXT: mv a0, a4
; CHECK-RV32-NEXT: .LBB36_6: ; CHECK-RV32-NEXT: .LBB36_6:
; CHECK-RV32-NEXT: mul a3, a5, a2
; CHECK-RV32-NEXT: add a1, a1, a3
; CHECK-RV32-NEXT: srli a4, a4, 2 ; CHECK-RV32-NEXT: srli a4, a4, 2
; CHECK-RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; CHECK-RV32-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-RV32-NEXT: vslidedown.vx v0, v24, a4 ; CHECK-RV32-NEXT: vslidedown.vx v0, v24, a4
; CHECK-RV32-NEXT: mul a3, a5, a2
; CHECK-RV32-NEXT: add a1, a1, a3
; CHECK-RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-RV32-NEXT: addi a0, sp, 16 ; CHECK-RV32-NEXT: addi a0, sp, 16
; CHECK-RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-RV32-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-RV32-NEXT: vsse64.v v8, (a1), a2, v0.t ; CHECK-RV32-NEXT: vsse64.v v8, (a1), a2, v0.t
; CHECK-RV32-NEXT: csrr a0, vlenb ; CHECK-RV32-NEXT: csrr a0, vlenb
; CHECK-RV32-NEXT: slli a0, a0, 3 ; CHECK-RV32-NEXT: slli a0, a0, 3
; CHECK-RV32-NEXT: add sp, sp, a0 ; CHECK-RV32-NEXT: add sp, sp, a0
; CHECK-RV32-NEXT: addi sp, sp, 16 ; CHECK-RV32-NEXT: addi sp, sp, 16
Show All 25 Lines
; CHECK-RV64-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill ; CHECK-RV64-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a7, e64, m8, ta, ma
; CHECK-RV64-NEXT: vmv1r.v v0, v24 ; CHECK-RV64-NEXT: vmv1r.v v0, v24
; CHECK-RV64-NEXT: vsse64.v v8, (a1), a2, v0.t ; CHECK-RV64-NEXT: vsse64.v v8, (a1), a2, v0.t
; CHECK-RV64-NEXT: sub a0, a5, a4 ; CHECK-RV64-NEXT: sub a0, a5, a4
; CHECK-RV64-NEXT: sltu t0, a5, a0 ; CHECK-RV64-NEXT: sltu t0, a5, a0
; CHECK-RV64-NEXT: addi t0, t0, -1 ; CHECK-RV64-NEXT: addi t0, t0, -1
; CHECK-RV64-NEXT: and a0, t0, a0 ; CHECK-RV64-NEXT: and a0, t0, a0
; CHECK-RV64-NEXT: mul a7, a7, a2
; CHECK-RV64-NEXT: add a7, a1, a7
; CHECK-RV64-NEXT: srli t0, a4, 3 ; CHECK-RV64-NEXT: srli t0, a4, 3
; CHECK-RV64-NEXT: vsetvli t1, zero, e8, mf4, ta, ma ; CHECK-RV64-NEXT: vsetvli t1, zero, e8, mf4, ta, ma
; CHECK-RV64-NEXT: vslidedown.vx v0, v24, t0 ; CHECK-RV64-NEXT: vslidedown.vx v0, v24, t0
; CHECK-RV64-NEXT: mul a7, a7, a2
; CHECK-RV64-NEXT: add a7, a1, a7
; CHECK-RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-RV64-NEXT: sub a0, a3, a6 ; CHECK-RV64-NEXT: sub a0, a3, a6
; CHECK-RV64-NEXT: sltu a3, a3, a0 ; CHECK-RV64-NEXT: sltu a3, a3, a0
; CHECK-RV64-NEXT: addi a3, a3, -1 ; CHECK-RV64-NEXT: addi a3, a3, -1
; CHECK-RV64-NEXT: and a0, a3, a0 ; CHECK-RV64-NEXT: and a0, a3, a0
; CHECK-RV64-NEXT: vsse64.v v16, (a7), a2, v0.t ; CHECK-RV64-NEXT: vsse64.v v16, (a7), a2, v0.t
; CHECK-RV64-NEXT: bltu a0, a4, .LBB36_6 ; CHECK-RV64-NEXT: bltu a0, a4, .LBB36_6
; CHECK-RV64-NEXT: # %bb.5: ; CHECK-RV64-NEXT: # %bb.5:
; CHECK-RV64-NEXT: mv a0, a4 ; CHECK-RV64-NEXT: mv a0, a4
; CHECK-RV64-NEXT: .LBB36_6: ; CHECK-RV64-NEXT: .LBB36_6:
; CHECK-RV64-NEXT: mul a3, a5, a2
; CHECK-RV64-NEXT: add a1, a1, a3
; CHECK-RV64-NEXT: srli a4, a4, 2 ; CHECK-RV64-NEXT: srli a4, a4, 2
; CHECK-RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma ; CHECK-RV64-NEXT: vsetvli a3, zero, e8, mf2, ta, ma
; CHECK-RV64-NEXT: vslidedown.vx v0, v24, a4 ; CHECK-RV64-NEXT: vslidedown.vx v0, v24, a4
; CHECK-RV64-NEXT: mul a3, a5, a2
; CHECK-RV64-NEXT: add a1, a1, a3
; CHECK-RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-RV64-NEXT: addi a0, sp, 16 ; CHECK-RV64-NEXT: addi a0, sp, 16
; CHECK-RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-RV64-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-RV64-NEXT: vsse64.v v8, (a1), a2, v0.t ; CHECK-RV64-NEXT: vsse64.v v8, (a1), a2, v0.t
; CHECK-RV64-NEXT: csrr a0, vlenb ; CHECK-RV64-NEXT: csrr a0, vlenb
; CHECK-RV64-NEXT: slli a0, a0, 3 ; CHECK-RV64-NEXT: slli a0, a0, 3
; CHECK-RV64-NEXT: add sp, sp, a0 ; CHECK-RV64-NEXT: add sp, sp, a0
; CHECK-RV64-NEXT: addi sp, sp, 16 ; CHECK-RV64-NEXT: addi sp, sp, 16
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
call void @llvm.experimental.vp.strided.store.nxv17f64.p0.i32(<vscale x 17 x double> %v, ptr %ptr, i32 %stride, <vscale x 17 x i1> %mask, i32 %evl) call void @llvm.experimental.vp.strided.store.nxv17f64.p0.i32(<vscale x 17 x double> %v, ptr %ptr, i32 %stride, <vscale x 17 x i1> %mask, i32 %evl)
ret void ret void
} }
declare void @llvm.experimental.vp.strided.store.nxv17f64.p0.i32(<vscale x 17 x double>, ptr, i32, <vscale x 17 x i1>, i32) declare void @llvm.experimental.vp.strided.store.nxv17f64.p0.i32(<vscale x 17 x double>, ptr, i32, <vscale x 17 x i1>, i32)

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec) %retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec)
ret {<4 x i32>, <4 x i32>} %retval ret {<4 x i32>, <4 x i32>} %retval
} }
define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) { define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
; CHECK-LABEL: vector_deinterleave_v2i64_v4i64: ; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v8, 2
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 2 ; CHECK-NEXT: vmv.v.i v0, 2
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vi v10, v12, 1, v0.t ; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t
; CHECK-NEXT: vmv.v.v v9, v10 ; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec) %retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec)
ret {<2 x i64>, <2 x i64>} %retval ret {<2 x i64>, <2 x i64>} %retval
} }
declare {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1>) declare {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1>)
declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>) declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>)
declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>) declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>)
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec) %retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec)
ret {<4 x float>, <4 x float>} %retval ret {<4 x float>, <4 x float>} %retval
} }
define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) { define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
; CHECK-LABEL: vector_deinterleave_v2f64_v4f64: ; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v12, v8, 2
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 2 ; CHECK-NEXT: vmv.v.i v0, 2
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 2
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vi v10, v12, 1, v0.t ; CHECK-NEXT: vrgather.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t
; CHECK-NEXT: vmv.v.v v9, v10 ; CHECK-NEXT: vslideup.vi v8, v10, 1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec) %retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec)
ret {<2 x double>, <2 x double>} %retval ret {<2 x double>, <2 x double>} %retval
} }
declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>) declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>)
declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>) declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>)
declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>) declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>)
declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>) declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>)
declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>) declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>)
declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>) declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>)

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll

Show First 20 Lines • Show All 98 Lines • ▼ Show 20 Lines
; This shouldn't be lowered to a vlseg because EMUL * NFIELDS >= 8 ; This shouldn't be lowered to a vlseg because EMUL * NFIELDS >= 8
define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_load_nxv8i64_nxv16i64(ptr %p) { define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_load_nxv8i64_nxv16i64(ptr %p) {
; CHECK-LABEL: vector_deinterleave_load_nxv8i64_nxv16i64: ; CHECK-LABEL: vector_deinterleave_load_nxv8i64_nxv16i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: li a2, 24 ; CHECK-NEXT: li a2, 40
; CHECK-NEXT: mul a1, a1, a2 ; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x28, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 40 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vl8re64.v v16, (a1) ; CHECK-NEXT: vl8re64.v v24, (a1)
; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: li a2, 24
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vadd.vv v0, v8, v8 ; CHECK-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vrgather.vv v8, v16, v0 ; CHECK-NEXT: vl8re64.v v0, (a0)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vv v16, v8, v8
; CHECK-NEXT: vrgather.vv v8, v0, v16
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vrgather.vv v8, v24, v0 ; CHECK-NEXT: vrgather.vv v0, v24, v16
; CHECK-NEXT: vadd.vi v0, v0, 1 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: vrgather.vv v24, v16, v0 ; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vadd.vi v24, v16, 1
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vrgather.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmv4r.v v12, v24 ; CHECK-NEXT: vrgather.vv v16, v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vrgather.vv v24, v0, v8
; CHECK-NEXT: vmv4r.v v0, v24
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmv4r.v v20, v24 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmv4r.v v12, v24
; CHECK-NEXT: vmv4r.v v20, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24 ; CHECK-NEXT: li a1, 40
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vec = load <vscale x 16 x i64>, ptr %p %vec = load <vscale x 16 x i64>, ptr %p
%retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.experimental.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec) %retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.experimental.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec)
ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %retval ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %retval
} }
▲ Show 20 Lines • Show All 83 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh | FileCheck %s ; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+v,+zfh,+zvfh | FileCheck %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+v,+zfh,+zvfh | FileCheck %s
; Integers ; Integers
define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv32i1(<vscale x 32 x i1> %vec) { define {<vscale x 16 x i1>, <vscale x 16 x i1>} @vector_deinterleave_nxv16i1_nxv32i1(<vscale x 32 x i1> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv16i1_nxv32i1: ; CHECK-LABEL: vector_deinterleave_nxv16i1_nxv32i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v12, v8, 1, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a0 ; CHECK-NEXT: vslidedown.vx v0, v0, a0
; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0 ; CHECK-NEXT: vmerge.vim v14, v8, 1, v0
; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v12, v10, 1, v0
; CHECK-NEXT: vnsrl.wi v8, v12, 0 ; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: vnsrl.wi v10, v12, 8 ; CHECK-NEXT: vnsrl.wi v10, v12, 8
; CHECK-NEXT: vmsne.vi v8, v10, 0 ; CHECK-NEXT: vmsne.vi v8, v10, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.experimental.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec) %retval = call {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.experimental.vector.deinterleave2.nxv32i1(<vscale x 32 x i1> %vec)
ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %retval ret {<vscale x 16 x i1>, <vscale x 16 x i1>} %retval
} }
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave2.nxv32i8(<vscale x 32 x i8>) declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave2.nxv32i8(<vscale x 32 x i8>)
declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave2.nxv16i16(<vscale x 16 x i16>) declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave2.nxv16i16(<vscale x 16 x i16>)
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>) declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>)
declare {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave2.nxv4i64(<vscale x 4 x i64>) declare {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave2.nxv4i64(<vscale x 4 x i64>)
define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv128i1(<vscale x 128 x i1> %vec) { define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv128i1(<vscale x 128 x i1> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv64i1_nxv128i1: ; CHECK-LABEL: vector_deinterleave_nxv64i1_nxv128i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: vmv1r.v v28, v8
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv.v.i v24, 0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmerge.vim v16, v8, 1, v0
; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v16, 0 ; CHECK-NEXT: vnsrl.wi v24, v16, 0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: vmv1r.v v0, v28
; CHECK-NEXT: vmerge.vim v24, v24, 1, v0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v24, 0 ; CHECK-NEXT: vnsrl.wi v28, v8, 0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs1r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v4, v16, 8 ; CHECK-NEXT: vnsrl.wi v24, v16, 8
; CHECK-NEXT: vnsrl.wi v0, v24, 8 ; CHECK-NEXT: vnsrl.wi v28, v8, 8
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmsne.vi v8, v0, 0 ; CHECK-NEXT: vmsne.vi v8, v24, 0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.experimental.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec) %retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.experimental.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec)
ret {<vscale x 64 x i1>, <vscale x 64 x i1>} %retval ret {<vscale x 64 x i1>, <vscale x 64 x i1>} %retval
} }
define {<vscale x 64 x i8>, <vscale x 64 x i8>} @vector_deinterleave_nxv64i8_nxv128i8(<vscale x 128 x i8> %vec) { define {<vscale x 64 x i8>, <vscale x 64 x i8>} @vector_deinterleave_nxv64i8_nxv128i8(<vscale x 128 x i8> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv64i8_nxv128i8: ; CHECK-LABEL: vector_deinterleave_nxv64i8_nxv128i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv8r.v v24, v8 ; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vnsrl.wi v8, v24, 0 ; CHECK-NEXT: vnsrl.wi v8, v24, 0
; CHECK-NEXT: vnsrl.wi v4, v16, 8 ; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vnsrl.wi v0, v24, 8 ; CHECK-NEXT: vnsrl.wi v0, v24, 8
; CHECK-NEXT: vnsrl.wi v4, v16, 8
; CHECK-NEXT: vmv8r.v v16, v0 ; CHECK-NEXT: vmv8r.v v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 64 x i8>, <vscale x 64 x i8>} @llvm.experimental.vector.deinterleave2.nxv128i8(<vscale x 128 x i8> %vec) %retval = call {<vscale x 64 x i8>, <vscale x 64 x i8>} @llvm.experimental.vector.deinterleave2.nxv128i8(<vscale x 128 x i8> %vec)
ret {<vscale x 64 x i8>, <vscale x 64 x i8>} %retval ret {<vscale x 64 x i8>, <vscale x 64 x i8>} %retval
} }
define {<vscale x 32 x i16>, <vscale x 32 x i16>} @vector_deinterleave_nxv32i16_nxv64i16(<vscale x 64 x i16> %vec) { define {<vscale x 32 x i16>, <vscale x 32 x i16>} @vector_deinterleave_nxv32i16_nxv64i16(<vscale x 64 x i16> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv32i16_nxv64i16: ; CHECK-LABEL: vector_deinterleave_nxv32i16_nxv64i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv8r.v v24, v8 ; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vnsrl.wi v8, v24, 0 ; CHECK-NEXT: vnsrl.wi v8, v24, 0
; CHECK-NEXT: vnsrl.wi v4, v16, 16 ; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vnsrl.wi v0, v24, 16 ; CHECK-NEXT: vnsrl.wi v0, v24, 16
; CHECK-NEXT: vnsrl.wi v4, v16, 16
; CHECK-NEXT: vmv8r.v v16, v0 ; CHECK-NEXT: vmv8r.v v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 32 x i16>, <vscale x 32 x i16>} @llvm.experimental.vector.deinterleave2.nxv64i16(<vscale x 64 x i16> %vec) %retval = call {<vscale x 32 x i16>, <vscale x 32 x i16>} @llvm.experimental.vector.deinterleave2.nxv64i16(<vscale x 64 x i16> %vec)
ret {<vscale x 32 x i16>, <vscale x 32 x i16>} %retval ret {<vscale x 32 x i16>, <vscale x 32 x i16>} %retval
} }
define {<vscale x 16 x i32>, <vscale x 16 x i32>} @vector_deinterleave_nxv16i32_nxvv32i32(<vscale x 32 x i32> %vec) { define {<vscale x 16 x i32>, <vscale x 16 x i32>} @vector_deinterleave_nxv16i32_nxvv32i32(<vscale x 32 x i32> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv16i32_nxvv32i32: ; CHECK-LABEL: vector_deinterleave_nxv16i32_nxvv32i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv8r.v v24, v16 ; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wx v20, v24, a0 ; CHECK-NEXT: vnsrl.wx v20, v24, a0
; CHECK-NEXT: vnsrl.wx v16, v8, a0 ; CHECK-NEXT: vnsrl.wx v16, v8, a0
; CHECK-NEXT: vnsrl.wi v4, v24, 0
; CHECK-NEXT: vnsrl.wi v0, v8, 0 ; CHECK-NEXT: vnsrl.wi v0, v8, 0
; CHECK-NEXT: vnsrl.wi v4, v24, 0
; CHECK-NEXT: vmv8r.v v8, v0 ; CHECK-NEXT: vmv8r.v v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 16 x i32>, <vscale x 16 x i32>} @llvm.experimental.vector.deinterleave2.nxv32i32(<vscale x 32 x i32> %vec) %retval = call {<vscale x 16 x i32>, <vscale x 16 x i32>} @llvm.experimental.vector.deinterleave2.nxv32i32(<vscale x 32 x i32> %vec)
ret {<vscale x 16 x i32>, <vscale x 16 x i32>} %retval ret {<vscale x 16 x i32>, <vscale x 16 x i32>} %retval
} }
define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv16i64(<vscale x 16 x i64> %vec) { define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv16i64(<vscale x 16 x i64> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv8i64_nxv16i64: ; CHECK-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
▲ Show 20 Lines • Show All 170 Lines • ▼ Show 20 Lines
declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave2.nxv8f32(<vscale x 8 x float>) declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave2.nxv8f32(<vscale x 8 x float>)
declare {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave2.nxv4f64(<vscale x 4 x double>) declare {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave2.nxv4f64(<vscale x 4 x double>)
define {<vscale x 32 x half>, <vscale x 32 x half>} @vector_deinterleave_nxv32f16_nxv64f16(<vscale x 64 x half> %vec) { define {<vscale x 32 x half>, <vscale x 32 x half>} @vector_deinterleave_nxv32f16_nxv64f16(<vscale x 64 x half> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv32f16_nxv64f16: ; CHECK-LABEL: vector_deinterleave_nxv32f16_nxv64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv8r.v v24, v8 ; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vnsrl.wi v8, v24, 0 ; CHECK-NEXT: vnsrl.wi v8, v24, 0
; CHECK-NEXT: vnsrl.wi v4, v16, 16 ; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vnsrl.wi v0, v24, 16 ; CHECK-NEXT: vnsrl.wi v0, v24, 16
; CHECK-NEXT: vnsrl.wi v4, v16, 16
; CHECK-NEXT: vmv8r.v v16, v0 ; CHECK-NEXT: vmv8r.v v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.experimental.vector.deinterleave2.nxv64f16(<vscale x 64 x half> %vec) %retval = call {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.experimental.vector.deinterleave2.nxv64f16(<vscale x 64 x half> %vec)
ret {<vscale x 32 x half>, <vscale x 32 x half>} %retval ret {<vscale x 32 x half>, <vscale x 32 x half>} %retval
} }
define {<vscale x 16 x float>, <vscale x 16 x float>} @vector_deinterleave_nxv16f32_nxv32f32(<vscale x 32 x float> %vec) { define {<vscale x 16 x float>, <vscale x 16 x float>} @vector_deinterleave_nxv16f32_nxv32f32(<vscale x 32 x float> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv16f32_nxv32f32: ; CHECK-LABEL: vector_deinterleave_nxv16f32_nxv32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv8r.v v24, v16 ; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wx v20, v24, a0 ; CHECK-NEXT: vnsrl.wx v20, v24, a0
; CHECK-NEXT: vnsrl.wx v16, v8, a0 ; CHECK-NEXT: vnsrl.wx v16, v8, a0
; CHECK-NEXT: vnsrl.wi v4, v24, 0
; CHECK-NEXT: vnsrl.wi v0, v8, 0 ; CHECK-NEXT: vnsrl.wi v0, v8, 0
; CHECK-NEXT: vnsrl.wi v4, v24, 0
; CHECK-NEXT: vmv8r.v v8, v0 ; CHECK-NEXT: vmv8r.v v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.experimental.vector.deinterleave2.nxv32f32(<vscale x 32 x float> %vec) %retval = call {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.experimental.vector.deinterleave2.nxv32f32(<vscale x 32 x float> %vec)
ret {<vscale x 16 x float>, <vscale x 16 x float>} %retval ret {<vscale x 16 x float>, <vscale x 16 x float>} %retval
} }
define {<vscale x 8 x double>, <vscale x 8 x double>} @vector_deinterleave_nxv8f64_nxv16f64(<vscale x 16 x double> %vec) { define {<vscale x 8 x double>, <vscale x 8 x double>} @vector_deinterleave_nxv8f64_nxv16f64(<vscale x 16 x double> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv8f64_nxv16f64: ; CHECK-LABEL: vector_deinterleave_nxv8f64_nxv16f64:
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck -check-prefixes=CHECK,RV32 %s ; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+zvfh | FileCheck -check-prefixes=CHECK,RV32 %s
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck -check-prefixes=CHECK,RV64 %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+zvfh | FileCheck -check-prefixes=CHECK,RV64 %s
; Integers ; Integers
define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) { define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
; CHECK-LABEL: vector_interleave_v32i1_v16i1: ; CHECK-LABEL: vector_interleave_v32i1_v16i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v8, 2 ; CHECK-NEXT: vslideup.vi v0, v8, 2
; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0 ; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 16 ; CHECK-NEXT: vslidedown.vi v10, v8, 16
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vwaddu.vv v12, v8, v10 ; CHECK-NEXT: vwaddu.vv v12, v8, v10
; CHECK-NEXT: li a1, -1 ; CHECK-NEXT: li a1, -1
; CHECK-NEXT: vwmaccu.vx v12, a1, v10 ; CHECK-NEXT: vwmaccu.vx v12, a1, v10
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vmsne.vi v0, v12, 0
▲ Show 20 Lines • Show All 166 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vid.v v24
; CHECK-NEXT: vsrl.vi v2, v24, 1
; CHECK-NEXT: vand.vi v24, v24, 1
; CHECK-NEXT: vmsne.vi v0, v24, 0
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a2, a1, 1 ; CHECK-NEXT: srli a2, a1, 1
; CHECK-NEXT: vsetvli a3, zero, e16, m2, ta, mu
; CHECK-NEXT: vid.v v24
; CHECK-NEXT: vand.vi v26, v24, 1
; CHECK-NEXT: vmsne.vi v0, v26, 0
; CHECK-NEXT: vsrl.vi v2, v24, 1
; CHECK-NEXT: csrr a3, vlenb ; CHECK-NEXT: csrr a3, vlenb
; CHECK-NEXT: slli a3, a3, 3 ; CHECK-NEXT: slli a3, a3, 3
; CHECK-NEXT: add a3, sp, a3 ; CHECK-NEXT: add a3, sp, a3
; CHECK-NEXT: addi a3, a3, 16 ; CHECK-NEXT: addi a3, a3, 16
; CHECK-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload
; CHECK-NEXT: vadd.vx v2, v2, a2, v0.t ; CHECK-NEXT: vadd.vx v2, v2, a2, v0.t
; CHECK-NEXT: vmv4r.v v12, v16 ; CHECK-NEXT: vmv4r.v v12, v16
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
▲ Show 20 Lines • Show All 108 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x i32> @llvm.experimental.vector.interleave2.nxv8i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) %res = call <vscale x 8 x i32> @llvm.experimental.vector.interleave2.nxv8i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
ret <vscale x 8 x i32> %res ret <vscale x 8 x i32> %res
} }
define <vscale x 4 x i64> @vector_interleave_nxv4i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { define <vscale x 4 x i64> @vector_interleave_nxv4i64_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: vector_interleave_nxv4i64_nxv2i64: ; CHECK-LABEL: vector_interleave_nxv4i64_nxv2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vsrl.vi v16, v12, 1
; CHECK-NEXT: vand.vi v12, v12, 1
; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vand.vi v13, v12, 1
; CHECK-NEXT: vmsne.vi v0, v13, 0
; CHECK-NEXT: vsrl.vi v16, v12, 1
; CHECK-NEXT: vadd.vx v16, v16, a0, v0.t ; CHECK-NEXT: vadd.vx v16, v16, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16 ; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x i64> @llvm.experimental.vector.interleave2.nxv4i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) %res = call <vscale x 4 x i64> @llvm.experimental.vector.interleave2.nxv4i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
ret <vscale x 4 x i64> %res ret <vscale x 4 x i64> %res
} }
▲ Show 20 Lines • Show All 83 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0 ; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv8r.v v0, v8 ; CHECK-NEXT: vmv8r.v v0, v8
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vid.v v24
; CHECK-NEXT: vsrl.vi v8, v24, 1
; CHECK-NEXT: vand.vi v24, v24, 1
; CHECK-NEXT: vmsne.vi v10, v24, 0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vid.v v24
; CHECK-NEXT: vand.vi v26, v24, 1
; CHECK-NEXT: vmsne.vi v10, v26, 0
; CHECK-NEXT: vsrl.vi v8, v24, 1
; CHECK-NEXT: vmv8r.v v24, v0 ; CHECK-NEXT: vmv8r.v v24, v0
; CHECK-NEXT: vmv4r.v v12, v4 ; CHECK-NEXT: vmv4r.v v12, v4
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t ; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
; CHECK-NEXT: vmv4r.v v28, v16 ; CHECK-NEXT: vmv4r.v v28, v16
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vrgatherei16.vv v0, v24, v8 ; CHECK-NEXT: vrgatherei16.vv v0, v24, v8
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 8 x float> @llvm.experimental.vector.interleave2.nxv8f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b) %res = call <vscale x 8 x float> @llvm.experimental.vector.interleave2.nxv8f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)
ret <vscale x 8 x float> %res ret <vscale x 8 x float> %res
} }
define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) { define <vscale x 4 x double> @vector_interleave_nxv4f64_nxv2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) {
; CHECK-LABEL: vector_interleave_nxv4f64_nxv2f64: ; CHECK-LABEL: vector_interleave_nxv4f64_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vsrl.vi v16, v12, 1
; CHECK-NEXT: vand.vi v12, v12, 1
; CHECK-NEXT: vmsne.vi v0, v12, 0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu
; CHECK-NEXT: vid.v v12
; CHECK-NEXT: vand.vi v13, v12, 1
; CHECK-NEXT: vmsne.vi v0, v13, 0
; CHECK-NEXT: vsrl.vi v16, v12, 1
; CHECK-NEXT: vadd.vx v16, v16, a0, v0.t ; CHECK-NEXT: vadd.vx v16, v16, a0, v0.t
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vrgatherei16.vv v12, v8, v16 ; CHECK-NEXT: vrgatherei16.vv v12, v8, v16
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = call <vscale x 4 x double> @llvm.experimental.vector.interleave2.nxv4f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b) %res = call <vscale x 4 x double> @llvm.experimental.vector.interleave2.nxv4f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b)
ret <vscale x 4 x double> %res ret <vscale x 4 x double> %res
} }
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: sub sp, sp, a0 ; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv8r.v v0, v8 ; CHECK-NEXT: vmv8r.v v0, v8
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vid.v v24
; CHECK-NEXT: vsrl.vi v8, v24, 1
; CHECK-NEXT: vand.vi v24, v24, 1
; CHECK-NEXT: vmsne.vi v10, v24, 0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 1 ; CHECK-NEXT: srli a0, a0, 1
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
; CHECK-NEXT: vid.v v24
; CHECK-NEXT: vand.vi v26, v24, 1
; CHECK-NEXT: vmsne.vi v10, v26, 0
; CHECK-NEXT: vsrl.vi v8, v24, 1
; CHECK-NEXT: vmv8r.v v24, v0 ; CHECK-NEXT: vmv8r.v v24, v0
; CHECK-NEXT: vmv4r.v v12, v4 ; CHECK-NEXT: vmv4r.v v12, v4
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t ; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
; CHECK-NEXT: vmv4r.v v28, v16 ; CHECK-NEXT: vmv4r.v v28, v16
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vrgatherei16.vv v0, v24, v8 ; CHECK-NEXT: vrgatherei16.vv v0, v24, v8
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
Show All 17 Lines

llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll

Show First 20 Lines • Show All 146 Lines • ▼ Show 20 Lines
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a3, a1, 2 ; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; CHECK-NEXT: srli a4, a1, 2
; CHECK-NEXT: vslidedown.vx v16, v0, a3 ; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v16, v0, a4
; CHECK-NEXT: slli a3, a1, 3 ; CHECK-NEXT: slli a4, a1, 3
; CHECK-NEXT: add a3, a0, a3 ; CHECK-NEXT: add a4, a0, a4
; CHECK-NEXT: vl8re64.v v24, (a3) ; CHECK-NEXT: vl8re64.v v8, (a4)
; CHECK-NEXT: slli a3, a1, 1 ; CHECK-NEXT: slli a4, a1, 1
; CHECK-NEXT: sub a4, a2, a3 ; CHECK-NEXT: sub a5, a2, a4
; CHECK-NEXT: sltu a5, a2, a4 ; CHECK-NEXT: sltu a6, a2, a5
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a4, a5, a4
; CHECK-NEXT: sub a5, a4, a1
; CHECK-NEXT: sltu a6, a4, a5
; CHECK-NEXT: addi a6, a6, -1 ; CHECK-NEXT: addi a6, a6, -1
; CHECK-NEXT: and a6, a6, a5 ; CHECK-NEXT: and a5, a6, a5
; CHECK-NEXT: srli a5, a1, 3 ; CHECK-NEXT: sub a6, a5, a1
; CHECK-NEXT: vl8re64.v v8, (a0) ; CHECK-NEXT: sltu a7, a5, a6
; CHECK-NEXT: vslidedown.vx v0, v16, a5 ; CHECK-NEXT: addi a7, a7, -1
; CHECK-NEXT: and a6, a7, a6
; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vslidedown.vx v0, v16, a3
; CHECK-NEXT: vsetvli zero, a6, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a6, e32, m4, ta, ma
; CHECK-NEXT: vfncvt.f.f.w v20, v24, v0.t ; CHECK-NEXT: vfncvt.f.f.w v20, v8, v0.t
; CHECK-NEXT: bltu a4, a1, .LBB8_2 ; CHECK-NEXT: bltu a5, a1, .LBB8_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a4, a1 ; CHECK-NEXT: mv a5, a1
; CHECK-NEXT: .LBB8_2: ; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v2, v1, a5 ; CHECK-NEXT: vslidedown.vx v2, v1, a3
; CHECK-NEXT: vsetvli zero, a4, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a5, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vfncvt.f.f.w v16, v8, v0.t ; CHECK-NEXT: vfncvt.f.f.w v16, v24, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB8_4 ; CHECK-NEXT: bltu a2, a4, .LBB8_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a4
; CHECK-NEXT: .LBB8_4: ; CHECK-NEXT: .LBB8_4:
; CHECK-NEXT: sub a0, a2, a1 ; CHECK-NEXT: sub a0, a2, a1
; CHECK-NEXT: sltu a3, a2, a0 ; CHECK-NEXT: sltu a3, a2, a0
; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a0, a3, a0 ; CHECK-NEXT: and a0, a3, a0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v2 ; CHECK-NEXT: vmv1r.v v0, v2
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
Show All 23 Lines

llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel -target-abi=lp64 < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel -target-abi=lp64 < %s | FileCheck %s
declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>*, i64) declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>*, i64)
declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>*, <vscale x 8 x i1>, i64, i64 immarg) declare { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.mask.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>*, <vscale x 8 x i1>, i64, i64 immarg)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, i8* , i64) declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, i8* , i64)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64) declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64, i64)
define i64 @test_vleff_nxv8i8(<vscale x 8 x i8> *%p, i64 %vl) { define i64 @test_vleff_nxv8i8(<vscale x 8 x i8> *%p, i64 %vl) {
; CHECK-LABEL: name: test_vleff_nxv8i8 ; CHECK-LABEL: name: test_vleff_nxv8i8
; CHECK: bb.0.entry: ; CHECK: bb.0.entry:
; CHECK-NEXT: liveins: $x10, $x11 ; CHECK-NEXT: liveins: $x10, $x11
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: [[PseudoVLE8FF_V_M1_:%[0-9]+]]:vr, [[PseudoVLE8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLE8FF_V_M1 $noreg, [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from %ir.p, align 1)
; CHECK-NEXT: [[PseudoVLE8FF_V_M1_:%[0-9]+]]:vr, [[PseudoVLE8FF_V_M1_1:%[0-9]+]]:gpr = PseudoVLE8FF_V_M1 [[DEF]], [[COPY1]], [[COPY]], 3 /* e8 */, 2 /* tu, ma */, implicit-def dead $vl :: (load unknown-size from %ir.p, align 1)
; CHECK-NEXT: $x10 = COPY [[PseudoVLE8FF_V_M1_1]] ; CHECK-NEXT: $x10 = COPY [[PseudoVLE8FF_V_M1_1]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
entry: entry:
%0 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8>* %p, i64 %vl) %0 = call { <vscale x 8 x i8>, i64 } @llvm.riscv.vleff.nxv8i8(<vscale x 8 x i8> undef, <vscale x 8 x i8>* %p, i64 %vl)
%1 = extractvalue { <vscale x 8 x i8>, i64 } %0, 1 %1 = extractvalue { <vscale x 8 x i8>, i64 } %0, 1
ret i64 %1 ret i64 %1
} }
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

Show First 20 Lines • Show All 277 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsext.vf4 v16, v8 ; RV32-NEXT: vsext.vf4 v16, v8
; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; RV32-NEXT: vmv1r.v v0, v12 ; RV32-NEXT: vmv1r.v v0, v12
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t ; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_nxv32i8: ; RV64-LABEL: vpgather_baseidx_nxv32i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v12, v0
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a4, a2, 1 ; RV64-NEXT: slli a3, a2, 1
; RV64-NEXT: sub a3, a1, a4 ; RV64-NEXT: sub a4, a1, a3
; RV64-NEXT: sltu a5, a1, a3 ; RV64-NEXT: sltu a5, a1, a4
; RV64-NEXT: addi a5, a5, -1 ; RV64-NEXT: addi a5, a5, -1
; RV64-NEXT: and a3, a5, a3 ; RV64-NEXT: and a5, a5, a4
; RV64-NEXT: vmv1r.v v13, v0 ; RV64-NEXT: sub a4, a5, a2
; RV64-NEXT: mv a5, a3 ; RV64-NEXT: sltu a6, a5, a4
; RV64-NEXT: bltu a3, a2, .LBB12_2 ; RV64-NEXT: addi a6, a6, -1
; RV64-NEXT: and a6, a6, a4
; RV64-NEXT: srli a4, a2, 2
; RV64-NEXT: vsetvli a7, zero, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vx v13, v0, a4
; RV64-NEXT: srli a4, a2, 3
; RV64-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v13, a4
; RV64-NEXT: vsetvli a7, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v11
; RV64-NEXT: vsetvli zero, a6, e8, m1, ta, ma
; RV64-NEXT: vluxei64.v v11, (a0), v16, v0.t
; RV64-NEXT: bltu a5, a2, .LBB12_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a5, a2 ; RV64-NEXT: mv a5, a2
; RV64-NEXT: .LBB12_2: ; RV64-NEXT: .LBB12_2:
; RV64-NEXT: srli a6, a2, 2
; RV64-NEXT: vsetvli a7, zero, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vx v12, v13, a6
; RV64-NEXT: vsetvli a6, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v10 ; RV64-NEXT: vsext.vf8 v16, v10
; RV64-NEXT: vsetvli zero, a5, e8, m1, ta, ma ; RV64-NEXT: vsetvli zero, a5, e8, m1, ta, ma
; RV64-NEXT: vmv1r.v v0, v12 ; RV64-NEXT: vmv1r.v v0, v13
; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v10, (a0), v16, v0.t
; RV64-NEXT: bltu a1, a4, .LBB12_4 ; RV64-NEXT: bltu a1, a3, .LBB12_4
; RV64-NEXT: # %bb.3: ; RV64-NEXT: # %bb.3:
; RV64-NEXT: mv a1, a4 ; RV64-NEXT: mv a1, a3
; RV64-NEXT: .LBB12_4: ; RV64-NEXT: .LBB12_4:
; RV64-NEXT: sub a4, a1, a2 ; RV64-NEXT: sub a3, a1, a2
; RV64-NEXT: sltu a5, a1, a4 ; RV64-NEXT: sltu a5, a1, a3
; RV64-NEXT: addi a5, a5, -1 ; RV64-NEXT: addi a5, a5, -1
; RV64-NEXT: and a5, a5, a4 ; RV64-NEXT: and a3, a5, a3
; RV64-NEXT: srli a4, a2, 3 ; RV64-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
; RV64-NEXT: vsetvli a6, zero, e8, mf4, ta, ma ; RV64-NEXT: vslidedown.vx v0, v12, a4
; RV64-NEXT: vslidedown.vx v0, v13, a4 ; RV64-NEXT: vsetvli a4, zero, e64, m8, ta, ma
; RV64-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v9 ; RV64-NEXT: vsext.vf8 v16, v9
; RV64-NEXT: vsetvli zero, a5, e8, m1, ta, ma ; RV64-NEXT: vsetvli zero, a3, e8, m1, ta, ma
; RV64-NEXT: vluxei64.v v9, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v9, (a0), v16, v0.t
; RV64-NEXT: bltu a1, a2, .LBB12_6 ; RV64-NEXT: bltu a1, a2, .LBB12_6
; RV64-NEXT: # %bb.5: ; RV64-NEXT: # %bb.5:
; RV64-NEXT: mv a1, a2 ; RV64-NEXT: mv a1, a2
; RV64-NEXT: .LBB12_6: ; RV64-NEXT: .LBB12_6:
; RV64-NEXT: vsetvli a5, zero, e64, m8, ta, ma ; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v8 ; RV64-NEXT: vsext.vf8 v16, v8
; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; RV64-NEXT: vmv1r.v v0, v13 ; RV64-NEXT: vmv1r.v v0, v12
; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t ; RV64-NEXT: vluxei64.v v8, (a0), v16, v0.t
; RV64-NEXT: sub a1, a3, a2
; RV64-NEXT: sltu a2, a3, a1
; RV64-NEXT: addi a2, a2, -1
; RV64-NEXT: and a1, a2, a1
; RV64-NEXT: vsetvli a2, zero, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vx v0, v12, a4
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV64-NEXT: vsext.vf8 v16, v11
; RV64-NEXT: vsetvli zero, a1, e8, m1, ta, ma
; RV64-NEXT: vluxei64.v v11, (a0), v16, v0.t
; RV64-NEXT: ret ; RV64-NEXT: ret
%ptrs = getelementptr inbounds i8, ptr %base, <vscale x 32 x i8> %idxs %ptrs = getelementptr inbounds i8, ptr %base, <vscale x 32 x i8> %idxs
%v = call <vscale x 32 x i8> @llvm.vp.gather.nxv32i8.nxv32p0(<vscale x 32 x ptr> %ptrs, <vscale x 32 x i1> %m, i32 %evl) %v = call <vscale x 32 x i8> @llvm.vp.gather.nxv32i8.nxv32p0(<vscale x 32 x ptr> %ptrs, <vscale x 32 x i1> %m, i32 %evl)
ret <vscale x 32 x i8> %v ret <vscale x 32 x i8> %v
} }
declare <vscale x 1 x i16> @llvm.vp.gather.nxv1i16.nxv1p0(<vscale x 1 x ptr>, <vscale x 1 x i1>, i32) declare <vscale x 1 x i16> @llvm.vp.gather.nxv1i16.nxv1p0(<vscale x 1 x ptr>, <vscale x 1 x i1>, i32)
▲ Show 20 Lines • Show All 2,152 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vpload.ll

Show First 20 Lines • Show All 453 Lines • ▼ Show 20 Lines
; CHECK-LABEL: vpload_nxv16f64: ; CHECK-LABEL: vpload_nxv16f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v8, v0 ; CHECK-NEXT: vmv1r.v v8, v0
; CHECK-NEXT: csrr a2, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: sub a3, a1, a2 ; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: sltu a4, a1, a3 ; CHECK-NEXT: sltu a4, a1, a3
; CHECK-NEXT: addi a4, a4, -1 ; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: and a3, a4, a3 ; CHECK-NEXT: and a3, a4, a3
; CHECK-NEXT: srli a4, a2, 3
; CHECK-NEXT: vsetvli a5, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a4
; CHECK-NEXT: slli a4, a2, 3 ; CHECK-NEXT: slli a4, a2, 3
; CHECK-NEXT: add a4, a0, a4 ; CHECK-NEXT: add a4, a0, a4
; CHECK-NEXT: srli a5, a2, 3
; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v0, a5
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a4), v0.t ; CHECK-NEXT: vle64.v v16, (a4), v0.t
; CHECK-NEXT: bltu a1, a2, .LBB37_2 ; CHECK-NEXT: bltu a1, a2, .LBB37_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, a2 ; CHECK-NEXT: mv a1, a2
; CHECK-NEXT: .LBB37_2: ; CHECK-NEXT: .LBB37_2:
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
Show All 24 Lines
; CHECK-NEXT: bltu a2, a5, .LBB38_2 ; CHECK-NEXT: bltu a2, a5, .LBB38_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a4, a5 ; CHECK-NEXT: mv a4, a5
; CHECK-NEXT: .LBB38_2: ; CHECK-NEXT: .LBB38_2:
; CHECK-NEXT: sub a6, a4, a3 ; CHECK-NEXT: sub a6, a4, a3
; CHECK-NEXT: sltu a7, a4, a6 ; CHECK-NEXT: sltu a7, a4, a6
; CHECK-NEXT: addi a7, a7, -1 ; CHECK-NEXT: addi a7, a7, -1
; CHECK-NEXT: and a6, a7, a6 ; CHECK-NEXT: and a6, a7, a6
; CHECK-NEXT: srli a7, a3, 3
; CHECK-NEXT: vsetvli t0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a7
; CHECK-NEXT: slli a7, a3, 3 ; CHECK-NEXT: slli a7, a3, 3
; CHECK-NEXT: add a7, a0, a7 ; CHECK-NEXT: add a7, a0, a7
; CHECK-NEXT: srli t0, a3, 3
; CHECK-NEXT: vsetvli t1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, t0
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v16, (a7), v0.t ; CHECK-NEXT: vle64.v v16, (a7), v0.t
; CHECK-NEXT: sub a5, a2, a5 ; CHECK-NEXT: sub a5, a2, a5
; CHECK-NEXT: sltu a2, a2, a5 ; CHECK-NEXT: sltu a2, a2, a5
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a2, a2, a5 ; CHECK-NEXT: and a2, a2, a5
; CHECK-NEXT: bltu a2, a3, .LBB38_4 ; CHECK-NEXT: bltu a2, a3, .LBB38_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a3
; CHECK-NEXT: .LBB38_4: ; CHECK-NEXT: .LBB38_4:
; CHECK-NEXT: srli a5, a3, 2
; CHECK-NEXT: vsetvli a6, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a5
; CHECK-NEXT: slli a5, a3, 4 ; CHECK-NEXT: slli a5, a3, 4
; CHECK-NEXT: add a5, a0, a5 ; CHECK-NEXT: add a5, a0, a5
; CHECK-NEXT: srli a6, a3, 2
; CHECK-NEXT: vsetvli a7, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v8, a6
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v24, (a5), v0.t ; CHECK-NEXT: vle64.v v24, (a5), v0.t
; CHECK-NEXT: bltu a4, a3, .LBB38_6 ; CHECK-NEXT: bltu a4, a3, .LBB38_6
; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: mv a4, a3 ; CHECK-NEXT: mv a4, a3
; CHECK-NEXT: .LBB38_6: ; CHECK-NEXT: .LBB38_6:
; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a4, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: vmv1r.v v0, v8
Show All 9 Lines

llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll

Show First 20 Lines • Show All 374 Lines • ▼ Show 20 Lines
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; CHECK-NEXT: vmv1r.v v1, v0 ; CHECK-NEXT: vmv1r.v v1, v0
; CHECK-NEXT: vmv8r.v v24, v16 ; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a2, a0, a1 ; CHECK-NEXT: add a4, a0, a1
; CHECK-NEXT: vl8r.v v16, (a2) ; CHECK-NEXT: vl8r.v v16, (a4)
; CHECK-NEXT: sub a2, a3, a1
; CHECK-NEXT: sltu a4, a3, a2
; CHECK-NEXT: addi a4, a4, -1
; CHECK-NEXT: vl8r.v v8, (a0) ; CHECK-NEXT: vl8r.v v8, (a0)
; CHECK-NEXT: and a2, a4, a2 ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vsetvli zero, a2, e8, m8, tu, ma ; CHECK-NEXT: sub a0, a3, a1
; CHECK-NEXT: vlm.v v0, (a2)
; CHECK-NEXT: sltu a2, a3, a0
; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a0, a2, a0
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, ma
; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0 ; CHECK-NEXT: vmerge.vvm v16, v16, v24, v0
; CHECK-NEXT: bltu a3, a1, .LBB28_2 ; CHECK-NEXT: bltu a3, a1, .LBB28_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a3, a1 ; CHECK-NEXT: mv a3, a1
; CHECK-NEXT: .LBB28_2: ; CHECK-NEXT: .LBB28_2:
; CHECK-NEXT: vsetvli zero, a3, e8, m8, tu, ma ; CHECK-NEXT: vsetvli zero, a3, e8, m8, tu, ma
; CHECK-NEXT: vmv1r.v v0, v1 ; CHECK-NEXT: vmv1r.v v0, v1
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
▲ Show 20 Lines • Show All 1,044 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vpstore.ll

Show First 20 Lines • Show All 375 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mv a3, a2 ; CHECK-NEXT: mv a3, a2
; CHECK-NEXT: .LBB30_2: ; CHECK-NEXT: .LBB30_2:
; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a3, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v8, (a0), v0.t ; CHECK-NEXT: vse64.v v8, (a0), v0.t
; CHECK-NEXT: sub a3, a1, a2 ; CHECK-NEXT: sub a3, a1, a2
; CHECK-NEXT: sltu a1, a1, a3 ; CHECK-NEXT: sltu a1, a1, a3
; CHECK-NEXT: addi a1, a1, -1 ; CHECK-NEXT: addi a1, a1, -1
; CHECK-NEXT: and a1, a1, a3 ; CHECK-NEXT: and a1, a1, a3
; CHECK-NEXT: srli a3, a2, 3 ; CHECK-NEXT: slli a3, a2, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf4, ta, ma ; CHECK-NEXT: add a0, a0, a3
; CHECK-NEXT: vslidedown.vx v0, v0, a3 ; CHECK-NEXT: srli a2, a2, 3
; CHECK-NEXT: slli a2, a2, 3 ; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma
; CHECK-NEXT: add a0, a0, a2 ; CHECK-NEXT: vslidedown.vx v0, v0, a2
; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; CHECK-NEXT: vse64.v v16, (a0), v0.t ; CHECK-NEXT: vse64.v v16, (a0), v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.vp.store.nxv16f64.p0(<vscale x 16 x double> %val, <vscale x 16 x double>* %ptr, <vscale x 16 x i1> %m, i32 %evl) call void @llvm.vp.store.nxv16f64.p0(<vscale x 16 x double> %val, <vscale x 16 x double>* %ptr, <vscale x 16 x i1> %m, i32 %evl)
ret void ret void
} }
declare void @llvm.vp.store.nxv17f64.p0(<vscale x 17 x double>, <vscale x 17 x double>*, <vscale x 17 x i1>, i32) declare void @llvm.vp.store.nxv17f64.p0(<vscale x 17 x double>, <vscale x 17 x double>*, <vscale x 17 x i1>, i32)
Show All 27 Lines
; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a6, e64, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vse64.v v8, (a1), v0.t ; CHECK-NEXT: vse64.v v8, (a1), v0.t
; CHECK-NEXT: sub a0, a5, a3 ; CHECK-NEXT: sub a0, a5, a3
; CHECK-NEXT: sltu a5, a5, a0 ; CHECK-NEXT: sltu a5, a5, a0
; CHECK-NEXT: addi a5, a5, -1 ; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a0, a5, a0 ; CHECK-NEXT: and a0, a5, a0
; CHECK-NEXT: srli a5, a3, 3
; CHECK-NEXT: vsetvli a6, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v24, a5
; CHECK-NEXT: slli a5, a3, 3 ; CHECK-NEXT: slli a5, a3, 3
; CHECK-NEXT: add a5, a1, a5 ; CHECK-NEXT: add a5, a1, a5
; CHECK-NEXT: srli a6, a3, 3
; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v0, v24, a6
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: sub a0, a2, a4 ; CHECK-NEXT: sub a0, a2, a4
; CHECK-NEXT: sltu a2, a2, a0 ; CHECK-NEXT: sltu a2, a2, a0
; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: addi a2, a2, -1
; CHECK-NEXT: and a0, a2, a0 ; CHECK-NEXT: and a0, a2, a0
; CHECK-NEXT: vse64.v v16, (a5), v0.t ; CHECK-NEXT: vse64.v v16, (a5), v0.t
; CHECK-NEXT: bltu a0, a3, .LBB31_6 ; CHECK-NEXT: bltu a0, a3, .LBB31_6
; CHECK-NEXT: # %bb.5: ; CHECK-NEXT: # %bb.5:
; CHECK-NEXT: mv a0, a3 ; CHECK-NEXT: mv a0, a3
; CHECK-NEXT: .LBB31_6: ; CHECK-NEXT: .LBB31_6:
; CHECK-NEXT: srli a2, a3, 2 ; CHECK-NEXT: slli a2, a3, 4
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: vslidedown.vx v0, v24, a2 ; CHECK-NEXT: srli a3, a3, 2
; CHECK-NEXT: slli a3, a3, 4 ; CHECK-NEXT: vsetvli a2, zero, e8, mf2, ta, ma
; CHECK-NEXT: add a1, a1, a3 ; CHECK-NEXT: vslidedown.vx v0, v24, a3
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vse64.v v8, (a1), v0.t ; CHECK-NEXT: vse64.v v8, (a1), v0.t
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
call void @llvm.vp.store.nxv17f64.p0(<vscale x 17 x double> %val, <vscale x 17 x double>* %ptr, <vscale x 17 x i1> %m, i32 %evl) call void @llvm.vp.store.nxv17f64.p0(<vscale x 17 x double> %val, <vscale x 17 x double>* %ptr, <vscale x 17 x i1> %m, i32 %evl)
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

Show First 20 Lines • Show All 880 Lines • ▼ Show 20 Lines
} }
; Test Widen VECREDUCE_SEQ_FADD ; Test Widen VECREDUCE_SEQ_FADD
declare half @llvm.vector.reduce.fadd.nxv3f16(half, <vscale x 3 x half>) declare half @llvm.vector.reduce.fadd.nxv3f16(half, <vscale x 3 x half>)
define half @vreduce_ord_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) { define half @vreduce_ord_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv3f16: ; CHECK-LABEL: vreduce_ord_fadd_nxv3f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a1, a1, a0 ; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: lui a2, 1048568
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a2
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vfredosum.vs v8, v8, v9 ; CHECK-NEXT: vfredosum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v) %red = call half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.nxv6f16(half, <vscale x 6 x half>) declare half @llvm.vector.reduce.fadd.nxv6f16(half, <vscale x 6 x half>)
define half @vreduce_ord_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) { define half @vreduce_ord_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv6f16: ; CHECK-LABEL: vreduce_ord_fadd_nxv6f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vmv.v.x v11, a0 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v9, v11, a0 ; CHECK-NEXT: vslideup.vx v9, v10, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfredosum.vs v8, v8, v10 ; CHECK-NEXT: vfredosum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v) %red = call half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.nxv10f16(half, <vscale x 10 x half>) declare half @llvm.vector.reduce.fadd.nxv10f16(half, <vscale x 10 x half>)
define half @vreduce_ord_fadd_nxv10f16(<vscale x 10 x half> %v, half %s) { define half @vreduce_ord_fadd_nxv10f16(<vscale x 10 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv10f16: ; CHECK-LABEL: vreduce_ord_fadd_nxv10f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v10, v12, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vmv.v.v v11, v12 ; CHECK-NEXT: vmv.v.v v11, v12
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v11, v12, a0 ; CHECK-NEXT: vslideup.vx v11, v12, a0
; CHECK-NEXT: vslideup.vx v10, v12, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfmv.s.f v12, fa0 ; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vfredosum.vs v8, v8, v12 ; CHECK-NEXT: vfredosum.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv10f16(half %s, <vscale x 10 x half> %v) %red = call half @llvm.vector.reduce.fadd.nxv10f16(half %s, <vscale x 10 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fadd.nxv12f16(half, <vscale x 12 x half>) declare half @llvm.vector.reduce.fadd.nxv12f16(half, <vscale x 12 x half>)
define half @vreduce_ord_fadd_nxv12f16(<vscale x 12 x half> %v, half %s) { define half @vreduce_ord_fadd_nxv12f16(<vscale x 12 x half> %v, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_nxv12f16: ; CHECK-LABEL: vreduce_ord_fadd_nxv12f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v11, a0 ; CHECK-NEXT: vmv.v.x v11, a0
; CHECK-NEXT: vfmv.s.f v12, fa0
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfredosum.vs v8, v8, v12 ; CHECK-NEXT: vfredosum.vs v8, v8, v12
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fadd.nxv12f16(half %s, <vscale x 12 x half> %v) %red = call half @llvm.vector.reduce.fadd.nxv12f16(half %s, <vscale x 12 x half> %v)
ret half %red ret half %red
} }
; Test Widen vector reduce type (fadd/fmin/fmax) ; Test Widen vector reduce type (fadd/fmin/fmax)
define half @vreduce_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) { define half @vreduce_fadd_nxv3f16(<vscale x 3 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv3f16: ; CHECK-LABEL: vreduce_fadd_nxv3f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3 ; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 1 ; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a1, a1, a0 ; CHECK-NEXT: add a1, a1, a0
; CHECK-NEXT: add a0, a1, a0 ; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: lui a2, 1048568
; CHECK-NEXT: vsetvli a3, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v9, a2
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v8, v9, a1 ; CHECK-NEXT: vslideup.vx v8, v9, a1
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v9, fa0 ; CHECK-NEXT: vfmv.s.f v9, fa0
; CHECK-NEXT: vfredusum.vs v8, v8, v9 ; CHECK-NEXT: vfredusum.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.nxv3f16(half %s, <vscale x 3 x half> %v)
ret half %red ret half %red
} }
define half @vreduce_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) { define half @vreduce_fadd_nxv6f16(<vscale x 6 x half> %v, half %s) {
; CHECK-LABEL: vreduce_fadd_nxv6f16: ; CHECK-LABEL: vreduce_fadd_nxv6f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: lui a0, 1048568 ; CHECK-NEXT: lui a0, 1048568
; CHECK-NEXT: vmv.v.x v11, a0 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0 ; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v9, v11, a0 ; CHECK-NEXT: vslideup.vx v9, v10, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT: vfmv.s.f v10, fa0
; CHECK-NEXT: vfredusum.vs v8, v8, v10 ; CHECK-NEXT: vfredusum.vs v8, v8, v10
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call reassoc half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v) %red = call reassoc half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v)
ret half %red ret half %red
} }
declare half @llvm.vector.reduce.fmin.nxv10f16(<vscale x 10 x half>) declare half @llvm.vector.reduce.fmin.nxv10f16(<vscale x 10 x half>)
define half @vreduce_fmin_nxv10f16(<vscale x 10 x half> %v) { define half @vreduce_fmin_nxv10f16(<vscale x 10 x half> %v) {
; CHECK-LABEL: vreduce_fmin_nxv10f16: ; CHECK-LABEL: vreduce_fmin_nxv10f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI73_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI73_0)
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vlse16.v v12, (a0), zero
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: lui a1, %hi(.LCPI73_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI73_0)
; CHECK-NEXT: vsetvli a2, zero, e16, m1, ta, ma
; CHECK-NEXT: vlse16.v v12, (a1), zero
; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v10, v12, a0
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: vmv.v.v v11, v12 ; CHECK-NEXT: vmv.v.v v11, v12
; CHECK-NEXT: add a1, a0, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
; CHECK-NEXT: vslideup.vx v11, v12, a0 ; CHECK-NEXT: vslideup.vx v11, v12, a0
; CHECK-NEXT: vslideup.vx v10, v12, a0
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vfredmin.vs v8, v8, v8 ; CHECK-NEXT: vfredmin.vs v8, v8, v8
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%red = call half @llvm.vector.reduce.fmin.nxv10f16(<vscale x 10 x half> %v) %red = call half @llvm.vector.reduce.fmin.nxv10f16(<vscale x 10 x half> %v)
ret half %red ret half %red
} }
Show All 15 Lines

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret half %r ret half %r
} }
declare half @llvm.vp.reduce.fadd.nxv64f16(half, <vscale x 64 x half>, <vscale x 64 x i1>, i32) declare half @llvm.vp.reduce.fadd.nxv64f16(half, <vscale x 64 x half>, <vscale x 64 x i1>, i32)
define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) { define half @vpreduce_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_fadd_nxv64f16: ; CHECK-LABEL: vpreduce_fadd_nxv64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a2, a1, 1 ; CHECK-NEXT: srli a1, a2, 1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v24, v0, a2 ; CHECK-NEXT: vslidedown.vx v24, v0, a1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: slli a1, a1, 2 ; CHECK-NEXT: sub a1, a0, a2
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: sltu a3, a0, a1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: bltu a0, a1, .LBB6_2 ; CHECK-NEXT: and a1, a3, a1
; CHECK-NEXT: bltu a0, a2, .LBB6_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: .LBB6_2: ; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: sub a1, a0, a1
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vfredusum.vs v25, v8, v25, v0.t
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredusum.vs v25, v16, v25, v0.t ; CHECK-NEXT: vfredusum.vs v25, v16, v25, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call reassoc half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl) %r = call reassoc half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)
ret half %r ret half %r
} }
define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) { define half @vpreduce_ord_fadd_nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vpreduce_ord_fadd_nxv64f16: ; CHECK-LABEL: vpreduce_ord_fadd_nxv64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a2, vlenb
; CHECK-NEXT: srli a2, a1, 1 ; CHECK-NEXT: srli a1, a2, 1
; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma ; CHECK-NEXT: vsetvli a3, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v24, v0, a2 ; CHECK-NEXT: vslidedown.vx v24, v0, a1
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma ; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: slli a1, a1, 2 ; CHECK-NEXT: sub a1, a0, a2
; CHECK-NEXT: vfmv.s.f v25, fa0 ; CHECK-NEXT: sltu a3, a0, a1
; CHECK-NEXT: mv a2, a0 ; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: bltu a0, a1, .LBB7_2 ; CHECK-NEXT: and a1, a3, a1
; CHECK-NEXT: bltu a0, a2, .LBB7_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, a1 ; CHECK-NEXT: mv a0, a2
; CHECK-NEXT: .LBB7_2: ; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vsetvli zero, a2, e16, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t ; CHECK-NEXT: vfmv.s.f v25, fa0
; CHECK-NEXT: sub a1, a0, a1
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: addi a0, a0, -1
; CHECK-NEXT: and a0, a0, a1
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT: vfredosum.vs v25, v8, v25, v0.t
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vmv1r.v v0, v24
; CHECK-NEXT: vfredosum.vs v25, v16, v25, v0.t ; CHECK-NEXT: vfredosum.vs v25, v16, v25, v0.t
; CHECK-NEXT: vfmv.f.s fa0, v25 ; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = call half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl) %r = call half @llvm.vp.reduce.fadd.nxv64f16(half %s, <vscale x 64 x half> %v, <vscale x 64 x i1> %m, i32 %evl)
ret half %r ret half %r
} }
▲ Show 20 Lines • Show All 195 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll

Show First 20 Lines • Show All 1,147 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
ret i32 %r ret i32 %r
} }
declare i32 @llvm.vp.reduce.umax.nxv32i32(i32, <vscale x 32 x i32>, <vscale x 32 x i1>, i32) declare i32 @llvm.vp.reduce.umax.nxv32i32(i32, <vscale x 32 x i32>, <vscale x 32 x i1>, i32)
define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) { define signext i32 @vpreduce_umax_nxv32i32(i32 signext %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpreduce_umax_nxv32i32: ; RV32-LABEL: vpreduce_umax_nxv32i32:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: csrr a2, vlenb ; RV32-NEXT: csrr a3, vlenb
; RV32-NEXT: srli a3, a2, 2 ; RV32-NEXT: srli a2, a3, 2
; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; RV32-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; RV32-NEXT: vslidedown.vx v24, v0, a3 ; RV32-NEXT: vslidedown.vx v24, v0, a2
; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV32-NEXT: slli a3, a3, 1
; RV32-NEXT: slli a2, a2, 1 ; RV32-NEXT: sub a2, a1, a3
; RV32-NEXT: vmv.s.x v25, a0 ; RV32-NEXT: sltu a4, a1, a2
; RV32-NEXT: mv a0, a1 ; RV32-NEXT: addi a4, a4, -1
; RV32-NEXT: bltu a1, a2, .LBB67_2 ; RV32-NEXT: and a2, a4, a2
; RV32-NEXT: bltu a1, a3, .LBB67_2
; RV32-NEXT: # %bb.1: ; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a2 ; RV32-NEXT: mv a1, a3
; RV32-NEXT: .LBB67_2: ; RV32-NEXT: .LBB67_2:
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV32-NEXT: vmv.s.x v25, a0
; RV32-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV32-NEXT: vredmaxu.vs v25, v8, v25, v0.t
; RV32-NEXT: sub a0, a1, a2 ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: sltu a1, a1, a0
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a0, a1, a0
; RV32-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: vmv1r.v v0, v24
; RV32-NEXT: vredmaxu.vs v25, v16, v25, v0.t ; RV32-NEXT: vredmaxu.vs v25, v16, v25, v0.t
; RV32-NEXT: vmv.x.s a0, v25 ; RV32-NEXT: vmv.x.s a0, v25
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpreduce_umax_nxv32i32: ; RV64-LABEL: vpreduce_umax_nxv32i32:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a3, vlenb
; RV64-NEXT: srli a3, a2, 2 ; RV64-NEXT: srli a2, a3, 2
; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; RV64-NEXT: vsetvli a4, zero, e8, mf2, ta, ma
; RV64-NEXT: vslidedown.vx v24, v0, a3 ; RV64-NEXT: vslidedown.vx v24, v0, a2
; RV64-NEXT: slli a3, a0, 32 ; RV64-NEXT: slli a0, a0, 32
; RV64-NEXT: slli a0, a2, 1 ; RV64-NEXT: srli a2, a0, 32
; RV64-NEXT: srli a3, a3, 32 ; RV64-NEXT: slli a3, a3, 1
; RV64-NEXT: mv a2, a1 ; RV64-NEXT: sub a0, a1, a3
; RV64-NEXT: bltu a1, a0, .LBB67_2 ; RV64-NEXT: sltu a4, a1, a0
; RV64-NEXT: addi a4, a4, -1
; RV64-NEXT: and a0, a4, a0
; RV64-NEXT: bltu a1, a3, .LBB67_2
; RV64-NEXT: # %bb.1: ; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a2, a0 ; RV64-NEXT: mv a1, a3
; RV64-NEXT: .LBB67_2: ; RV64-NEXT: .LBB67_2:
; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma ; RV64-NEXT: vsetivli zero, 1, e32, m1, ta, ma
; RV64-NEXT: vmv.s.x v25, a3 ; RV64-NEXT: vmv.s.x v25, a2
; RV64-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV64-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t ; RV64-NEXT: vredmaxu.vs v25, v8, v25, v0.t
; RV64-NEXT: sub a0, a1, a0
; RV64-NEXT: sltu a1, a1, a0
; RV64-NEXT: addi a1, a1, -1
; RV64-NEXT: and a0, a1, a0
; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV64-NEXT: vsetvli zero, a0, e32, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v24 ; RV64-NEXT: vmv1r.v v0, v24
; RV64-NEXT: vredmaxu.vs v25, v16, v25, v0.t ; RV64-NEXT: vredmaxu.vs v25, v16, v25, v0.t
; RV64-NEXT: vmv.x.s a0, v25 ; RV64-NEXT: vmv.x.s a0, v25
; RV64-NEXT: ret ; RV64-NEXT: ret
%r = call i32 @llvm.vp.reduce.umax.nxv32i32(i32 %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 %evl) %r = call i32 @llvm.vp.reduce.umax.nxv32i32(i32 %s, <vscale x 32 x i32> %v, <vscale x 32 x i1> %m, i32 %evl)
ret i32 %r ret i32 %r
} }
▲ Show 20 Lines • Show All 1,123 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll

Show First 20 Lines • Show All 1,224 Lines • ▼ Show 20 Lines
declare i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64>) declare i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64>)
define i64 @vreduce_umax_nxv1i64(<vscale x 1 x i64> %v) { define i64 @vreduce_umax_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_umax_nxv1i64: ; RV32-LABEL: vreduce_umax_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vredmaxu.vs v8, v8, v8 ; RV32-NEXT: vredmaxu.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_umax_nxv1i64: ; RV64-LABEL: vreduce_umax_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT: vredmaxu.vs v8, v8, v8 ; RV64-NEXT: vredmaxu.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%red = call i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64> %v) %red = call i64 @llvm.vector.reduce.umax.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64>) declare i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64>)
define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) { define i64 @vreduce_smax_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_smax_nxv1i64: ; RV32-LABEL: vreduce_smax_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vredmax.vs v8, v8, v8 ; RV32-NEXT: vredmax.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_smax_nxv1i64: ; RV64-LABEL: vreduce_smax_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT: vredmax.vs v8, v8, v8 ; RV64-NEXT: vredmax.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%red = call i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64> %v) %red = call i64 @llvm.vector.reduce.smax.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64>) declare i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64>)
define i64 @vreduce_umin_nxv1i64(<vscale x 1 x i64> %v) { define i64 @vreduce_umin_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_umin_nxv1i64: ; RV32-LABEL: vreduce_umin_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vredminu.vs v8, v8, v8 ; RV32-NEXT: vredminu.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_umin_nxv1i64: ; RV64-LABEL: vreduce_umin_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT: vredminu.vs v8, v8, v8 ; RV64-NEXT: vredminu.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%red = call i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64> %v) %red = call i64 @llvm.vector.reduce.umin.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64>) declare i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64>)
define i64 @vreduce_smin_nxv1i64(<vscale x 1 x i64> %v) { define i64 @vreduce_smin_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_smin_nxv1i64: ; RV32-LABEL: vreduce_smin_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vredmin.vs v8, v8, v8 ; RV32-NEXT: vredmin.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_smin_nxv1i64: ; RV64-LABEL: vreduce_smin_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT: vredmin.vs v8, v8, v8 ; RV64-NEXT: vredmin.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%red = call i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64> %v) %red = call i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64>) declare i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64>)
define i64 @vreduce_and_nxv1i64(<vscale x 1 x i64> %v) { define i64 @vreduce_and_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_and_nxv1i64: ; RV32-LABEL: vreduce_and_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vredand.vs v8, v8, v8 ; RV32-NEXT: vredand.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_and_nxv1i64: ; RV64-LABEL: vreduce_and_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT: vredand.vs v8, v8, v8 ; RV64-NEXT: vredand.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
%red = call i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64> %v) %red = call i64 @llvm.vector.reduce.and.nxv1i64(<vscale x 1 x i64> %v)
ret i64 %red ret i64 %red
} }
declare i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64>) declare i64 @llvm.vector.reduce.or.nxv1i64(<vscale x 1 x i64>)
define i64 @vreduce_or_nxv1i64(<vscale x 1 x i64> %v) { define i64 @vreduce_or_nxv1i64(<vscale x 1 x i64> %v) {
; RV32-LABEL: vreduce_or_nxv1i64: ; RV32-LABEL: vreduce_or_nxv1i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32-NEXT: vredor.vs v8, v8, v8 ; RV32-NEXT: vredor.vs v8, v8, v8
; RV32-NEXT: vmv.x.s a0, v8 ; RV32-NEXT: li a0, 32
; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; RV32-NEXT: vsetivli zero, 1, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v8, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a0
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v9
; RV32-NEXT: vmv.x.s a0, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vreduce_or_nxv1i64: ; RV64-LABEL: vreduce_or_nxv1i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64-NEXT: vredor.vs v8, v8, v8 ; RV64-NEXT: vredor.vs v8, v8, v8
; RV64-NEXT: vmv.x.s a0, v8 ; RV64-NEXT: vmv.x.s a0, v8
; RV64-NEXT: ret ; RV64-NEXT: ret
▲ Show 20 Lines • Show All 538 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

Show First 20 Lines • Show All 1,658 Lines • ▼ Show 20 Lines; CHECK-ZVBB64-NEXT: ret
%b.splat = shufflevector <vscale x 1 x i64> %b.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer %b.splat = shufflevector <vscale x 1 x i64> %b.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b.splat) %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> %b.splat)
ret <vscale x 1 x i64> %x ret <vscale x 1 x i64> %x
} }
define <vscale x 1 x i64> @vror_vi_nxv1i64(<vscale x 1 x i64> %a) { define <vscale x 1 x i64> @vror_vi_nxv1i64(<vscale x 1 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_nxv1i64: ; CHECK-RV32-LABEL: vror_vi_nxv1i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v9, 1
; CHECK-RV32-NEXT: vrsub.vi v9, v9, 0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-RV32-NEXT: vand.vx v9, v9, a0
; CHECK-RV32-NEXT: vmv.v.x v9, a0 ; CHECK-RV32-NEXT: vsll.vv v9, v8, v9
; CHECK-RV32-NEXT: vand.vi v9, v9, 1 ; CHECK-RV32-NEXT: vmv.v.x v10, a0
; CHECK-RV32-NEXT: vsrl.vv v9, v8, v9 ; CHECK-RV32-NEXT: vand.vi v10, v10, 1
; CHECK-RV32-NEXT: vmv.v.i v10, 1 ; CHECK-RV32-NEXT: vsrl.vv v8, v8, v10
; CHECK-RV32-NEXT: vrsub.vi v10, v10, 0 ; CHECK-RV32-NEXT: vor.vv v8, v8, v9
; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vsll.vv v8, v8, v10
; CHECK-RV32-NEXT: vor.vv v8, v9, v8
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_nxv1i64: ; CHECK-RV64-LABEL: vror_vi_nxv1i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-RV64-NEXT: vsll.vx v9, v8, a0 ; CHECK-RV64-NEXT: vsll.vx v9, v8, a0
; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1 ; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1
; CHECK-RV64-NEXT: vor.vv v8, v8, v9 ; CHECK-RV64-NEXT: vor.vv v8, v8, v9
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: vror_vi_nxv1i64: ; CHECK-ZVBB-LABEL: vror_vi_nxv1i64:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> shufflevector(<vscale x 1 x i64> insertelement(<vscale x 1 x i64> poison, i64 1, i32 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer)) %x = call <vscale x 1 x i64> @llvm.fshr.nxv1i64(<vscale x 1 x i64> %a, <vscale x 1 x i64> %a, <vscale x 1 x i64> shufflevector(<vscale x 1 x i64> insertelement(<vscale x 1 x i64> poison, i64 1, i32 0), <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer))
ret <vscale x 1 x i64> %x ret <vscale x 1 x i64> %x
} }
define <vscale x 1 x i64> @vror_vi_rotl_nxv1i64(<vscale x 1 x i64> %a) { define <vscale x 1 x i64> @vror_vi_rotl_nxv1i64(<vscale x 1 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_rotl_nxv1i64: ; CHECK-RV32-LABEL: vror_vi_rotl_nxv1i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v9, 1
; CHECK-RV32-NEXT: vrsub.vi v9, v9, 0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-RV32-NEXT: vand.vx v9, v9, a0
; CHECK-RV32-NEXT: vmv.v.x v9, a0 ; CHECK-RV32-NEXT: vsrl.vv v9, v8, v9
; CHECK-RV32-NEXT: vand.vi v9, v9, 1 ; CHECK-RV32-NEXT: vmv.v.x v10, a0
; CHECK-RV32-NEXT: vsll.vv v9, v8, v9 ; CHECK-RV32-NEXT: vand.vi v10, v10, 1
; CHECK-RV32-NEXT: vmv.v.i v10, 1 ; CHECK-RV32-NEXT: vsll.vv v8, v8, v10
; CHECK-RV32-NEXT: vrsub.vi v10, v10, 0 ; CHECK-RV32-NEXT: vor.vv v8, v8, v9
; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v10
; CHECK-RV32-NEXT: vor.vv v8, v9, v8
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_rotl_nxv1i64: ; CHECK-RV64-LABEL: vror_vi_rotl_nxv1i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-RV64-NEXT: vsrl.vx v9, v8, a0 ; CHECK-RV64-NEXT: vsrl.vx v9, v8, a0
; CHECK-RV64-NEXT: vadd.vv v8, v8, v8 ; CHECK-RV64-NEXT: vadd.vv v8, v8, v8
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines; CHECK-ZVBB64-NEXT: ret
%b.splat = shufflevector <vscale x 2 x i64> %b.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer %b.splat = shufflevector <vscale x 2 x i64> %b.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b.splat) %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b.splat)
ret <vscale x 2 x i64> %x ret <vscale x 2 x i64> %x
} }
define <vscale x 2 x i64> @vror_vi_nxv2i64(<vscale x 2 x i64> %a) { define <vscale x 2 x i64> @vror_vi_nxv2i64(<vscale x 2 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_nxv2i64: ; CHECK-RV32-LABEL: vror_vi_nxv2i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v10, 1
; CHECK-RV32-NEXT: vrsub.vi v10, v10, 0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vmv.v.x v10, a0 ; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
; CHECK-RV32-NEXT: vand.vi v10, v10, 1 ; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10 ; CHECK-RV32-NEXT: vand.vi v12, v12, 1
; CHECK-RV32-NEXT: vmv.v.i v12, 1 ; CHECK-RV32-NEXT: vsrl.vv v8, v8, v12
; CHECK-RV32-NEXT: vrsub.vi v12, v12, 0 ; CHECK-RV32-NEXT: vor.vv v8, v8, v10
; CHECK-RV32-NEXT: vand.vx v12, v12, a0
; CHECK-RV32-NEXT: vsll.vv v8, v8, v12
; CHECK-RV32-NEXT: vor.vv v8, v10, v8
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_nxv2i64: ; CHECK-RV64-LABEL: vror_vi_nxv2i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-RV64-NEXT: vsll.vx v10, v8, a0 ; CHECK-RV64-NEXT: vsll.vx v10, v8, a0
; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1 ; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1
; CHECK-RV64-NEXT: vor.vv v8, v8, v10 ; CHECK-RV64-NEXT: vor.vv v8, v8, v10
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: vror_vi_nxv2i64: ; CHECK-ZVBB-LABEL: vror_vi_nxv2i64:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> shufflevector(<vscale x 2 x i64> insertelement(<vscale x 2 x i64> poison, i64 1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)) %x = call <vscale x 2 x i64> @llvm.fshr.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vscale x 2 x i64> shufflevector(<vscale x 2 x i64> insertelement(<vscale x 2 x i64> poison, i64 1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer))
ret <vscale x 2 x i64> %x ret <vscale x 2 x i64> %x
} }
define <vscale x 2 x i64> @vror_vi_rotl_nxv2i64(<vscale x 2 x i64> %a) { define <vscale x 2 x i64> @vror_vi_rotl_nxv2i64(<vscale x 2 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_rotl_nxv2i64: ; CHECK-RV32-LABEL: vror_vi_rotl_nxv2i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v10, 1
; CHECK-RV32-NEXT: vrsub.vi v10, v10, 0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-RV32-NEXT: vand.vx v10, v10, a0
; CHECK-RV32-NEXT: vmv.v.x v10, a0 ; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10
; CHECK-RV32-NEXT: vand.vi v10, v10, 1 ; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: vsll.vv v10, v8, v10 ; CHECK-RV32-NEXT: vand.vi v12, v12, 1
; CHECK-RV32-NEXT: vmv.v.i v12, 1 ; CHECK-RV32-NEXT: vsll.vv v8, v8, v12
; CHECK-RV32-NEXT: vrsub.vi v12, v12, 0 ; CHECK-RV32-NEXT: vor.vv v8, v8, v10
; CHECK-RV32-NEXT: vand.vx v12, v12, a0
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v12
; CHECK-RV32-NEXT: vor.vv v8, v10, v8
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_rotl_nxv2i64: ; CHECK-RV64-LABEL: vror_vi_rotl_nxv2i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-RV64-NEXT: vsrl.vx v10, v8, a0 ; CHECK-RV64-NEXT: vsrl.vx v10, v8, a0
; CHECK-RV64-NEXT: vadd.vv v8, v8, v8 ; CHECK-RV64-NEXT: vadd.vv v8, v8, v8
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines; CHECK-ZVBB64-NEXT: ret
%b.splat = shufflevector <vscale x 4 x i64> %b.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer %b.splat = shufflevector <vscale x 4 x i64> %b.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b.splat) %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> %b.splat)
ret <vscale x 4 x i64> %x ret <vscale x 4 x i64> %x
} }
define <vscale x 4 x i64> @vror_vi_nxv4i64(<vscale x 4 x i64> %a) { define <vscale x 4 x i64> @vror_vi_nxv4i64(<vscale x 4 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_nxv4i64: ; CHECK-RV32-LABEL: vror_vi_nxv4i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v12, 1
; CHECK-RV32-NEXT: vrsub.vi v12, v12, 0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-RV32-NEXT: vand.vx v12, v12, a0
; CHECK-RV32-NEXT: vmv.v.x v12, a0 ; CHECK-RV32-NEXT: vsll.vv v12, v8, v12
; CHECK-RV32-NEXT: vand.vi v12, v12, 1 ; CHECK-RV32-NEXT: vmv.v.x v16, a0
; CHECK-RV32-NEXT: vsrl.vv v12, v8, v12 ; CHECK-RV32-NEXT: vand.vi v16, v16, 1
; CHECK-RV32-NEXT: vmv.v.i v16, 1 ; CHECK-RV32-NEXT: vsrl.vv v8, v8, v16
; CHECK-RV32-NEXT: vrsub.vi v16, v16, 0 ; CHECK-RV32-NEXT: vor.vv v8, v8, v12
; CHECK-RV32-NEXT: vand.vx v16, v16, a0
; CHECK-RV32-NEXT: vsll.vv v8, v8, v16
; CHECK-RV32-NEXT: vor.vv v8, v12, v8
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_nxv4i64: ; CHECK-RV64-LABEL: vror_vi_nxv4i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-RV64-NEXT: vsll.vx v12, v8, a0 ; CHECK-RV64-NEXT: vsll.vx v12, v8, a0
; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1 ; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1
; CHECK-RV64-NEXT: vor.vv v8, v8, v12 ; CHECK-RV64-NEXT: vor.vv v8, v8, v12
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: vror_vi_nxv4i64: ; CHECK-ZVBB-LABEL: vror_vi_nxv4i64:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> shufflevector(<vscale x 4 x i64> insertelement(<vscale x 4 x i64> poison, i64 1, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)) %x = call <vscale x 4 x i64> @llvm.fshr.nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %a, <vscale x 4 x i64> shufflevector(<vscale x 4 x i64> insertelement(<vscale x 4 x i64> poison, i64 1, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer))
ret <vscale x 4 x i64> %x ret <vscale x 4 x i64> %x
} }
define <vscale x 4 x i64> @vror_vi_rotl_nxv4i64(<vscale x 4 x i64> %a) { define <vscale x 4 x i64> @vror_vi_rotl_nxv4i64(<vscale x 4 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_rotl_nxv4i64: ; CHECK-RV32-LABEL: vror_vi_rotl_nxv4i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v12, 1
; CHECK-RV32-NEXT: vrsub.vi v12, v12, 0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-RV32-NEXT: vand.vx v12, v12, a0
; CHECK-RV32-NEXT: vmv.v.x v12, a0 ; CHECK-RV32-NEXT: vsrl.vv v12, v8, v12
; CHECK-RV32-NEXT: vand.vi v12, v12, 1 ; CHECK-RV32-NEXT: vmv.v.x v16, a0
; CHECK-RV32-NEXT: vsll.vv v12, v8, v12 ; CHECK-RV32-NEXT: vand.vi v16, v16, 1
; CHECK-RV32-NEXT: vmv.v.i v16, 1 ; CHECK-RV32-NEXT: vsll.vv v8, v8, v16
; CHECK-RV32-NEXT: vrsub.vi v16, v16, 0 ; CHECK-RV32-NEXT: vor.vv v8, v8, v12
; CHECK-RV32-NEXT: vand.vx v16, v16, a0
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v16
; CHECK-RV32-NEXT: vor.vv v8, v12, v8
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_rotl_nxv4i64: ; CHECK-RV64-LABEL: vror_vi_rotl_nxv4i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-RV64-NEXT: vsrl.vx v12, v8, a0 ; CHECK-RV64-NEXT: vsrl.vx v12, v8, a0
; CHECK-RV64-NEXT: vadd.vv v8, v8, v8 ; CHECK-RV64-NEXT: vadd.vv v8, v8, v8
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines; CHECK-ZVBB64-NEXT: ret
%b.splat = shufflevector <vscale x 8 x i64> %b.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer %b.splat = shufflevector <vscale x 8 x i64> %b.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b.splat) %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b.splat)
ret <vscale x 8 x i64> %x ret <vscale x 8 x i64> %x
} }
define <vscale x 8 x i64> @vror_vi_nxv8i64(<vscale x 8 x i64> %a) { define <vscale x 8 x i64> @vror_vi_nxv8i64(<vscale x 8 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_nxv8i64: ; CHECK-RV32-LABEL: vror_vi_nxv8i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v16, 1
; CHECK-RV32-NEXT: vrsub.vi v16, v16, 0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-RV32-NEXT: vand.vx v16, v16, a0
; CHECK-RV32-NEXT: vmv.v.x v16, a0 ; CHECK-RV32-NEXT: vsll.vv v16, v8, v16
; CHECK-RV32-NEXT: vand.vi v16, v16, 1 ; CHECK-RV32-NEXT: vmv.v.x v24, a0
; CHECK-RV32-NEXT: vsrl.vv v16, v8, v16 ; CHECK-RV32-NEXT: vand.vi v24, v24, 1
; CHECK-RV32-NEXT: vmv.v.i v24, 1 ; CHECK-RV32-NEXT: vsrl.vv v8, v8, v24
; CHECK-RV32-NEXT: vrsub.vi v24, v24, 0 ; CHECK-RV32-NEXT: vor.vv v8, v8, v16
; CHECK-RV32-NEXT: vand.vx v24, v24, a0
; CHECK-RV32-NEXT: vsll.vv v8, v8, v24
; CHECK-RV32-NEXT: vor.vv v8, v16, v8
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_nxv8i64: ; CHECK-RV64-LABEL: vror_vi_nxv8i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-RV64-NEXT: vsll.vx v16, v8, a0 ; CHECK-RV64-NEXT: vsll.vx v16, v8, a0
; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1 ; CHECK-RV64-NEXT: vsrl.vi v8, v8, 1
; CHECK-RV64-NEXT: vor.vv v8, v8, v16 ; CHECK-RV64-NEXT: vor.vv v8, v8, v16
; CHECK-RV64-NEXT: ret ; CHECK-RV64-NEXT: ret
; ;
; CHECK-ZVBB-LABEL: vror_vi_nxv8i64: ; CHECK-ZVBB-LABEL: vror_vi_nxv8i64:
; CHECK-ZVBB: # %bb.0: ; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-ZVBB-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1 ; CHECK-ZVBB-NEXT: vror.vi v8, v8, 1
; CHECK-ZVBB-NEXT: ret ; CHECK-ZVBB-NEXT: ret
%x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> shufflevector(<vscale x 8 x i64> insertelement(<vscale x 8 x i64> poison, i64 1, i32 0), <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer)) %x = call <vscale x 8 x i64> @llvm.fshr.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> shufflevector(<vscale x 8 x i64> insertelement(<vscale x 8 x i64> poison, i64 1, i32 0), <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer))
ret <vscale x 8 x i64> %x ret <vscale x 8 x i64> %x
} }
define <vscale x 8 x i64> @vror_vi_rotl_nxv8i64(<vscale x 8 x i64> %a) { define <vscale x 8 x i64> @vror_vi_rotl_nxv8i64(<vscale x 8 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_rotl_nxv8i64: ; CHECK-RV32-LABEL: vror_vi_rotl_nxv8i64:
; CHECK-RV32: # %bb.0: ; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv.v.i v16, 1
; CHECK-RV32-NEXT: vrsub.vi v16, v16, 0
; CHECK-RV32-NEXT: li a0, 63 ; CHECK-RV32-NEXT: li a0, 63
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-RV32-NEXT: vand.vx v16, v16, a0
; CHECK-RV32-NEXT: vmv.v.x v16, a0 ; CHECK-RV32-NEXT: vsrl.vv v16, v8, v16
; CHECK-RV32-NEXT: vand.vi v16, v16, 1 ; CHECK-RV32-NEXT: vmv.v.x v24, a0
; CHECK-RV32-NEXT: vsll.vv v16, v8, v16 ; CHECK-RV32-NEXT: vand.vi v24, v24, 1
; CHECK-RV32-NEXT: vmv.v.i v24, 1 ; CHECK-RV32-NEXT: vsll.vv v8, v8, v24
; CHECK-RV32-NEXT: vrsub.vi v24, v24, 0 ; CHECK-RV32-NEXT: vor.vv v8, v8, v16
; CHECK-RV32-NEXT: vand.vx v24, v24, a0
; CHECK-RV32-NEXT: vsrl.vv v8, v8, v24
; CHECK-RV32-NEXT: vor.vv v8, v16, v8
; CHECK-RV32-NEXT: ret ; CHECK-RV32-NEXT: ret
; ;
; CHECK-RV64-LABEL: vror_vi_rotl_nxv8i64: ; CHECK-RV64-LABEL: vror_vi_rotl_nxv8i64:
; CHECK-RV64: # %bb.0: ; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a0, 63 ; CHECK-RV64-NEXT: li a0, 63
; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-RV64-NEXT: vsrl.vx v16, v8, a0 ; CHECK-RV64-NEXT: vsrl.vx v16, v8, a0
; CHECK-RV64-NEXT: vadd.vv v8, v8, v8 ; CHECK-RV64-NEXT: vadd.vv v8, v8, v8
Show All 12 Lines

llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll

Show First 20 Lines • Show All 291 Lines • ▼ Show 20 Lines
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a3, a1, 2 ; CHECK-NEXT: srli a3, a1, 3
; CHECK-NEXT: vsetvli a4, zero, e8, mf2, ta, ma ; CHECK-NEXT: srli a4, a1, 2
; CHECK-NEXT: vslidedown.vx v16, v0, a3 ; CHECK-NEXT: vsetvli a5, zero, e8, mf2, ta, ma
; CHECK-NEXT: vsetvli a3, zero, e8, mf4, ta, ma ; CHECK-NEXT: vslidedown.vx v16, v0, a4
; CHECK-NEXT: slli a3, a1, 3 ; CHECK-NEXT: slli a4, a1, 3
; CHECK-NEXT: add a3, a0, a3 ; CHECK-NEXT: add a4, a0, a4
; CHECK-NEXT: vl8re64.v v24, (a3) ; CHECK-NEXT: vl8re64.v v8, (a4)
; CHECK-NEXT: slli a3, a1, 1 ; CHECK-NEXT: slli a4, a1, 1
; CHECK-NEXT: sub a4, a2, a3 ; CHECK-NEXT: sub a5, a2, a4
; CHECK-NEXT: sltu a5, a2, a4 ; CHECK-NEXT: sltu a6, a2, a5
; CHECK-NEXT: addi a5, a5, -1
; CHECK-NEXT: and a4, a5, a4
; CHECK-NEXT: sub a5, a4, a1
; CHECK-NEXT: sltu a6, a4, a5
; CHECK-NEXT: addi a6, a6, -1 ; CHECK-NEXT: addi a6, a6, -1
; CHECK-NEXT: and a6, a6, a5 ; CHECK-NEXT: and a5, a6, a5
; CHECK-NEXT: srli a5, a1, 3 ; CHECK-NEXT: sub a6, a5, a1
; CHECK-NEXT: vl8re64.v v8, (a0) ; CHECK-NEXT: sltu a7, a5, a6
; CHECK-NEXT: vslidedown.vx v0, v16, a5 ; CHECK-NEXT: addi a7, a7, -1
; CHECK-NEXT: and a6, a7, a6
; CHECK-NEXT: vsetvli a7, zero, e8, mf4, ta, ma
; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: vslidedown.vx v0, v16, a3
; CHECK-NEXT: vsetvli zero, a6, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a6, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v20, v24, 0, v0.t ; CHECK-NEXT: vnsrl.wi v20, v8, 0, v0.t
; CHECK-NEXT: bltu a4, a1, .LBB17_2 ; CHECK-NEXT: bltu a5, a1, .LBB17_2
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a4, a1 ; CHECK-NEXT: mv a5, a1
; CHECK-NEXT: .LBB17_2: ; CHECK-NEXT: .LBB17_2:
; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
; CHECK-NEXT: vslidedown.vx v2, v1, a5 ; CHECK-NEXT: vslidedown.vx v2, v1, a3
; CHECK-NEXT: vsetvli zero, a4, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a5, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vnsrl.wi v16, v8, 0, v0.t ; CHECK-NEXT: vnsrl.wi v16, v24, 0, v0.t
; CHECK-NEXT: bltu a2, a3, .LBB17_4 ; CHECK-NEXT: bltu a2, a4, .LBB17_4
; CHECK-NEXT: # %bb.3: ; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: mv a2, a3 ; CHECK-NEXT: mv a2, a4
; CHECK-NEXT: .LBB17_4: ; CHECK-NEXT: .LBB17_4:
; CHECK-NEXT: sub a0, a2, a1 ; CHECK-NEXT: sub a0, a2, a1
; CHECK-NEXT: sltu a3, a2, a0 ; CHECK-NEXT: sltu a3, a2, a0
; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: addi a3, a3, -1
; CHECK-NEXT: and a0, a3, a0 ; CHECK-NEXT: and a0, a3, a0
; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma
; CHECK-NEXT: vmv1r.v v0, v2 ; CHECK-NEXT: vmv1r.v v0, v2
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
Show All 23 Lines

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

Show First 20 Lines • Show All 716 Lines • ▼ Show 20 Lines
; RV32MV-NEXT: lw s2, 32(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32MV-NEXT: lw s3, 28(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32MV-NEXT: lw s4, 24(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32MV-NEXT: addi sp, sp, 48 ; RV32MV-NEXT: addi sp, sp, 48
; RV32MV-NEXT: ret ; RV32MV-NEXT: ret
; ;
; RV64MV-LABEL: test_srem_vec: ; RV64MV-LABEL: test_srem_vec:
; RV64MV: # %bb.0: ; RV64MV: # %bb.0:
; RV64MV-NEXT: lbu a1, 12(a0) ; RV64MV-NEXT: ld a1, 0(a0)
; RV64MV-NEXT: lwu a2, 8(a0) ; RV64MV-NEXT: lwu a2, 8(a0)
; RV64MV-NEXT: slli a1, a1, 32 ; RV64MV-NEXT: srli a3, a1, 2
; RV64MV-NEXT: ld a3, 0(a0) ; RV64MV-NEXT: lbu a4, 12(a0)
; RV64MV-NEXT: or a1, a2, a1 ; RV64MV-NEXT: slli a5, a2, 62
; RV64MV-NEXT: slli a1, a1, 29 ; RV64MV-NEXT: or a3, a5, a3
; RV64MV-NEXT: srai a1, a1, 31 ; RV64MV-NEXT: srai a3, a3, 31
; RV64MV-NEXT: srli a4, a3, 2 ; RV64MV-NEXT: slli a4, a4, 32
; RV64MV-NEXT: slli a2, a2, 62
; RV64MV-NEXT: or a2, a2, a4 ; RV64MV-NEXT: or a2, a2, a4
; RV64MV-NEXT: slli a2, a2, 29
; RV64MV-NEXT: lui a4, %hi(.LCPI3_0) ; RV64MV-NEXT: lui a4, %hi(.LCPI3_0)
; RV64MV-NEXT: ld a4, %lo(.LCPI3_0)(a4) ; RV64MV-NEXT: ld a4, %lo(.LCPI3_0)(a4)
; RV64MV-NEXT: srai a2, a2, 31 ; RV64MV-NEXT: srai a2, a2, 31
; RV64MV-NEXT: slli a3, a3, 31 ; RV64MV-NEXT: slli a1, a1, 31
; RV64MV-NEXT: srai a3, a3, 31 ; RV64MV-NEXT: srai a1, a1, 31
; RV64MV-NEXT: mulh a4, a2, a4 ; RV64MV-NEXT: mulh a4, a2, a4
; RV64MV-NEXT: srli a5, a4, 63 ; RV64MV-NEXT: srli a5, a4, 63
; RV64MV-NEXT: srai a4, a4, 1 ; RV64MV-NEXT: srai a4, a4, 1
; RV64MV-NEXT: add a4, a4, a5 ; RV64MV-NEXT: add a4, a4, a5
; RV64MV-NEXT: lui a5, %hi(.LCPI3_1) ; RV64MV-NEXT: lui a5, %hi(.LCPI3_1)
; RV64MV-NEXT: ld a5, %lo(.LCPI3_1)(a5) ; RV64MV-NEXT: ld a5, %lo(.LCPI3_1)(a5)
; RV64MV-NEXT: add a2, a2, a4 ; RV64MV-NEXT: add a2, a2, a4
; RV64MV-NEXT: slli a4, a4, 3 ; RV64MV-NEXT: slli a4, a4, 2
; RV64MV-NEXT: sub a2, a2, a4 ; RV64MV-NEXT: add a2, a2, a4
; RV64MV-NEXT: mulh a4, a3, a5 ; RV64MV-NEXT: mulh a4, a3, a5
; RV64MV-NEXT: srli a5, a4, 63 ; RV64MV-NEXT: srli a5, a4, 63
; RV64MV-NEXT: srai a4, a4, 1
; RV64MV-NEXT: add a4, a4, a5
; RV64MV-NEXT: lui a5, %hi(.LCPI3_2)
; RV64MV-NEXT: ld a5, %lo(.LCPI3_2)(a5)
; RV64MV-NEXT: add a3, a3, a4
; RV64MV-NEXT: slli a4, a4, 3
; RV64MV-NEXT: sub a3, a3, a4
; RV64MV-NEXT: mulh a4, a1, a5
; RV64MV-NEXT: srli a5, a4, 63
; RV64MV-NEXT: add a4, a4, a5 ; RV64MV-NEXT: add a4, a4, a5
; RV64MV-NEXT: li a5, 6 ; RV64MV-NEXT: li a5, 6
; RV64MV-NEXT: mul a4, a4, a5 ; RV64MV-NEXT: mul a4, a4, a5
; RV64MV-NEXT: sub a3, a3, a4 ; RV64MV-NEXT: sub a1, a1, a4
; RV64MV-NEXT: lui a4, %hi(.LCPI3_2)
; RV64MV-NEXT: ld a4, %lo(.LCPI3_2)(a4)
; RV64MV-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; RV64MV-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64MV-NEXT: vslide1down.vx v8, v8, a1
; RV64MV-NEXT: vslide1down.vx v8, v8, a3 ; RV64MV-NEXT: vslide1down.vx v8, v8, a3
; RV64MV-NEXT: vslide1down.vx v8, v8, a2 ; RV64MV-NEXT: vslide1down.vx v8, v8, a2
; RV64MV-NEXT: mulh a2, a1, a4
; RV64MV-NEXT: srli a3, a2, 63
; RV64MV-NEXT: srai a2, a2, 1
; RV64MV-NEXT: add a2, a2, a3
; RV64MV-NEXT: slli a3, a2, 2
; RV64MV-NEXT: add a1, a1, a2
; RV64MV-NEXT: add a1, a1, a3
; RV64MV-NEXT: vslide1down.vx v8, v8, a1
; RV64MV-NEXT: vslidedown.vi v8, v8, 1 ; RV64MV-NEXT: vslidedown.vi v8, v8, 1
; RV64MV-NEXT: lui a1, %hi(.LCPI3_3) ; RV64MV-NEXT: lui a1, %hi(.LCPI3_3)
; RV64MV-NEXT: addi a1, a1, %lo(.LCPI3_3) ; RV64MV-NEXT: addi a1, a1, %lo(.LCPI3_3)
; RV64MV-NEXT: vle64.v v10, (a1) ; RV64MV-NEXT: vle64.v v10, (a1)
; RV64MV-NEXT: li a1, -1 ; RV64MV-NEXT: li a1, -1
; RV64MV-NEXT: srli a1, a1, 31 ; RV64MV-NEXT: srli a1, a1, 31
; RV64MV-NEXT: vand.vx v8, v8, a1 ; RV64MV-NEXT: vand.vx v8, v8, a1
; RV64MV-NEXT: vmsne.vv v0, v8, v10 ; RV64MV-NEXT: vmsne.vv v0, v8, v10
Show All 28 Lines