[AMDGPU] Don't suppress printing the .l and .h register suffixes.

[kosarev]

Summary

We don't seem to have a use for the -amdgpu-keep-16-bit-reg-suffixes
option anymore. Was introduced in https://reviews.llvm.org/D79435.

[Joe_Nash]

I believe those register classes which would print .l or .h on those targets pre-GFX11 are not used in any instruction actually selected by ISel. But if there was, this would change the default assembly printing for them. Can you verify that there are none? It is a similar question to the one raised here https://reviews.llvm.org/D156105#4540254

[kosarev]

I believe those register classes which would print .l or .h on those targets pre-GFX11 are not used in any instruction actually selected by ISel. But if there was, this would change the default assembly printing for them. Can you verify that there are none? It is a similar question to the one raised here https://reviews.llvm.org/D156105#4540254

I don't see any operand definitions using VGPR_LO/HI16. I think any instructions using them would fail on MC tests; it's registers that have the suffixes, not register classes, so codegen should be irrelevant.

[Joe_Nash]

LGTM

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp

 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/TargetParser/TargetParser.h"
 
 using namespace llvm;
 using namespace llvm::AMDGPU;
 
-static cl::opt<bool> Keep16BitSuffixes(
-  "amdgpu-keep-16-bit-reg-suffixes",
-  cl::desc("Keep .l and .h suffixes in asm for debugging purposes"),
-  cl::init(false),
-  cl::ReallyHidden);
-
 void AMDGPUInstPrinter::printRegName(raw_ostream &OS, MCRegister Reg) const {
   // FIXME: The current implementation of
   // AsmParser::parseRegisterOrRegisterNumber in MC implies we either emit this
   // as an integer or we provide a name which represents a physical register.
   // For CFI instructions we really want to emit a name for the DWARF register
   // instead, because there may be multiple DWARF registers corresponding to a
   // single physical register. One case where this problem manifests is with
   // wave32/wave64 where using the physical register name is ambiguous: if we
case AMDGPU::PRIVATE_RSRC_REG:
     llvm_unreachable("pseudo-register should not ever be emitted");
   case AMDGPU::SCC:
     llvm_unreachable("pseudo scc should not ever be emitted");
   default:
     break;
   }
 #endif
 
-  StringRef RegName(getRegisterName(RegNo));
-  if (!Keep16BitSuffixes)
-    if (!RegName.consume_back(".l"))
-      RegName.consume_back(".h");
-
-  O << RegName;
+  O << getRegisterName(RegNo);
 }
 
 void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo,
                                     const MCSubtargetInfo &STI, raw_ostream &O) {
   auto Opcode = MI->getOpcode();
   auto Flags = MII.get(Opcode).TSFlags;
   if (OpNo == 0) {
     if (Flags & SIInstrFlags::VOP3 && Flags & SIInstrFlags::DPP)

llvm/test/CodeGen/AMDGPU/lo16-hi16-illegal-copy.mir

-# RUN: not llc -march=amdgcn -mcpu=gfx802 -start-before postrapseudos -asm-verbose=0 -amdgpu-keep-16-bit-reg-suffixes -verify-machineinstrs %s -o - 2>&1 | FileCheck -check-prefixes=ERR,GFX8-ERR %s
-# RUN: not llc -march=amdgcn -mcpu=gfx802 -start-before postrapseudos -asm-verbose=0 -amdgpu-keep-16-bit-reg-suffixes -verify-machineinstrs %s -o - 2>&1 | FileCheck -check-prefix=GCN %s
-# RUN: not llc -march=amdgcn -mcpu=gfx900 -start-before postrapseudos -asm-verbose=0 -amdgpu-keep-16-bit-reg-suffixes -verify-machineinstrs %s -o - 2>&1 | FileCheck -check-prefix=ERR %s
-# RUN: not llc -march=amdgcn -mcpu=gfx900 -start-before postrapseudos -asm-verbose=0 -amdgpu-keep-16-bit-reg-suffixes -verify-machineinstrs %s -o - 2>&1 | FileCheck -check-prefixes=GCN,GFX9 %s
+# RUN: not llc -march=amdgcn -mcpu=gfx802 -start-before postrapseudos -asm-verbose=0 -verify-machineinstrs %s -o - 2>&1 | FileCheck -check-prefixes=ERR,GFX8-ERR %s
+# RUN: not llc -march=amdgcn -mcpu=gfx802 -start-before postrapseudos -asm-verbose=0 -verify-machineinstrs %s -o - 2>&1 | FileCheck -check-prefix=GCN %s
+# RUN: not llc -march=amdgcn -mcpu=gfx900 -start-before postrapseudos -asm-verbose=0 -verify-machineinstrs %s -o - 2>&1 | FileCheck -check-prefix=ERR %s
+# RUN: not llc -march=amdgcn -mcpu=gfx900 -start-before postrapseudos -asm-verbose=0 -verify-machineinstrs %s -o - 2>&1 | FileCheck -check-prefixes=GCN,GFX9 %s
 
 # Note: GFX8 did not allow SDWA SGPR sources. Therefor no HI16 subregs can be used there.
 
 # GCN-LABEL: {{^}}lo_to_lo_illegal_vgpr_to_sgpr:
 # GCN: ; illegal copy v0.l to s1.l
 # ERR: error: <unknown>:0:0: in function lo_to_lo_illegal_vgpr_to_sgpr void (): illegal VGPR to SGPR copy
 name: lo_to_lo_illegal_vgpr_to_sgpr
 tracksRegLiveness: true