[DAG] Fold (abds x, y) -> (abdu x, y) iff both args are known positive

[RKSimon]

Summary

This is a generic DAG combine version of D151055 which recognizes when a signed ABDS can be safely replaced with a unsigned ABDU instruction if it has better legality.

Alive2: https://alive2.llvm.org/ce/z/pb5BjG

[lkail]

LGTM!

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (ISD::isConstantSplatVectorAllZeros(N1.getNode())) {
         return N0;
     }
   }
 
   // fold (abd x, undef) -> 0
   if (N0.isUndef() || N1.isUndef())
     return DAG.getConstant(0, DL, VT);
 
+  // fold (abds x, y) -> (abdu x, y) iff both args are known positive
+  if (Opcode == ISD::ABDS && hasOperation(ISD::ABDU, VT) &&
+      DAG.SignBitIsZero(N0) && DAG.SignBitIsZero(N1))
+    return DAG.getNode(ISD::ABDU, DL, VT, N1, N0);
+
   return SDValue();
 }
 
 /// Perform optimizations common to nodes that compute two values. LoOp and HiOp
 /// give the opcodes for the two computations that are being performed. Return
 /// true if a simplification was made.
 SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
                                                 unsigned HiOp) {

llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll

 ; CHECK-NEXT:    vperm 0, 4, 2, 5
 ; CHECK-NEXT:    vperm 5, 4, 3, 5
 ; CHECK-NEXT:    addi 3, 3, .LCPI0_2@toc@l
 ; CHECK-NEXT:    lxv 39, 0(3)
 ; CHECK-NEXT:    vperm 6, 4, 2, 1
 ; CHECK-NEXT:    vperm 1, 4, 3, 1
 ; CHECK-NEXT:    vperm 2, 4, 2, 7
 ; CHECK-NEXT:    vperm 3, 4, 3, 7
-; CHECK-NEXT:    xvnegsp 36, 38
-; CHECK-NEXT:    xvnegsp 35, 35
-; CHECK-NEXT:    xvnegsp 34, 34
-; CHECK-NEXT:    vabsduw 2, 2, 3
-; CHECK-NEXT:    xvnegsp 35, 33
-; CHECK-NEXT:    vabsduw 3, 4, 3
-; CHECK-NEXT:    xvnegsp 36, 37
-; CHECK-NEXT:    xvnegsp 37, 32
-; CHECK-NEXT:    vpkuwum 2, 2, 2
-; CHECK-NEXT:    vabsduw 4, 5, 4
+; CHECK-NEXT:    vabsduw 4, 5, 0
+; CHECK-NEXT:    vabsduw 2, 3, 2
+; CHECK-NEXT:    vabsduw 3, 1, 6
 ; CHECK-NEXT:    vpkuwum 3, 4, 3
+; CHECK-NEXT:    vpkuwum 2, 2, 2
 ; CHECK-NEXT:    vpkuhum 2, 2, 3
 ; CHECK-NEXT:    blr
 entry:
   %aa = zext <12 x i8> %a to <12 x i32>
   %bb = zext <12 x i8> %b to <12 x i32>
   %s = sub nsw <12 x i32> %aa, %bb
   %c = icmp slt <12 x i32> %s, zeroinitializer
   %ss = sub nsw <12 x i32> zeroinitializer, %s
   %sel = select <12 x i1> %c, <12 x i32> %ss, <12 x i32> %s
   %ret = trunc <12 x i32> %sel to <12 x i8>
   ret <12 x i8> %ret
 }