[PowerPC] Use ABDU to replace ABDS when operands are known to be zero extended

[lkail]

Summary

For pwr9 cpu, we can save xvnegsp instruction. Alive2 proof https://alive2.llvm.org/ce/z/LWaEEg.

[RKSimon]

Why not handle this generically in DAGCombiner::visitABD?

[lkail]

Simon has got a better solution.

llvm/lib/Target/PowerPC/PPCISelLowering.h

private:
     SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineFMALike(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
     SDValue combineVectorShuffle(ShuffleVectorSDNode *SVN,
                                  SelectionDAG &DAG) const;
     SDValue combineVReverseMemOP(ShuffleVectorSDNode *SVN, LSBaseSDNode *LSBase,
                                  DAGCombinerInfo &DCI) const;
+    SDValue combineABDS(SDNode *N, DAGCombinerInfo &DCI) const;
 
     /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
     /// SETCC with integer subtraction when (1) there is a legal way of doing it
     /// (2) keeping the result of comparison in GPR has performance benefit.
     SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
 
     SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
                             int &RefinementSteps, bool &UseOneConstNR,

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

   setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, ISD::ANY_EXTEND});
 
   setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE});
 
   if (Subtarget.useCRBits()) {
     setTargetDAGCombine({ISD::TRUNCATE, ISD::SETCC, ISD::SELECT_CC});
   }
 
+  if (Subtarget.hasP9Altivec())
+    setTargetDAGCombine({ISD::ABDS});
+
   setLibcallName(RTLIB::LOG_F128, "logf128");
   setLibcallName(RTLIB::LOG2_F128, "log2f128");
   setLibcallName(RTLIB::LOG10_F128, "log10f128");
   setLibcallName(RTLIB::EXP_F128, "expf128");
   setLibcallName(RTLIB::EXP2_F128, "exp2f128");
   setLibcallName(RTLIB::SIN_F128, "sinf128");
   setLibcallName(RTLIB::COS_F128, "cosf128");
   setLibcallName(RTLIB::POW_F128, "powf128");
if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
                          DAG.getConstant(CompOpc, dl, MVT::i32),
                          DAG.getRegister(PPC::CR6, MVT::i32),
                          N->getOperand(4), CompNode.getValue(1));
     }
     break;
   }
   case ISD::BUILD_VECTOR:
     return DAGCombineBuildVector(N, DCI);
+  case ISD::ABDS:
+    return combineABDS(N, DCI);
   }
 
   return SDValue();
 }
 
 SDValue
 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
                                  SelectionDAG &DAG,
Value *PPCTargetLowering::emitMaskedAtomicCmpXchgIntrinsic(
   emitTrailingFence(Builder, CI, Ord);
   Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
   Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
   Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
   Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
   return Builder.CreateOr(
       Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 64)), "val64");
 }
+
+SDValue PPCTargetLowering::combineABDS(SDNode *N, DAGCombinerInfo &DCI) const {
+  assert((N->getOpcode() == ISD::ABDS) && "Need ABDS node here");
+  assert(Subtarget.hasP9Altivec() &&
+         "Only combine this when P9 altivec supported!");
+  EVT VT = N->getValueType(0);
+  if (VT != MVT::v4i32 && VT != MVT::v8i16 && VT != MVT::v16i8)
+    return SDValue();
+  // If we know sign bits of elements to be zeros, we can convert ABDS to
+  // ABDU.
+  SDValue Op0 = N->getOperand(0);
+  SDValue Op1 = N->getOperand(1);
+  if (!DCI.DAG.SignBitIsZero(Op0) || !DCI.DAG.SignBitIsZero(Op1))
+    return SDValue();
+  SDLoc DL(N);
+  return DCI.DAG.getNode(ISD::ABDU, DL, VT, Op0, Op1);
+}

llvm/test/CodeGen/PowerPC/vec-zext-abdu.ll

 ; CHECK-NEXT:    vperm 0, 4, 2, 5
 ; CHECK-NEXT:    vperm 5, 4, 3, 5
 ; CHECK-NEXT:    addi 3, 3, .LCPI0_2@toc@l
 ; CHECK-NEXT:    lxv 39, 0(3)
 ; CHECK-NEXT:    vperm 6, 4, 2, 1
 ; CHECK-NEXT:    vperm 1, 4, 3, 1
 ; CHECK-NEXT:    vperm 2, 4, 2, 7
 ; CHECK-NEXT:    vperm 3, 4, 3, 7
-; CHECK-NEXT:    xvnegsp 36, 38
-; CHECK-NEXT:    xvnegsp 35, 35
-; CHECK-NEXT:    xvnegsp 34, 34
+; CHECK-NEXT:    vabsduw 4, 0, 5
 ; CHECK-NEXT:    vabsduw 2, 2, 3
-; CHECK-NEXT:    xvnegsp 35, 33
-; CHECK-NEXT:    vabsduw 3, 4, 3
-; CHECK-NEXT:    xvnegsp 36, 37
-; CHECK-NEXT:    xvnegsp 37, 32
-; CHECK-NEXT:    vpkuwum 2, 2, 2
-; CHECK-NEXT:    vabsduw 4, 5, 4
+; CHECK-NEXT:    vabsduw 3, 6, 1
 ; CHECK-NEXT:    vpkuwum 3, 4, 3
+; CHECK-NEXT:    vpkuwum 2, 2, 2
 ; CHECK-NEXT:    vpkuhum 2, 2, 3
 ; CHECK-NEXT:    blr
 entry:
   %aa = zext <12 x i8> %a to <12 x i32>
   %bb = zext <12 x i8> %b to <12 x i32>
   %s = sub nsw <12 x i32> %aa, %bb
   %c = icmp slt <12 x i32> %s, zeroinitializer
   %ss = sub nsw <12 x i32> zeroinitializer, %s
   %sel = select <12 x i1> %c, <12 x i32> %ss, <12 x i32> %s
   %ret = trunc <12 x i32> %sel to <12 x i8>
   ret <12 x i8> %ret
 }