[AArch64] Add SVE lowering for vector.reduce.fminimum and fmaximum

[dmgreen]

Summary

Following what is already performed for vector.reduce.fmin/fmax, this adds lowering for the new vector.reduce.fminimum/fmaximum nodes to the SVE fminv and fmaxv instructions via the existing FMINV_PRED/FMAXV_PRED nodes.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

13578–13581

This code also affect fixed length SVE code generation, which means we'll need tests within sve-fixed-length-fp-reduce.ll and sve-streaming-mode-fixed-length-fp-reduce.ll as well.

[cameron.mcinally]

llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll

35

Typo: "FMAXNMV"

[dmgreen]

I was avoiding the fixed-length SVE, as the nodes were not marked custom they would go via the existing expansion. I can add support for them here too though, it's only two extra lines and a number of copied tests.

[dmgreen]

Add fixed length support and tests.

[dmgreen]

Rebase to see if precommit tests do better, now that the Neon side has been committed.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

for (auto VT : {MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2f32,
       setOperationAction(ISD::FTRUNC, VT, Custom);
       setOperationAction(ISD::FSQRT, VT, Custom);
       setOperationAction(ISD::FABS, VT, Custom);
       setOperationAction(ISD::FP_EXTEND, VT, Custom);
       setOperationAction(ISD::FP_ROUND, VT, Custom);
       setOperationAction(ISD::VECREDUCE_FADD, VT, Custom);
       setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
       setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_FMAXIMUM, VT, Custom);
+      setOperationAction(ISD::VECREDUCE_FMINIMUM, VT, Custom);
       setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom);
       setOperationAction(ISD::VECTOR_SPLICE, VT, Custom);
       setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom);
       setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom);
 
       setOperationAction(ISD::SELECT_CC, VT, Expand);
       setOperationAction(ISD::FREM, VT, Expand);
       setOperationAction(ISD::FPOW, VT, Expand);
SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
   case ISD::VECREDUCE_XOR:
   case ISD::VECREDUCE_SMAX:
   case ISD::VECREDUCE_SMIN:
   case ISD::VECREDUCE_UMAX:
   case ISD::VECREDUCE_UMIN:
   case ISD::VECREDUCE_FADD:
   case ISD::VECREDUCE_FMAX:
   case ISD::VECREDUCE_FMIN:
+  case ISD::VECREDUCE_FMAXIMUM:
+  case ISD::VECREDUCE_FMINIMUM:
     return LowerVECREDUCE(Op, DAG);
   case ISD::ATOMIC_LOAD_SUB:
     return LowerATOMIC_LOAD_SUB(Op, DAG);
   case ISD::ATOMIC_LOAD_AND:
     return LowerATOMIC_LOAD_AND(Op, DAG);
   case ISD::DYNAMIC_STACKALLOC:
     return LowerDYNAMIC_STACKALLOC(Op, DAG);
   case ISD::VSCALE:
if (SrcVT.isScalableVector() ||
     case ISD::VECREDUCE_XOR:
       return LowerReductionToSVE(AArch64ISD::EORV_PRED, Op, DAG);
     case ISD::VECREDUCE_FADD:
       return LowerReductionToSVE(AArch64ISD::FADDV_PRED, Op, DAG);
     case ISD::VECREDUCE_FMAX:
       return LowerReductionToSVE(AArch64ISD::FMAXNMV_PRED, Op, DAG);
     case ISD::VECREDUCE_FMIN:
       return LowerReductionToSVE(AArch64ISD::FMINNMV_PRED, Op, DAG);
+    case ISD::VECREDUCE_FMAXIMUM:
+      return LowerReductionToSVE(AArch64ISD::FMAXV_PRED, Op, DAG);
+    case ISD::VECREDUCE_FMINIMUM:
+      return LowerReductionToSVE(AArch64ISD::FMINV_PRED, Op, DAG);
     default:
       llvm_unreachable("Unhandled fixed length reduction");
     }
   }
 
   // Lower NEON reductions.
   SDLoc dl(Op);
   switch (Op.getOpcode()) {

llvm/test/CodeGen/AArch64/sve-fp-reduce.ll

 define half @fadda_nxv6f16(<vscale x 6 x half> %v, half %s) {
 ; CHECK-LABEL: fadda_nxv6f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    addvl sp, sp, #-1
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
-; CHECK-NEXT:    mov w8, #32768
+; CHECK-NEXT:    mov w8, #32768 // =0x8000
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    ptrue p1.d
 ; CHECK-NEXT:    st1h { z0.h }, p0, [sp]
 ; CHECK-NEXT:    fmov s0, s1
 ; CHECK-NEXT:    mov z2.h, w8
 ; CHECK-NEXT:    st1h { z2.d }, p1, [sp, #3, mul vl]
 ; CHECK-NEXT:    ld1h { z2.h }, p0/z, [sp]
 ; CHECK-NEXT:    fadda h0, p0, h0, z2.h
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
 ; CHECK-NEXT:    addvl sp, sp, #1
 ; CHECK-NEXT:    ldr x29, [sp], #16 // 8-byte Folded Reload
 ; CHECK-NEXT:    ret
   %res = call half @llvm.vector.reduce.fadd.nxv6f16(half %s, <vscale x 6 x half> %v)
   ret half %res
 }
 
 define half @fadda_nxv10f16(<vscale x 10 x half> %v, half %s) {
 ; CHECK-LABEL: fadda_nxv10f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    addvl sp, sp, #-3
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 24 * VG
-; CHECK-NEXT:    mov w8, #32768
+; CHECK-NEXT:    mov w8, #32768 // =0x8000
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    ptrue p1.d
 ; CHECK-NEXT:    st1h { z1.h }, p0, [sp]
 ; CHECK-NEXT:    // kill: def $h2 killed $h2 def $z2
 ; CHECK-NEXT:    mov z3.h, w8
 ; CHECK-NEXT:    addvl x8, sp, #1
 ; CHECK-NEXT:    st1h { z3.d }, p1, [sp, #1, mul vl]
 ; CHECK-NEXT:    fadda h2, p0, h2, z0.h

 ; CHECK-NEXT:    ret
   %res = call half @llvm.vector.reduce.fadd.nxv10f16(half %s, <vscale x 10 x half> %v)
   ret half %res
 }
 
 define half @fadda_nxv12f16(<vscale x 12 x half> %v, half %s) {
 ; CHECK-LABEL: fadda_nxv12f16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #32768
+; CHECK-NEXT:    mov w8, #32768 // =0x8000
 ; CHECK-NEXT:    // kill: def $h2 killed $h2 def $z2
 ; CHECK-NEXT:    uunpklo z1.s, z1.h
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    fadda h2, p0, h2, z0.h
 ; CHECK-NEXT:    mov z3.h, w8
 ; CHECK-NEXT:    uzp1 z1.h, z1.h, z3.h
 ; CHECK-NEXT:    fadda h2, p0, h2, z1.h
 ; CHECK-NEXT:    fmov s0, s2

 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    faddv d1, p0, z1.d
 ; CHECK-NEXT:    fadd d0, d0, d1
 ; CHECK-NEXT:    ret
   %res = call fast double @llvm.vector.reduce.fadd.nxv2f64(double %init, <vscale x 2 x double> %a)
   ret double %res
 }
 
-; FMAXV
+; FMAXNMV
 
 define half @fmaxv_nxv2f16(<vscale x 2 x half> %a) {
 ; CHECK-LABEL: fmaxv_nxv2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    fmaxnmv h0, p0, z0.h
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
 ; CHECK-NEXT:    ret

 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    fmaxnmv d0, p0, z0.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double> %a)
   ret double %res
 }
 
-; FMINV
+; FMINNMV
 
 define half @fminv_nxv2f16(<vscale x 2 x half> %a) {
 ; CHECK-LABEL: fminv_nxv2f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    fminnmv h0, p0, z0.h
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
 ; CHECK-NEXT:    ret

 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    fminnmv d0, p0, z0.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double> %a)
   ret double %res
 }
 
+
+
+
+; FMAXV
+
+define half @fmaximumv_nxv2f16(<vscale x 2 x half> %a) {
+; CHECK-LABEL: fmaximumv_nxv2f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fmaxv h0, p0, z0.h
+; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call half @llvm.vector.reduce.fmaximum.nxv2f16(<vscale x 2 x half> %a)
+  ret half %res
+}
+
+define half @fmaximumv_nxv4f16(<vscale x 4 x half> %a) {
+; CHECK-LABEL: fmaximumv_nxv4f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fmaxv h0, p0, z0.h
+; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call half @llvm.vector.reduce.fmaximum.nxv4f16(<vscale x 4 x half> %a)
+  ret half %res
+}
+
+define half @fmaximumv_nxv8f16(<vscale x 8 x half> %a) {
+; CHECK-LABEL: fmaximumv_nxv8f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    fmaxv h0, p0, z0.h
+; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call half @llvm.vector.reduce.fmaximum.nxv8f16(<vscale x 8 x half> %a)
+  ret half %res
+}
+
+define float @fmaximumv_nxv2f32(<vscale x 2 x float> %a) {
+; CHECK-LABEL: fmaximumv_nxv2f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fmaxv s0, p0, z0.s
+; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float> %a)
+  ret float %res
+}
+
+define float @fmaximumv_nxv4f32(<vscale x 4 x float> %a) {
+; CHECK-LABEL: fmaximumv_nxv4f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fmaxv s0, p0, z0.s
+; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call float @llvm.vector.reduce.fmaximum.nxv4f32(<vscale x 4 x float> %a)
+  ret float %res
+}
+
+define double @fmaximumv_nxv2f64(<vscale x 2 x double> %a) {
+; CHECK-LABEL: fmaximumv_nxv2f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fmaxv d0, p0, z0.d
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call double @llvm.vector.reduce.fmaximum.nxv2f64(<vscale x 2 x double> %a)
+  ret double %res
+}
+
+; FMINV
+
+define half @fminimumv_nxv2f16(<vscale x 2 x half> %a) {
+; CHECK-LABEL: fminimumv_nxv2f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fminv h0, p0, z0.h
+; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call half @llvm.vector.reduce.fminimum.nxv2f16(<vscale x 2 x half> %a)
+  ret half %res
+}
+
+define half @fminimumv_nxv4f16(<vscale x 4 x half> %a) {
+; CHECK-LABEL: fminimumv_nxv4f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fminv h0, p0, z0.h
+; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call half @llvm.vector.reduce.fminimum.nxv4f16(<vscale x 4 x half> %a)
+  ret half %res
+}
+
+define half @fminimumv_nxv8f16(<vscale x 8 x half> %a) {
+; CHECK-LABEL: fminimumv_nxv8f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    fminv h0, p0, z0.h
+; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call half @llvm.vector.reduce.fminimum.nxv8f16(<vscale x 8 x half> %a)
+  ret half %res
+}
+
+define float @fminimumv_nxv2f32(<vscale x 2 x float> %a) {
+; CHECK-LABEL: fminimumv_nxv2f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fminv s0, p0, z0.s
+; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float> %a)
+  ret float %res
+}
+
+define float @fminimumv_nxv4f32(<vscale x 4 x float> %a) {
+; CHECK-LABEL: fminimumv_nxv4f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.s
+; CHECK-NEXT:    fminv s0, p0, z0.s
+; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call float @llvm.vector.reduce.fminimum.nxv4f32(<vscale x 4 x float> %a)
+  ret float %res
+}
+
+define double @fminimumv_nxv2f64(<vscale x 2 x double> %a) {
+; CHECK-LABEL: fminimumv_nxv2f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fminv d0, p0, z0.d
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call double @llvm.vector.reduce.fminimum.nxv2f64(<vscale x 2 x double> %a)
+  ret double %res
+}
+
 define float @fadd_reduct_reassoc_v4v8f32(<vscale x 4 x float> %a, <vscale x 8 x float> %b) {
 ; CHECK-LABEL: fadd_reduct_reassoc_v4v8f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fadd z1.s, z1.s, z2.s
 ; CHECK-NEXT:    ptrue p0.s
 ; CHECK-NEXT:    fadd z0.s, z0.s, z1.s
 ; CHECK-NEXT:    faddv s0, p0, z0.s
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 killed $z0

 declare double @llvm.vector.reduce.fmax.nxv2f64(<vscale x 2 x double>)
 
 declare half @llvm.vector.reduce.fmin.nxv2f16(<vscale x 2 x half>)
 declare half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half>)
 declare half @llvm.vector.reduce.fmin.nxv8f16(<vscale x 8 x half>)
 declare float @llvm.vector.reduce.fmin.nxv2f32(<vscale x 2 x float>)
 declare float @llvm.vector.reduce.fmin.nxv4f32(<vscale x 4 x float>)
 declare double @llvm.vector.reduce.fmin.nxv2f64(<vscale x 2 x double>)
+
+declare half @llvm.vector.reduce.fmaximum.nxv2f16(<vscale x 2 x half>)
+declare half @llvm.vector.reduce.fmaximum.nxv4f16(<vscale x 4 x half>)
+declare half @llvm.vector.reduce.fmaximum.nxv8f16(<vscale x 8 x half>)
+declare float @llvm.vector.reduce.fmaximum.nxv2f32(<vscale x 2 x float>)
+declare float @llvm.vector.reduce.fmaximum.nxv4f32(<vscale x 4 x float>)
+declare double @llvm.vector.reduce.fmaximum.nxv2f64(<vscale x 2 x double>)
+
+declare half @llvm.vector.reduce.fminimum.nxv2f16(<vscale x 2 x half>)
+declare half @llvm.vector.reduce.fminimum.nxv4f16(<vscale x 4 x half>)
+declare half @llvm.vector.reduce.fminimum.nxv8f16(<vscale x 8 x half>)
+declare float @llvm.vector.reduce.fminimum.nxv2f32(<vscale x 2 x float>)
+declare float @llvm.vector.reduce.fminimum.nxv4f32(<vscale x 4 x float>)
+declare double @llvm.vector.reduce.fminimum.nxv2f64(<vscale x 2 x double>)

llvm/test/CodeGen/AArch64/sve-split-fp-reduce.ll

 ; CHECK-NEXT:    fadd z1.s, z1.s, z2.s
 ; CHECK-NEXT:    faddv s1, p0, z1.s
 ; CHECK-NEXT:    fadd s0, s0, s1
 ; CHECK-NEXT:    ret
   %res = call fast float @llvm.vector.reduce.fadd.nxv8f32(float %init, <vscale x 8 x float> %a)
   ret float %res
 }
 
-; FMAXV
+; FMAXMNV
 
 define double @fmaxv_nxv8f64(<vscale x 8 x double> %a) {
 ; CHECK-LABEL: fmaxv_nxv8f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.d
 ; CHECK-NEXT:    fmaxnm z1.d, p0/m, z1.d, z3.d
 ; CHECK-NEXT:    fmaxnm z0.d, p0/m, z0.d, z2.d
 ; CHECK-NEXT:    fmaxnm z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT:    fmaxnmv d0, p0, z0.d
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call double @llvm.vector.reduce.fmax.nxv8f64(<vscale x 8 x double> %a)
   ret double %res
 }
 
-; FMINV
+; FMINNMV
 
 define half @fminv_nxv16f16(<vscale x 16 x half> %a) {
 ; CHECK-LABEL: fminv_nxv16f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p0.h
 ; CHECK-NEXT:    fminnm z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    fminnmv h0, p0, z0.h
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
 ; CHECK-NEXT:    ret
   %res = call half @llvm.vector.reduce.fmin.nxv16f16(<vscale x 16 x half> %a)
   ret half %res
 }
 
+; FMAXV
+
+define double @fmaximumv_nxv8f64(<vscale x 8 x double> %a) {
+; CHECK-LABEL: fmaximumv_nxv8f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.d
+; CHECK-NEXT:    fmax z1.d, p0/m, z1.d, z3.d
+; CHECK-NEXT:    fmax z0.d, p0/m, z0.d, z2.d
+; CHECK-NEXT:    fmax z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT:    fmaxv d0, p0, z0.d
+; CHECK-NEXT:    // kill: def $d0 killed $d0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call double @llvm.vector.reduce.fmaximum.nxv8f64(<vscale x 8 x double> %a)
+  ret double %res
+}
+
+; FMINV
+
+define half @fminimumv_nxv16f16(<vscale x 16 x half> %a) {
+; CHECK-LABEL: fminimumv_nxv16f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    ptrue p0.h
+; CHECK-NEXT:    fmin z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    fminv h0, p0, z0.h
+; CHECK-NEXT:    // kill: def $h0 killed $h0 killed $z0
+; CHECK-NEXT:    ret
+  %res = call half @llvm.vector.reduce.fminimum.nxv16f16(<vscale x 16 x half> %a)
+  ret half %res
+}
+
 declare double @llvm.vector.reduce.fadd.nxv8f64(double, <vscale x 8 x double>)
 declare float @llvm.vector.reduce.fadd.nxv8f32(float, <vscale x 8 x float>)
 
 declare double @llvm.vector.reduce.fmax.nxv8f64(<vscale x 8 x double>)
-
 declare half @llvm.vector.reduce.fmin.nxv16f16(<vscale x 16 x half>)
+declare double @llvm.vector.reduce.fmaximum.nxv8f64(<vscale x 8 x double>)
+declare half @llvm.vector.reduce.fminimum.nxv16f16(<vscale x 16 x half>)