[doc][LoongArch] Add missed release note about `ual` feature addition

[SixWeining]

Summary

I meant to fold this into 47601815ec3a4f31c797c75748af08acfabc46dc
but failed to do so.

[xen0n]

Thanks for the catch!

llvm/docs/ReleaseNotes.rst

176

nit: "A" (the following sound is not a vowel)

177

nit: "for generic 64-bit"

Here "for" (compared to "on") is to signify it's controlled by target instead of host spec.

[MaskRay]

llvm/docs/ReleaseNotes.rst

177

Target feature is internal and mentioning it in release notes may be excessive (if we do, there are too many to enumerate ...). I think we can omit mentioning the target feature. Focusing on the behavior about the user-facing -m[no-]unaligned-access is more useful.

[SixWeining]

llvm/docs/ReleaseNotes.rst

176

Thanks. I will modify it later.

177

I think it depends on the different users we are targeting. Command line options like -m[no-]unaligned-access are targeting clang users while target features are targeting llvm users.

[SixWeining]

Address xen0n's comments.

clang/docs/ReleaseNotes.rst

 Windows Support
 ^^^^^^^^^^^^^^^
 
 LoongArch Support
 ^^^^^^^^^^^^^^^^^
 
 - Patchable function entry (``-fpatchable-function-entry``) is now supported
   on LoongArch.
+- Unaligned memory accesses can be toggled by ``-m[no-]unaligned-access`` or the
+  aliases ``-m[no-]strict-align``.
 
 RISC-V Support
 ^^^^^^^^^^^^^^
 - Added ``-mrvv-vector-bits=`` option to give an upper and lower bound on vector
   length. Valid values are powers of 2 between 64 and 65536. A value of 32
   should eventually be supported. We also accept "zvl" to use the Zvl*b
   extension from ``-march`` or ``-mcpu`` to the be the upper and lower bound.
 - Fixed incorrect ABI lowering of ``_Float16`` in the case of structs

llvm/docs/ReleaseNotes.rst

 ------------------------------
 
 * ...
 
 Changes to the LoongArch Backend
 --------------------------------
 
 * The ``lp64s`` ABI is supported now and has been tested on Rust bare-matal target.
+* A target feature ``ual`` is introduced to allow unaligned memory accesses and
+  this feature is enabled by default for generic 64-bit processors.
 
 Changes to the MIPS Backend
 ---------------------------
 
 * ...
 
 Changes to the PowerPC Backend
 ------------------------------