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Differential D152658

[InstCombine] Change SimplifyDemandedVectorElts to use PoisonElts instead of UndefElts
Changes PlannedPublic

Authored by ManuelJBrito on Jun 11 2023, 2:35 PM.

Details

Reviewers
t.p.northover
uweigand
arsenm
RKSimon
efriedma
nikic
spatel
lebedev.ri
Summary

This patch changes InstCombine's SimplifyDemandedVectorElts to use PoisonElts instead of UndefElts. It now treats undef elements as DemandedElts and keeps track of poison elements only.
This fixes some undef related bugs marked with LLVM PR44185 in

https://web.ist.utl.pt/nuno.lopes/alive2/index.php?hash=a9bc405e427c007f.

Such as:

Transforms/InstCombine/insert-const-shuf.ll
Transforms/InstCombine/sub-of-negatible.ll
Transforms/InstCombine/vec_shuffle.ll

At this point, frontends should not be emitting undef values, so losing the undef optimizations should be OK.

In most cases, it should be OK to go from UndefElts to PoisonElts because PoisonElts is a subset of UndefElts.
The only cases that might be of concern are the ones where target specific intrinsics are optimized based on SimplifyDemandedVectorElts.
After this patch they might be emitting poison where there was previously undef. This might break the semantics of those intrinsics. Requesting reviewers for those cases.

This change also allows for more aggressive optimization because poison is more undefined than undef. ​For example:

gep(X, poison) -> poison is OK 
gep(X, undef) -> undef is NOT OK. (see https://github.com/llvm/llvm-project/issues/44790)

Previously we weren't allowed to do this because there was no way to distinguish between undef and poison elements.
These optimizations can be done in follow-up patches.

Diff Detail

Event Timeline

ManuelJBrito created this revision.Jun 11 2023, 2:35 PM
Herald added a reviewer: lebedev.ri. · View Herald TranscriptJun 11 2023, 2:35 PM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: pmatos, asb, foad and 7 others. · View Herald Transcript
ManuelJBrito requested review of this revision.Jun 11 2023, 2:35 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJun 11 2023, 2:35 PM
Herald added subscribers: llvm-commits, cfe-commits, • pcwang-thead and 2 others. · View Herald Transcript
nlopes added inline comments.Jun 11 2023, 3:08 PM
llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
3102–3105

this change doesn't look correct. The bits are undefined, doesn't seem like you can use poison here.

llvm/test/Transforms/InstCombine/vec_shuffle.ll
1302

Why does it regress here (goes from poison to undef)?

Harbormaster completed remote builds in B238059: Diff 530339.Jun 11 2023, 5:44 PM
ManuelJBrito added inline comments.Jun 16 2023, 8:45 AM
llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp
3102–3105

Thanks, I'll fix it. This will cause some regressions in the cases where only the upper half is demanded.
Eventually we could fold those cases to freeze(poison).

llvm/test/Transforms/InstCombine/vec_shuffle.ll
1302

This regression is due to the change in foldVectorBinop in InstructionCombining.cpp
It seems that without this canonicalization, demanded elements doesn't trigger causing the regression.

I changed it to match poison instead of undef, because of the following:

shufflevector < 4 x i32 > %1, < 4 x i32 > undef , <1, 2, 6, 7> --> shufflevector < 4 x i32 > %1, < 4 x i32 > undef , <1, 2, undef, undef>

Now we don't do this because it would insert poison.

Not simplifying the mask causes the following assert to fail:

assert(ShMask[I] < (int)NumElts && "Not expecting narrowing shuffle")
ManuelJBrito updated this revision to Diff 532687.Jun 19 2023, 9:39 AM

Address comments.
Cannot use poison for undefined part of result in SSE4A intrinsics.
Regressions:

  • x86-sse4a-inseltpoison.ll
  • x86-sse4a.ll

Fix regressions in vec_shuffle.ll by skipping mask elements from second operand in foldVectorBinop.

Harbormaster completed remote builds in B239838: Diff 532687.Jun 19 2023, 9:39 AM
ManuelJBrito added a comment.Jun 26 2023, 5:28 AM

Ping

ManuelJBrito updated this revision to Diff 536882.Jul 3 2023, 1:35 PM

rebase & ping

Harbormaster completed remote builds in B242877: Diff 536882.Jul 3 2023, 4:10 PM
ManuelJBrito added a comment.Jul 11 2023, 7:53 AM

ping :)

Herald added a subscriber: wangpc. · View Herald TranscriptJul 11 2023, 7:53 AM
aqjune added a comment.Jul 11 2023, 8:57 AM

Hi, thanks for your hard work!

llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
1653

This seems to be

1653

Nevermind, please ignore this comment.

llvm/test/Transforms/InstCombine/vec_shuffle.ll
373

Do you have any idea about the reason of this regression?

llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll
297

This looks interesting - do you have idea how the undef elements are introduced?

llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll
451

Do you have any idea about why the 5'th element is undef, not poison?

llvm/test/Transforms/SLPVectorizer/X86/pr49081.ll
11

This change looks interesting, I think it is worth investigating why this happened.

ManuelJBrito planned changes to this revision.Jul 18 2023, 3:09 AM

Hello @aqjune thanks for the comments !! Some users of SimplifyDemandedVectorElts might need some more tweaking to prevent regressions for the cases you noted. I'll work on this as soon as I can!

Revision Contents

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Diff 536882

clang/test/CodeGen/SystemZ/builtins-systemz-zvector-constrained.c

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Linesvoid test_core(void) {
vec_xst(vd, idx, ptrd); vec_xst(vd, idx, ptrd);
vec_xstd2(vd, idx, ptrd); vec_xstd2(vd, idx, ptrd);
vd = vec_splat(vd, 0); vd = vec_splat(vd, 0);
// CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vd = vec_splat(vd, 1); vd = vec_splat(vd, 1);
// CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> undef, <2 x i32> <i32 1, i32 1> // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> <i32 1, i32 1>
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vd = vec_splats(d); vd = vec_splats(d);
// CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer
// CHECK-ASM: vlrepg // CHECK-ASM: vlrepg
vd = vec_mergeh(vd, vd); vd = vec_mergeh(vd, vd);
// shufflevector <2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x i32> <i32 0, i32 2> // shufflevector <2 x double> %{{.*}}, <2 x double> %{{.*}}, <2 x i32> <i32 0, i32 2>
▲ Show 20 Lines • Show All 225 Lines • Show Last 20 Lines

clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c

Show First 20 Lines • Show All 726 Lines • ▼ Show 20 Linesvoid test_core(void) {
// CHECK: <2 x i64> <i64 2305843009205305344, i64 2305843009205305344> // CHECK: <2 x i64> <i64 2305843009205305344, i64 2305843009205305344>
vul = vec_genmasks_64(30, 11); vul = vec_genmasks_64(30, 11);
// CHECK: <2 x i64> <i64 -4503582447501313, i64 -4503582447501313> // CHECK: <2 x i64> <i64 -4503582447501313, i64 -4503582447501313>
vsc = vec_splat(vsc, 0); vsc = vec_splat(vsc, 0);
// CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> poison, <16 x i32> zeroinitializer // CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> poison, <16 x i32> zeroinitializer
// CHECK-ASM: vrepb // CHECK-ASM: vrepb
vsc = vec_splat(vsc, 15); vsc = vec_splat(vsc, 15);
// CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> undef, <16 x i32> <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15> // CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> poison, <16 x i32> <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
// CHECK-ASM: vrepb // CHECK-ASM: vrepb
vuc = vec_splat(vuc, 0); vuc = vec_splat(vuc, 0);
// CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> poison, <16 x i32> zeroinitializer // CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> poison, <16 x i32> zeroinitializer
// CHECK-ASM: vrepb // CHECK-ASM: vrepb
vuc = vec_splat(vuc, 15); vuc = vec_splat(vuc, 15);
// CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> undef, <16 x i32> <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15> // CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> poison, <16 x i32> <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
// CHECK-ASM: vrepb // CHECK-ASM: vrepb
vbc = vec_splat(vbc, 0); vbc = vec_splat(vbc, 0);
// CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> poison, <16 x i32> zeroinitializer // CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> poison, <16 x i32> zeroinitializer
// CHECK-ASM: vrepb // CHECK-ASM: vrepb
vbc = vec_splat(vbc, 15); vbc = vec_splat(vbc, 15);
// CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> undef, <16 x i32> <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15> // CHECK: shufflevector <16 x i8> %{{.*}}, <16 x i8> poison, <16 x i32> <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
// CHECK-ASM: vrepb // CHECK-ASM: vrepb
vss = vec_splat(vss, 0); vss = vec_splat(vss, 0);
// CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> poison, <8 x i32> zeroinitializer // CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> poison, <8 x i32> zeroinitializer
// CHECK-ASM: vreph // CHECK-ASM: vreph
vss = vec_splat(vss, 7); vss = vec_splat(vss, 7);
// CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> undef, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> // CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> poison, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
// CHECK-ASM: vreph // CHECK-ASM: vreph
vus = vec_splat(vus, 0); vus = vec_splat(vus, 0);
// CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> poison, <8 x i32> zeroinitializer // CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> poison, <8 x i32> zeroinitializer
// CHECK-ASM: vreph // CHECK-ASM: vreph
vus = vec_splat(vus, 7); vus = vec_splat(vus, 7);
// CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> undef, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> // CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> poison, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
// CHECK-ASM: vreph // CHECK-ASM: vreph
vbs = vec_splat(vbs, 0); vbs = vec_splat(vbs, 0);
// CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> poison, <8 x i32> zeroinitializer // CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> poison, <8 x i32> zeroinitializer
// CHECK-ASM: vreph // CHECK-ASM: vreph
vbs = vec_splat(vbs, 7); vbs = vec_splat(vbs, 7);
// CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> undef, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7> // CHECK: shufflevector <8 x i16> %{{.*}}, <8 x i16> poison, <8 x i32> <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
// CHECK-ASM: vreph // CHECK-ASM: vreph
vsi = vec_splat(vsi, 0); vsi = vec_splat(vsi, 0);
// CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> poison, <4 x i32> zeroinitializer // CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> poison, <4 x i32> zeroinitializer
// CHECK-ASM: vrepf // CHECK-ASM: vrepf
vsi = vec_splat(vsi, 3); vsi = vec_splat(vsi, 3);
// CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> // CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
// CHECK-ASM: vrepf // CHECK-ASM: vrepf
vui = vec_splat(vui, 0); vui = vec_splat(vui, 0);
// CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> poison, <4 x i32> zeroinitializer // CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> poison, <4 x i32> zeroinitializer
// CHECK-ASM: vrepf // CHECK-ASM: vrepf
vui = vec_splat(vui, 3); vui = vec_splat(vui, 3);
// CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> // CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
// CHECK-ASM: vrepf // CHECK-ASM: vrepf
vbi = vec_splat(vbi, 0); vbi = vec_splat(vbi, 0);
// CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> poison, <4 x i32> zeroinitializer // CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> poison, <4 x i32> zeroinitializer
// CHECK-ASM: vrepf // CHECK-ASM: vrepf
vbi = vec_splat(vbi, 3); vbi = vec_splat(vbi, 3);
// CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> // CHECK: shufflevector <4 x i32> %{{.*}}, <4 x i32> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
// CHECK-ASM: vrepf // CHECK-ASM: vrepf
vsl = vec_splat(vsl, 0); vsl = vec_splat(vsl, 0);
// CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> poison, <2 x i32> zeroinitializer // CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> poison, <2 x i32> zeroinitializer
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vsl = vec_splat(vsl, 1); vsl = vec_splat(vsl, 1);
// CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> undef, <2 x i32> <i32 1, i32 1> // CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> poison, <2 x i32> <i32 1, i32 1>
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vul = vec_splat(vul, 0); vul = vec_splat(vul, 0);
// CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> poison, <2 x i32> zeroinitializer // CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> poison, <2 x i32> zeroinitializer
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vul = vec_splat(vul, 1); vul = vec_splat(vul, 1);
// CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> undef, <2 x i32> <i32 1, i32 1> // CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> poison, <2 x i32> <i32 1, i32 1>
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vbl = vec_splat(vbl, 0); vbl = vec_splat(vbl, 0);
// CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> poison, <2 x i32> zeroinitializer // CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> poison, <2 x i32> zeroinitializer
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vbl = vec_splat(vbl, 1); vbl = vec_splat(vbl, 1);
// CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> undef, <2 x i32> <i32 1, i32 1> // CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> poison, <2 x i32> <i32 1, i32 1>
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vd = vec_splat(vd, 0); vd = vec_splat(vd, 0);
// CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vd = vec_splat(vd, 1); vd = vec_splat(vd, 1);
// CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> undef, <2 x i32> <i32 1, i32 1> // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> <i32 1, i32 1>
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vsc = vec_splat_s8(-128); vsc = vec_splat_s8(-128);
// CHECK: <16 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128> // CHECK: <16 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>
vsc = vec_splat_s8(127); vsc = vec_splat_s8(127);
// CHECK: <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127> // CHECK: <16 x i8> <i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127, i8 127>
vuc = vec_splat_u8(1); vuc = vec_splat_u8(1);
// CHECK: <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1> // CHECK: <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
▲ Show 20 Lines • Show All 3,807 Lines • Show Last 20 Lines

clang/test/CodeGen/SystemZ/builtins-systemz-zvector2-constrained.c

Show First 20 Lines • Show All 127 Lines • ▼ Show 20 Linesvoid test_core(void) {
// CHECK-ASM: vst // CHECK-ASM: vst
vec_xst(vd, idx, ptrd); vec_xst(vd, idx, ptrd);
// CHECK-ASM: vst // CHECK-ASM: vst
vf = vec_splat(vf, 0); vf = vec_splat(vf, 0);
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> poison, <4 x i32> zeroinitializer // CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> poison, <4 x i32> zeroinitializer
// CHECK-ASM: vrepf // CHECK-ASM: vrepf
vf = vec_splat(vf, 1); vf = vec_splat(vf, 1);
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> // CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK-ASM: vrepf // CHECK-ASM: vrepf
vd = vec_splat(vd, 0); vd = vec_splat(vd, 0);
// CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vd = vec_splat(vd, 1); vd = vec_splat(vd, 1);
// CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> undef, <2 x i32> <i32 1, i32 1> // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> <i32 1, i32 1>
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vf = vec_splats(f); vf = vec_splats(f);
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> poison, <4 x i32> zeroinitializer // CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> poison, <4 x i32> zeroinitializer
// CHECK-ASM: vlrepf // CHECK-ASM: vlrepf
vd = vec_splats(d); vd = vec_splats(d);
// CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer
// CHECK-ASM: vlrepg // CHECK-ASM: vlrepg
▲ Show 20 Lines • Show All 393 Lines • Show Last 20 Lines

clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c

Show First 20 Lines • Show All 232 Lines • ▼ Show 20 Linesvoid test_core(void) {
vec_store_len_r(vuc, ptruc, idx); vec_store_len_r(vuc, ptruc, idx);
// CHECK: call void @llvm.s390.vstrl(<16 x i8> %{{.*}}, i32 %{{.*}}, ptr %{{.*}}) // CHECK: call void @llvm.s390.vstrl(<16 x i8> %{{.*}}, i32 %{{.*}}, ptr %{{.*}})
// CHECK-ASM: vstrlr // CHECK-ASM: vstrlr
vf = vec_splat(vf, 0); vf = vec_splat(vf, 0);
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> poison, <4 x i32> zeroinitializer // CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> poison, <4 x i32> zeroinitializer
// CHECK-ASM: vrepf // CHECK-ASM: vrepf
vf = vec_splat(vf, 1); vf = vec_splat(vf, 1);
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> // CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK-ASM: vrepf // CHECK-ASM: vrepf
vd = vec_splat(vd, 0); vd = vec_splat(vd, 0);
// CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vd = vec_splat(vd, 1); vd = vec_splat(vd, 1);
// CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> undef, <2 x i32> <i32 1, i32 1> // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> <i32 1, i32 1>
// CHECK-ASM: vrepg // CHECK-ASM: vrepg
vf = vec_splats(f); vf = vec_splats(f);
// CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> poison, <4 x i32> zeroinitializer // CHECK: shufflevector <4 x float> %{{.*}}, <4 x float> poison, <4 x i32> zeroinitializer
// CHECK-ASM: vlrepf // CHECK-ASM: vlrepf
vd = vec_splats(d); vd = vec_splats(d);
// CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer // CHECK: shufflevector <2 x double> %{{.*}}, <2 x double> poison, <2 x i32> zeroinitializer
// CHECK-ASM: vlrepg // CHECK-ASM: vlrepg
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clang/test/CodeGen/aarch64-neon-vcmla.c

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// CHECK: ret <4 x half> [[RES]] // CHECK: ret <4 x half> [[RES]]
float16x4_t test_vcmla_lane_f16(float16x4_t acc, float16x4_t lhs, float16x4_t rhs) { float16x4_t test_vcmla_lane_f16(float16x4_t acc, float16x4_t lhs, float16x4_t rhs) {
return vcmla_lane_f16(acc, lhs, rhs, 1); return vcmla_lane_f16(acc, lhs, rhs, 1);
} }
// ACLE says this exists, but it won't map to a single instruction if lane > 1. // ACLE says this exists, but it won't map to a single instruction if lane > 1.
// CHECK-LABEL: @test_vcmla_laneq_f16( // CHECK-LABEL: @test_vcmla_laneq_f16(
// CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32> // CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> undef, <2 x i32> <i32 3, i32 3> // CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> poison, <2 x i32> <i32 3, i32 3>
// CHECK: [[DUP_FLT:%.*]] = bitcast <2 x i32> [[DUP]] to <4 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <2 x i32> [[DUP]] to <4 x half>
// CHECK: [[RES:%.*]] = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %acc, <4 x half> %lhs, <4 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot0.v4f16(<4 x half> %acc, <4 x half> %lhs, <4 x half> [[DUP_FLT]])
// CHECK: ret <4 x half> [[RES]] // CHECK: ret <4 x half> [[RES]]
float16x4_t test_vcmla_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t rhs) { float16x4_t test_vcmla_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t rhs) {
return vcmla_laneq_f16(acc, lhs, rhs, 3); return vcmla_laneq_f16(acc, lhs, rhs, 3);
} }
// CHECK-LABEL: @test_vcmlaq_lane_f16( // CHECK-LABEL: @test_vcmlaq_lane_f16(
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32> // CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> // CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: ret <8 x half> [[RES]] // CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) { float16x8_t test_vcmlaq_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
return vcmlaq_lane_f16(acc, lhs, rhs, 1); return vcmlaq_lane_f16(acc, lhs, rhs, 1);
} }
// CHECK-LABEL: @test_vcmlaq_laneq_f16( // CHECK-LABEL: @test_vcmlaq_laneq_f16(
// CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32> // CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> // CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot0.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: ret <8 x half> [[RES]] // CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_laneq_f16(float16x8_t acc, float16x8_t lhs, float16x8_t rhs) { float16x8_t test_vcmlaq_laneq_f16(float16x8_t acc, float16x8_t lhs, float16x8_t rhs) {
return vcmlaq_laneq_f16(acc, lhs, rhs, 3); return vcmlaq_laneq_f16(acc, lhs, rhs, 3);
} }
// CHECK-LABEL: @test_vcmla_lane_f32( // CHECK-LABEL: @test_vcmla_lane_f32(
// CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> %rhs) // CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> %rhs)
// CHECK: ret <2 x float> [[RES]] // CHECK: ret <2 x float> [[RES]]
float32x2_t test_vcmla_lane_f32(float32x2_t acc, float32x2_t lhs, float32x2_t rhs) { float32x2_t test_vcmla_lane_f32(float32x2_t acc, float32x2_t lhs, float32x2_t rhs) {
return vcmla_lane_f32(acc, lhs, rhs, 0); return vcmla_lane_f32(acc, lhs, rhs, 0);
} }
// ACLE says this exists, but it won't map to a single instruction if lane > 1. // ACLE says this exists, but it won't map to a single instruction if lane > 1.
// CHECK-LABEL: @test_vcmla_laneq_f32( // CHECK-LABEL: @test_vcmla_laneq_f32(
// CHECK: [[CPLX:%.*]] = bitcast <4 x float> %rhs to <2 x i64> // CHECK: [[CPLX:%.*]] = bitcast <4 x float> %rhs to <2 x i64>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i64> [[CPLX]], <2 x i64> undef, <1 x i32> <i32 1> // CHECK: [[DUP:%.*]] = shufflevector <2 x i64> [[CPLX]], <2 x i64> poison, <1 x i32> <i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <1 x i64> [[DUP]] to <2 x float> // CHECK: [[DUP_FLT:%.*]] = bitcast <1 x i64> [[DUP]] to <2 x float>
// CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot0.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> [[DUP_FLT]])
// CHECK: ret <2 x float> [[RES]] // CHECK: ret <2 x float> [[RES]]
float32x2_t test_vcmla_laneq_f32(float32x2_t acc, float32x2_t lhs, float32x4_t rhs) { float32x2_t test_vcmla_laneq_f32(float32x2_t acc, float32x2_t lhs, float32x4_t rhs) {
return vcmla_laneq_f32(acc, lhs, rhs, 1); return vcmla_laneq_f32(acc, lhs, rhs, 1);
} }
// CHECK-LABEL: @test_vcmlaq_lane_f32( // CHECK-LABEL: @test_vcmlaq_lane_f32(
// CHECK: [[CPLX:%.*]] = bitcast <2 x float> %rhs to i64 // CHECK: [[CPLX:%.*]] = bitcast <2 x float> %rhs to i64
// CHECK: [[CPLX_VEC:%.*]] = insertelement <2 x i64> undef, i64 [[CPLX]], i64 0 // CHECK: [[CPLX_VEC:%.*]] = insertelement <2 x i64> poison, i64 [[CPLX]], i64 0
// CHECK: [[CPLX2:%.*]] = bitcast <2 x i64> [[CPLX_VEC]] to <4 x float> // CHECK: [[CPLX2:%.*]] = bitcast <2 x i64> [[CPLX_VEC]] to <4 x float>
// CHECK: [[DUP:%.*]] = shufflevector <4 x float> [[CPLX2]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1> // CHECK: [[DUP:%.*]] = shufflevector <4 x float> [[CPLX2]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
// CHECK: [[RES:%.*]] = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %acc, <4 x float> %lhs, <4 x float> [[DUP]]) // CHECK: [[RES:%.*]] = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot0.v4f32(<4 x float> %acc, <4 x float> %lhs, <4 x float> [[DUP]])
// CHECK: ret <4 x float> [[RES]] // CHECK: ret <4 x float> [[RES]]
float32x4_t test_vcmlaq_lane_f32(float32x4_t acc, float32x4_t lhs, float32x2_t rhs) { float32x4_t test_vcmlaq_lane_f32(float32x4_t acc, float32x4_t lhs, float32x2_t rhs) {
return vcmlaq_lane_f32(acc, lhs, rhs, 0); return vcmlaq_lane_f32(acc, lhs, rhs, 0);
} }
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// CHECK: ret <4 x half> [[RES]] // CHECK: ret <4 x half> [[RES]]
float16x4_t test_vcmla_rot90_lane_f16(float16x4_t acc, float16x4_t lhs, float16x4_t rhs) { float16x4_t test_vcmla_rot90_lane_f16(float16x4_t acc, float16x4_t lhs, float16x4_t rhs) {
return vcmla_rot90_lane_f16(acc, lhs, rhs, 1); return vcmla_rot90_lane_f16(acc, lhs, rhs, 1);
} }
// ACLE says this exists, but it won't map to a single instruction if lane > 1. // ACLE says this exists, but it won't map to a single instruction if lane > 1.
// CHECK-LABEL: @test_vcmla_rot90_laneq_f16( // CHECK-LABEL: @test_vcmla_rot90_laneq_f16(
// CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32> // CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> undef, <2 x i32> <i32 3, i32 3> // CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> poison, <2 x i32> <i32 3, i32 3>
// CHECK: [[DUP_FLT:%.*]] = bitcast <2 x i32> [[DUP]] to <4 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <2 x i32> [[DUP]] to <4 x half>
// CHECK: [[RES:%.*]] = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v4f16(<4 x half> %acc, <4 x half> %lhs, <4 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot90.v4f16(<4 x half> %acc, <4 x half> %lhs, <4 x half> [[DUP_FLT]])
// CHECK: ret <4 x half> [[RES]] // CHECK: ret <4 x half> [[RES]]
float16x4_t test_vcmla_rot90_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t rhs) { float16x4_t test_vcmla_rot90_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t rhs) {
return vcmla_rot90_laneq_f16(acc, lhs, rhs, 3); return vcmla_rot90_laneq_f16(acc, lhs, rhs, 3);
} }
// CHECK-LABEL: @test_vcmlaq_rot90_lane_f16( // CHECK-LABEL: @test_vcmlaq_rot90_lane_f16(
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32> // CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> // CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: ret <8 x half> [[RES]] // CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_rot90_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) { float16x8_t test_vcmlaq_rot90_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
return vcmlaq_rot90_lane_f16(acc, lhs, rhs, 1); return vcmlaq_rot90_lane_f16(acc, lhs, rhs, 1);
} }
// CHECK-LABEL: @test_vcmlaq_rot90_laneq_f16( // CHECK-LABEL: @test_vcmlaq_rot90_laneq_f16(
// CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32> // CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> // CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot90.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: ret <8 x half> [[RES]] // CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_rot90_laneq_f16(float16x8_t acc, float16x8_t lhs, float16x8_t rhs) { float16x8_t test_vcmlaq_rot90_laneq_f16(float16x8_t acc, float16x8_t lhs, float16x8_t rhs) {
return vcmlaq_rot90_laneq_f16(acc, lhs, rhs, 3); return vcmlaq_rot90_laneq_f16(acc, lhs, rhs, 3);
} }
// CHECK-LABEL: @test_vcmla_rot90_lane_f32( // CHECK-LABEL: @test_vcmla_rot90_lane_f32(
// CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot90.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> %rhs) // CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot90.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> %rhs)
// CHECK: ret <2 x float> [[RES]] // CHECK: ret <2 x float> [[RES]]
float32x2_t test_vcmla_rot90_lane_f32(float32x2_t acc, float32x2_t lhs, float32x2_t rhs) { float32x2_t test_vcmla_rot90_lane_f32(float32x2_t acc, float32x2_t lhs, float32x2_t rhs) {
return vcmla_rot90_lane_f32(acc, lhs, rhs, 0); return vcmla_rot90_lane_f32(acc, lhs, rhs, 0);
} }
// ACLE says this exists, but it won't map to a single instruction if lane > 1. // ACLE says this exists, but it won't map to a single instruction if lane > 1.
// CHECK-LABEL: @test_vcmla_rot90_laneq_f32( // CHECK-LABEL: @test_vcmla_rot90_laneq_f32(
// CHECK: [[CPLX:%.*]] = bitcast <4 x float> %rhs to <2 x i64> // CHECK: [[CPLX:%.*]] = bitcast <4 x float> %rhs to <2 x i64>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i64> [[CPLX]], <2 x i64> undef, <1 x i32> <i32 1> // CHECK: [[DUP:%.*]] = shufflevector <2 x i64> [[CPLX]], <2 x i64> poison, <1 x i32> <i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <1 x i64> [[DUP]] to <2 x float> // CHECK: [[DUP_FLT:%.*]] = bitcast <1 x i64> [[DUP]] to <2 x float>
// CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot90.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot90.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> [[DUP_FLT]])
// CHECK: ret <2 x float> [[RES]] // CHECK: ret <2 x float> [[RES]]
float32x2_t test_vcmla_rot90_laneq_f32(float32x2_t acc, float32x2_t lhs, float32x4_t rhs) { float32x2_t test_vcmla_rot90_laneq_f32(float32x2_t acc, float32x2_t lhs, float32x4_t rhs) {
return vcmla_rot90_laneq_f32(acc, lhs, rhs, 1); return vcmla_rot90_laneq_f32(acc, lhs, rhs, 1);
} }
// CHECK-LABEL: @test_vcmlaq_rot90_lane_f32( // CHECK-LABEL: @test_vcmlaq_rot90_lane_f32(
// CHECK: [[CPLX:%.*]] = bitcast <2 x float> %rhs to i64 // CHECK: [[CPLX:%.*]] = bitcast <2 x float> %rhs to i64
// CHECK: [[CPLX_VEC:%.*]] = insertelement <2 x i64> undef, i64 [[CPLX]], i64 0 // CHECK: [[CPLX_VEC:%.*]] = insertelement <2 x i64> poison, i64 [[CPLX]], i64 0
// CHECK: [[CPLX2:%.*]] = bitcast <2 x i64> [[CPLX_VEC]] to <4 x float> // CHECK: [[CPLX2:%.*]] = bitcast <2 x i64> [[CPLX_VEC]] to <4 x float>
// CHECK: [[DUP:%.*]] = shufflevector <4 x float> [[CPLX2]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1> // CHECK: [[DUP:%.*]] = shufflevector <4 x float> [[CPLX2]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
// CHECK: [[RES:%.*]] = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot90.v4f32(<4 x float> %acc, <4 x float> %lhs, <4 x float> [[DUP]]) // CHECK: [[RES:%.*]] = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot90.v4f32(<4 x float> %acc, <4 x float> %lhs, <4 x float> [[DUP]])
// CHECK: ret <4 x float> [[RES]] // CHECK: ret <4 x float> [[RES]]
float32x4_t test_vcmlaq_rot90_lane_f32(float32x4_t acc, float32x4_t lhs, float32x2_t rhs) { float32x4_t test_vcmlaq_rot90_lane_f32(float32x4_t acc, float32x4_t lhs, float32x2_t rhs) {
return vcmlaq_rot90_lane_f32(acc, lhs, rhs, 0); return vcmlaq_rot90_lane_f32(acc, lhs, rhs, 0);
} }
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// CHECK: ret <4 x half> [[RES]] // CHECK: ret <4 x half> [[RES]]
float16x4_t test_vcmla_rot180_lane_f16(float16x4_t acc, float16x4_t lhs, float16x4_t rhs) { float16x4_t test_vcmla_rot180_lane_f16(float16x4_t acc, float16x4_t lhs, float16x4_t rhs) {
return vcmla_rot180_lane_f16(acc, lhs, rhs, 1); return vcmla_rot180_lane_f16(acc, lhs, rhs, 1);
} }
// ACLE says this exists, but it won't map to a single instruction if lane > 1. // ACLE says this exists, but it won't map to a single instruction if lane > 1.
// CHECK-LABEL: @test_vcmla_rot180_laneq_f16( // CHECK-LABEL: @test_vcmla_rot180_laneq_f16(
// CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32> // CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> undef, <2 x i32> <i32 3, i32 3> // CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> poison, <2 x i32> <i32 3, i32 3>
// CHECK: [[DUP_FLT:%.*]] = bitcast <2 x i32> [[DUP]] to <4 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <2 x i32> [[DUP]] to <4 x half>
// CHECK: [[RES:%.*]] = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot180.v4f16(<4 x half> %acc, <4 x half> %lhs, <4 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot180.v4f16(<4 x half> %acc, <4 x half> %lhs, <4 x half> [[DUP_FLT]])
// CHECK: ret <4 x half> [[RES]] // CHECK: ret <4 x half> [[RES]]
float16x4_t test_vcmla_rot180_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t rhs) { float16x4_t test_vcmla_rot180_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t rhs) {
return vcmla_rot180_laneq_f16(acc, lhs, rhs, 3); return vcmla_rot180_laneq_f16(acc, lhs, rhs, 3);
} }
// CHECK-LABEL: @test_vcmlaq_rot180_lane_f16( // CHECK-LABEL: @test_vcmlaq_rot180_lane_f16(
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32> // CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> // CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: ret <8 x half> [[RES]] // CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_rot180_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) { float16x8_t test_vcmlaq_rot180_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
return vcmlaq_rot180_lane_f16(acc, lhs, rhs, 1); return vcmlaq_rot180_lane_f16(acc, lhs, rhs, 1);
} }
// CHECK-LABEL: @test_vcmlaq_rot180_laneq_f16( // CHECK-LABEL: @test_vcmlaq_rot180_laneq_f16(
// CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32> // CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> // CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot180.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: ret <8 x half> [[RES]] // CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_rot180_laneq_f16(float16x8_t acc, float16x8_t lhs, float16x8_t rhs) { float16x8_t test_vcmlaq_rot180_laneq_f16(float16x8_t acc, float16x8_t lhs, float16x8_t rhs) {
return vcmlaq_rot180_laneq_f16(acc, lhs, rhs, 3); return vcmlaq_rot180_laneq_f16(acc, lhs, rhs, 3);
} }
// CHECK-LABEL: @test_vcmla_rot180_lane_f32( // CHECK-LABEL: @test_vcmla_rot180_lane_f32(
// CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot180.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> %rhs) // CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot180.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> %rhs)
// CHECK: ret <2 x float> [[RES]] // CHECK: ret <2 x float> [[RES]]
float32x2_t test_vcmla_rot180_lane_f32(float32x2_t acc, float32x2_t lhs, float32x2_t rhs) { float32x2_t test_vcmla_rot180_lane_f32(float32x2_t acc, float32x2_t lhs, float32x2_t rhs) {
return vcmla_rot180_lane_f32(acc, lhs, rhs, 0); return vcmla_rot180_lane_f32(acc, lhs, rhs, 0);
} }
// ACLE says this exists, but it won't map to a single instruction if lane > 1. // ACLE says this exists, but it won't map to a single instruction if lane > 1.
// CHECK-LABEL: @test_vcmla_rot180_laneq_f32( // CHECK-LABEL: @test_vcmla_rot180_laneq_f32(
// CHECK: [[CPLX:%.*]] = bitcast <4 x float> %rhs to <2 x i64> // CHECK: [[CPLX:%.*]] = bitcast <4 x float> %rhs to <2 x i64>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i64> [[CPLX]], <2 x i64> undef, <1 x i32> <i32 1> // CHECK: [[DUP:%.*]] = shufflevector <2 x i64> [[CPLX]], <2 x i64> poison, <1 x i32> <i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <1 x i64> [[DUP]] to <2 x float> // CHECK: [[DUP_FLT:%.*]] = bitcast <1 x i64> [[DUP]] to <2 x float>
// CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot180.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot180.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> [[DUP_FLT]])
// CHECK: ret <2 x float> [[RES]] // CHECK: ret <2 x float> [[RES]]
float32x2_t test_vcmla_rot180_laneq_f32(float32x2_t acc, float32x2_t lhs, float32x4_t rhs) { float32x2_t test_vcmla_rot180_laneq_f32(float32x2_t acc, float32x2_t lhs, float32x4_t rhs) {
return vcmla_rot180_laneq_f32(acc, lhs, rhs, 1); return vcmla_rot180_laneq_f32(acc, lhs, rhs, 1);
} }
// CHECK-LABEL: @test_vcmlaq_rot180_lane_f32( // CHECK-LABEL: @test_vcmlaq_rot180_lane_f32(
// CHECK: [[CPLX:%.*]] = bitcast <2 x float> %rhs to i64 // CHECK: [[CPLX:%.*]] = bitcast <2 x float> %rhs to i64
// CHECK: [[CPLX_VEC:%.*]] = insertelement <2 x i64> undef, i64 [[CPLX]], i64 0 // CHECK: [[CPLX_VEC:%.*]] = insertelement <2 x i64> poison, i64 [[CPLX]], i64 0
// CHECK: [[CPLX2:%.*]] = bitcast <2 x i64> [[CPLX_VEC]] to <4 x float> // CHECK: [[CPLX2:%.*]] = bitcast <2 x i64> [[CPLX_VEC]] to <4 x float>
// CHECK: [[DUP:%.*]] = shufflevector <4 x float> [[CPLX2]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1> // CHECK: [[DUP:%.*]] = shufflevector <4 x float> [[CPLX2]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
// CHECK: [[RES:%.*]] = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot180.v4f32(<4 x float> %acc, <4 x float> %lhs, <4 x float> [[DUP]]) // CHECK: [[RES:%.*]] = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot180.v4f32(<4 x float> %acc, <4 x float> %lhs, <4 x float> [[DUP]])
// CHECK: ret <4 x float> [[RES]] // CHECK: ret <4 x float> [[RES]]
float32x4_t test_vcmlaq_rot180_lane_f32(float32x4_t acc, float32x4_t lhs, float32x2_t rhs) { float32x4_t test_vcmlaq_rot180_lane_f32(float32x4_t acc, float32x4_t lhs, float32x2_t rhs) {
return vcmlaq_rot180_lane_f32(acc, lhs, rhs, 0); return vcmlaq_rot180_lane_f32(acc, lhs, rhs, 0);
} }
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// CHECK: ret <4 x half> [[RES]] // CHECK: ret <4 x half> [[RES]]
float16x4_t test_vcmla_rot270_lane_f16(float16x4_t acc, float16x4_t lhs, float16x4_t rhs) { float16x4_t test_vcmla_rot270_lane_f16(float16x4_t acc, float16x4_t lhs, float16x4_t rhs) {
return vcmla_rot270_lane_f16(acc, lhs, rhs, 1); return vcmla_rot270_lane_f16(acc, lhs, rhs, 1);
} }
// ACLE says this exists, but it won't map to a single instruction if lane > 1. // ACLE says this exists, but it won't map to a single instruction if lane > 1.
// CHECK-LABEL: @test_vcmla_rot270_laneq_f16( // CHECK-LABEL: @test_vcmla_rot270_laneq_f16(
// CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32> // CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> undef, <2 x i32> <i32 3, i32 3> // CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> poison, <2 x i32> <i32 3, i32 3>
// CHECK: [[DUP_FLT:%.*]] = bitcast <2 x i32> [[DUP]] to <4 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <2 x i32> [[DUP]] to <4 x half>
// CHECK: [[RES:%.*]] = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot270.v4f16(<4 x half> %acc, <4 x half> %lhs, <4 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <4 x half> @llvm.aarch64.neon.vcmla.rot270.v4f16(<4 x half> %acc, <4 x half> %lhs, <4 x half> [[DUP_FLT]])
// CHECK: ret <4 x half> [[RES]] // CHECK: ret <4 x half> [[RES]]
float16x4_t test_vcmla_rot270_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t rhs) { float16x4_t test_vcmla_rot270_laneq_f16(float16x4_t acc, float16x4_t lhs, float16x8_t rhs) {
return vcmla_rot270_laneq_f16(acc, lhs, rhs, 3); return vcmla_rot270_laneq_f16(acc, lhs, rhs, 3);
} }
// CHECK-LABEL: @test_vcmlaq_rot270_lane_f16( // CHECK-LABEL: @test_vcmlaq_rot270_lane_f16(
// CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32> // CHECK: [[CPLX:%.*]] = bitcast <4 x half> %rhs to <2 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> // CHECK: [[DUP:%.*]] = shufflevector <2 x i32> [[CPLX]], <2 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: ret <8 x half> [[RES]] // CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_rot270_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) { float16x8_t test_vcmlaq_rot270_lane_f16(float16x8_t acc, float16x8_t lhs, float16x4_t rhs) {
return vcmlaq_rot270_lane_f16(acc, lhs, rhs, 1); return vcmlaq_rot270_lane_f16(acc, lhs, rhs, 1);
} }
// CHECK-LABEL: @test_vcmlaq_rot270_laneq_f16( // CHECK-LABEL: @test_vcmlaq_rot270_laneq_f16(
// CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32> // CHECK: [[CPLX:%.*]] = bitcast <8 x half> %rhs to <4 x i32>
// CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> // CHECK: [[DUP:%.*]] = shufflevector <4 x i32> [[CPLX]], <4 x i32> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
// CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half> // CHECK: [[DUP_FLT:%.*]] = bitcast <4 x i32> [[DUP]] to <8 x half>
// CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <8 x half> @llvm.aarch64.neon.vcmla.rot270.v8f16(<8 x half> %acc, <8 x half> %lhs, <8 x half> [[DUP_FLT]])
// CHECK: ret <8 x half> [[RES]] // CHECK: ret <8 x half> [[RES]]
float16x8_t test_vcmlaq_rot270_laneq_f16(float16x8_t acc, float16x8_t lhs, float16x8_t rhs) { float16x8_t test_vcmlaq_rot270_laneq_f16(float16x8_t acc, float16x8_t lhs, float16x8_t rhs) {
return vcmlaq_rot270_laneq_f16(acc, lhs, rhs, 3); return vcmlaq_rot270_laneq_f16(acc, lhs, rhs, 3);
} }
// CHECK-LABEL: @test_vcmla_rot270_lane_f32( // CHECK-LABEL: @test_vcmla_rot270_lane_f32(
// CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot270.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> %rhs) // CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot270.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> %rhs)
// CHECK: ret <2 x float> [[RES]] // CHECK: ret <2 x float> [[RES]]
float32x2_t test_vcmla_rot270_lane_f32(float32x2_t acc, float32x2_t lhs, float32x2_t rhs) { float32x2_t test_vcmla_rot270_lane_f32(float32x2_t acc, float32x2_t lhs, float32x2_t rhs) {
return vcmla_rot270_lane_f32(acc, lhs, rhs, 0); return vcmla_rot270_lane_f32(acc, lhs, rhs, 0);
} }
// ACLE says this exists, but it won't map to a single instruction if lane > 1. // ACLE says this exists, but it won't map to a single instruction if lane > 1.
// CHECK-LABEL: @test_vcmla_rot270_laneq_f32( // CHECK-LABEL: @test_vcmla_rot270_laneq_f32(
// CHECK: [[CPLX:%.*]] = bitcast <4 x float> %rhs to <2 x i64> // CHECK: [[CPLX:%.*]] = bitcast <4 x float> %rhs to <2 x i64>
// CHECK: [[DUP:%.*]] = shufflevector <2 x i64> [[CPLX]], <2 x i64> undef, <1 x i32> <i32 1> // CHECK: [[DUP:%.*]] = shufflevector <2 x i64> [[CPLX]], <2 x i64> poison, <1 x i32> <i32 1>
// CHECK: [[DUP_FLT:%.*]] = bitcast <1 x i64> [[DUP]] to <2 x float> // CHECK: [[DUP_FLT:%.*]] = bitcast <1 x i64> [[DUP]] to <2 x float>
// CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot270.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> [[DUP_FLT]]) // CHECK: [[RES:%.*]] = tail call <2 x float> @llvm.aarch64.neon.vcmla.rot270.v2f32(<2 x float> %acc, <2 x float> %lhs, <2 x float> [[DUP_FLT]])
// CHECK: ret <2 x float> [[RES]] // CHECK: ret <2 x float> [[RES]]
float32x2_t test_vcmla_rot270_laneq_f32(float32x2_t acc, float32x2_t lhs, float32x4_t rhs) { float32x2_t test_vcmla_rot270_laneq_f32(float32x2_t acc, float32x2_t lhs, float32x4_t rhs) {
return vcmla_rot270_laneq_f32(acc, lhs, rhs, 1); return vcmla_rot270_laneq_f32(acc, lhs, rhs, 1);
} }
// CHECK-LABEL: @test_vcmlaq_rot270_lane_f32( // CHECK-LABEL: @test_vcmlaq_rot270_lane_f32(
// CHECK: [[CPLX:%.*]] = bitcast <2 x float> %rhs to i64 // CHECK: [[CPLX:%.*]] = bitcast <2 x float> %rhs to i64
// CHECK: [[CPLX_VEC:%.*]] = insertelement <2 x i64> undef, i64 [[CPLX]], i64 0 // CHECK: [[CPLX_VEC:%.*]] = insertelement <2 x i64> poison, i64 [[CPLX]], i64 0
// CHECK: [[CPLX2:%.*]] = bitcast <2 x i64> [[DUP]] to <4 x float> // CHECK: [[CPLX2:%.*]] = bitcast <2 x i64> [[DUP]] to <4 x float>
// CHECK: [[DUP:%.*]] = shufflevector <4 x float> [[CPLX2]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1> // CHECK: [[DUP:%.*]] = shufflevector <4 x float> [[CPLX2]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
// CHECK: [[RES:%.*]] = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot270.v4f32(<4 x float> %acc, <4 x float> %lhs, <4 x float> [[DUP]]) // CHECK: [[RES:%.*]] = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot270.v4f32(<4 x float> %acc, <4 x float> %lhs, <4 x float> [[DUP]])
// CHECK: ret <4 x float> [[RES]] // CHECK: ret <4 x float> [[RES]]
float32x4_t test_vcmlaq_rot270_lane_f32(float32x4_t acc, float32x4_t lhs, float32x2_t rhs) { float32x4_t test_vcmlaq_rot270_lane_f32(float32x4_t acc, float32x4_t lhs, float32x2_t rhs) {
return vcmlaq_rot270_lane_f32(acc, lhs, rhs, 0); return vcmlaq_rot270_lane_f32(acc, lhs, rhs, 0);
} }
// CHECK-LABEL: @test_vcmlaq_rot270_laneq_f32( // CHECK-LABEL: @test_vcmlaq_rot270_laneq_f32(
// CHECK: [[DUP:%.*]] = shufflevector <4 x float> %rhs, <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 2, i32 3> // CHECK: [[DUP:%.*]] = shufflevector <4 x float> %rhs, <4 x float> poison, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
// CHECK: [[RES:%.*]] = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot270.v4f32(<4 x float> %acc, <4 x float> %lhs, <4 x float> [[DUP]]) // CHECK: [[RES:%.*]] = tail call <4 x float> @llvm.aarch64.neon.vcmla.rot270.v4f32(<4 x float> %acc, <4 x float> %lhs, <4 x float> [[DUP]])
// CHECK: ret <4 x float> [[RES]] // CHECK: ret <4 x float> [[RES]]
float32x4_t test_vcmlaq_rot270_laneq_f32(float32x4_t acc, float32x4_t lhs, float32x4_t rhs) { float32x4_t test_vcmlaq_rot270_laneq_f32(float32x4_t acc, float32x4_t lhs, float32x4_t rhs) {
return vcmlaq_rot270_laneq_f32(acc, lhs, rhs, 1); return vcmlaq_rot270_laneq_f32(acc, lhs, rhs, 1);
} }

clang/test/CodeGen/nofpclass.c

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// CLFINITEONLY-NEXT: [[EXT1:%.*]] = fpext half [[C_SROA_0_2_VEC_EXTRACT]] to float // CLFINITEONLY-NEXT: [[EXT1:%.*]] = fpext half [[C_SROA_0_2_VEC_EXTRACT]] to float
// CLFINITEONLY-NEXT: [[MUL_AD:%.*]] = fmul nnan ninf float [[EXT]], [[EXT1]] // CLFINITEONLY-NEXT: [[MUL_AD:%.*]] = fmul nnan ninf float [[EXT]], [[EXT1]]
// CLFINITEONLY-NEXT: [[MUL_I:%.*]] = fadd nnan ninf float [[MUL_AD]], [[MUL_AD]] // CLFINITEONLY-NEXT: [[MUL_I:%.*]] = fadd nnan ninf float [[MUL_AD]], [[MUL_AD]]
// CLFINITEONLY-NEXT: [[MUL_AC:%.*]] = fmul nnan ninf float [[EXT]], [[EXT]] // CLFINITEONLY-NEXT: [[MUL_AC:%.*]] = fmul nnan ninf float [[EXT]], [[EXT]]
// CLFINITEONLY-NEXT: [[MUL_BD:%.*]] = fmul nnan ninf float [[EXT1]], [[EXT1]] // CLFINITEONLY-NEXT: [[MUL_BD:%.*]] = fmul nnan ninf float [[EXT1]], [[EXT1]]
// CLFINITEONLY-NEXT: [[MUL_R:%.*]] = fsub nnan ninf float [[MUL_AC]], [[MUL_BD]] // CLFINITEONLY-NEXT: [[MUL_R:%.*]] = fsub nnan ninf float [[MUL_AC]], [[MUL_BD]]
// CLFINITEONLY-NEXT: [[UNPROMOTION:%.*]] = fptrunc float [[MUL_R]] to half // CLFINITEONLY-NEXT: [[UNPROMOTION:%.*]] = fptrunc float [[MUL_R]] to half
// CLFINITEONLY-NEXT: [[UNPROMOTION9:%.*]] = fptrunc float [[MUL_I]] to half // CLFINITEONLY-NEXT: [[UNPROMOTION9:%.*]] = fptrunc float [[MUL_I]] to half
// CLFINITEONLY-NEXT: [[RETVAL_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x half> undef, half [[UNPROMOTION]], i64 0 // CLFINITEONLY-NEXT: [[RETVAL_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x half> poison, half [[UNPROMOTION]], i64 0
// CLFINITEONLY-NEXT: [[RETVAL_SROA_0_2_VEC_INSERT:%.*]] = insertelement <2 x half> [[RETVAL_SROA_0_0_VEC_INSERT]], half [[UNPROMOTION9]], i64 1 // CLFINITEONLY-NEXT: [[RETVAL_SROA_0_2_VEC_INSERT:%.*]] = insertelement <2 x half> [[RETVAL_SROA_0_0_VEC_INSERT]], half [[UNPROMOTION9]], i64 1
// CLFINITEONLY-NEXT: ret <2 x half> [[RETVAL_SROA_0_2_VEC_INSERT]] // CLFINITEONLY-NEXT: ret <2 x half> [[RETVAL_SROA_0_2_VEC_INSERT]]
// //
// NONANS: Function Attrs: noinline nounwind optnone // NONANS: Function Attrs: noinline nounwind optnone
// NONANS-LABEL: define dso_local nofpclass(nan) <2 x half> @defined_complex_func_f16_ret // NONANS-LABEL: define dso_local nofpclass(nan) <2 x half> @defined_complex_func_f16_ret
// NONANS-SAME: (<2 x half> noundef nofpclass(nan) [[C_COERCE:%.*]]) #[[ATTR4]] { // NONANS-SAME: (<2 x half> noundef nofpclass(nan) [[C_COERCE:%.*]]) #[[ATTR4]] {
// NONANS-NEXT: entry: // NONANS-NEXT: entry:
// NONANS-NEXT: [[RETVAL:%.*]] = alloca { half, half }, align 2 // NONANS-NEXT: [[RETVAL:%.*]] = alloca { half, half }, align 2
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// CLFINITEONLY-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca { double, double }, align 8 // CLFINITEONLY-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca { double, double }, align 8
// CLFINITEONLY-NEXT: [[CONV:%.*]] = fpext float [[F32]] to double // CLFINITEONLY-NEXT: [[CONV:%.*]] = fpext float [[F32]] to double
// CLFINITEONLY-NEXT: [[CF16_REAL:%.*]] = load half, ptr [[CF16]], align 8 // CLFINITEONLY-NEXT: [[CF16_REAL:%.*]] = load half, ptr [[CF16]], align 8
// CLFINITEONLY-NEXT: [[CF16_IMAGP:%.*]] = getelementptr inbounds { half, half }, ptr [[CF16]], i64 0, i32 1 // CLFINITEONLY-NEXT: [[CF16_IMAGP:%.*]] = getelementptr inbounds { half, half }, ptr [[CF16]], i64 0, i32 1
// CLFINITEONLY-NEXT: [[CF16_IMAG:%.*]] = load half, ptr [[CF16_IMAGP]], align 2 // CLFINITEONLY-NEXT: [[CF16_IMAG:%.*]] = load half, ptr [[CF16_IMAGP]], align 2
// CLFINITEONLY-NEXT: [[INDIRECT_ARG_TEMP_IMAGP:%.*]] = getelementptr inbounds { double, double }, ptr [[INDIRECT_ARG_TEMP]], i64 0, i32 1 // CLFINITEONLY-NEXT: [[INDIRECT_ARG_TEMP_IMAGP:%.*]] = getelementptr inbounds { double, double }, ptr [[INDIRECT_ARG_TEMP]], i64 0, i32 1
// CLFINITEONLY-NEXT: store double [[CF64_COERCE0]], ptr [[INDIRECT_ARG_TEMP]], align 8 // CLFINITEONLY-NEXT: store double [[CF64_COERCE0]], ptr [[INDIRECT_ARG_TEMP]], align 8
// CLFINITEONLY-NEXT: store double [[CF64_COERCE1]], ptr [[INDIRECT_ARG_TEMP_IMAGP]], align 8 // CLFINITEONLY-NEXT: store double [[CF64_COERCE1]], ptr [[INDIRECT_ARG_TEMP_IMAGP]], align 8
// CLFINITEONLY-NEXT: [[COERCE5_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x half> undef, half [[CF16_REAL]], i64 0 // CLFINITEONLY-NEXT: [[COERCE5_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x half> poison, half [[CF16_REAL]], i64 0
// CLFINITEONLY-NEXT: [[COERCE5_SROA_0_2_VEC_INSERT:%.*]] = insertelement <2 x half> [[COERCE5_SROA_0_0_VEC_INSERT]], half [[CF16_IMAG]], i64 1 // CLFINITEONLY-NEXT: [[COERCE5_SROA_0_2_VEC_INSERT:%.*]] = insertelement <2 x half> [[COERCE5_SROA_0_0_VEC_INSERT]], half [[CF16_IMAG]], i64 1
// CLFINITEONLY-NEXT: [[CALL:%.*]] = tail call nnan ninf nofpclass(nan inf) float (float, ...) @variadic(float noundef nofpclass(nan inf) [[F32]], double noundef nofpclass(nan inf) [[CONV]], double noundef nofpclass(nan inf) [[F64]], half noundef nofpclass(nan inf) [[F16]], double noundef nofpclass(nan inf) [[V2F32_COERCE]], <2 x double> noundef nofpclass(nan inf) [[V2F64]], i32 noundef [[V2F16_COERCE]], <2 x float> noundef nofpclass(nan inf) [[CF32_COERCE]], ptr noundef nonnull byval({ double, double }) align 8 [[INDIRECT_ARG_TEMP]], <2 x half> noundef nofpclass(nan inf) [[COERCE5_SROA_0_2_VEC_INSERT]]) #[[ATTR10]] // CLFINITEONLY-NEXT: [[CALL:%.*]] = tail call nnan ninf nofpclass(nan inf) float (float, ...) @variadic(float noundef nofpclass(nan inf) [[F32]], double noundef nofpclass(nan inf) [[CONV]], double noundef nofpclass(nan inf) [[F64]], half noundef nofpclass(nan inf) [[F16]], double noundef nofpclass(nan inf) [[V2F32_COERCE]], <2 x double> noundef nofpclass(nan inf) [[V2F64]], i32 noundef [[V2F16_COERCE]], <2 x float> noundef nofpclass(nan inf) [[CF32_COERCE]], ptr noundef nonnull byval({ double, double }) align 8 [[INDIRECT_ARG_TEMP]], <2 x half> noundef nofpclass(nan inf) [[COERCE5_SROA_0_2_VEC_INSERT]]) #[[ATTR10]]
// CLFINITEONLY-NEXT: ret float [[CALL]] // CLFINITEONLY-NEXT: ret float [[CALL]]
// //
// NONANS: Function Attrs: noinline nounwind optnone // NONANS: Function Attrs: noinline nounwind optnone
// NONANS-LABEL: define dso_local nofpclass(nan) float @call_variadic // NONANS-LABEL: define dso_local nofpclass(nan) float @call_variadic
// NONANS-SAME: (float noundef nofpclass(nan) [[F32:%.*]], double noundef nofpclass(nan) [[F64:%.*]], half noundef nofpclass(nan) [[F16:%.*]], double noundef nofpclass(nan) [[V2F32_COERCE:%.*]], <2 x double> noundef nofpclass(nan) [[V2F64:%.*]], i32 noundef [[V2F16_COERCE:%.*]], <2 x float> noundef nofpclass(nan) [[CF32_COERCE:%.*]], double noundef nofpclass(nan) [[CF64_COERCE0:%.*]], double noundef nofpclass(nan) [[CF64_COERCE1:%.*]], ptr noundef byval({ half, half }) align 8 [[CF16:%.*]]) #[[ATTR2]] { // NONANS-SAME: (float noundef nofpclass(nan) [[F32:%.*]], double noundef nofpclass(nan) [[F64:%.*]], half noundef nofpclass(nan) [[F16:%.*]], double noundef nofpclass(nan) [[V2F32_COERCE:%.*]], <2 x double> noundef nofpclass(nan) [[V2F64:%.*]], i32 noundef [[V2F16_COERCE:%.*]], <2 x float> noundef nofpclass(nan) [[CF32_COERCE:%.*]], double noundef nofpclass(nan) [[CF64_COERCE0:%.*]], double noundef nofpclass(nan) [[CF64_COERCE1:%.*]], ptr noundef byval({ half, half }) align 8 [[CF16:%.*]]) #[[ATTR2]] {
// NONANS-NEXT: entry: // NONANS-NEXT: entry:
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// CLFINITEONLY-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca { double, double }, align 8 // CLFINITEONLY-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca { double, double }, align 8
// CLFINITEONLY-NEXT: [[CONV:%.*]] = fpext float [[F32]] to double // CLFINITEONLY-NEXT: [[CONV:%.*]] = fpext float [[F32]] to double
// CLFINITEONLY-NEXT: [[CF16_REAL:%.*]] = load half, ptr [[CF16]], align 8 // CLFINITEONLY-NEXT: [[CF16_REAL:%.*]] = load half, ptr [[CF16]], align 8
// CLFINITEONLY-NEXT: [[CF16_IMAGP:%.*]] = getelementptr inbounds { half, half }, ptr [[CF16]], i64 0, i32 1 // CLFINITEONLY-NEXT: [[CF16_IMAGP:%.*]] = getelementptr inbounds { half, half }, ptr [[CF16]], i64 0, i32 1
// CLFINITEONLY-NEXT: [[CF16_IMAG:%.*]] = load half, ptr [[CF16_IMAGP]], align 2 // CLFINITEONLY-NEXT: [[CF16_IMAG:%.*]] = load half, ptr [[CF16_IMAGP]], align 2
// CLFINITEONLY-NEXT: [[INDIRECT_ARG_TEMP_IMAGP:%.*]] = getelementptr inbounds { double, double }, ptr [[INDIRECT_ARG_TEMP]], i64 0, i32 1 // CLFINITEONLY-NEXT: [[INDIRECT_ARG_TEMP_IMAGP:%.*]] = getelementptr inbounds { double, double }, ptr [[INDIRECT_ARG_TEMP]], i64 0, i32 1
// CLFINITEONLY-NEXT: store double [[CF64_COERCE0]], ptr [[INDIRECT_ARG_TEMP]], align 8 // CLFINITEONLY-NEXT: store double [[CF64_COERCE0]], ptr [[INDIRECT_ARG_TEMP]], align 8
// CLFINITEONLY-NEXT: store double [[CF64_COERCE1]], ptr [[INDIRECT_ARG_TEMP_IMAGP]], align 8 // CLFINITEONLY-NEXT: store double [[CF64_COERCE1]], ptr [[INDIRECT_ARG_TEMP_IMAGP]], align 8
// CLFINITEONLY-NEXT: [[COERCE5_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x half> undef, half [[CF16_REAL]], i64 0 // CLFINITEONLY-NEXT: [[COERCE5_SROA_0_0_VEC_INSERT:%.*]] = insertelement <2 x half> poison, half [[CF16_REAL]], i64 0
// CLFINITEONLY-NEXT: [[COERCE5_SROA_0_2_VEC_INSERT:%.*]] = insertelement <2 x half> [[COERCE5_SROA_0_0_VEC_INSERT]], half [[CF16_IMAG]], i64 1 // CLFINITEONLY-NEXT: [[COERCE5_SROA_0_2_VEC_INSERT:%.*]] = insertelement <2 x half> [[COERCE5_SROA_0_0_VEC_INSERT]], half [[CF16_IMAG]], i64 1
// CLFINITEONLY-NEXT: [[CALL:%.*]] = tail call nnan ninf nofpclass(nan inf) float (float, ...) [[FPTR]](float noundef nofpclass(nan inf) [[F32]], double noundef nofpclass(nan inf) [[CONV]], double noundef nofpclass(nan inf) [[F64]], half noundef nofpclass(nan inf) [[F16]], double noundef nofpclass(nan inf) [[V2F32_COERCE]], <2 x double> noundef nofpclass(nan inf) [[V2F64]], i32 noundef [[V2F16_COERCE]], <2 x float> noundef nofpclass(nan inf) [[CF32_COERCE]], ptr noundef nonnull byval({ double, double }) align 8 [[INDIRECT_ARG_TEMP]], <2 x half> noundef nofpclass(nan inf) [[COERCE5_SROA_0_2_VEC_INSERT]]) #[[ATTR10]] // CLFINITEONLY-NEXT: [[CALL:%.*]] = tail call nnan ninf nofpclass(nan inf) float (float, ...) [[FPTR]](float noundef nofpclass(nan inf) [[F32]], double noundef nofpclass(nan inf) [[CONV]], double noundef nofpclass(nan inf) [[F64]], half noundef nofpclass(nan inf) [[F16]], double noundef nofpclass(nan inf) [[V2F32_COERCE]], <2 x double> noundef nofpclass(nan inf) [[V2F64]], i32 noundef [[V2F16_COERCE]], <2 x float> noundef nofpclass(nan inf) [[CF32_COERCE]], ptr noundef nonnull byval({ double, double }) align 8 [[INDIRECT_ARG_TEMP]], <2 x half> noundef nofpclass(nan inf) [[COERCE5_SROA_0_2_VEC_INSERT]]) #[[ATTR10]]
// CLFINITEONLY-NEXT: ret float [[CALL]] // CLFINITEONLY-NEXT: ret float [[CALL]]
// //
// NONANS: Function Attrs: noinline nounwind optnone // NONANS: Function Attrs: noinline nounwind optnone
// NONANS-LABEL: define dso_local nofpclass(nan) float @call_variadic_indirect // NONANS-LABEL: define dso_local nofpclass(nan) float @call_variadic_indirect
// NONANS-SAME: (ptr noundef [[FPTR:%.*]], float noundef nofpclass(nan) [[F32:%.*]], double noundef nofpclass(nan) [[F64:%.*]], half noundef nofpclass(nan) [[F16:%.*]], double noundef nofpclass(nan) [[V2F32_COERCE:%.*]], <2 x double> noundef nofpclass(nan) [[V2F64:%.*]], i32 noundef [[V2F16_COERCE:%.*]], <2 x float> noundef nofpclass(nan) [[CF32_COERCE:%.*]], double noundef nofpclass(nan) [[CF64_COERCE0:%.*]], double noundef nofpclass(nan) [[CF64_COERCE1:%.*]], ptr noundef byval({ half, half }) align 8 [[CF16:%.*]]) #[[ATTR2]] { // NONANS-SAME: (ptr noundef [[FPTR:%.*]], float noundef nofpclass(nan) [[F32:%.*]], double noundef nofpclass(nan) [[F64:%.*]], half noundef nofpclass(nan) [[F16:%.*]], double noundef nofpclass(nan) [[V2F32_COERCE:%.*]], <2 x double> noundef nofpclass(nan) [[V2F64:%.*]], i32 noundef [[V2F16_COERCE:%.*]], <2 x float> noundef nofpclass(nan) [[CF32_COERCE:%.*]], double noundef nofpclass(nan) [[CF64_COERCE0:%.*]], double noundef nofpclass(nan) [[CF64_COERCE1:%.*]], ptr noundef byval({ half, half }) align 8 [[CF16:%.*]]) #[[ATTR2]] {
// NONANS-NEXT: entry: // NONANS-NEXT: entry:
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clang/test/Headers/wasm.c

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// //
v128_t test_v128_load(const void *mem) { v128_t test_v128_load(const void *mem) {
return wasm_v128_load(mem); return wasm_v128_load(mem);
} }
// CHECK-LABEL: @test_v128_load8_splat( // CHECK-LABEL: @test_v128_load8_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[MEM:%.*]], align 1, !tbaa [[TBAA2]] // CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[MEM:%.*]], align 1, !tbaa [[TBAA2]]
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> undef, i8 [[TMP0]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> poison, i8 [[TMP0]], i64 0
// CHECK-NEXT: [[VECINIT16_I:%.*]] = shufflevector <16 x i8> [[VECINIT_I]], <16 x i8> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT16_I:%.*]] = shufflevector <16 x i8> [[VECINIT_I]], <16 x i8> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VECINIT16_I]] to <4 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[VECINIT16_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_v128_load8_splat(const void *mem) { v128_t test_v128_load8_splat(const void *mem) {
return wasm_v128_load8_splat(mem); return wasm_v128_load8_splat(mem);
} }
// CHECK-LABEL: @test_v128_load16_splat( // CHECK-LABEL: @test_v128_load16_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[MEM:%.*]], align 1, !tbaa [[TBAA2]] // CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[MEM:%.*]], align 1, !tbaa [[TBAA2]]
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 [[TMP0]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[TMP0]], i64 0
// CHECK-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i16> [[VECINIT_I]], <8 x i16> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT8_I:%.*]] = shufflevector <8 x i16> [[VECINIT_I]], <8 x i16> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[VECINIT8_I]] to <4 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[VECINIT8_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_v128_load16_splat(const void *mem) { v128_t test_v128_load16_splat(const void *mem) {
return wasm_v128_load16_splat(mem); return wasm_v128_load16_splat(mem);
} }
// CHECK-LABEL: @test_v128_load32_splat( // CHECK-LABEL: @test_v128_load32_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[MEM:%.*]], align 1, !tbaa [[TBAA2]] // CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[MEM:%.*]], align 1, !tbaa [[TBAA2]]
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 [[TMP0]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
// CHECK-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i32> [[VECINIT_I]], <4 x i32> poison, <4 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT4_I:%.*]] = shufflevector <4 x i32> [[VECINIT_I]], <4 x i32> poison, <4 x i32> zeroinitializer
// CHECK-NEXT: ret <4 x i32> [[VECINIT4_I]] // CHECK-NEXT: ret <4 x i32> [[VECINIT4_I]]
// //
v128_t test_v128_load32_splat(const void *mem) { v128_t test_v128_load32_splat(const void *mem) {
return wasm_v128_load32_splat(mem); return wasm_v128_load32_splat(mem);
} }
// CHECK-LABEL: @test_v128_load64_splat( // CHECK-LABEL: @test_v128_load64_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[MEM:%.*]], align 1, !tbaa [[TBAA2]] // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[MEM:%.*]], align 1, !tbaa [[TBAA2]]
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> undef, i64 [[TMP0]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> poison, i64 [[TMP0]], i64 0
// CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i64> [[VECINIT_I]], <2 x i64> poison, <2 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <2 x i64> [[VECINIT_I]], <2 x i64> poison, <2 x i32> zeroinitializer
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[VECINIT2_I]] to <4 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[VECINIT2_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_v128_load64_splat(const void *mem) { v128_t test_v128_load64_splat(const void *mem) {
return wasm_v128_load64_splat(mem); return wasm_v128_load64_splat(mem);
} }
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// CHECK-NEXT: ret void // CHECK-NEXT: ret void
// //
void test_v128_store64_lane(uint64_t *ptr, v128_t vec) { void test_v128_store64_lane(uint64_t *ptr, v128_t vec) {
wasm_v128_store64_lane(ptr, vec, 1); wasm_v128_store64_lane(ptr, vec, 1);
} }
// CHECK-LABEL: @test_i8x16_make( // CHECK-LABEL: @test_i8x16_make(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> undef, i8 [[C0:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> <i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 [[C0:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <16 x i8> [[VECINIT_I]], i8 [[C1:%.*]], i64 1 // CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <16 x i8> [[VECINIT_I]], i8 [[C1:%.*]], i64 1
// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <16 x i8> [[VECINIT1_I]], i8 [[C2:%.*]], i64 2 // CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <16 x i8> [[VECINIT1_I]], i8 [[C2:%.*]], i64 2
// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <16 x i8> [[VECINIT2_I]], i8 [[C3:%.*]], i64 3 // CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <16 x i8> [[VECINIT2_I]], i8 [[C3:%.*]], i64 3
// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <16 x i8> [[VECINIT3_I]], i8 [[C4:%.*]], i64 4 // CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <16 x i8> [[VECINIT3_I]], i8 [[C4:%.*]], i64 4
// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <16 x i8> [[VECINIT4_I]], i8 [[C5:%.*]], i64 5 // CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <16 x i8> [[VECINIT4_I]], i8 [[C5:%.*]], i64 5
// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <16 x i8> [[VECINIT5_I]], i8 [[C6:%.*]], i64 6 // CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <16 x i8> [[VECINIT5_I]], i8 [[C6:%.*]], i64 6
// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <16 x i8> [[VECINIT6_I]], i8 [[C7:%.*]], i64 7 // CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <16 x i8> [[VECINIT6_I]], i8 [[C7:%.*]], i64 7
// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <16 x i8> [[VECINIT7_I]], i8 [[C8:%.*]], i64 8 // CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <16 x i8> [[VECINIT7_I]], i8 [[C8:%.*]], i64 8
// CHECK-NEXT: [[VECINIT9_I:%.*]] = insertelement <16 x i8> [[VECINIT8_I]], i8 [[C9:%.*]], i64 9 // CHECK-NEXT: [[VECINIT9_I:%.*]] = insertelement <16 x i8> [[VECINIT8_I]], i8 [[C9:%.*]], i64 9
// CHECK-NEXT: [[VECINIT10_I:%.*]] = insertelement <16 x i8> [[VECINIT9_I]], i8 [[C10:%.*]], i64 10 // CHECK-NEXT: [[VECINIT10_I:%.*]] = insertelement <16 x i8> [[VECINIT9_I]], i8 [[C10:%.*]], i64 10
// CHECK-NEXT: [[VECINIT11_I:%.*]] = insertelement <16 x i8> [[VECINIT10_I]], i8 [[C11:%.*]], i64 11 // CHECK-NEXT: [[VECINIT11_I:%.*]] = insertelement <16 x i8> [[VECINIT10_I]], i8 [[C11:%.*]], i64 11
// CHECK-NEXT: [[VECINIT12_I:%.*]] = insertelement <16 x i8> [[VECINIT11_I]], i8 [[C12:%.*]], i64 12 // CHECK-NEXT: [[VECINIT12_I:%.*]] = insertelement <16 x i8> [[VECINIT11_I]], i8 [[C12:%.*]], i64 12
// CHECK-NEXT: [[VECINIT13_I:%.*]] = insertelement <16 x i8> [[VECINIT12_I]], i8 [[C13:%.*]], i64 13 // CHECK-NEXT: [[VECINIT13_I:%.*]] = insertelement <16 x i8> [[VECINIT12_I]], i8 [[C13:%.*]], i64 13
// CHECK-NEXT: [[VECINIT14_I:%.*]] = insertelement <16 x i8> [[VECINIT13_I]], i8 [[C14:%.*]], i64 14 // CHECK-NEXT: [[VECINIT14_I:%.*]] = insertelement <16 x i8> [[VECINIT13_I]], i8 [[C14:%.*]], i64 14
// CHECK-NEXT: [[VECINIT15_I:%.*]] = insertelement <16 x i8> [[VECINIT14_I]], i8 [[C15:%.*]], i64 15 // CHECK-NEXT: [[VECINIT15_I:%.*]] = insertelement <16 x i8> [[VECINIT14_I]], i8 [[C15:%.*]], i64 15
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[VECINIT15_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[VECINIT15_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_i8x16_make(int8_t c0, int8_t c1, int8_t c2, int8_t c3, int8_t c4, int8_t c5, int8_t c6, int8_t c7, int8_t c8, int8_t c9, int8_t c10, int8_t c11, int8_t c12, int8_t c13, int8_t c14, int8_t c15) { v128_t test_i8x16_make(int8_t c0, int8_t c1, int8_t c2, int8_t c3, int8_t c4, int8_t c5, int8_t c6, int8_t c7, int8_t c8, int8_t c9, int8_t c10, int8_t c11, int8_t c12, int8_t c13, int8_t c14, int8_t c15) {
return wasm_i8x16_make(c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15); return wasm_i8x16_make(c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15);
} }
// CHECK-LABEL: @test_u8x16_make( // CHECK-LABEL: @test_u8x16_make(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> undef, i8 [[C0:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> <i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 poison, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>, i8 [[C0:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <16 x i8> [[VECINIT_I]], i8 [[C1:%.*]], i64 1 // CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <16 x i8> [[VECINIT_I]], i8 [[C1:%.*]], i64 1
// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <16 x i8> [[VECINIT1_I]], i8 [[C2:%.*]], i64 2 // CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <16 x i8> [[VECINIT1_I]], i8 [[C2:%.*]], i64 2
// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <16 x i8> [[VECINIT2_I]], i8 [[C3:%.*]], i64 3 // CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <16 x i8> [[VECINIT2_I]], i8 [[C3:%.*]], i64 3
// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <16 x i8> [[VECINIT3_I]], i8 [[C4:%.*]], i64 4 // CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <16 x i8> [[VECINIT3_I]], i8 [[C4:%.*]], i64 4
// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <16 x i8> [[VECINIT4_I]], i8 [[C5:%.*]], i64 5 // CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <16 x i8> [[VECINIT4_I]], i8 [[C5:%.*]], i64 5
// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <16 x i8> [[VECINIT5_I]], i8 [[C6:%.*]], i64 6 // CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <16 x i8> [[VECINIT5_I]], i8 [[C6:%.*]], i64 6
// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <16 x i8> [[VECINIT6_I]], i8 [[C7:%.*]], i64 7 // CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <16 x i8> [[VECINIT6_I]], i8 [[C7:%.*]], i64 7
// CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <16 x i8> [[VECINIT7_I]], i8 [[C8:%.*]], i64 8 // CHECK-NEXT: [[VECINIT8_I:%.*]] = insertelement <16 x i8> [[VECINIT7_I]], i8 [[C8:%.*]], i64 8
// CHECK-NEXT: [[VECINIT9_I:%.*]] = insertelement <16 x i8> [[VECINIT8_I]], i8 [[C9:%.*]], i64 9 // CHECK-NEXT: [[VECINIT9_I:%.*]] = insertelement <16 x i8> [[VECINIT8_I]], i8 [[C9:%.*]], i64 9
// CHECK-NEXT: [[VECINIT10_I:%.*]] = insertelement <16 x i8> [[VECINIT9_I]], i8 [[C10:%.*]], i64 10 // CHECK-NEXT: [[VECINIT10_I:%.*]] = insertelement <16 x i8> [[VECINIT9_I]], i8 [[C10:%.*]], i64 10
// CHECK-NEXT: [[VECINIT11_I:%.*]] = insertelement <16 x i8> [[VECINIT10_I]], i8 [[C11:%.*]], i64 11 // CHECK-NEXT: [[VECINIT11_I:%.*]] = insertelement <16 x i8> [[VECINIT10_I]], i8 [[C11:%.*]], i64 11
// CHECK-NEXT: [[VECINIT12_I:%.*]] = insertelement <16 x i8> [[VECINIT11_I]], i8 [[C12:%.*]], i64 12 // CHECK-NEXT: [[VECINIT12_I:%.*]] = insertelement <16 x i8> [[VECINIT11_I]], i8 [[C12:%.*]], i64 12
// CHECK-NEXT: [[VECINIT13_I:%.*]] = insertelement <16 x i8> [[VECINIT12_I]], i8 [[C13:%.*]], i64 13 // CHECK-NEXT: [[VECINIT13_I:%.*]] = insertelement <16 x i8> [[VECINIT12_I]], i8 [[C13:%.*]], i64 13
// CHECK-NEXT: [[VECINIT14_I:%.*]] = insertelement <16 x i8> [[VECINIT13_I]], i8 [[C14:%.*]], i64 14 // CHECK-NEXT: [[VECINIT14_I:%.*]] = insertelement <16 x i8> [[VECINIT13_I]], i8 [[C14:%.*]], i64 14
// CHECK-NEXT: [[VECINIT15_I:%.*]] = insertelement <16 x i8> [[VECINIT14_I]], i8 [[C15:%.*]], i64 15 // CHECK-NEXT: [[VECINIT15_I:%.*]] = insertelement <16 x i8> [[VECINIT14_I]], i8 [[C15:%.*]], i64 15
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[VECINIT15_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[VECINIT15_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_u8x16_make(uint8_t c0, uint8_t c1, uint8_t c2, uint8_t c3, uint8_t c4, uint8_t c5, uint8_t c6, uint8_t c7, uint8_t c8, uint8_t c9, uint8_t c10, uint8_t c11, uint8_t c12, uint8_t c13, uint8_t c14, uint8_t c15) { v128_t test_u8x16_make(uint8_t c0, uint8_t c1, uint8_t c2, uint8_t c3, uint8_t c4, uint8_t c5, uint8_t c6, uint8_t c7, uint8_t c8, uint8_t c9, uint8_t c10, uint8_t c11, uint8_t c12, uint8_t c13, uint8_t c14, uint8_t c15) {
return wasm_u8x16_make(c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15); return wasm_u8x16_make(c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15);
} }
// CHECK-LABEL: @test_i16x8_make( // CHECK-LABEL: @test_i16x8_make(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 [[C0:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[C0:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[C1:%.*]], i64 1 // CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[C1:%.*]], i64 1
// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[C2:%.*]], i64 2 // CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[C2:%.*]], i64 2
// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[C3:%.*]], i64 3 // CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[C3:%.*]], i64 3
// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[C4:%.*]], i64 4 // CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[C4:%.*]], i64 4
// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[C5:%.*]], i64 5 // CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[C5:%.*]], i64 5
// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[C6:%.*]], i64 6 // CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[C6:%.*]], i64 6
// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[C7:%.*]], i64 7 // CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[C7:%.*]], i64 7
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_i16x8_make(int16_t c0, int16_t c1, int16_t c2, int16_t c3, int16_t c4, int16_t c5, int16_t c6, int16_t c7) { v128_t test_i16x8_make(int16_t c0, int16_t c1, int16_t c2, int16_t c3, int16_t c4, int16_t c5, int16_t c6, int16_t c7) {
return wasm_i16x8_make(c0, c1, c2, c3, c4, c5, c6, c7); return wasm_i16x8_make(c0, c1, c2, c3, c4, c5, c6, c7);
} }
// CHECK-LABEL: @test_u16x8_make( // CHECK-LABEL: @test_u16x8_make(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 [[C0:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[C0:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[C1:%.*]], i64 1 // CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[C1:%.*]], i64 1
// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[C2:%.*]], i64 2 // CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[C2:%.*]], i64 2
// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[C3:%.*]], i64 3 // CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[C3:%.*]], i64 3
// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[C4:%.*]], i64 4 // CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[C4:%.*]], i64 4
// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[C5:%.*]], i64 5 // CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[C5:%.*]], i64 5
// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[C6:%.*]], i64 6 // CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[C6:%.*]], i64 6
// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[C7:%.*]], i64 7 // CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[C7:%.*]], i64 7
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_u16x8_make(uint16_t c0, uint16_t c1, uint16_t c2, uint16_t c3, uint16_t c4, uint16_t c5, uint16_t c6, uint16_t c7) { v128_t test_u16x8_make(uint16_t c0, uint16_t c1, uint16_t c2, uint16_t c3, uint16_t c4, uint16_t c5, uint16_t c6, uint16_t c7) {
return wasm_u16x8_make(c0, c1, c2, c3, c4, c5, c6, c7); return wasm_u16x8_make(c0, c1, c2, c3, c4, c5, c6, c7);
} }
// CHECK-LABEL: @test_i32x4_make( // CHECK-LABEL: @test_i32x4_make(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 [[C0:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[C0:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[C1:%.*]], i64 1 // CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[C1:%.*]], i64 1
// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[C2:%.*]], i64 2 // CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[C2:%.*]], i64 2
// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[C3:%.*]], i64 3 // CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[C3:%.*]], i64 3
// CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]] // CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]]
// //
v128_t test_i32x4_make(int32_t c0, int32_t c1, int32_t c2, int32_t c3) { v128_t test_i32x4_make(int32_t c0, int32_t c1, int32_t c2, int32_t c3) {
return wasm_i32x4_make(c0, c1, c2, c3); return wasm_i32x4_make(c0, c1, c2, c3);
} }
// CHECK-LABEL: @test_u32x4_make( // CHECK-LABEL: @test_u32x4_make(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 [[C0:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[C0:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[C1:%.*]], i64 1 // CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[C1:%.*]], i64 1
// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[C2:%.*]], i64 2 // CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[C2:%.*]], i64 2
// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[C3:%.*]], i64 3 // CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[C3:%.*]], i64 3
// CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]] // CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]]
// //
v128_t test_u32x4_make(uint32_t c0, uint32_t c1, uint32_t c2, uint32_t c3) { v128_t test_u32x4_make(uint32_t c0, uint32_t c1, uint32_t c2, uint32_t c3) {
return wasm_u32x4_make(c0, c1, c2, c3); return wasm_u32x4_make(c0, c1, c2, c3);
} }
// CHECK-LABEL: @test_i64x2_make( // CHECK-LABEL: @test_i64x2_make(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> undef, i64 [[C0:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> poison, i64 [[C0:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 [[C1:%.*]], i64 1 // CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 [[C1:%.*]], i64 1
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VECINIT1_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VECINIT1_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_i64x2_make(int64_t c0, int64_t c1) { v128_t test_i64x2_make(int64_t c0, int64_t c1) {
return wasm_i64x2_make(c0, c1); return wasm_i64x2_make(c0, c1);
} }
// CHECK-LABEL: @test_u64x2_make( // CHECK-LABEL: @test_u64x2_make(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> undef, i64 [[C0:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> poison, i64 [[C0:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 [[C1:%.*]], i64 1 // CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i64> [[VECINIT_I]], i64 [[C1:%.*]], i64 1
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VECINIT1_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VECINIT1_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_u64x2_make(uint64_t c0, uint64_t c1) { v128_t test_u64x2_make(uint64_t c0, uint64_t c1) {
return wasm_u64x2_make(c0, c1); return wasm_u64x2_make(c0, c1);
} }
// CHECK-LABEL: @test_f32x4_make( // CHECK-LABEL: @test_f32x4_make(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float [[C0:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[C0:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[C1:%.*]], i64 1 // CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[C1:%.*]], i64 1
// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float [[C2:%.*]], i64 2 // CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float [[C2:%.*]], i64 2
// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[C3:%.*]], i64 3 // CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[C3:%.*]], i64 3
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[VECINIT3_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[VECINIT3_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_f32x4_make(float c0, float c1, float c2, float c3) { v128_t test_f32x4_make(float c0, float c1, float c2, float c3) {
return wasm_f32x4_make(c0, c1, c2, c3); return wasm_f32x4_make(c0, c1, c2, c3);
} }
// CHECK-LABEL: @test_f64x2_make( // CHECK-LABEL: @test_f64x2_make(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double [[C0:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x double> poison, double [[C0:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double [[C1:%.*]], i64 1 // CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double [[C1:%.*]], i64 1
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[VECINIT1_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[VECINIT1_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_f64x2_make(double c0, double c1) { v128_t test_f64x2_make(double c0, double c1) {
return wasm_f64x2_make(c0, c1); return wasm_f64x2_make(c0, c1);
} }
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// CHECK-NEXT: ret <4 x i32> <i32 0, i32 1078263808, i32 0, i32 1078263808> // CHECK-NEXT: ret <4 x i32> <i32 0, i32 1078263808, i32 0, i32 1078263808>
// //
v128_t test_f64x2_const_splat(void) { v128_t test_f64x2_const_splat(void) {
return wasm_f64x2_const_splat(42); return wasm_f64x2_const_splat(42);
} }
// CHECK-LABEL: @test_i8x16_splat( // CHECK-LABEL: @test_i8x16_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> undef, i8 [[A:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> poison, i8 [[A:%.*]], i64 0
// CHECK-NEXT: [[VECINIT15_I:%.*]] = shufflevector <16 x i8> [[VECINIT_I]], <16 x i8> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT15_I:%.*]] = shufflevector <16 x i8> [[VECINIT_I]], <16 x i8> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[VECINIT15_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[VECINIT15_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_i8x16_splat(int8_t a) { v128_t test_i8x16_splat(int8_t a) {
return wasm_i8x16_splat(a); return wasm_i8x16_splat(a);
} }
// CHECK-LABEL: @test_u8x16_splat( // CHECK-LABEL: @test_u8x16_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> undef, i8 [[A:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <16 x i8> poison, i8 [[A:%.*]], i64 0
// CHECK-NEXT: [[VECINIT15_I:%.*]] = shufflevector <16 x i8> [[VECINIT_I]], <16 x i8> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT15_I:%.*]] = shufflevector <16 x i8> [[VECINIT_I]], <16 x i8> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[VECINIT15_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[VECINIT15_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_u8x16_splat(uint8_t a) { v128_t test_u8x16_splat(uint8_t a) {
return wasm_u8x16_splat(a); return wasm_u8x16_splat(a);
} }
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// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_u8x16_replace_lane(v128_t a, uint8_t b) { v128_t test_u8x16_replace_lane(v128_t a, uint8_t b) {
return wasm_u8x16_replace_lane(a, 15, b); return wasm_u8x16_replace_lane(a, 15, b);
} }
// CHECK-LABEL: @test_i16x8_splat( // CHECK-LABEL: @test_i16x8_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 [[A:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[A:%.*]], i64 0
// CHECK-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i16> [[VECINIT_I]], <8 x i16> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i16> [[VECINIT_I]], <8 x i16> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_i16x8_splat(int16_t a) { v128_t test_i16x8_splat(int16_t a) {
return wasm_i16x8_splat(a); return wasm_i16x8_splat(a);
} }
// CHECK-LABEL: @test_u16x8_splat( // CHECK-LABEL: @test_u16x8_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 [[A:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> poison, i16 [[A:%.*]], i64 0
// CHECK-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i16> [[VECINIT_I]], <8 x i16> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT7_I:%.*]] = shufflevector <8 x i16> [[VECINIT_I]], <8 x i16> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[VECINIT7_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_u16x8_splat(uint16_t a) { v128_t test_u16x8_splat(uint16_t a) {
return wasm_u16x8_splat(a); return wasm_u16x8_splat(a);
} }
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// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_u16x8_replace_lane(v128_t a, uint16_t b) { v128_t test_u16x8_replace_lane(v128_t a, uint16_t b) {
return wasm_u16x8_replace_lane(a, 7, b); return wasm_u16x8_replace_lane(a, 7, b);
} }
// CHECK-LABEL: @test_i32x4_splat( // CHECK-LABEL: @test_i32x4_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 [[A:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[A:%.*]], i64 0
// CHECK-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i32> [[VECINIT_I]], <4 x i32> poison, <4 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i32> [[VECINIT_I]], <4 x i32> poison, <4 x i32> zeroinitializer
// CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]] // CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]]
// //
v128_t test_i32x4_splat(int32_t a) { v128_t test_i32x4_splat(int32_t a) {
return wasm_i32x4_splat(a); return wasm_i32x4_splat(a);
} }
// CHECK-LABEL: @test_u32x4_splat( // CHECK-LABEL: @test_u32x4_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 [[A:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> poison, i32 [[A:%.*]], i64 0
// CHECK-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i32> [[VECINIT_I]], <4 x i32> poison, <4 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT3_I:%.*]] = shufflevector <4 x i32> [[VECINIT_I]], <4 x i32> poison, <4 x i32> zeroinitializer
// CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]] // CHECK-NEXT: ret <4 x i32> [[VECINIT3_I]]
// //
v128_t test_u32x4_splat(uint32_t a) { v128_t test_u32x4_splat(uint32_t a) {
return wasm_u32x4_splat(a); return wasm_u32x4_splat(a);
} }
// CHECK-LABEL: @test_i32x4_extract_lane( // CHECK-LABEL: @test_i32x4_extract_lane(
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// CHECK-NEXT: ret <4 x i32> [[VECINS_I]] // CHECK-NEXT: ret <4 x i32> [[VECINS_I]]
// //
v128_t test_u32x4_replace_lane(v128_t a, uint32_t b) { v128_t test_u32x4_replace_lane(v128_t a, uint32_t b) {
return wasm_u32x4_replace_lane(a, 3, b); return wasm_u32x4_replace_lane(a, 3, b);
} }
// CHECK-LABEL: @test_i64x2_splat( // CHECK-LABEL: @test_i64x2_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i64> [[VECINIT_I]], <2 x i64> poison, <2 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i64> [[VECINIT_I]], <2 x i64> poison, <2 x i32> zeroinitializer
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VECINIT1_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VECINIT1_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_i64x2_splat(int64_t a) { v128_t test_i64x2_splat(int64_t a) {
return wasm_i64x2_splat(a); return wasm_i64x2_splat(a);
} }
// CHECK-LABEL: @test_u64x2_splat( // CHECK-LABEL: @test_u64x2_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i64> [[VECINIT_I]], <2 x i64> poison, <2 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x i64> [[VECINIT_I]], <2 x i64> poison, <2 x i32> zeroinitializer
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VECINIT1_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[VECINIT1_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_u64x2_splat(uint64_t a) { v128_t test_u64x2_splat(uint64_t a) {
return wasm_u64x2_splat(a); return wasm_u64x2_splat(a);
} }
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// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_u64x2_replace_lane(v128_t a, uint64_t b) { v128_t test_u64x2_replace_lane(v128_t a, uint64_t b) {
return wasm_u64x2_replace_lane(a, 1, b); return wasm_u64x2_replace_lane(a, 1, b);
} }
// CHECK-LABEL: @test_f32x4_splat( // CHECK-LABEL: @test_f32x4_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float [[A:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> poison, float [[A:%.*]], i64 0
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[VECINIT_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[VECINIT_I]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer // CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <4 x i32> zeroinitializer
// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_f32x4_splat(float a) { v128_t test_f32x4_splat(float a) {
return wasm_f32x4_splat(a); return wasm_f32x4_splat(a);
} }
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// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_f32x4_replace_lane(v128_t a, float b) { v128_t test_f32x4_replace_lane(v128_t a, float b) {
return wasm_f32x4_replace_lane(a, 3, b); return wasm_f32x4_replace_lane(a, 3, b);
} }
// CHECK-LABEL: @test_f64x2_splat( // CHECK-LABEL: @test_f64x2_splat(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double [[A:%.*]], i64 0 // CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x double> poison, double [[A:%.*]], i64 0
// CHECK-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x double> [[VECINIT_I]], <2 x double> poison, <2 x i32> zeroinitializer // CHECK-NEXT: [[VECINIT1_I:%.*]] = shufflevector <2 x double> [[VECINIT_I]], <2 x double> poison, <2 x i32> zeroinitializer
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[VECINIT1_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[VECINIT1_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_f64x2_splat(double a) { v128_t test_f64x2_splat(double a) {
return wasm_f64x2_splat(a); return wasm_f64x2_splat(a);
} }
▲ Show 20 Lines • Show All 726 Lines • ▼ Show 20 Linesv128_t test_i8x16_popcnt(v128_t a) {
return wasm_i8x16_popcnt(a); return wasm_i8x16_popcnt(a);
} }
// CHECK-LABEL: @test_i8x16_shl( // CHECK-LABEL: @test_i8x16_shl(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i8 // CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i8
// CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7 // CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> undef, i8 [[TMP2]], i64 0 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> poison, i8 [[TMP2]], i64 0
// CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <16 x i8> [[TMP3]], <16 x i8> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <16 x i8> [[TMP3]], <16 x i8> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SHL_I:%.*]] = shl <16 x i8> [[TMP0]], [[SH_PROM_I]] // CHECK-NEXT: [[SHL_I:%.*]] = shl <16 x i8> [[TMP0]], [[SH_PROM_I]]
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[SHL_I]] to <4 x i32> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[SHL_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP4]] // CHECK-NEXT: ret <4 x i32> [[TMP4]]
// //
v128_t test_i8x16_shl(v128_t a, uint32_t b) { v128_t test_i8x16_shl(v128_t a, uint32_t b) {
return wasm_i8x16_shl(a, b); return wasm_i8x16_shl(a, b);
} }
// CHECK-LABEL: @test_i8x16_shr( // CHECK-LABEL: @test_i8x16_shr(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i8 // CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i8
// CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7 // CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> undef, i8 [[TMP2]], i64 0 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> poison, i8 [[TMP2]], i64 0
// CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <16 x i8> [[TMP3]], <16 x i8> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <16 x i8> [[TMP3]], <16 x i8> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SHR_I:%.*]] = ashr <16 x i8> [[TMP0]], [[SH_PROM_I]] // CHECK-NEXT: [[SHR_I:%.*]] = ashr <16 x i8> [[TMP0]], [[SH_PROM_I]]
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[SHR_I]] to <4 x i32> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[SHR_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP4]] // CHECK-NEXT: ret <4 x i32> [[TMP4]]
// //
v128_t test_i8x16_shr(v128_t a, uint32_t b) { v128_t test_i8x16_shr(v128_t a, uint32_t b) {
return wasm_i8x16_shr(a, b); return wasm_i8x16_shr(a, b);
} }
// CHECK-LABEL: @test_u8x16_shr( // CHECK-LABEL: @test_u8x16_shr(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i8 // CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i8
// CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7 // CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], 7
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> undef, i8 [[TMP2]], i64 0 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> poison, i8 [[TMP2]], i64 0
// CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <16 x i8> [[TMP3]], <16 x i8> poison, <16 x i32> zeroinitializer // CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <16 x i8> [[TMP3]], <16 x i8> poison, <16 x i32> zeroinitializer
// CHECK-NEXT: [[SHR_I:%.*]] = lshr <16 x i8> [[TMP0]], [[SH_PROM_I]] // CHECK-NEXT: [[SHR_I:%.*]] = lshr <16 x i8> [[TMP0]], [[SH_PROM_I]]
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[SHR_I]] to <4 x i32> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[SHR_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP4]] // CHECK-NEXT: ret <4 x i32> [[TMP4]]
// //
v128_t test_u8x16_shr(v128_t a, uint32_t b) { v128_t test_u8x16_shr(v128_t a, uint32_t b) {
return wasm_u8x16_shr(a, b); return wasm_u8x16_shr(a, b);
} }
▲ Show 20 Lines • Show All 173 Lines • ▼ Show 20 Linesuint32_t test_i16x8_bitmask(v128_t a) {
return wasm_i16x8_bitmask(a); return wasm_i16x8_bitmask(a);
} }
// CHECK-LABEL: @test_i16x8_shl( // CHECK-LABEL: @test_i16x8_shl(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i16 // CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i16
// CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15 // CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> undef, i16 [[TMP2]], i64 0 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> poison, i16 [[TMP2]], i64 0
// CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SHL_I:%.*]] = shl <8 x i16> [[TMP0]], [[SH_PROM_I]] // CHECK-NEXT: [[SHL_I:%.*]] = shl <8 x i16> [[TMP0]], [[SH_PROM_I]]
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[SHL_I]] to <4 x i32> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[SHL_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP4]] // CHECK-NEXT: ret <4 x i32> [[TMP4]]
// //
v128_t test_i16x8_shl(v128_t a, uint32_t b) { v128_t test_i16x8_shl(v128_t a, uint32_t b) {
return wasm_i16x8_shl(a, b); return wasm_i16x8_shl(a, b);
} }
// CHECK-LABEL: @test_i16x8_shr( // CHECK-LABEL: @test_i16x8_shr(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i16 // CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i16
// CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15 // CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> undef, i16 [[TMP2]], i64 0 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> poison, i16 [[TMP2]], i64 0
// CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SHR_I:%.*]] = ashr <8 x i16> [[TMP0]], [[SH_PROM_I]] // CHECK-NEXT: [[SHR_I:%.*]] = ashr <8 x i16> [[TMP0]], [[SH_PROM_I]]
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[SHR_I]] to <4 x i32> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[SHR_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP4]] // CHECK-NEXT: ret <4 x i32> [[TMP4]]
// //
v128_t test_i16x8_shr(v128_t a, uint32_t b) { v128_t test_i16x8_shr(v128_t a, uint32_t b) {
return wasm_i16x8_shr(a, b); return wasm_i16x8_shr(a, b);
} }
// CHECK-LABEL: @test_u16x8_shr( // CHECK-LABEL: @test_u16x8_shr(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i16 // CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[B:%.*]] to i16
// CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15 // CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 15
// CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> undef, i16 [[TMP2]], i64 0 // CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i16> poison, i16 [[TMP2]], i64 0
// CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> poison, <8 x i32> zeroinitializer // CHECK-NEXT: [[SH_PROM_I:%.*]] = shufflevector <8 x i16> [[TMP3]], <8 x i16> poison, <8 x i32> zeroinitializer
// CHECK-NEXT: [[SHR_I:%.*]] = lshr <8 x i16> [[TMP0]], [[SH_PROM_I]] // CHECK-NEXT: [[SHR_I:%.*]] = lshr <8 x i16> [[TMP0]], [[SH_PROM_I]]
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[SHR_I]] to <4 x i32> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[SHR_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP4]] // CHECK-NEXT: ret <4 x i32> [[TMP4]]
// //
v128_t test_u16x8_shr(v128_t a, uint32_t b) { v128_t test_u16x8_shr(v128_t a, uint32_t b) {
return wasm_u16x8_shr(a, b); return wasm_u16x8_shr(a, b);
} }
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// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_f32x4_convert_u32x4(v128_t a) { v128_t test_f32x4_convert_u32x4(v128_t a) {
return wasm_f32x4_convert_u32x4(a); return wasm_f32x4_convert_u32x4(a);
} }
// CHECK-LABEL: @test_f64x2_convert_low_i32x4( // CHECK-LABEL: @test_f64x2_convert_low_i32x4(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 1> // CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
// CHECK-NEXT: [[CONV_I:%.*]] = sitofp <2 x i32> [[VECINIT2_I]] to <2 x double> // CHECK-NEXT: [[CONV_I:%.*]] = sitofp <2 x i32> [[VECINIT2_I]] to <2 x double>
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[CONV_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[CONV_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_f64x2_convert_low_i32x4(v128_t a) { v128_t test_f64x2_convert_low_i32x4(v128_t a) {
return wasm_f64x2_convert_low_i32x4(a); return wasm_f64x2_convert_low_i32x4(a);
} }
// CHECK-LABEL: @test_f64x2_convert_low_u32x4( // CHECK-LABEL: @test_f64x2_convert_low_u32x4(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 1> // CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
// CHECK-NEXT: [[CONV_I:%.*]] = uitofp <2 x i32> [[VECINIT2_I]] to <2 x double> // CHECK-NEXT: [[CONV_I:%.*]] = uitofp <2 x i32> [[VECINIT2_I]] to <2 x double>
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[CONV_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x double> [[CONV_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_f64x2_convert_low_u32x4(v128_t a) { v128_t test_f64x2_convert_low_u32x4(v128_t a) {
return wasm_f64x2_convert_low_u32x4(a); return wasm_f64x2_convert_low_u32x4(a);
} }
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// //
v128_t test_f32x4_demote_f64x2_zero(v128_t a) { v128_t test_f32x4_demote_f64x2_zero(v128_t a) {
return wasm_f32x4_demote_f64x2_zero(a); return wasm_f32x4_demote_f64x2_zero(a);
} }
// CHECK-LABEL: @test_f64x2_promote_low_f32x4( // CHECK-LABEL: @test_f64x2_promote_low_f32x4(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <4 x float> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <4 x float>
// CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> undef, <2 x i32> <i32 0, i32 1> // CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x float> [[TMP0]], <4 x float> poison, <2 x i32> <i32 0, i32 1>
// CHECK-NEXT: [[CONV_I:%.*]] = fpext <2 x float> [[VECINIT2_I]] to <2 x double> // CHECK-NEXT: [[CONV_I:%.*]] = fpext <2 x float> [[VECINIT2_I]] to <2 x double>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[CONV_I]] to <4 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x double> [[CONV_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_f64x2_promote_low_f32x4(v128_t a) { v128_t test_f64x2_promote_low_f32x4(v128_t a) {
return wasm_f64x2_promote_low_f32x4(a); return wasm_f64x2_promote_low_f32x4(a);
} }
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// //
v128_t test_u16x8_narrow_i32x4(v128_t a, v128_t b) { v128_t test_u16x8_narrow_i32x4(v128_t a, v128_t b) {
return wasm_u16x8_narrow_i32x4(a, b); return wasm_u16x8_narrow_i32x4(a, b);
} }
// CHECK-LABEL: @test_i16x8_extend_low_i8x16( // CHECK-LABEL: @test_i16x8_extend_low_i8x16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT14_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I:%.*]] = sext <8 x i8> [[VECINIT14_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I:%.*]] = sext <8 x i8> [[VECINIT14_I]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[CONV_I]] to <4 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[CONV_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_i16x8_extend_low_i8x16(v128_t a) { v128_t test_i16x8_extend_low_i8x16(v128_t a) {
return wasm_i16x8_extend_low_i8x16(a); return wasm_i16x8_extend_low_i8x16(a);
} }
// CHECK-LABEL: @test_i16x8_extend_high_i8x16( // CHECK-LABEL: @test_i16x8_extend_high_i8x16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // CHECK-NEXT: [[VECINIT14_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[CONV_I:%.*]] = sext <8 x i8> [[VECINIT14_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I:%.*]] = sext <8 x i8> [[VECINIT14_I]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[CONV_I]] to <4 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[CONV_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_i16x8_extend_high_i8x16(v128_t a) { v128_t test_i16x8_extend_high_i8x16(v128_t a) {
return wasm_i16x8_extend_high_i8x16(a); return wasm_i16x8_extend_high_i8x16(a);
} }
// CHECK-LABEL: @test_u16x8_extend_low_u8x16( // CHECK-LABEL: @test_u16x8_extend_low_u8x16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT14_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I:%.*]] = zext <8 x i8> [[VECINIT14_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I:%.*]] = zext <8 x i8> [[VECINIT14_I]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[CONV_I]] to <4 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[CONV_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_u16x8_extend_low_u8x16(v128_t a) { v128_t test_u16x8_extend_low_u8x16(v128_t a) {
return wasm_u16x8_extend_low_u8x16(a); return wasm_u16x8_extend_low_u8x16(a);
} }
// CHECK-LABEL: @test_u16x8_extend_high_u8x16( // CHECK-LABEL: @test_u16x8_extend_high_u8x16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // CHECK-NEXT: [[VECINIT14_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[CONV_I:%.*]] = zext <8 x i8> [[VECINIT14_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I:%.*]] = zext <8 x i8> [[VECINIT14_I]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[CONV_I]] to <4 x i32> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[CONV_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
v128_t test_u16x8_extend_high_u8x16(v128_t a) { v128_t test_u16x8_extend_high_u8x16(v128_t a) {
return wasm_u16x8_extend_high_u8x16(a); return wasm_u16x8_extend_high_u8x16(a);
} }
// CHECK-LABEL: @test_i32x4_extend_low_i16x8( // CHECK-LABEL: @test_i32x4_extend_low_i16x8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> // CHECK-NEXT: [[VECINIT6_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK-NEXT: [[CONV_I:%.*]] = sext <4 x i16> [[VECINIT6_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I:%.*]] = sext <4 x i16> [[VECINIT6_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[CONV_I]] // CHECK-NEXT: ret <4 x i32> [[CONV_I]]
// //
v128_t test_i32x4_extend_low_i16x8(v128_t a) { v128_t test_i32x4_extend_low_i16x8(v128_t a) {
return wasm_i32x4_extend_low_i16x8(a); return wasm_i32x4_extend_low_i16x8(a);
} }
// CHECK-LABEL: @test_i32x4_extend_high_i16x8( // CHECK-LABEL: @test_i32x4_extend_high_i16x8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT6_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I:%.*]] = sext <4 x i16> [[VECINIT6_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I:%.*]] = sext <4 x i16> [[VECINIT6_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[CONV_I]] // CHECK-NEXT: ret <4 x i32> [[CONV_I]]
// //
v128_t test_i32x4_extend_high_i16x8(v128_t a) { v128_t test_i32x4_extend_high_i16x8(v128_t a) {
return wasm_i32x4_extend_high_i16x8(a); return wasm_i32x4_extend_high_i16x8(a);
} }
// CHECK-LABEL: @test_u32x4_extend_low_u16x8( // CHECK-LABEL: @test_u32x4_extend_low_u16x8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> // CHECK-NEXT: [[VECINIT6_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK-NEXT: [[CONV_I:%.*]] = zext <4 x i16> [[VECINIT6_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I:%.*]] = zext <4 x i16> [[VECINIT6_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[CONV_I]] // CHECK-NEXT: ret <4 x i32> [[CONV_I]]
// //
v128_t test_u32x4_extend_low_u16x8(v128_t a) { v128_t test_u32x4_extend_low_u16x8(v128_t a) {
return wasm_u32x4_extend_low_u16x8(a); return wasm_u32x4_extend_low_u16x8(a);
} }
// CHECK-LABEL: @test_u32x4_extend_high_u16x8( // CHECK-LABEL: @test_u32x4_extend_high_u16x8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT6_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I:%.*]] = zext <4 x i16> [[VECINIT6_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I:%.*]] = zext <4 x i16> [[VECINIT6_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[CONV_I]] // CHECK-NEXT: ret <4 x i32> [[CONV_I]]
// //
v128_t test_u32x4_extend_high_u16x8(v128_t a) { v128_t test_u32x4_extend_high_u16x8(v128_t a) {
return wasm_u32x4_extend_high_u16x8(a); return wasm_u32x4_extend_high_u16x8(a);
} }
// CHECK-LABEL: @test_i64x2_extend_low_i32x4( // CHECK-LABEL: @test_i64x2_extend_low_i32x4(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 1> // CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
// CHECK-NEXT: [[CONV_I:%.*]] = sext <2 x i32> [[VECINIT2_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I:%.*]] = sext <2 x i32> [[VECINIT2_I]] to <2 x i64>
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[CONV_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[CONV_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_i64x2_extend_low_i32x4(v128_t a) { v128_t test_i64x2_extend_low_i32x4(v128_t a) {
return wasm_i64x2_extend_low_i32x4(a); return wasm_i64x2_extend_low_i32x4(a);
} }
// CHECK-LABEL: @test_i64x2_extend_high_i32x4( // CHECK-LABEL: @test_i64x2_extend_high_i32x4(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> undef, <2 x i32> <i32 2, i32 3> // CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
// CHECK-NEXT: [[CONV_I:%.*]] = sext <2 x i32> [[VECINIT2_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I:%.*]] = sext <2 x i32> [[VECINIT2_I]] to <2 x i64>
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[CONV_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[CONV_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_i64x2_extend_high_i32x4(v128_t a) { v128_t test_i64x2_extend_high_i32x4(v128_t a) {
return wasm_i64x2_extend_high_i32x4(a); return wasm_i64x2_extend_high_i32x4(a);
} }
// CHECK-LABEL: @test_u64x2_extend_low_u32x4( // CHECK-LABEL: @test_u64x2_extend_low_u32x4(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 1> // CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
// CHECK-NEXT: [[CONV_I:%.*]] = zext <2 x i32> [[VECINIT2_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I:%.*]] = zext <2 x i32> [[VECINIT2_I]] to <2 x i64>
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[CONV_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[CONV_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_u64x2_extend_low_u32x4(v128_t a) { v128_t test_u64x2_extend_low_u32x4(v128_t a) {
return wasm_u64x2_extend_low_u32x4(a); return wasm_u64x2_extend_low_u32x4(a);
} }
// CHECK-LABEL: @test_u64x2_extend_high_u32x4( // CHECK-LABEL: @test_u64x2_extend_high_u32x4(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> undef, <2 x i32> <i32 2, i32 3> // CHECK-NEXT: [[VECINIT2_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
// CHECK-NEXT: [[CONV_I:%.*]] = zext <2 x i32> [[VECINIT2_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I:%.*]] = zext <2 x i32> [[VECINIT2_I]] to <2 x i64>
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[CONV_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[CONV_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_u64x2_extend_high_u32x4(v128_t a) { v128_t test_u64x2_extend_high_u32x4(v128_t a) {
return wasm_u64x2_extend_high_u32x4(a); return wasm_u64x2_extend_high_u32x4(a);
} }
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// //
v128_t test_u32x4_extadd_pairwise_u16x8(v128_t a) { v128_t test_u32x4_extadd_pairwise_u16x8(v128_t a) {
return wasm_u32x4_extadd_pairwise_u16x8(a); return wasm_u32x4_extadd_pairwise_u16x8(a);
} }
// CHECK-LABEL: @test_i16x8_extmul_low_i8x16( // CHECK-LABEL: @test_i16x8_extmul_low_i8x16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT14_I_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I_I:%.*]] = sext <8 x i8> [[VECINIT14_I_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I_I:%.*]] = sext <8 x i8> [[VECINIT14_I_I]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I2_I:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT14_I2_I:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <8 x i8> [[VECINIT14_I2_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <8 x i8> [[VECINIT14_I2_I]] to <8 x i16>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <8 x i16> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <8 x i16> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[MUL_I]] to <4 x i32> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[MUL_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
v128_t test_i16x8_extmul_low_i8x16(v128_t a, v128_t b) { v128_t test_i16x8_extmul_low_i8x16(v128_t a, v128_t b) {
return wasm_i16x8_extmul_low_i8x16(a, b); return wasm_i16x8_extmul_low_i8x16(a, b);
} }
// CHECK-LABEL: @test_i16x8_extmul_high_i8x16( // CHECK-LABEL: @test_i16x8_extmul_high_i8x16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // CHECK-NEXT: [[VECINIT14_I_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[CONV_I_I:%.*]] = sext <8 x i8> [[VECINIT14_I_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I_I:%.*]] = sext <8 x i8> [[VECINIT14_I_I]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I2_I:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // CHECK-NEXT: [[VECINIT14_I2_I:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <8 x i8> [[VECINIT14_I2_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <8 x i8> [[VECINIT14_I2_I]] to <8 x i16>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <8 x i16> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <8 x i16> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[MUL_I]] to <4 x i32> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[MUL_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
v128_t test_i16x8_extmul_high_i8x16(v128_t a, v128_t b) { v128_t test_i16x8_extmul_high_i8x16(v128_t a, v128_t b) {
return wasm_i16x8_extmul_high_i8x16(a, b); return wasm_i16x8_extmul_high_i8x16(a, b);
} }
// CHECK-LABEL: @test_u16x8_extmul_low_u8x16( // CHECK-LABEL: @test_u16x8_extmul_low_u8x16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT14_I_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I_I:%.*]] = zext <8 x i8> [[VECINIT14_I_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I_I:%.*]] = zext <8 x i8> [[VECINIT14_I_I]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I2_I:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT14_I2_I:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <8 x i8> [[VECINIT14_I2_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <8 x i8> [[VECINIT14_I2_I]] to <8 x i16>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <8 x i16> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <8 x i16> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[MUL_I]] to <4 x i32> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[MUL_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
v128_t test_u16x8_extmul_low_u8x16(v128_t a, v128_t b) { v128_t test_u16x8_extmul_low_u8x16(v128_t a, v128_t b) {
return wasm_u16x8_extmul_low_u8x16(a, b); return wasm_u16x8_extmul_low_u8x16(a, b);
} }
// CHECK-LABEL: @test_u16x8_extmul_high_u8x16( // CHECK-LABEL: @test_u16x8_extmul_high_u8x16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // CHECK-NEXT: [[VECINIT14_I_I:%.*]] = shufflevector <16 x i8> [[TMP0]], <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[CONV_I_I:%.*]] = zext <8 x i8> [[VECINIT14_I_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I_I:%.*]] = zext <8 x i8> [[VECINIT14_I_I]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <16 x i8> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <16 x i8>
// CHECK-NEXT: [[VECINIT14_I2_I:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // CHECK-NEXT: [[VECINIT14_I2_I:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <8 x i8> [[VECINIT14_I2_I]] to <8 x i16> // CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <8 x i8> [[VECINIT14_I2_I]] to <8 x i16>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <8 x i16> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <8 x i16> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[MUL_I]] to <4 x i32> // CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[MUL_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
v128_t test_u16x8_extmul_high_u8x16(v128_t a, v128_t b) { v128_t test_u16x8_extmul_high_u8x16(v128_t a, v128_t b) {
return wasm_u16x8_extmul_high_u8x16(a, b); return wasm_u16x8_extmul_high_u8x16(a, b);
} }
// CHECK-LABEL: @test_i32x4_extmul_low_i16x8( // CHECK-LABEL: @test_i32x4_extmul_low_i16x8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> // CHECK-NEXT: [[VECINIT6_I_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK-NEXT: [[CONV_I_I:%.*]] = sext <4 x i16> [[VECINIT6_I_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I_I:%.*]] = sext <4 x i16> [[VECINIT6_I_I]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I2_I:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> // CHECK-NEXT: [[VECINIT6_I2_I:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <4 x i16> [[VECINIT6_I2_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <4 x i16> [[VECINIT6_I2_I]] to <4 x i32>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <4 x i32> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <4 x i32> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: ret <4 x i32> [[MUL_I]] // CHECK-NEXT: ret <4 x i32> [[MUL_I]]
// //
v128_t test_i32x4_extmul_low_i16x8(v128_t a, v128_t b) { v128_t test_i32x4_extmul_low_i16x8(v128_t a, v128_t b) {
return wasm_i32x4_extmul_low_i16x8(a, b); return wasm_i32x4_extmul_low_i16x8(a, b);
} }
// CHECK-LABEL: @test_i32x4_extmul_high_i16x8( // CHECK-LABEL: @test_i32x4_extmul_high_i16x8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT6_I_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I_I:%.*]] = sext <4 x i16> [[VECINIT6_I_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I_I:%.*]] = sext <4 x i16> [[VECINIT6_I_I]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I2_I:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT6_I2_I:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <4 x i16> [[VECINIT6_I2_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <4 x i16> [[VECINIT6_I2_I]] to <4 x i32>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <4 x i32> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <4 x i32> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: ret <4 x i32> [[MUL_I]] // CHECK-NEXT: ret <4 x i32> [[MUL_I]]
// //
v128_t test_i32x4_extmul_high_i16x8(v128_t a, v128_t b) { v128_t test_i32x4_extmul_high_i16x8(v128_t a, v128_t b) {
return wasm_i32x4_extmul_high_i16x8(a, b); return wasm_i32x4_extmul_high_i16x8(a, b);
} }
// CHECK-LABEL: @test_u32x4_extmul_low_u16x8( // CHECK-LABEL: @test_u32x4_extmul_low_u16x8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> // CHECK-NEXT: [[VECINIT6_I_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK-NEXT: [[CONV_I_I:%.*]] = zext <4 x i16> [[VECINIT6_I_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I_I:%.*]] = zext <4 x i16> [[VECINIT6_I_I]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I2_I:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> // CHECK-NEXT: [[VECINIT6_I2_I:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <4 x i16> [[VECINIT6_I2_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <4 x i16> [[VECINIT6_I2_I]] to <4 x i32>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <4 x i32> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <4 x i32> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: ret <4 x i32> [[MUL_I]] // CHECK-NEXT: ret <4 x i32> [[MUL_I]]
// //
v128_t test_u32x4_extmul_low_u16x8(v128_t a, v128_t b) { v128_t test_u32x4_extmul_low_u16x8(v128_t a, v128_t b) {
return wasm_u32x4_extmul_low_u16x8(a, b); return wasm_u32x4_extmul_low_u16x8(a, b);
} }
// CHECK-LABEL: @test_u32x4_extmul_high_u16x8( // CHECK-LABEL: @test_u32x4_extmul_high_u16x8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT6_I_I:%.*]] = shufflevector <8 x i16> [[TMP0]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I_I:%.*]] = zext <4 x i16> [[VECINIT6_I_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I_I:%.*]] = zext <4 x i16> [[VECINIT6_I_I]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B:%.*]] to <8 x i16>
// CHECK-NEXT: [[VECINIT6_I2_I:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> // CHECK-NEXT: [[VECINIT6_I2_I:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <4 x i16> [[VECINIT6_I2_I]] to <4 x i32> // CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <4 x i16> [[VECINIT6_I2_I]] to <4 x i32>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <4 x i32> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <4 x i32> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: ret <4 x i32> [[MUL_I]] // CHECK-NEXT: ret <4 x i32> [[MUL_I]]
// //
v128_t test_u32x4_extmul_high_u16x8(v128_t a, v128_t b) { v128_t test_u32x4_extmul_high_u16x8(v128_t a, v128_t b) {
return wasm_u32x4_extmul_high_u16x8(a, b); return wasm_u32x4_extmul_high_u16x8(a, b);
} }
// CHECK-LABEL: @test_i64x2_extmul_low_i32x4( // CHECK-LABEL: @test_i64x2_extmul_low_i32x4(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT2_I_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 1> // CHECK-NEXT: [[VECINIT2_I_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
// CHECK-NEXT: [[CONV_I_I:%.*]] = sext <2 x i32> [[VECINIT2_I_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I_I:%.*]] = sext <2 x i32> [[VECINIT2_I_I]] to <2 x i64>
// CHECK-NEXT: [[VECINIT2_I2_I:%.*]] = shufflevector <4 x i32> [[B:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 1> // CHECK-NEXT: [[VECINIT2_I2_I:%.*]] = shufflevector <4 x i32> [[B:%.*]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <2 x i32> [[VECINIT2_I2_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <2 x i32> [[VECINIT2_I2_I]] to <2 x i64>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <2 x i64> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <2 x i64> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[MUL_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[MUL_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_i64x2_extmul_low_i32x4(v128_t a, v128_t b) { v128_t test_i64x2_extmul_low_i32x4(v128_t a, v128_t b) {
return wasm_i64x2_extmul_low_i32x4(a, b); return wasm_i64x2_extmul_low_i32x4(a, b);
} }
// CHECK-LABEL: @test_i64x2_extmul_high_i32x4( // CHECK-LABEL: @test_i64x2_extmul_high_i32x4(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT2_I_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> undef, <2 x i32> <i32 2, i32 3> // CHECK-NEXT: [[VECINIT2_I_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
// CHECK-NEXT: [[CONV_I_I:%.*]] = sext <2 x i32> [[VECINIT2_I_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I_I:%.*]] = sext <2 x i32> [[VECINIT2_I_I]] to <2 x i64>
// CHECK-NEXT: [[VECINIT2_I2_I:%.*]] = shufflevector <4 x i32> [[B:%.*]], <4 x i32> undef, <2 x i32> <i32 2, i32 3> // CHECK-NEXT: [[VECINIT2_I2_I:%.*]] = shufflevector <4 x i32> [[B:%.*]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <2 x i32> [[VECINIT2_I2_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I3_I:%.*]] = sext <2 x i32> [[VECINIT2_I2_I]] to <2 x i64>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <2 x i64> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nsw <2 x i64> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[MUL_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[MUL_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_i64x2_extmul_high_i32x4(v128_t a, v128_t b) { v128_t test_i64x2_extmul_high_i32x4(v128_t a, v128_t b) {
return wasm_i64x2_extmul_high_i32x4(a, b); return wasm_i64x2_extmul_high_i32x4(a, b);
} }
// CHECK-LABEL: @test_u64x2_extmul_low_u32x4( // CHECK-LABEL: @test_u64x2_extmul_low_u32x4(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT2_I_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 1> // CHECK-NEXT: [[VECINIT2_I_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
// CHECK-NEXT: [[CONV_I_I:%.*]] = zext <2 x i32> [[VECINIT2_I_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I_I:%.*]] = zext <2 x i32> [[VECINIT2_I_I]] to <2 x i64>
// CHECK-NEXT: [[VECINIT2_I2_I:%.*]] = shufflevector <4 x i32> [[B:%.*]], <4 x i32> undef, <2 x i32> <i32 0, i32 1> // CHECK-NEXT: [[VECINIT2_I2_I:%.*]] = shufflevector <4 x i32> [[B:%.*]], <4 x i32> poison, <2 x i32> <i32 0, i32 1>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <2 x i32> [[VECINIT2_I2_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <2 x i32> [[VECINIT2_I2_I]] to <2 x i64>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <2 x i64> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <2 x i64> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[MUL_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[MUL_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_u64x2_extmul_low_u32x4(v128_t a, v128_t b) { v128_t test_u64x2_extmul_low_u32x4(v128_t a, v128_t b) {
return wasm_u64x2_extmul_low_u32x4(a, b); return wasm_u64x2_extmul_low_u32x4(a, b);
} }
// CHECK-LABEL: @test_u64x2_extmul_high_u32x4( // CHECK-LABEL: @test_u64x2_extmul_high_u32x4(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[VECINIT2_I_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> undef, <2 x i32> <i32 2, i32 3> // CHECK-NEXT: [[VECINIT2_I_I:%.*]] = shufflevector <4 x i32> [[A:%.*]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
// CHECK-NEXT: [[CONV_I_I:%.*]] = zext <2 x i32> [[VECINIT2_I_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I_I:%.*]] = zext <2 x i32> [[VECINIT2_I_I]] to <2 x i64>
// CHECK-NEXT: [[VECINIT2_I2_I:%.*]] = shufflevector <4 x i32> [[B:%.*]], <4 x i32> undef, <2 x i32> <i32 2, i32 3> // CHECK-NEXT: [[VECINIT2_I2_I:%.*]] = shufflevector <4 x i32> [[B:%.*]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
// CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <2 x i32> [[VECINIT2_I2_I]] to <2 x i64> // CHECK-NEXT: [[CONV_I3_I:%.*]] = zext <2 x i32> [[VECINIT2_I2_I]] to <2 x i64>
// CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <2 x i64> [[CONV_I3_I]], [[CONV_I_I]] // CHECK-NEXT: [[MUL_I:%.*]] = mul nuw <2 x i64> [[CONV_I3_I]], [[CONV_I_I]]
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[MUL_I]] to <4 x i32> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[MUL_I]] to <4 x i32>
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
v128_t test_u64x2_extmul_high_u32x4(v128_t a, v128_t b) { v128_t test_u64x2_extmul_high_u32x4(v128_t a, v128_t b) {
return wasm_u64x2_extmul_high_u32x4(a, b); return wasm_u64x2_extmul_high_u32x4(a, b);
} }
Show All 12 Lines

llvm/include/llvm/Analysis/TargetTransformInfo.h

Show First 20 Lines • Show All 659 Lines • ▼ Show 20 Linespublic:
/// Can be used to implement target-specific instruction combining. /// Can be used to implement target-specific instruction combining.
/// \see instCombineIntrinsic /// \see instCombineIntrinsic
std::optional<Value *> simplifyDemandedUseBitsIntrinsic( std::optional<Value *> simplifyDemandedUseBitsIntrinsic(
InstCombiner & IC, IntrinsicInst & II, APInt DemandedMask, InstCombiner & IC, IntrinsicInst & II, APInt DemandedMask,
KnownBits & Known, bool &KnownBitsComputed) const; KnownBits & Known, bool &KnownBitsComputed) const;
/// Can be used to implement target-specific instruction combining. /// Can be used to implement target-specific instruction combining.
/// \see instCombineIntrinsic /// \see instCombineIntrinsic
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner & IC, IntrinsicInst & II, APInt DemandedElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
APInt & UndefElts, APInt & UndefElts2, APInt & UndefElts3, APInt &PoisonElts, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const; SimplifyAndSetOp) const;
/// @} /// @}
/// \name Scalar Target Information /// \name Scalar Target Information
/// @{ /// @{
/// Flags indicating the kind of support for population count. /// Flags indicating the kind of support for population count.
▲ Show 20 Lines • Show All 1,066 Lines • ▼ Show 20 Linespublic:
getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) = 0; getPreferredTailFoldingStyle(bool IVUpdateMayOverflow = true) = 0;
virtual std::optional<Instruction *> instCombineIntrinsic( virtual std::optional<Instruction *> instCombineIntrinsic(
InstCombiner &IC, IntrinsicInst &II) = 0; InstCombiner &IC, IntrinsicInst &II) = 0;
virtual std::optional<Value *> simplifyDemandedUseBitsIntrinsic( virtual std::optional<Value *> simplifyDemandedUseBitsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask,
KnownBits & Known, bool &KnownBitsComputed) = 0; KnownBits & Known, bool &KnownBitsComputed) = 0;
virtual std::optional<Value *> simplifyDemandedVectorEltsIntrinsic( virtual std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) = 0; SimplifyAndSetOp) = 0;
virtual bool isLegalAddImmediate(int64_t Imm) = 0; virtual bool isLegalAddImmediate(int64_t Imm) = 0;
virtual bool isLegalICmpImmediate(int64_t Imm) = 0; virtual bool isLegalICmpImmediate(int64_t Imm) = 0;
virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV, virtual bool isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
int64_t BaseOffset, bool HasBaseReg, int64_t BaseOffset, bool HasBaseReg,
int64_t Scale, unsigned AddrSpace, int64_t Scale, unsigned AddrSpace,
Instruction *I) = 0; Instruction *I) = 0;
▲ Show 20 Lines • Show All 413 Lines • ▼ Show 20 Linespublic:
std::optional<Value *> std::optional<Value *>
simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
APInt DemandedMask, KnownBits &Known, APInt DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) override { bool &KnownBitsComputed) override {
return Impl.simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known, return Impl.simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
KnownBitsComputed); KnownBitsComputed);
} }
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) override { SimplifyAndSetOp) override {
return Impl.simplifyDemandedVectorEltsIntrinsic( return Impl.simplifyDemandedVectorEltsIntrinsic(
IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, IC, II, DemandedElts, PoisonElts, PoisonElts2, PoisonElts3,
SimplifyAndSetOp); SimplifyAndSetOp);
} }
bool isLegalAddImmediate(int64_t Imm) override { bool isLegalAddImmediate(int64_t Imm) override {
return Impl.isLegalAddImmediate(Imm); return Impl.isLegalAddImmediate(Imm);
} }
bool isLegalICmpImmediate(int64_t Imm) override { bool isLegalICmpImmediate(int64_t Imm) override {
return Impl.isLegalICmpImmediate(Imm); return Impl.isLegalICmpImmediate(Imm);
} }
▲ Show 20 Lines • Show All 656 Lines • Show Last 20 Lines

llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

Show First 20 Lines • Show All 190 Lines • ▼ Show 20 Linespublic:
std::optional<Value *> std::optional<Value *>
simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
APInt DemandedMask, KnownBits &Known, APInt DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) const { bool &KnownBitsComputed) const {
return std::nullopt; return std::nullopt;
} }
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const { SimplifyAndSetOp) const {
return std::nullopt; return std::nullopt;
} }
void getUnrollingPreferences(Loop *, ScalarEvolution &, void getUnrollingPreferences(Loop *, ScalarEvolution &,
TTI::UnrollingPreferences &, TTI::UnrollingPreferences &,
OptimizationRemarkEmitter *) const {} OptimizationRemarkEmitter *) const {}
▲ Show 20 Lines • Show All 1,181 Lines • Show Last 20 Lines

llvm/include/llvm/CodeGen/BasicTTIImpl.h

Show First 20 Lines • Show All 648 Lines • ▼ Show 20 Linespublic:
simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
APInt DemandedMask, KnownBits &Known, APInt DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) { bool &KnownBitsComputed) {
return BaseT::simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known, return BaseT::simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
KnownBitsComputed); KnownBitsComputed);
} }
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) { SimplifyAndSetOp) {
return BaseT::simplifyDemandedVectorEltsIntrinsic( return BaseT::simplifyDemandedVectorEltsIntrinsic(
IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, IC, II, DemandedElts, PoisonElts, PoisonElts2, PoisonElts3,
SimplifyAndSetOp); SimplifyAndSetOp);
} }
virtual std::optional<unsigned> virtual std::optional<unsigned>
getCacheSize(TargetTransformInfo::CacheLevel Level) const { getCacheSize(TargetTransformInfo::CacheLevel Level) const {
return std::optional<unsigned>( return std::optional<unsigned>(
getST()->getCacheSize(static_cast<unsigned>(Level))); getST()->getCacheSize(static_cast<unsigned>(Level)));
} }
▲ Show 20 Lines • Show All 1,805 Lines • Show Last 20 Lines

llvm/include/llvm/Transforms/InstCombine/InstCombiner.h

Show First 20 Lines • Show All 380 Lines • ▼ Show 20 Linespublic:
// Call target specific combiners // Call target specific combiners
std::optional<Instruction *> targetInstCombineIntrinsic(IntrinsicInst &II); std::optional<Instruction *> targetInstCombineIntrinsic(IntrinsicInst &II);
std::optional<Value *> std::optional<Value *>
targetSimplifyDemandedUseBitsIntrinsic(IntrinsicInst &II, APInt DemandedMask, targetSimplifyDemandedUseBitsIntrinsic(IntrinsicInst &II, APInt DemandedMask,
KnownBits &Known, KnownBits &Known,
bool &KnownBitsComputed); bool &KnownBitsComputed);
std::optional<Value *> targetSimplifyDemandedVectorEltsIntrinsic( std::optional<Value *> targetSimplifyDemandedVectorEltsIntrinsic(
IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, IntrinsicInst &II, APInt DemandedElts, APInt &PoisonElts,
APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp); SimplifyAndSetOp);
/// Inserts an instruction \p New before instruction \p Old /// Inserts an instruction \p New before instruction \p Old
/// ///
/// Also adds the new instruction to the worklist and returns \p New so that /// Also adds the new instruction to the worklist and returns \p New so that
/// it is suitable for use as the return from the visitation patterns. /// it is suitable for use as the return from the visitation patterns.
Instruction *InsertNewInstBefore(Instruction *New, Instruction &Old) { Instruction *InsertNewInstBefore(Instruction *New, Instruction &Old) {
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines OverflowResult computeOverflowForSignedSub(const Value *LHS, const Value *RHS,
const Instruction *CxtI) const { const Instruction *CxtI) const {
return llvm::computeOverflowForSignedSub(LHS, RHS, DL, &AC, CxtI, &DT); return llvm::computeOverflowForSignedSub(LHS, RHS, DL, &AC, CxtI, &DT);
} }
virtual bool SimplifyDemandedBits(Instruction *I, unsigned OpNo, virtual bool SimplifyDemandedBits(Instruction *I, unsigned OpNo,
const APInt &DemandedMask, KnownBits &Known, const APInt &DemandedMask, KnownBits &Known,
unsigned Depth = 0) = 0; unsigned Depth = 0) = 0;
virtual Value * virtual Value *
SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, APInt &UndefElts, SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, APInt &PoisonElts,
unsigned Depth = 0, unsigned Depth = 0,
bool AllowMultipleUsers = false) = 0; bool AllowMultipleUsers = false) = 0;
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const; bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const;
}; };
} // namespace llvm } // namespace llvm
#undef DEBUG_TYPE #undef DEBUG_TYPE
#endif #endif

llvm/lib/Analysis/TargetTransformInfo.cpp

Show First 20 Lines • Show All 350 Lines • ▼ Show 20 Lines
std::optional<Value *> TargetTransformInfo::simplifyDemandedUseBitsIntrinsic( std::optional<Value *> TargetTransformInfo::simplifyDemandedUseBitsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known, InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) const { bool &KnownBitsComputed) const {
return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known, return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
KnownBitsComputed); KnownBitsComputed);
} }
std::optional<Value *> TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &PoisonElts,
APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const { SimplifyAndSetOp) const {
return TTIImpl->simplifyDemandedVectorEltsIntrinsic( return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, IC, II, DemandedElts, PoisonElts, PoisonElts2, PoisonElts3,
SimplifyAndSetOp); SimplifyAndSetOp);
} }
void TargetTransformInfo::getUnrollingPreferences( void TargetTransformInfo::getUnrollingPreferences(
Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP, Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP,
OptimizationRemarkEmitter *ORE) const { OptimizationRemarkEmitter *ORE) const {
return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE); return TTIImpl->getUnrollingPreferences(L, SE, UP, ORE);
} }
▲ Show 20 Lines • Show All 916 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h

Show First 20 Lines • Show All 113 Lines • ▼ Show 20 Linespublic:
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind); TTI::TargetCostKind CostKind);
std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC, std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const; IntrinsicInst &II) const;
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const; SimplifyAndSetOp) const;
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const; TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const;
unsigned getMinVectorRegisterBitWidth() const { unsigned getMinVectorRegisterBitWidth() const {
return ST->getMinVectorRegisterBitWidth(); return ST->getMinVectorRegisterBitWidth();
} }
▲ Show 20 Lines • Show All 281 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Show First 20 Lines • Show All 1,890 Lines • ▼ Show 20 Lines case Intrinsic::aarch64_sve_dupq_lane:
return instCombineSVEDupqLane(IC, II); return instCombineSVEDupqLane(IC, II);
} }
return std::nullopt; return std::nullopt;
} }
std::optional<Value *> AArch64TTIImpl::simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> AArch64TTIImpl::simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt OrigDemandedElts, InstCombiner &IC, IntrinsicInst &II, APInt OrigDemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const { SimplifyAndSetOp) const {
switch (II.getIntrinsicID()) { switch (II.getIntrinsicID()) {
default: default:
break; break;
case Intrinsic::aarch64_neon_fcvtxn: case Intrinsic::aarch64_neon_fcvtxn:
case Intrinsic::aarch64_neon_rshrn: case Intrinsic::aarch64_neon_rshrn:
case Intrinsic::aarch64_neon_sqrshrn: case Intrinsic::aarch64_neon_sqrshrn:
case Intrinsic::aarch64_neon_sqrshrun: case Intrinsic::aarch64_neon_sqrshrun:
case Intrinsic::aarch64_neon_sqshrn: case Intrinsic::aarch64_neon_sqshrn:
case Intrinsic::aarch64_neon_sqshrun: case Intrinsic::aarch64_neon_sqshrun:
case Intrinsic::aarch64_neon_sqxtn: case Intrinsic::aarch64_neon_sqxtn:
case Intrinsic::aarch64_neon_sqxtun: case Intrinsic::aarch64_neon_sqxtun:
case Intrinsic::aarch64_neon_uqrshrn: case Intrinsic::aarch64_neon_uqrshrn:
case Intrinsic::aarch64_neon_uqshrn: case Intrinsic::aarch64_neon_uqshrn:
case Intrinsic::aarch64_neon_uqxtn: case Intrinsic::aarch64_neon_uqxtn:
SimplifyAndSetOp(&II, 0, OrigDemandedElts, UndefElts); SimplifyAndSetOp(&II, 0, OrigDemandedElts, PoisonElts);
break; break;
} }
return std::nullopt; return std::nullopt;
} }
TypeSize TypeSize
AArch64TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const { AArch64TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
▲ Show 20 Lines • Show All 1,882 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp

Show First 20 Lines • Show All 1,300 Lines • ▼ Show 20 Lines if (IsLoad) {
return Shuffle; return Shuffle;
} }
return NewCall; return NewCall;
} }
std::optional<Value *> GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> GCNTTIImpl::simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &PoisonElts,
APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const { SimplifyAndSetOp) const {
switch (II.getIntrinsicID()) { switch (II.getIntrinsicID()) {
case Intrinsic::amdgcn_buffer_load: case Intrinsic::amdgcn_buffer_load:
case Intrinsic::amdgcn_buffer_load_format: case Intrinsic::amdgcn_buffer_load_format:
case Intrinsic::amdgcn_raw_buffer_load: case Intrinsic::amdgcn_raw_buffer_load:
case Intrinsic::amdgcn_raw_ptr_buffer_load: case Intrinsic::amdgcn_raw_ptr_buffer_load:
case Intrinsic::amdgcn_raw_buffer_load_format: case Intrinsic::amdgcn_raw_buffer_load_format:
Show All 21 Lines

llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h

Show First 20 Lines • Show All 217 Lines • ▼ Show 20 Linespublic:
Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV, Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,
Value *NewV) const; Value *NewV) const;
bool canSimplifyLegacyMulToMul(const Instruction &I, const Value *Op0, bool canSimplifyLegacyMulToMul(const Instruction &I, const Value *Op0,
const Value *Op1, InstCombiner &IC) const; const Value *Op1, InstCombiner &IC) const;
std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC, std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const; IntrinsicInst &II) const;
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const; SimplifyAndSetOp) const;
InstructionCost getVectorSplitCost() { return 0; } InstructionCost getVectorSplitCost() { return 0; }
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
ArrayRef<int> Mask, ArrayRef<int> Mask,
TTI::TargetCostKind CostKind, int Index, TTI::TargetCostKind CostKind, int Index,
Show All 26 Lines

llvm/lib/Target/ARM/ARMTargetTransformInfo.h

Show First 20 Lines • Show All 116 Lines • ▼ Show 20 Linespublic:
/// and Arm MVE are IEEE-754 compliant. /// and Arm MVE are IEEE-754 compliant.
bool isFPVectorizationPotentiallyUnsafe() { bool isFPVectorizationPotentiallyUnsafe() {
return !ST->isTargetDarwin() && !ST->hasMVEFloatOps(); return !ST->isTargetDarwin() && !ST->hasMVEFloatOps();
} }
std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC, std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const; IntrinsicInst &II) const;
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const; SimplifyAndSetOp) const;
/// \name Scalar TTI Implementations /// \name Scalar TTI Implementations
/// @{ /// @{
InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, InstructionCost getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
const APInt &Imm, Type *Ty); const APInt &Imm, Type *Ty);
▲ Show 20 Lines • Show All 232 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp

Show First 20 Lines • Show All 246 Lines • ▼ Show 20 Lines case Intrinsic::arm_mve_vmldava: {
return std::nullopt; return std::nullopt;
} }
} }
return std::nullopt; return std::nullopt;
} }
std::optional<Value *> ARMTTIImpl::simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> ARMTTIImpl::simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt OrigDemandedElts, InstCombiner &IC, IntrinsicInst &II, APInt OrigDemandedElts,
APInt &UndefElts, APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const { SimplifyAndSetOp) const {
// Compute the demanded bits for a narrowing MVE intrinsic. The TopOpc is the // Compute the demanded bits for a narrowing MVE intrinsic. The TopOpc is the
// opcode specifying a Top/Bottom instruction, which can change between // opcode specifying a Top/Bottom instruction, which can change between
// instructions. // instructions.
auto SimplifyNarrowInstrTopBottom =[&](unsigned TopOpc) { auto SimplifyNarrowInstrTopBottom =[&](unsigned TopOpc) {
unsigned NumElts = cast<FixedVectorType>(II.getType())->getNumElements(); unsigned NumElts = cast<FixedVectorType>(II.getType())->getNumElements();
unsigned IsTop = cast<ConstantInt>(II.getOperand(TopOpc))->getZExtValue(); unsigned IsTop = cast<ConstantInt>(II.getOperand(TopOpc))->getZExtValue();
// The only odd/even lanes of operand 0 will only be demanded depending // The only odd/even lanes of operand 0 will only be demanded depending
// on whether this is a top/bottom instruction. // on whether this is a top/bottom instruction.
APInt DemandedElts = APInt DemandedElts =
APInt::getSplat(NumElts, IsTop ? APInt::getLowBitsSet(2, 1) APInt::getSplat(NumElts, IsTop ? APInt::getLowBitsSet(2, 1)
: APInt::getHighBitsSet(2, 1)); : APInt::getHighBitsSet(2, 1));
SimplifyAndSetOp(&II, 0, OrigDemandedElts & DemandedElts, UndefElts); SimplifyAndSetOp(&II, 0, OrigDemandedElts & DemandedElts, PoisonElts);
// The other lanes will be defined from the inserted elements. // The other lanes will be defined from the inserted elements.
UndefElts &= APInt::getSplat(NumElts, !IsTop ? APInt::getLowBitsSet(2, 1) PoisonElts &= APInt::getSplat(NumElts, !IsTop ? APInt::getLowBitsSet(2, 1)
: APInt::getHighBitsSet(2, 1)); : APInt::getHighBitsSet(2, 1));
return std::nullopt; return std::nullopt;
}; };
switch (II.getIntrinsicID()) { switch (II.getIntrinsicID()) {
default: default:
break; break;
case Intrinsic::arm_mve_vcvt_narrow: case Intrinsic::arm_mve_vcvt_narrow:
▲ Show 20 Lines • Show All 2,183 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86InstCombineIntrinsic.cpp

Show First 20 Lines • Show All 1,991 Lines • ▼ Show 20 Linesstatic Value *simplifyX86vpermv(const IntrinsicInst &II,
auto V1 = II.getArgOperand(0); auto V1 = II.getArgOperand(0);
return Builder.CreateShuffleVector(V1, ArrayRef(Indexes, Size)); return Builder.CreateShuffleVector(V1, ArrayRef(Indexes, Size));
} }
std::optional<Instruction *> std::optional<Instruction *>
X86TTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const { X86TTIImpl::instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const {
auto SimplifyDemandedVectorEltsLow = [&IC](Value *Op, unsigned Width, auto SimplifyDemandedVectorEltsLow = [&IC](Value *Op, unsigned Width,
unsigned DemandedWidth) { unsigned DemandedWidth) {
APInt UndefElts(Width, 0); APInt PoisonElts(Width, 0);
APInt DemandedElts = APInt::getLowBitsSet(Width, DemandedWidth); APInt DemandedElts = APInt::getLowBitsSet(Width, DemandedWidth);
return IC.SimplifyDemandedVectorElts(Op, DemandedElts, UndefElts); return IC.SimplifyDemandedVectorElts(Op, DemandedElts, PoisonElts);
}; };
Intrinsic::ID IID = II.getIntrinsicID(); Intrinsic::ID IID = II.getIntrinsicID();
switch (IID) { switch (IID) {
case Intrinsic::x86_bmi_bextr_32: case Intrinsic::x86_bmi_bextr_32:
case Intrinsic::x86_bmi_bextr_64: case Intrinsic::x86_bmi_bextr_64:
case Intrinsic::x86_tbm_bextri_u32: case Intrinsic::x86_tbm_bextri_u32:
case Intrinsic::x86_tbm_bextri_u64: case Intrinsic::x86_tbm_bextri_u64:
▲ Show 20 Lines • Show All 473 Lines • ▼ Show 20 Lines if (auto *C = dyn_cast<ConstantInt>(II.getArgOperand(2))) {
unsigned Imm = C->getZExtValue(); unsigned Imm = C->getZExtValue();
bool MadeChange = false; bool MadeChange = false;
Value *Arg0 = II.getArgOperand(0); Value *Arg0 = II.getArgOperand(0);
Value *Arg1 = II.getArgOperand(1); Value *Arg1 = II.getArgOperand(1);
unsigned VWidth = unsigned VWidth =
cast<FixedVectorType>(Arg0->getType())->getNumElements(); cast<FixedVectorType>(Arg0->getType())->getNumElements();
APInt UndefElts1(VWidth, 0); APInt PoisonElts1(VWidth, 0);
APInt DemandedElts1 = APInt DemandedElts1 =
APInt::getSplat(VWidth, APInt(2, (Imm & 0x01) ? 2 : 1)); APInt::getSplat(VWidth, APInt(2, (Imm & 0x01) ? 2 : 1));
if (Value *V = if (Value *V =
IC.SimplifyDemandedVectorElts(Arg0, DemandedElts1, UndefElts1)) { IC.SimplifyDemandedVectorElts(Arg0, DemandedElts1, PoisonElts1)) {
IC.replaceOperand(II, 0, V); IC.replaceOperand(II, 0, V);
MadeChange = true; MadeChange = true;
} }
APInt UndefElts2(VWidth, 0); APInt PoisonElts2(VWidth, 0);
APInt DemandedElts2 = APInt DemandedElts2 =
APInt::getSplat(VWidth, APInt(2, (Imm & 0x10) ? 2 : 1)); APInt::getSplat(VWidth, APInt(2, (Imm & 0x10) ? 2 : 1));
if (Value *V = if (Value *V =
IC.SimplifyDemandedVectorElts(Arg1, DemandedElts2, UndefElts2)) { IC.SimplifyDemandedVectorElts(Arg1, DemandedElts2, PoisonElts2)) {
IC.replaceOperand(II, 1, V); IC.replaceOperand(II, 1, V);
MadeChange = true; MadeChange = true;
} }
// If either input elements are undef, the result is zero. // If either input elements are poison, the result is zero.
if (DemandedElts1.isSubsetOf(UndefElts1) || if (DemandedElts1.isSubsetOf(PoisonElts1) ||
DemandedElts2.isSubsetOf(UndefElts2)) { DemandedElts2.isSubsetOf(PoisonElts2)) {
return IC.replaceInstUsesWith(II, return IC.replaceInstUsesWith(II,
ConstantAggregateZero::get(II.getType())); ConstantAggregateZero::get(II.getType()));
} }
if (MadeChange) { if (MadeChange) {
return &II; return &II;
} }
} }
▲ Show 20 Lines • Show All 327 Lines • ▼ Show 20 Lines case Intrinsic::x86_avx2_pmovmskb: {
KnownBitsComputed = true; KnownBitsComputed = true;
break; break;
} }
} }
return std::nullopt; return std::nullopt;
} }
std::optional<Value *> X86TTIImpl::simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> X86TTIImpl::simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &PoisonElts,
APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
simplifyAndSetOp) const { simplifyAndSetOp) const {
unsigned VWidth = cast<FixedVectorType>(II.getType())->getNumElements(); unsigned VWidth = cast<FixedVectorType>(II.getType())->getNumElements();
switch (II.getIntrinsicID()) { switch (II.getIntrinsicID()) {
default: default:
break; break;
case Intrinsic::x86_xop_vfrcz_ss: case Intrinsic::x86_xop_vfrcz_ss:
case Intrinsic::x86_xop_vfrcz_sd: case Intrinsic::x86_xop_vfrcz_sd:
// The instructions for these intrinsics are speced to zero upper bits not // The instructions for these intrinsics are speced to zero upper bits not
// pass them through like other scalar intrinsics. So we shouldn't just // pass them through like other scalar intrinsics. So we shouldn't just
// use Arg0 if DemandedElts[0] is clear like we do for other intrinsics. // use Arg0 if DemandedElts[0] is clear like we do for other intrinsics.
// Instead we should return a zero vector. // Instead we should return a zero vector.
if (!DemandedElts[0]) { if (!DemandedElts[0]) {
IC.addToWorklist(&II); IC.addToWorklist(&II);
return ConstantAggregateZero::get(II.getType()); return ConstantAggregateZero::get(II.getType());
} }
// Only the lower element is used. // Only the lower element is used.
DemandedElts = 1; DemandedElts = 1;
simplifyAndSetOp(&II, 0, DemandedElts, UndefElts); simplifyAndSetOp(&II, 0, DemandedElts, PoisonElts);
// Only the lower element is undefined. The high elements are zero. // Only the lower element is undefined. The high elements are zero.
UndefElts = UndefElts[0]; PoisonElts = PoisonElts[0];
break; break;
// Unary scalar-as-vector operations that work column-wise. // Unary scalar-as-vector operations that work column-wise.
case Intrinsic::x86_sse_rcp_ss: case Intrinsic::x86_sse_rcp_ss:
case Intrinsic::x86_sse_rsqrt_ss: case Intrinsic::x86_sse_rsqrt_ss:
simplifyAndSetOp(&II, 0, DemandedElts, UndefElts); simplifyAndSetOp(&II, 0, DemandedElts, PoisonElts);
// If lowest element of a scalar op isn't used then use Arg0. // If lowest element of a scalar op isn't used then use Arg0.
if (!DemandedElts[0]) { if (!DemandedElts[0]) {
IC.addToWorklist(&II); IC.addToWorklist(&II);
return II.getArgOperand(0); return II.getArgOperand(0);
} }
// TODO: If only low elt lower SQRT to FSQRT (with rounding/exceptions // TODO: If only low elt lower SQRT to FSQRT (with rounding/exceptions
// checks). // checks).
break; break;
// Binary scalar-as-vector operations that work column-wise. The high // Binary scalar-as-vector operations that work column-wise. The high
// elements come from operand 0. The low element is a function of both // elements come from operand 0. The low element is a function of both
// operands. // operands.
case Intrinsic::x86_sse_min_ss: case Intrinsic::x86_sse_min_ss:
case Intrinsic::x86_sse_max_ss: case Intrinsic::x86_sse_max_ss:
case Intrinsic::x86_sse_cmp_ss: case Intrinsic::x86_sse_cmp_ss:
case Intrinsic::x86_sse2_min_sd: case Intrinsic::x86_sse2_min_sd:
case Intrinsic::x86_sse2_max_sd: case Intrinsic::x86_sse2_max_sd:
case Intrinsic::x86_sse2_cmp_sd: { case Intrinsic::x86_sse2_cmp_sd: {
simplifyAndSetOp(&II, 0, DemandedElts, UndefElts); simplifyAndSetOp(&II, 0, DemandedElts, PoisonElts);
// If lowest element of a scalar op isn't used then use Arg0. // If lowest element of a scalar op isn't used then use Arg0.
if (!DemandedElts[0]) { if (!DemandedElts[0]) {
IC.addToWorklist(&II); IC.addToWorklist(&II);
return II.getArgOperand(0); return II.getArgOperand(0);
} }
// Only lower element is used for operand 1. // Only lower element is used for operand 1.
DemandedElts = 1; DemandedElts = 1;
simplifyAndSetOp(&II, 1, DemandedElts, UndefElts2); simplifyAndSetOp(&II, 1, DemandedElts, PoisonElts2);
// Lower element is undefined if both lower elements are undefined. // Lower element is undefined if both lower elements are undefined.
// Consider things like undef&0. The result is known zero, not undef. // Consider things like undef&0. The result is known zero, not undef.
if (!UndefElts2[0]) if (!PoisonElts2[0])
UndefElts.clearBit(0); PoisonElts.clearBit(0);
break; break;
} }
// Binary scalar-as-vector operations that work column-wise. The high // Binary scalar-as-vector operations that work column-wise. The high
// elements come from operand 0 and the low element comes from operand 1. // elements come from operand 0 and the low element comes from operand 1.
case Intrinsic::x86_sse41_round_ss: case Intrinsic::x86_sse41_round_ss:
case Intrinsic::x86_sse41_round_sd: { case Intrinsic::x86_sse41_round_sd: {
// Don't use the low element of operand 0. // Don't use the low element of operand 0.
APInt DemandedElts2 = DemandedElts; APInt DemandedElts2 = DemandedElts;
DemandedElts2.clearBit(0); DemandedElts2.clearBit(0);
simplifyAndSetOp(&II, 0, DemandedElts2, UndefElts); simplifyAndSetOp(&II, 0, DemandedElts2, PoisonElts);
// If lowest element of a scalar op isn't used then use Arg0. // If lowest element of a scalar op isn't used then use Arg0.
if (!DemandedElts[0]) { if (!DemandedElts[0]) {
IC.addToWorklist(&II); IC.addToWorklist(&II);
return II.getArgOperand(0); return II.getArgOperand(0);
} }
// Only lower element is used for operand 1. // Only lower element is used for operand 1.
DemandedElts = 1; DemandedElts = 1;
simplifyAndSetOp(&II, 1, DemandedElts, UndefElts2); simplifyAndSetOp(&II, 1, DemandedElts, PoisonElts2);
// Take the high undef elements from operand 0 and take the lower element // Take the high poison elements from operand 0 and take the lower element
// from operand 1. // from operand 1.
UndefElts.clearBit(0); PoisonElts.clearBit(0);
UndefElts |= UndefElts2[0]; PoisonElts |= PoisonElts2[0];
break; break;
} }
// Three input scalar-as-vector operations that work column-wise. The high // Three input scalar-as-vector operations that work column-wise. The high
// elements come from operand 0 and the low element is a function of all // elements come from operand 0 and the low element is a function of all
// three inputs. // three inputs.
case Intrinsic::x86_avx512_mask_add_ss_round: case Intrinsic::x86_avx512_mask_add_ss_round:
case Intrinsic::x86_avx512_mask_div_ss_round: case Intrinsic::x86_avx512_mask_div_ss_round:
case Intrinsic::x86_avx512_mask_mul_ss_round: case Intrinsic::x86_avx512_mask_mul_ss_round:
case Intrinsic::x86_avx512_mask_sub_ss_round: case Intrinsic::x86_avx512_mask_sub_ss_round:
case Intrinsic::x86_avx512_mask_max_ss_round: case Intrinsic::x86_avx512_mask_max_ss_round:
case Intrinsic::x86_avx512_mask_min_ss_round: case Intrinsic::x86_avx512_mask_min_ss_round:
case Intrinsic::x86_avx512_mask_add_sd_round: case Intrinsic::x86_avx512_mask_add_sd_round:
case Intrinsic::x86_avx512_mask_div_sd_round: case Intrinsic::x86_avx512_mask_div_sd_round:
case Intrinsic::x86_avx512_mask_mul_sd_round: case Intrinsic::x86_avx512_mask_mul_sd_round:
case Intrinsic::x86_avx512_mask_sub_sd_round: case Intrinsic::x86_avx512_mask_sub_sd_round:
case Intrinsic::x86_avx512_mask_max_sd_round: case Intrinsic::x86_avx512_mask_max_sd_round:
case Intrinsic::x86_avx512_mask_min_sd_round: case Intrinsic::x86_avx512_mask_min_sd_round:
simplifyAndSetOp(&II, 0, DemandedElts, UndefElts); simplifyAndSetOp(&II, 0, DemandedElts, PoisonElts);
// If lowest element of a scalar op isn't used then use Arg0. // If lowest element of a scalar op isn't used then use Arg0.
if (!DemandedElts[0]) { if (!DemandedElts[0]) {
IC.addToWorklist(&II); IC.addToWorklist(&II);
return II.getArgOperand(0); return II.getArgOperand(0);
} }
// Only lower element is used for operand 1 and 2. // Only lower element is used for operand 1 and 2.
DemandedElts = 1; DemandedElts = 1;
simplifyAndSetOp(&II, 1, DemandedElts, UndefElts2); simplifyAndSetOp(&II, 1, DemandedElts, PoisonElts2);
simplifyAndSetOp(&II, 2, DemandedElts, UndefElts3); simplifyAndSetOp(&II, 2, DemandedElts, PoisonElts3);
// Lower element is undefined if all three lower elements are undefined. // Lower element is undefined if all three lower elements are undefined.
// Consider things like undef&0. The result is known zero, not undef. // Consider things like undef&0. The result is known zero, not undef.
if (!UndefElts2[0] || !UndefElts3[0]) // TODO : If either is poison then the result is poison
UndefElts.clearBit(0); if (!PoisonElts2[0] || !PoisonElts3[0])
PoisonElts.clearBit(0);
break; break;
// TODO: Add fmaddsub support? // TODO: Add fmaddsub support?
case Intrinsic::x86_sse3_addsub_pd: case Intrinsic::x86_sse3_addsub_pd:
case Intrinsic::x86_sse3_addsub_ps: case Intrinsic::x86_sse3_addsub_ps:
case Intrinsic::x86_avx_addsub_pd_256: case Intrinsic::x86_avx_addsub_pd_256:
case Intrinsic::x86_avx_addsub_ps_256: { case Intrinsic::x86_avx_addsub_ps_256: {
// If none of the even or none of the odd lanes are required, turn this // If none of the even or none of the odd lanes are required, turn this
// into a generic FP math instruction. // into a generic FP math instruction.
APInt SubMask = APInt::getSplat(VWidth, APInt(2, 0x1)); APInt SubMask = APInt::getSplat(VWidth, APInt(2, 0x1));
APInt AddMask = APInt::getSplat(VWidth, APInt(2, 0x2)); APInt AddMask = APInt::getSplat(VWidth, APInt(2, 0x2));
bool IsSubOnly = DemandedElts.isSubsetOf(SubMask); bool IsSubOnly = DemandedElts.isSubsetOf(SubMask);
bool IsAddOnly = DemandedElts.isSubsetOf(AddMask); bool IsAddOnly = DemandedElts.isSubsetOf(AddMask);
if (IsSubOnly || IsAddOnly) { if (IsSubOnly || IsAddOnly) {
assert((IsSubOnly ^ IsAddOnly) && "Can't be both add-only and sub-only"); assert((IsSubOnly ^ IsAddOnly) && "Can't be both add-only and sub-only");
IRBuilderBase::InsertPointGuard Guard(IC.Builder); IRBuilderBase::InsertPointGuard Guard(IC.Builder);
IC.Builder.SetInsertPoint(&II); IC.Builder.SetInsertPoint(&II);
Value *Arg0 = II.getArgOperand(0), *Arg1 = II.getArgOperand(1); Value *Arg0 = II.getArgOperand(0), *Arg1 = II.getArgOperand(1);
return IC.Builder.CreateBinOp( return IC.Builder.CreateBinOp(
IsSubOnly ? Instruction::FSub : Instruction::FAdd, Arg0, Arg1); IsSubOnly ? Instruction::FSub : Instruction::FAdd, Arg0, Arg1);
} }
simplifyAndSetOp(&II, 0, DemandedElts, UndefElts); simplifyAndSetOp(&II, 0, DemandedElts, PoisonElts);
simplifyAndSetOp(&II, 1, DemandedElts, UndefElts2); simplifyAndSetOp(&II, 1, DemandedElts, PoisonElts2);
UndefElts &= UndefElts2; PoisonElts &= PoisonElts2;
break; break;
} }
// General per-element vector operations. // General per-element vector operations.
case Intrinsic::x86_avx2_psllv_d: case Intrinsic::x86_avx2_psllv_d:
case Intrinsic::x86_avx2_psllv_d_256: case Intrinsic::x86_avx2_psllv_d_256:
case Intrinsic::x86_avx2_psllv_q: case Intrinsic::x86_avx2_psllv_q:
case Intrinsic::x86_avx2_psllv_q_256: case Intrinsic::x86_avx2_psllv_q_256:
case Intrinsic::x86_avx2_psrlv_d: case Intrinsic::x86_avx2_psrlv_d:
case Intrinsic::x86_avx2_psrlv_d_256: case Intrinsic::x86_avx2_psrlv_d_256:
case Intrinsic::x86_avx2_psrlv_q: case Intrinsic::x86_avx2_psrlv_q:
case Intrinsic::x86_avx2_psrlv_q_256: case Intrinsic::x86_avx2_psrlv_q_256:
case Intrinsic::x86_avx2_psrav_d: case Intrinsic::x86_avx2_psrav_d:
case Intrinsic::x86_avx2_psrav_d_256: { case Intrinsic::x86_avx2_psrav_d_256: {
simplifyAndSetOp(&II, 0, DemandedElts, UndefElts); simplifyAndSetOp(&II, 0, DemandedElts, PoisonElts);
simplifyAndSetOp(&II, 1, DemandedElts, UndefElts2); simplifyAndSetOp(&II, 1, DemandedElts, PoisonElts2);
UndefElts &= UndefElts2; PoisonElts &= PoisonElts2;
break; break;
} }
case Intrinsic::x86_sse2_packssdw_128: case Intrinsic::x86_sse2_packssdw_128:
case Intrinsic::x86_sse2_packsswb_128: case Intrinsic::x86_sse2_packsswb_128:
case Intrinsic::x86_sse2_packuswb_128: case Intrinsic::x86_sse2_packuswb_128:
case Intrinsic::x86_sse41_packusdw: case Intrinsic::x86_sse41_packusdw:
case Intrinsic::x86_avx2_packssdw: case Intrinsic::x86_avx2_packssdw:
Show All 23 Lines for (int OpNum = 0; OpNum != 2; ++OpNum) {
for (unsigned Elt = 0; Elt != InnerVWidthPerLane; ++Elt) { for (unsigned Elt = 0; Elt != InnerVWidthPerLane; ++Elt) {
unsigned Idx = LaneIdx + Elt + InnerVWidthPerLane * OpNum; unsigned Idx = LaneIdx + Elt + InnerVWidthPerLane * OpNum;
if (DemandedElts[Idx]) if (DemandedElts[Idx])
OpDemandedElts.setBit((Lane * InnerVWidthPerLane) + Elt); OpDemandedElts.setBit((Lane * InnerVWidthPerLane) + Elt);
} }
} }
// Demand elements from the operand. // Demand elements from the operand.
APInt OpUndefElts(InnerVWidth, 0); APInt OpPoisonElts(InnerVWidth, 0);
simplifyAndSetOp(&II, OpNum, OpDemandedElts, OpUndefElts); simplifyAndSetOp(&II, OpNum, OpDemandedElts, OpPoisonElts);
// Pack the operand's UNDEF elements, one lane at a time. // Pack the operand's UNDEF elements, one lane at a time.
OpUndefElts = OpUndefElts.zext(VWidth); OpPoisonElts = OpPoisonElts.zext(VWidth);
for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
APInt LaneElts = OpUndefElts.lshr(InnerVWidthPerLane * Lane); APInt LaneElts = OpPoisonElts.lshr(InnerVWidthPerLane * Lane);
LaneElts = LaneElts.getLoBits(InnerVWidthPerLane); LaneElts = LaneElts.getLoBits(InnerVWidthPerLane);
LaneElts <<= InnerVWidthPerLane * (2 * Lane + OpNum); LaneElts <<= InnerVWidthPerLane * (2 * Lane + OpNum);
UndefElts |= LaneElts; PoisonElts |= LaneElts;
} }
} }
break; break;
} }
// PSHUFB // PSHUFB
case Intrinsic::x86_ssse3_pshuf_b_128: case Intrinsic::x86_ssse3_pshuf_b_128:
case Intrinsic::x86_avx2_pshuf_b: case Intrinsic::x86_avx2_pshuf_b:
case Intrinsic::x86_avx512_pshuf_b_512: case Intrinsic::x86_avx512_pshuf_b_512:
// PERMILVAR // PERMILVAR
case Intrinsic::x86_avx_vpermilvar_ps: case Intrinsic::x86_avx_vpermilvar_ps:
case Intrinsic::x86_avx_vpermilvar_ps_256: case Intrinsic::x86_avx_vpermilvar_ps_256:
case Intrinsic::x86_avx512_vpermilvar_ps_512: case Intrinsic::x86_avx512_vpermilvar_ps_512:
case Intrinsic::x86_avx_vpermilvar_pd: case Intrinsic::x86_avx_vpermilvar_pd:
case Intrinsic::x86_avx_vpermilvar_pd_256: case Intrinsic::x86_avx_vpermilvar_pd_256:
case Intrinsic::x86_avx512_vpermilvar_pd_512: case Intrinsic::x86_avx512_vpermilvar_pd_512:
// PERMV // PERMV
case Intrinsic::x86_avx2_permd: case Intrinsic::x86_avx2_permd:
case Intrinsic::x86_avx2_permps: { case Intrinsic::x86_avx2_permps: {
simplifyAndSetOp(&II, 1, DemandedElts, UndefElts); simplifyAndSetOp(&II, 1, DemandedElts, PoisonElts);
break; break;
} }
// SSE4A instructions leave the upper 64-bits of the 128-bit result // SSE4A instructions leave the upper 64-bits of the 128-bit result
// in an undefined state. // in an undefined state.
case Intrinsic::x86_sse4a_extrq: case Intrinsic::x86_sse4a_extrq:
case Intrinsic::x86_sse4a_extrqi: case Intrinsic::x86_sse4a_extrqi:
case Intrinsic::x86_sse4a_insertq: case Intrinsic::x86_sse4a_insertq:
case Intrinsic::x86_sse4a_insertqi: case Intrinsic::x86_sse4a_insertqi:
UndefElts.setHighBits(VWidth / 2); // Cannot use poison too undefined.
nlopesUnsubmitted
Not Done
ReplyInline Actions

this change doesn't look correct. The bits are undefined, doesn't seem like you can use poison here.

nlopes: this change doesn't look correct. The bits are undefined, doesn't seem like you can use poison…
ManuelJBritoAuthorUnsubmitted
Done
ReplyInline Actions

Thanks, I'll fix it. This will cause some regressions in the cases where only the upper half is demanded.
Eventually we could fold those cases to freeze(poison).

ManuelJBrito: Thanks, I'll fix it. This will cause some regressions in the cases where only the upper half is…
break; break;
} }
return std::nullopt; return std::nullopt;
} }

llvm/lib/Target/X86/X86TargetTransformInfo.h

Show First 20 Lines • Show All 187 Lines • ▼ Show 20 Linespublic:
std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC, std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const; IntrinsicInst &II) const;
std::optional<Value *> std::optional<Value *>
simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II, simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
APInt DemandedMask, KnownBits &Known, APInt DemandedMask, KnownBits &Known,
bool &KnownBitsComputed) const; bool &KnownBitsComputed) const;
std::optional<Value *> simplifyDemandedVectorEltsIntrinsic( std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts,
APInt &UndefElts2, APInt &UndefElts3, APInt &PoisonElts, APInt &PoisonElts2, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) const; SimplifyAndSetOp) const;
unsigned getAtomicMemIntrinsicMaxElementSize() const; unsigned getAtomicMemIntrinsicMaxElementSize() const;
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
TTI::TargetCostKind CostKind); TTI::TargetCostKind CostKind);
▲ Show 20 Lines • Show All 100 Lines • Show Last 20 Lines

llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp

Show First 20 Lines • Show All 367 Lines • ▼ Show 20 Lines if (ConstMask->isAllOnesValue()) {
return S; return S;
} }
if (isa<ScalableVectorType>(ConstMask->getType())) if (isa<ScalableVectorType>(ConstMask->getType()))
return nullptr; return nullptr;
// Use masked off lanes to simplify operands via SimplifyDemandedVectorElts // Use masked off lanes to simplify operands via SimplifyDemandedVectorElts
APInt DemandedElts = possiblyDemandedEltsInMask(ConstMask); APInt DemandedElts = possiblyDemandedEltsInMask(ConstMask);
APInt UndefElts(DemandedElts.getBitWidth(), 0); APInt PoisonElts(DemandedElts.getBitWidth(), 0);
if (Value *V = if (Value *V =
SimplifyDemandedVectorElts(II.getOperand(0), DemandedElts, UndefElts)) SimplifyDemandedVectorElts(II.getOperand(0), DemandedElts, PoisonElts))
return replaceOperand(II, 0, V); return replaceOperand(II, 0, V);
return nullptr; return nullptr;
} }
// TODO, Obvious Missing Transforms: // TODO, Obvious Missing Transforms:
// * Single constant active lane load -> load // * Single constant active lane load -> load
// * Dereferenceable address & few lanes -> scalarize speculative load/selects // * Dereferenceable address & few lanes -> scalarize speculative load/selects
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines if (ConstMask->isAllOnesValue()) {
return S; return S;
} }
} }
if (isa<ScalableVectorType>(ConstMask->getType())) if (isa<ScalableVectorType>(ConstMask->getType()))
return nullptr; return nullptr;
// Use masked off lanes to simplify operands via SimplifyDemandedVectorElts // Use masked off lanes to simplify operands via SimplifyDemandedVectorElts
APInt DemandedElts = possiblyDemandedEltsInMask(ConstMask); APInt DemandedElts = possiblyDemandedEltsInMask(ConstMask);
APInt UndefElts(DemandedElts.getBitWidth(), 0); APInt PoisonElts(DemandedElts.getBitWidth(), 0);
if (Value *V = if (Value *V =
SimplifyDemandedVectorElts(II.getOperand(0), DemandedElts, UndefElts)) SimplifyDemandedVectorElts(II.getOperand(0), DemandedElts, PoisonElts))
return replaceOperand(II, 0, V); return replaceOperand(II, 0, V);
if (Value *V = if (Value *V =
SimplifyDemandedVectorElts(II.getOperand(1), DemandedElts, UndefElts)) SimplifyDemandedVectorElts(II.getOperand(1), DemandedElts, PoisonElts))
return replaceOperand(II, 1, V); return replaceOperand(II, 1, V);
return nullptr; return nullptr;
} }
/// This function transforms launder.invariant.group and strip.invariant.group /// This function transforms launder.invariant.group and strip.invariant.group
/// like: /// like:
/// launder(launder(%x)) -> launder(%x) (the result is not the argument) /// launder(launder(%x)) -> launder(%x) (the result is not the argument)
▲ Show 20 Lines • Show All 987 Lines • ▼ Show 20 Lines if (auto *MI = dyn_cast<AnyMemIntrinsic>(II)) {
if (Changed) return II; if (Changed) return II;
} }
// For fixed width vector result intrinsics, use the generic demanded vector // For fixed width vector result intrinsics, use the generic demanded vector
// support. // support.
if (auto *IIFVTy = dyn_cast<FixedVectorType>(II->getType())) { if (auto *IIFVTy = dyn_cast<FixedVectorType>(II->getType())) {
auto VWidth = IIFVTy->getNumElements(); auto VWidth = IIFVTy->getNumElements();
APInt UndefElts(VWidth, 0); APInt PoisonElts(VWidth, 0);
APInt AllOnesEltMask(APInt::getAllOnes(VWidth)); APInt AllOnesEltMask(APInt::getAllOnes(VWidth));
if (Value *V = SimplifyDemandedVectorElts(II, AllOnesEltMask, UndefElts)) { if (Value *V = SimplifyDemandedVectorElts(II, AllOnesEltMask, PoisonElts)) {
if (V != II) if (V != II)
return replaceInstUsesWith(*II, V); return replaceInstUsesWith(*II, V);
return II; return II;
} }
} }
if (II->isCommutative()) { if (II->isCommutative()) {
if (CallInst *NewCall = canonicalizeConstantArg0ToArg1(CI)) if (CallInst *NewCall = canonicalizeConstantArg0ToArg1(CI))
▲ Show 20 Lines • Show All 2,589 Lines • Show Last 20 Lines

llvm/lib/Transforms/InstCombine/InstCombineInternal.h

Show First 20 Lines • Show All 490 Lines • ▼ Show 20 Lines Value *simplifyShrShlDemandedBits(
Instruction *Shr, const APInt &ShrOp1, Instruction *Shl, Instruction *Shr, const APInt &ShrOp1, Instruction *Shl,
const APInt &ShlOp1, const APInt &DemandedMask, KnownBits &Known); const APInt &ShlOp1, const APInt &DemandedMask, KnownBits &Known);
/// Tries to simplify operands to an integer instruction based on its /// Tries to simplify operands to an integer instruction based on its
/// demanded bits. /// demanded bits.
bool SimplifyDemandedInstructionBits(Instruction &Inst); bool SimplifyDemandedInstructionBits(Instruction &Inst);
Value *SimplifyDemandedVectorElts(Value *V, APInt DemandedElts, Value *SimplifyDemandedVectorElts(Value *V, APInt DemandedElts,
APInt &UndefElts, unsigned Depth = 0, APInt &PoisonElts, unsigned Depth = 0,
bool AllowMultipleUsers = false) override; bool AllowMultipleUsers = false) override;
/// Canonicalize the position of binops relative to shufflevector. /// Canonicalize the position of binops relative to shufflevector.
Instruction *foldVectorBinop(BinaryOperator &Inst); Instruction *foldVectorBinop(BinaryOperator &Inst);
Instruction *foldVectorSelect(SelectInst &Sel); Instruction *foldVectorSelect(SelectInst &Sel);
Instruction *foldSelectShuffle(ShuffleVectorInst &Shuf); Instruction *foldSelectShuffle(ShuffleVectorInst &Shuf);
/// Given a binary operator, cast instruction, or select which has a PHI node /// Given a binary operator, cast instruction, or select which has a PHI node
▲ Show 20 Lines • Show All 215 Lines • Show Last 20 Lines

llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp

Show First 20 Lines • Show All 2,410 Lines • ▼ Show 20 Lines else if (isSplatValue(TVal) && match(FVal, m_VecReverse(m_Value(Y))) &&
return createSelReverse(C, TVal, Y); return createSelReverse(C, TVal, Y);
} }
auto *VecTy = dyn_cast<FixedVectorType>(Sel.getType()); auto *VecTy = dyn_cast<FixedVectorType>(Sel.getType());
if (!VecTy) if (!VecTy)
return nullptr; return nullptr;
unsigned NumElts = VecTy->getNumElements(); unsigned NumElts = VecTy->getNumElements();
APInt UndefElts(NumElts, 0); APInt PoisonElts(NumElts, 0);
APInt AllOnesEltMask(APInt::getAllOnes(NumElts)); APInt AllOnesEltMask(APInt::getAllOnes(NumElts));
if (Value *V = SimplifyDemandedVectorElts(&Sel, AllOnesEltMask, UndefElts)) { if (Value *V = SimplifyDemandedVectorElts(&Sel, AllOnesEltMask, PoisonElts)) {
if (V != &Sel) if (V != &Sel)
return replaceInstUsesWith(Sel, V); return replaceInstUsesWith(Sel, V);
return &Sel; return &Sel;
} }
// A select of a "select shuffle" with a common operand can be rearranged // A select of a "select shuffle" with a common operand can be rearranged
// to select followed by "select shuffle". Because of poison, this only works // to select followed by "select shuffle". Because of poison, this only works
// in the case of a shuffle with no undefined mask elements. // in the case of a shuffle with no undefined mask elements.
▲ Show 20 Lines • Show All 1,229 Lines • Show Last 20 Lines

llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp

Show First 20 Lines • Show All 1,218 Lines • ▼ Show 20 Lines if ((BitMask1 & DemandedMask) == (BitMask2 & DemandedMask)) {
return InsertNewInstWith(New, *Shl); return InsertNewInstWith(New, *Shl);
} }
return nullptr; return nullptr;
} }
/// The specified value produces a vector with any number of elements. /// The specified value produces a vector with any number of elements.
/// This method analyzes which elements of the operand are undef or poison and /// This method analyzes which elements of the operand are poison and
/// returns that information in UndefElts. /// returns that information in PoisonElts.
/// ///
/// DemandedElts contains the set of elements that are actually used by the /// DemandedElts contains the set of elements that are actually used by the
/// caller, and by default (AllowMultipleUsers equals false) the value is /// caller, and by default (AllowMultipleUsers equals false) the value is
/// simplified only if it has a single caller. If AllowMultipleUsers is set /// simplified only if it has a single caller. If AllowMultipleUsers is set
/// to true, DemandedElts refers to the union of sets of elements that are /// to true, DemandedElts refers to the union of sets of elements that are
/// used by all callers. /// used by all callers.
/// ///
/// If the information about demanded elements can be used to simplify the /// If the information about demanded elements can be used to simplify the
/// operation, the operation is simplified, then the resultant value is /// operation, the operation is simplified, then the resultant value is
/// returned. This returns null if no change was made. /// returned. This returns null if no change was made.
Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V, Value *InstCombinerImpl::SimplifyDemandedVectorElts(Value *V,
APInt DemandedElts, APInt DemandedElts,
APInt &UndefElts, APInt &PoisonElts,
unsigned Depth, unsigned Depth,
bool AllowMultipleUsers) { bool AllowMultipleUsers) {
// Cannot analyze scalable type. The number of vector elements is not a // Cannot analyze scalable type. The number of vector elements is not a
// compile-time constant. // compile-time constant.
if (isa<ScalableVectorType>(V->getType())) if (isa<ScalableVectorType>(V->getType()))
return nullptr; return nullptr;
unsigned VWidth = cast<FixedVectorType>(V->getType())->getNumElements(); unsigned VWidth = cast<FixedVectorType>(V->getType())->getNumElements();
APInt EltMask(APInt::getAllOnes(VWidth)); APInt EltMask(APInt::getAllOnes(VWidth));
assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!"); assert((DemandedElts & ~EltMask) == 0 && "Invalid DemandedElts!");
if (match(V, m_Undef())) { if (match(V, m_Poison())) {
// If the entire vector is undef or poison, just return this info. // If the entire vector is poison, just return this info.
UndefElts = EltMask; PoisonElts = EltMask;
return nullptr; return nullptr;
} }
if (DemandedElts.isZero()) { // If nothing is demanded, provide poison. if (DemandedElts.isZero()) { // If nothing is demanded, provide poison.
UndefElts = EltMask; PoisonElts = EltMask;
return PoisonValue::get(V->getType()); return PoisonValue::get(V->getType());
} }
UndefElts = 0; PoisonElts = 0;
if (auto *C = dyn_cast<Constant>(V)) { if (auto *C = dyn_cast<Constant>(V)) {
// Check if this is identity. If so, return 0 since we are not simplifying // Check if this is identity. If so, return 0 since we are not simplifying
// anything. // anything.
if (DemandedElts.isAllOnes()) if (DemandedElts.isAllOnes())
return nullptr; return nullptr;
Type *EltTy = cast<VectorType>(V->getType())->getElementType(); Type *EltTy = cast<VectorType>(V->getType())->getElementType();
Constant *Poison = PoisonValue::get(EltTy); Constant *Poison = PoisonValue::get(EltTy);
SmallVector<Constant*, 16> Elts; SmallVector<Constant*, 16> Elts;
for (unsigned i = 0; i != VWidth; ++i) { for (unsigned i = 0; i != VWidth; ++i) {
if (!DemandedElts[i]) { // If not demanded, set to poison. if (!DemandedElts[i]) { // If not demanded, set to poison.
Elts.push_back(Poison); Elts.push_back(Poison);
UndefElts.setBit(i); PoisonElts.setBit(i);
continue; continue;
} }
Constant *Elt = C->getAggregateElement(i); Constant *Elt = C->getAggregateElement(i);
if (!Elt) return nullptr; if (!Elt) return nullptr;
Elts.push_back(Elt); Elts.push_back(Elt);
if (isa<UndefValue>(Elt)) // Already undef or poison. if (isa<PoisonValue>(Elt)) // Already poison.
UndefElts.setBit(i); PoisonElts.setBit(i);
} }
// If we changed the constant, return it. // If we changed the constant, return it.
Constant *NewCV = ConstantVector::get(Elts); Constant *NewCV = ConstantVector::get(Elts);
return NewCV != C ? NewCV : nullptr; return NewCV != C ? NewCV : nullptr;
} }
// Limit search depth. // Limit search depth.
if (Depth == 10) if (Depth == 10)
return nullptr; return nullptr;
if (!AllowMultipleUsers) { if (!AllowMultipleUsers) {
// If multiple users are using the root value, proceed with // If multiple users are using the root value, proceed with
// simplification conservatively assuming that all elements // simplification conservatively assuming that all elements
// are needed. // are needed.
if (!V->hasOneUse()) { if (!V->hasOneUse()) {
// Quit if we find multiple users of a non-root value though. // Quit if we find multiple users of a non-root value though.
// They'll be handled when it's their turn to be visited by // They'll be handled when it's their turn to be visited by
// the main instcombine process. // the main instcombine process.
if (Depth != 0) if (Depth != 0)
// TODO: Just compute the UndefElts information recursively. // TODO: Just compute the PoisonElts information recursively.
return nullptr; return nullptr;
// Conservatively assume that all elements are needed. // Conservatively assume that all elements are needed.
DemandedElts = EltMask; DemandedElts = EltMask;
} }
} }
Instruction *I = dyn_cast<Instruction>(V); Instruction *I = dyn_cast<Instruction>(V);
if (!I) return nullptr; // Only analyze instructions. if (!I) return nullptr; // Only analyze instructions.
bool MadeChange = false; bool MadeChange = false;
auto simplifyAndSetOp = [&](Instruction *Inst, unsigned OpNum, auto simplifyAndSetOp = [&](Instruction *Inst, unsigned OpNum,
APInt Demanded, APInt &Undef) { APInt Demanded, APInt &Poison) {
auto *II = dyn_cast<IntrinsicInst>(Inst); auto *II = dyn_cast<IntrinsicInst>(Inst);
Value *Op = II ? II->getArgOperand(OpNum) : Inst->getOperand(OpNum); Value *Op = II ? II->getArgOperand(OpNum) : Inst->getOperand(OpNum);
if (Value *V = SimplifyDemandedVectorElts(Op, Demanded, Undef, Depth + 1)) { if (Value *V = SimplifyDemandedVectorElts(Op, Demanded, Poison, Depth + 1)) {
replaceOperand(*Inst, OpNum, V); replaceOperand(*Inst, OpNum, V);
MadeChange = true; MadeChange = true;
} }
}; };
APInt UndefElts2(VWidth, 0); APInt PoisonElts2(VWidth, 0);
APInt UndefElts3(VWidth, 0); APInt PoisonElts3(VWidth, 0);
switch (I->getOpcode()) { switch (I->getOpcode()) {
default: break; default: break;
case Instruction::GetElementPtr: { case Instruction::GetElementPtr: {
// The LangRef requires that struct geps have all constant indices. As // The LangRef requires that struct geps have all constant indices. As
// such, we can't convert any operand to partial undef. // such, we can't convert any operand to partial undef.
auto mayIndexStructType = [](GetElementPtrInst &GEP) { auto mayIndexStructType = [](GetElementPtrInst &GEP) {
for (auto I = gep_type_begin(GEP), E = gep_type_end(GEP); for (auto I = gep_type_begin(GEP), E = gep_type_end(GEP);
I != E; I++) I != E; I++)
if (I.isStruct()) if (I.isStruct())
return true; return true;
return false; return false;
}; };
if (mayIndexStructType(cast<GetElementPtrInst>(*I))) if (mayIndexStructType(cast<GetElementPtrInst>(*I)))
break; break;
// Conservatively track the demanded elements back through any vector // Conservatively track the demanded elements back through any vector
// operands we may have. We know there must be at least one, or we // operands we may have. We know there must be at least one, or we
// wouldn't have a vector result to get here. Note that we intentionally // wouldn't have a vector result to get here. Note that we intentionally
// merge the undef bits here since gepping with either an poison base or // merge the poison bits here since gepping with either an poison base or
// index results in poison. // index results in poison.
for (unsigned i = 0; i < I->getNumOperands(); i++) { for (unsigned i = 0; i < I->getNumOperands(); i++) {
if (i == 0 ? match(I->getOperand(i), m_Undef()) if (match(I->getOperand(i), m_Poison())) {
: match(I->getOperand(i), m_Poison())) { // If the entire vector is poison, just return this info.
// If the entire vector is undefined, just return this info. PoisonElts = EltMask;
UndefElts = EltMask;
return nullptr; return nullptr;
} }
if (I->getOperand(i)->getType()->isVectorTy()) { if (I->getOperand(i)->getType()->isVectorTy()) {
APInt UndefEltsOp(VWidth, 0); APInt PoisonEltsOp(VWidth, 0);
simplifyAndSetOp(I, i, DemandedElts, UndefEltsOp); simplifyAndSetOp(I, i, DemandedElts, PoisonEltsOp);
// gep(x, undef) is not undef, so skip considering idx ops here PoisonElts |= PoisonEltsOp;
// Note that we could propagate poison, but we can't distinguish between
// undef & poison bits ATM
if (i == 0)
UndefElts |= UndefEltsOp;
} }
} }
break; break;
} }
case Instruction::InsertElement: { case Instruction::InsertElement: {
// If this is a variable index, we don't know which element it overwrites. // If this is a variable index, we don't know which element it overwrites.
// demand exactly the same input as we produce. // demand exactly the same input as we produce.
ConstantInt *Idx = dyn_cast<ConstantInt>(I->getOperand(2)); ConstantInt *Idx = dyn_cast<ConstantInt>(I->getOperand(2));
if (!Idx) { if (!Idx) {
// Note that we can't propagate undef elt info, because we don't know // Note that we can't propagate poison elt info, because we don't know
// which elt is getting updated. // which elt is getting updated.
simplifyAndSetOp(I, 0, DemandedElts, UndefElts2); simplifyAndSetOp(I, 0, DemandedElts, PoisonElts2);
break; break;
} }
// The element inserted overwrites whatever was there, so the input demanded // The element inserted overwrites whatever was there, so the input demanded
// set is simpler than the output set. // set is simpler than the output set.
unsigned IdxNo = Idx->getZExtValue(); unsigned IdxNo = Idx->getZExtValue();
APInt PreInsertDemandedElts = DemandedElts; APInt PreInsertDemandedElts = DemandedElts;
if (IdxNo < VWidth) if (IdxNo < VWidth)
PreInsertDemandedElts.clearBit(IdxNo); PreInsertDemandedElts.clearBit(IdxNo);
// If we only demand the element that is being inserted and that element // If we only demand the element that is being inserted and that element
// was extracted from the same index in another vector with the same type, // was extracted from the same index in another vector with the same type,
// replace this insert with that other vector. // replace this insert with that other vector.
// Note: This is attempted before the call to simplifyAndSetOp because that // Note: This is attempted before the call to simplifyAndSetOp because that
// may change UndefElts to a value that does not match with Vec. // may change PoisonElts to a value that does not match with Vec.
Value *Vec; Value *Vec;
if (PreInsertDemandedElts == 0 && if (PreInsertDemandedElts == 0 &&
match(I->getOperand(1), match(I->getOperand(1),
m_ExtractElt(m_Value(Vec), m_SpecificInt(IdxNo))) && m_ExtractElt(m_Value(Vec), m_SpecificInt(IdxNo))) &&
Vec->getType() == I->getType()) { Vec->getType() == I->getType()) {
return Vec; return Vec;
} }
simplifyAndSetOp(I, 0, PreInsertDemandedElts, UndefElts); simplifyAndSetOp(I, 0, PreInsertDemandedElts, PoisonElts);
// If this is inserting an element that isn't demanded, remove this // If this is inserting an element that isn't demanded, remove this
// insertelement. // insertelement.
if (IdxNo >= VWidth || !DemandedElts[IdxNo]) { if (IdxNo >= VWidth || !DemandedElts[IdxNo]) {
Worklist.push(I); Worklist.push(I);
return I->getOperand(0); return I->getOperand(0);
} }
// The inserted element is defined. // The inserted element is defined.
UndefElts.clearBit(IdxNo); PoisonElts.clearBit(IdxNo);
break; break;
} }
case Instruction::ShuffleVector: { case Instruction::ShuffleVector: {
auto *Shuffle = cast<ShuffleVectorInst>(I); auto *Shuffle = cast<ShuffleVectorInst>(I);
assert(Shuffle->getOperand(0)->getType() == assert(Shuffle->getOperand(0)->getType() ==
Shuffle->getOperand(1)->getType() && Shuffle->getOperand(1)->getType() &&
"Expected shuffle operands to have same type"); "Expected shuffle operands to have same type");
unsigned OpWidth = cast<FixedVectorType>(Shuffle->getOperand(0)->getType()) unsigned OpWidth = cast<FixedVectorType>(Shuffle->getOperand(0)->getType())
->getNumElements(); ->getNumElements();
// Handle trivial case of a splat. Only check the first element of LHS // Handle trivial case of a splat. Only check the first element of LHS
// operand. // operand.
if (all_of(Shuffle->getShuffleMask(), [](int Elt) { return Elt == 0; }) && if (all_of(Shuffle->getShuffleMask(), [](int Elt) { return Elt == 0; }) &&
DemandedElts.isAllOnes()) { DemandedElts.isAllOnes()) {
if (!match(I->getOperand(1), m_Undef())) { if (!match(I->getOperand(1), m_Undef())) {
I->setOperand(1, PoisonValue::get(I->getOperand(1)->getType())); I->setOperand(1, PoisonValue::get(I->getOperand(1)->getType()));
MadeChange = true; MadeChange = true;
} }
APInt LeftDemanded(OpWidth, 1); APInt LeftDemanded(OpWidth, 1);
APInt LHSUndefElts(OpWidth, 0); APInt LHSPoisonElts(OpWidth, 0);
simplifyAndSetOp(I, 0, LeftDemanded, LHSUndefElts); simplifyAndSetOp(I, 0, LeftDemanded, LHSPoisonElts);
if (LHSUndefElts[0]) if (LHSPoisonElts[0])
UndefElts = EltMask; PoisonElts = EltMask;
else else
UndefElts.clearAllBits(); PoisonElts.clearAllBits();
break; break;
} }
APInt LeftDemanded(OpWidth, 0), RightDemanded(OpWidth, 0); APInt LeftDemanded(OpWidth, 0), RightDemanded(OpWidth, 0);
for (unsigned i = 0; i < VWidth; i++) { for (unsigned i = 0; i < VWidth; i++) {
if (DemandedElts[i]) { if (DemandedElts[i]) {
unsigned MaskVal = Shuffle->getMaskValue(i); unsigned MaskVal = Shuffle->getMaskValue(i);
if (MaskVal != -1u) { if (MaskVal != -1u) {
assert(MaskVal < OpWidth * 2 && assert(MaskVal < OpWidth * 2 &&
"shufflevector mask index out of range!"); "shufflevector mask index out of range!");
if (MaskVal < OpWidth) if (MaskVal < OpWidth)
LeftDemanded.setBit(MaskVal); LeftDemanded.setBit(MaskVal);
else else
RightDemanded.setBit(MaskVal - OpWidth); RightDemanded.setBit(MaskVal - OpWidth);
} }
} }
} }
APInt LHSUndefElts(OpWidth, 0); APInt LHSPoisonElts(OpWidth, 0);
simplifyAndSetOp(I, 0, LeftDemanded, LHSUndefElts); simplifyAndSetOp(I, 0, LeftDemanded, LHSPoisonElts);
APInt RHSUndefElts(OpWidth, 0); APInt RHSPoisonElts(OpWidth, 0);
simplifyAndSetOp(I, 1, RightDemanded, RHSUndefElts); simplifyAndSetOp(I, 1, RightDemanded, RHSPoisonElts);
// If this shuffle does not change the vector length and the elements // If this shuffle does not change the vector length and the elements
// demanded by this shuffle are an identity mask, then this shuffle is // demanded by this shuffle are an identity mask, then this shuffle is
// unnecessary. // unnecessary.
// //
// We are assuming canonical form for the mask, so the source vector is // We are assuming canonical form for the mask, so the source vector is
// operand 0 and operand 1 is not used. // operand 0 and operand 1 is not used.
// //
Show All 9 Lines if (VWidth == OpWidth) {
IsIdentityShuffle = false; IsIdentityShuffle = false;
break; break;
} }
} }
if (IsIdentityShuffle) if (IsIdentityShuffle)
return Shuffle->getOperand(0); return Shuffle->getOperand(0);
} }
bool NewUndefElts = false; bool NewPoisonElts = false;
unsigned LHSIdx = -1u, LHSValIdx = -1u; unsigned LHSIdx = -1u, LHSValIdx = -1u;
unsigned RHSIdx = -1u, RHSValIdx = -1u; unsigned RHSIdx = -1u, RHSValIdx = -1u;
bool LHSUniform = true; bool LHSUniform = true;
bool RHSUniform = true; bool RHSUniform = true;
for (unsigned i = 0; i < VWidth; i++) { for (unsigned i = 0; i < VWidth; i++) {
unsigned MaskVal = Shuffle->getMaskValue(i); unsigned MaskVal = Shuffle->getMaskValue(i);
if (MaskVal == -1u) { if (MaskVal == -1u) {
UndefElts.setBit(i); PoisonElts.setBit(i);
} else if (!DemandedElts[i]) { } else if (!DemandedElts[i]) {
NewUndefElts = true; NewPoisonElts = true;
UndefElts.setBit(i); PoisonElts.setBit(i);
} else if (MaskVal < OpWidth) { } else if (MaskVal < OpWidth) {
if (LHSUndefElts[MaskVal]) { if (LHSPoisonElts[MaskVal]) {
NewUndefElts = true; NewPoisonElts = true;
UndefElts.setBit(i); PoisonElts.setBit(i);
} else { } else {
LHSIdx = LHSIdx == -1u ? i : OpWidth; LHSIdx = LHSIdx == -1u ? i : OpWidth;
LHSValIdx = LHSValIdx == -1u ? MaskVal : OpWidth; LHSValIdx = LHSValIdx == -1u ? MaskVal : OpWidth;
LHSUniform = LHSUniform && (MaskVal == i); LHSUniform = LHSUniform && (MaskVal == i);
} }
} else { } else {
if (RHSUndefElts[MaskVal - OpWidth]) { if (RHSPoisonElts[MaskVal - OpWidth]) {
NewUndefElts = true; NewPoisonElts = true;
UndefElts.setBit(i); PoisonElts.setBit(i);
} else { } else {
RHSIdx = RHSIdx == -1u ? i : OpWidth; RHSIdx = RHSIdx == -1u ? i : OpWidth;
RHSValIdx = RHSValIdx == -1u ? MaskVal - OpWidth : OpWidth; RHSValIdx = RHSValIdx == -1u ? MaskVal - OpWidth : OpWidth;
RHSUniform = RHSUniform && (MaskVal - OpWidth == i); RHSUniform = RHSUniform && (MaskVal - OpWidth == i);
} }
} }
} }
Show All 26 Lines if (OpWidth ==
if (Op && Value) { if (Op && Value) {
Instruction *New = InsertElementInst::Create( Instruction *New = InsertElementInst::Create(
Op, Value, ConstantInt::get(Type::getInt64Ty(I->getContext()), Idx), Op, Value, ConstantInt::get(Type::getInt64Ty(I->getContext()), Idx),
Shuffle->getName()); Shuffle->getName());
InsertNewInstWith(New, *Shuffle); InsertNewInstWith(New, *Shuffle);
return New; return New;
} }
} }
if (NewUndefElts) { if (NewPoisonElts) {
// Add additional discovered undefs. // Add additional discovered poisons.
SmallVector<int, 16> Elts; SmallVector<int, 16> Elts;
for (unsigned i = 0; i < VWidth; ++i) { for (unsigned i = 0; i < VWidth; ++i) {
if (UndefElts[i]) if (PoisonElts[i])
Elts.push_back(PoisonMaskElem); Elts.push_back(PoisonMaskElem);
else else
Elts.push_back(Shuffle->getMaskValue(i)); Elts.push_back(Shuffle->getMaskValue(i));
} }
Shuffle->setShuffleMask(Elts); Shuffle->setShuffleMask(Elts);
MadeChange = true; MadeChange = true;
} }
break; break;
} }
case Instruction::Select: { case Instruction::Select: {
// If this is a vector select, try to transform the select condition based // If this is a vector select, try to transform the select condition based
// on the current demanded elements. // on the current demanded elements.
SelectInst *Sel = cast<SelectInst>(I); SelectInst *Sel = cast<SelectInst>(I);
if (Sel->getCondition()->getType()->isVectorTy()) { if (Sel->getCondition()->getType()->isVectorTy()) {
// TODO: We are not doing anything with UndefElts based on this call. // TODO: We are not doing anything with PoisonElts based on this call.
// It is overwritten below based on the other select operands. If an // Output element is poison if select condition element is poison
// element of the select condition is known undef, then we are free to simplifyAndSetOp(I, 0, DemandedElts, PoisonElts);
// choose the output value from either arm of the select. If we know that
// one of those values is undef, then the output can be undef.
simplifyAndSetOp(I, 0, DemandedElts, UndefElts);
} }
// Next, see if we can transform the arms of the select. // Next, see if we can transform the arms of the select.
APInt DemandedLHS(DemandedElts), DemandedRHS(DemandedElts); APInt DemandedLHS(DemandedElts), DemandedRHS(DemandedElts);
if (auto *CV = dyn_cast<ConstantVector>(Sel->getCondition())) { if (auto *CV = dyn_cast<ConstantVector>(Sel->getCondition())) {
for (unsigned i = 0; i < VWidth; i++) { for (unsigned i = 0; i < VWidth; i++) {
// isNullValue() always returns false when called on a ConstantExpr. // isNullValue() always returns false when called on a ConstantExpr.
// Skip constant expressions to avoid propagating incorrect information. // Skip constant expressions to avoid propagating incorrect information.
Constant *CElt = CV->getAggregateElement(i); Constant *CElt = CV->getAggregateElement(i);
if (isa<ConstantExpr>(CElt)) if (isa<ConstantExpr>(CElt))
continue; continue;
// TODO: If a select condition element is undef, we can demand from
// either side. If one side is known undef, choosing that side would
// propagate undef.
if (CElt->isNullValue()) if (CElt->isNullValue())
DemandedLHS.clearBit(i); DemandedLHS.clearBit(i);
else else
DemandedRHS.clearBit(i); DemandedRHS.clearBit(i);
} }
} }
simplifyAndSetOp(I, 1, DemandedLHS, UndefElts2); simplifyAndSetOp(I, 1, DemandedLHS, PoisonElts2);
simplifyAndSetOp(I, 2, DemandedRHS, UndefElts3); simplifyAndSetOp(I, 2, DemandedRHS, PoisonElts3);
// Output elements are undefined if the element from each arm is undefined. // Output elements are poison if the element from each arm is poison.
// TODO: This can be improved. See comment in select condition handling. PoisonElts = PoisonElts2 & PoisonElts3;
UndefElts = UndefElts2 & UndefElts3;
break; break;
} }
case Instruction::BitCast: { case Instruction::BitCast: {
// Vector->vector casts only. // Vector->vector casts only.
VectorType *VTy = dyn_cast<VectorType>(I->getOperand(0)->getType()); VectorType *VTy = dyn_cast<VectorType>(I->getOperand(0)->getType());
if (!VTy) break; if (!VTy) break;
unsigned InVWidth = cast<FixedVectorType>(VTy)->getNumElements(); unsigned InVWidth = cast<FixedVectorType>(VTy)->getNumElements();
APInt InputDemandedElts(InVWidth, 0); APInt InputDemandedElts(InVWidth, 0);
UndefElts2 = APInt(InVWidth, 0); PoisonElts2 = APInt(InVWidth, 0);
unsigned Ratio; unsigned Ratio;
if (VWidth == InVWidth) { if (VWidth == InVWidth) {
// If we are converting from <4 x i32> -> <4 x f32>, we demand the same // If we are converting from <4 x i32> -> <4 x f32>, we demand the same
// elements as are demanded of us. // elements as are demanded of us.
Ratio = 1; Ratio = 1;
InputDemandedElts = DemandedElts; InputDemandedElts = DemandedElts;
} else if ((VWidth % InVWidth) == 0) { } else if ((VWidth % InVWidth) == 0) {
Show All 12 Lines if (VWidth == InVWidth) {
for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx) for (unsigned InIdx = 0; InIdx != InVWidth; ++InIdx)
if (DemandedElts[InIdx / Ratio]) if (DemandedElts[InIdx / Ratio])
InputDemandedElts.setBit(InIdx); InputDemandedElts.setBit(InIdx);
} else { } else {
// Unsupported so far. // Unsupported so far.
break; break;
} }
simplifyAndSetOp(I, 0, InputDemandedElts, UndefElts2); simplifyAndSetOp(I, 0, InputDemandedElts, PoisonElts2);
if (VWidth == InVWidth) { if (VWidth == InVWidth) {
UndefElts = UndefElts2; PoisonElts = PoisonElts2;
} else if ((VWidth % InVWidth) == 0) { } else if ((VWidth % InVWidth) == 0) {
// If the number of elements in the output is a multiple of the number of // If the number of elements in the output is a multiple of the number of
// elements in the input then an output element is undef if the // elements in the input then an output element is poison if the
// corresponding input element is undef. // corresponding input element is poison.
for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx)
if (UndefElts2[OutIdx / Ratio]) if (PoisonElts2[OutIdx / Ratio])
UndefElts.setBit(OutIdx); PoisonElts.setBit(OutIdx);
} else if ((InVWidth % VWidth) == 0) { } else if ((InVWidth % VWidth) == 0) {
// If the number of elements in the input is a multiple of the number of // If the number of elements in the input is a multiple of the number of
// elements in the output then an output element is undef if all of the // elements in the output then an output element is poison if all of the
// corresponding input elements are undef. // corresponding input elements are poison.
for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) { for (unsigned OutIdx = 0; OutIdx != VWidth; ++OutIdx) {
APInt SubUndef = UndefElts2.lshr(OutIdx * Ratio).zextOrTrunc(Ratio); APInt SubPoison = PoisonElts2.lshr(OutIdx * Ratio).zextOrTrunc(Ratio);
if (SubUndef.popcount() == Ratio) if (SubPoison.popcount() == Ratio)
UndefElts.setBit(OutIdx); PoisonElts.setBit(OutIdx);
} }
} else { } else {
llvm_unreachable("Unimp"); llvm_unreachable("Unimp");
} }
break; break;
} }
case Instruction::FPTrunc: case Instruction::FPTrunc:
case Instruction::FPExt: case Instruction::FPExt:
simplifyAndSetOp(I, 0, DemandedElts, UndefElts); simplifyAndSetOp(I, 0, DemandedElts, PoisonElts);
break; break;
case Instruction::Call: { case Instruction::Call: {
IntrinsicInst *II = dyn_cast<IntrinsicInst>(I); IntrinsicInst *II = dyn_cast<IntrinsicInst>(I);
if (!II) break; if (!II) break;
switch (II->getIntrinsicID()) { switch (II->getIntrinsicID()) {
case Intrinsic::masked_gather: // fallthrough case Intrinsic::masked_gather: // fallthrough
case Intrinsic::masked_load: { case Intrinsic::masked_load: {
// Subtlety: If we load from a pointer, the pointer must be valid // Subtlety: If we load from a pointer, the pointer must be valid
// regardless of whether the element is demanded. Doing otherwise risks // regardless of whether the element is demanded. Doing otherwise risks
// segfaults which didn't exist in the original program. // segfaults which didn't exist in the original program.
APInt DemandedPtrs(APInt::getAllOnes(VWidth)), APInt DemandedPtrs(APInt::getAllOnes(VWidth)),
DemandedPassThrough(DemandedElts); DemandedPassThrough(DemandedElts);
if (auto *CV = dyn_cast<ConstantVector>(II->getOperand(2))) if (auto *CV = dyn_cast<ConstantVector>(II->getOperand(2)))
for (unsigned i = 0; i < VWidth; i++) { for (unsigned i = 0; i < VWidth; i++) {
Constant *CElt = CV->getAggregateElement(i); Constant *CElt = CV->getAggregateElement(i);
if (CElt->isNullValue()) if (CElt->isNullValue())
DemandedPtrs.clearBit(i); DemandedPtrs.clearBit(i);
else if (CElt->isAllOnesValue()) else if (CElt->isAllOnesValue())
DemandedPassThrough.clearBit(i); DemandedPassThrough.clearBit(i);
} }
if (II->getIntrinsicID() == Intrinsic::masked_gather) if (II->getIntrinsicID() == Intrinsic::masked_gather)
simplifyAndSetOp(II, 0, DemandedPtrs, UndefElts2); simplifyAndSetOp(II, 0, DemandedPtrs, PoisonElts2);
simplifyAndSetOp(II, 3, DemandedPassThrough, UndefElts3); simplifyAndSetOp(II, 3, DemandedPassThrough, PoisonElts3);
// Output elements are undefined if the element from both sources are. // Output elements are poison if the element from both sources are.
// TODO: can strengthen via mask as well. // TODO: can strengthen via mask as well.
UndefElts = UndefElts2 & UndefElts3; PoisonElts = PoisonElts2 & PoisonElts3;
break; break;
} }
default: { default: {
// Handle target specific intrinsics // Handle target specific intrinsics
std::optional<Value *> V = targetSimplifyDemandedVectorEltsIntrinsic( std::optional<Value *> V = targetSimplifyDemandedVectorEltsIntrinsic(
*II, DemandedElts, UndefElts, UndefElts2, UndefElts3, *II, DemandedElts, PoisonElts, PoisonElts2, PoisonElts3,
simplifyAndSetOp); simplifyAndSetOp);
if (V) if (V)
return *V; return *V;
break; break;
} }
} // switch on IntrinsicID } // switch on IntrinsicID
break; break;
} // case Call } // case Call
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines if (DemandedElts == 1 && !X->hasOneUse() && !Y->hasOneUse() &&
}; };
if (User *ShufBO = findShufBO(/* MatchShufAsOp0 */ true)) if (User *ShufBO = findShufBO(/* MatchShufAsOp0 */ true))
return ShufBO; return ShufBO;
if (User *ShufBO = findShufBO(/* MatchShufAsOp0 */ false)) if (User *ShufBO = findShufBO(/* MatchShufAsOp0 */ false))
return ShufBO; return ShufBO;
} }
simplifyAndSetOp(I, 0, DemandedElts, UndefElts); simplifyAndSetOp(I, 0, DemandedElts, PoisonElts);
simplifyAndSetOp(I, 1, DemandedElts, UndefElts2); simplifyAndSetOp(I, 1, DemandedElts, PoisonElts2);
// Output elements are undefined if both are undefined. Consider things // Output elements are poison if either are poison.
// like undef & 0. The result is known zero, not undef. PoisonElts |= PoisonElts2;
UndefElts &= UndefElts2;
} }
// If we've proven all of the lanes undef, return an undef value. // If we've proven all of the lanes poison, return a poison value.
// TODO: Intersect w/demanded lanes // TODO: Intersect w/demanded lanes
if (UndefElts.isAllOnes()) if (PoisonElts.isAllOnes())
return UndefValue::get(I->getType()); return PoisonValue::get(I->getType());;
return MadeChange ? I : nullptr; return MadeChange ? I : nullptr;
} }

llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp

Show First 20 Lines • Show All 572 Lines • ▼ Show 20 Lines if (IndexC) {
unsigned NumElts = EC.getKnownMinValue(); unsigned NumElts = EC.getKnownMinValue();
// This instruction only demands the single element from the input vector. // This instruction only demands the single element from the input vector.
// Skip for scalable type, the number of elements is unknown at // Skip for scalable type, the number of elements is unknown at
// compile-time. // compile-time.
if (!EC.isScalable() && NumElts != 1) { if (!EC.isScalable() && NumElts != 1) {
// If the input vector has a single use, simplify it based on this use // If the input vector has a single use, simplify it based on this use
// property. // property.
if (SrcVec->hasOneUse()) { if (SrcVec->hasOneUse()) {
APInt UndefElts(NumElts, 0); APInt PoisonElts(NumElts, 0);
APInt DemandedElts(NumElts, 0); APInt DemandedElts(NumElts, 0);
DemandedElts.setBit(IndexC->getZExtValue()); DemandedElts.setBit(IndexC->getZExtValue());
if (Value *V = if (Value *V =
SimplifyDemandedVectorElts(SrcVec, DemandedElts, UndefElts)) SimplifyDemandedVectorElts(SrcVec, DemandedElts, PoisonElts))
return replaceOperand(EI, 0, V); return replaceOperand(EI, 0, V);
} else { } else {
// If the input vector has multiple uses, simplify it based on a union // If the input vector has multiple uses, simplify it based on a union
// of all elements used. // of all elements used.
APInt DemandedElts = findDemandedEltsByAllUsers(SrcVec); APInt DemandedElts = findDemandedEltsByAllUsers(SrcVec);
if (!DemandedElts.isAllOnes()) { if (!DemandedElts.isAllOnes()) {
APInt UndefElts(NumElts, 0); APInt PoisonElts(NumElts, 0);
if (Value *V = SimplifyDemandedVectorElts( if (Value *V = SimplifyDemandedVectorElts(
SrcVec, DemandedElts, UndefElts, 0 /* Depth */, SrcVec, DemandedElts, PoisonElts, 0 /* Depth */,
true /* AllowMultipleUsers */)) { true /* AllowMultipleUsers */)) {
if (V != SrcVec) { if (V != SrcVec) {
Worklist.addValue(SrcVec); Worklist.addValue(SrcVec);
SrcVec->replaceAllUsesWith(V); SrcVec->replaceAllUsesWith(V);
return &EI; return &EI;
} }
} }
} }
▲ Show 20 Lines • Show All 1,102 Lines • ▼ Show 20 Lines if (isShuffleRootCandidate(IE)) {
return new ShuffleVectorInst(LR.first, LR.second, Mask); return new ShuffleVectorInst(LR.first, LR.second, Mask);
} }
} }
} }
} }
if (auto VecTy = dyn_cast<FixedVectorType>(VecOp->getType())) { if (auto VecTy = dyn_cast<FixedVectorType>(VecOp->getType())) {
unsigned VWidth = VecTy->getNumElements(); unsigned VWidth = VecTy->getNumElements();
APInt UndefElts(VWidth, 0); APInt PoisonElts(VWidth, 0);
APInt AllOnesEltMask(APInt::getAllOnes(VWidth)); APInt AllOnesEltMask(APInt::getAllOnes(VWidth));
if (Value *V = SimplifyDemandedVectorElts(&IE, AllOnesEltMask, UndefElts)) { if (Value *V = SimplifyDemandedVectorElts(&IE, AllOnesEltMask, PoisonElts)) {
if (V != &IE) if (V != &IE)
return replaceInstUsesWith(IE, V); return replaceInstUsesWith(IE, V);
return &IE; return &IE;
} }
} }
if (Instruction *Shuf = foldConstantInsEltIntoShuffle(IE)) if (Instruction *Shuf = foldConstantInsEltIntoShuffle(IE))
return Shuf; return Shuf;
▲ Show 20 Lines • Show All 1,123 Lines • ▼ Show 20 Lines if (Instruction *I = narrowVectorSelect(SVI, Builder))
return I; return I;
if (Instruction *I = foldShuffleOfUnaryOps(SVI, Builder)) if (Instruction *I = foldShuffleOfUnaryOps(SVI, Builder))
return I; return I;
if (Instruction *I = foldCastShuffle(SVI, Builder)) if (Instruction *I = foldCastShuffle(SVI, Builder))
return I; return I;
APInt UndefElts(VWidth, 0); APInt PoisonElts(VWidth, 0);
APInt AllOnesEltMask(APInt::getAllOnes(VWidth)); APInt AllOnesEltMask(APInt::getAllOnes(VWidth));
if (Value *V = SimplifyDemandedVectorElts(&SVI, AllOnesEltMask, UndefElts)) { if (Value *V = SimplifyDemandedVectorElts(&SVI, AllOnesEltMask, PoisonElts)) {
if (V != &SVI) if (V != &SVI)
return replaceInstUsesWith(SVI, V); return replaceInstUsesWith(SVI, V);
return &SVI; return &SVI;
} }
if (Instruction *I = foldIdentityExtractShuffle(SVI)) if (Instruction *I = foldIdentityExtractShuffle(SVI))
return I; return I;
// These transforms have the potential to lose undef knowledge, so they are // These transforms have the potential to lose undef knowledge, so they are
// intentionally placed after SimplifyDemandedVectorElts(). // intentionally placed after SimplifyDemandedVectorElts().
if (Instruction *I = foldShuffleWithInsert(SVI, *this)) if (Instruction *I = foldShuffleWithInsert(SVI, *this))
return I; return I;
if (Instruction *I = foldIdentityPaddedShuffles(SVI)) if (Instruction *I = foldIdentityPaddedShuffles(SVI))
return I; return I;
if (match(RHS, m_Undef()) && canEvaluateShuffled(LHS, Mask)) { if (match(RHS, m_Poison()) && canEvaluateShuffled(LHS, Mask)) {
Value *V = evaluateInDifferentElementOrder(LHS, Mask, Builder); Value *V = evaluateInDifferentElementOrder(LHS, Mask, Builder);
return replaceInstUsesWith(SVI, V); return replaceInstUsesWith(SVI, V);
} }
// SROA generates shuffle+bitcast when the extracted sub-vector is bitcast to // SROA generates shuffle+bitcast when the extracted sub-vector is bitcast to
// a non-vector type. We can instead bitcast the original vector followed by // a non-vector type. We can instead bitcast the original vector followed by
// an extract of the desired element: // an extract of the desired element:
// //
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 LinesInstruction *InstCombinerImpl::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
// we only merge two shuffles if the result is either a splat or one of the // we only merge two shuffles if the result is either a splat or one of the
// input shuffle masks. In this case, merging the shuffles just removes // input shuffle masks. In this case, merging the shuffles just removes
// one instruction, which we know is safe. This is good for things like // one instruction, which we know is safe. This is good for things like
// turning: (splat(splat)) -> splat, or // turning: (splat(splat)) -> splat, or
// merge(V[0..n], V[n+1..2n]) -> V[0..2n] // merge(V[0..n], V[n+1..2n]) -> V[0..2n]
ShuffleVectorInst* LHSShuffle = dyn_cast<ShuffleVectorInst>(LHS); ShuffleVectorInst* LHSShuffle = dyn_cast<ShuffleVectorInst>(LHS);
ShuffleVectorInst* RHSShuffle = dyn_cast<ShuffleVectorInst>(RHS); ShuffleVectorInst* RHSShuffle = dyn_cast<ShuffleVectorInst>(RHS);
if (LHSShuffle) if (LHSShuffle)
if (!match(LHSShuffle->getOperand(1), m_Undef()) && !match(RHS, m_Undef())) if (!match(LHSShuffle->getOperand(1), m_Poison()) && !match(RHS, m_Poison()))
LHSShuffle = nullptr; LHSShuffle = nullptr;
if (RHSShuffle) if (RHSShuffle)
if (!match(RHSShuffle->getOperand(1), m_Undef())) if (!match(RHSShuffle->getOperand(1), m_Poison()))
RHSShuffle = nullptr; RHSShuffle = nullptr;
if (!LHSShuffle && !RHSShuffle) if (!LHSShuffle && !RHSShuffle)
return MadeChange ? &SVI : nullptr; return MadeChange ? &SVI : nullptr;
Value* LHSOp0 = nullptr; Value* LHSOp0 = nullptr;
Value* LHSOp1 = nullptr; Value* LHSOp1 = nullptr;
Value* RHSOp0 = nullptr; Value* RHSOp0 = nullptr;
unsigned LHSOp0Width = 0; unsigned LHSOp0Width = 0;
unsigned RHSOp0Width = 0; unsigned RHSOp0Width = 0;
if (LHSShuffle) { if (LHSShuffle) {
LHSOp0 = LHSShuffle->getOperand(0); LHSOp0 = LHSShuffle->getOperand(0);
LHSOp1 = LHSShuffle->getOperand(1); LHSOp1 = LHSShuffle->getOperand(1);
LHSOp0Width = cast<FixedVectorType>(LHSOp0->getType())->getNumElements(); LHSOp0Width = cast<FixedVectorType>(LHSOp0->getType())->getNumElements();
} }
if (RHSShuffle) { if (RHSShuffle) {
RHSOp0 = RHSShuffle->getOperand(0); RHSOp0 = RHSShuffle->getOperand(0);
RHSOp0Width = cast<FixedVectorType>(RHSOp0->getType())->getNumElements(); RHSOp0Width = cast<FixedVectorType>(RHSOp0->getType())->getNumElements();
} }
Value* newLHS = LHS; Value* newLHS = LHS;
Value* newRHS = RHS; Value* newRHS = RHS;
if (LHSShuffle) { if (LHSShuffle) {
// case 1 // case 1
if (match(RHS, m_Undef())) { if (match(RHS, m_Poison())) {
newLHS = LHSOp0; newLHS = LHSOp0;
newRHS = LHSOp1; newRHS = LHSOp1;
} }
// case 2 or 4 // case 2 or 4
else if (LHSOp0Width == LHSWidth) { else if (LHSOp0Width == LHSWidth) {
newLHS = LHSOp0; newLHS = LHSOp0;
} }
} }
▲ Show 20 Lines • Show All 95 Lines • Show Last 20 Lines

llvm/lib/Transforms/InstCombine/InstructionCombining.cpp

Show First 20 Lines • Show All 180 Lines • ▼ Show 20 Linesstd::optional<Value *> InstCombiner::targetSimplifyDemandedUseBitsIntrinsic(
if (II.getCalledFunction()->isTargetIntrinsic()) { if (II.getCalledFunction()->isTargetIntrinsic()) {
return TTI.simplifyDemandedUseBitsIntrinsic(*this, II, DemandedMask, Known, return TTI.simplifyDemandedUseBitsIntrinsic(*this, II, DemandedMask, Known,
KnownBitsComputed); KnownBitsComputed);
} }
return std::nullopt; return std::nullopt;
} }
std::optional<Value *> InstCombiner::targetSimplifyDemandedVectorEltsIntrinsic( std::optional<Value *> InstCombiner::targetSimplifyDemandedVectorEltsIntrinsic(
IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts, APInt &UndefElts2, IntrinsicInst &II, APInt DemandedElts, APInt &PoisonElts, APInt &PoisonElts2,
APInt &UndefElts3, APInt &PoisonElts3,
std::function<void(Instruction *, unsigned, APInt, APInt &)> std::function<void(Instruction *, unsigned, APInt, APInt &)>
SimplifyAndSetOp) { SimplifyAndSetOp) {
// Handle target specific intrinsics // Handle target specific intrinsics
if (II.getCalledFunction()->isTargetIntrinsic()) { if (II.getCalledFunction()->isTargetIntrinsic()) {
return TTI.simplifyDemandedVectorEltsIntrinsic( return TTI.simplifyDemandedVectorEltsIntrinsic(
*this, II, DemandedElts, UndefElts, UndefElts2, UndefElts3, *this, II, DemandedElts, PoisonElts, PoisonElts2, PoisonElts3,
SimplifyAndSetOp); SimplifyAndSetOp);
} }
return std::nullopt; return std::nullopt;
} }
bool InstCombiner::isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const { bool InstCombiner::isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const {
return TTI.isValidAddrSpaceCast(FromAS, ToAS); return TTI.isValidAddrSpaceCast(FromAS, ToAS);
} }
▲ Show 20 Lines • Show All 1,439 Lines • ▼ Show 20 Lines if (InstVTy &&
unsigned SrcVecNumElts = unsigned SrcVecNumElts =
cast<FixedVectorType>(V1->getType())->getNumElements(); cast<FixedVectorType>(V1->getType())->getNumElements();
UndefValue *UndefScalar = UndefValue::get(C->getType()->getScalarType()); UndefValue *UndefScalar = UndefValue::get(C->getType()->getScalarType());
SmallVector<Constant *, 16> NewVecC(SrcVecNumElts, UndefScalar); SmallVector<Constant *, 16> NewVecC(SrcVecNumElts, UndefScalar);
bool MayChange = true; bool MayChange = true;
unsigned NumElts = InstVTy->getNumElements(); unsigned NumElts = InstVTy->getNumElements();
for (unsigned I = 0; I < NumElts; ++I) { for (unsigned I = 0; I < NumElts; ++I) {
Constant *CElt = C->getAggregateElement(I); Constant *CElt = C->getAggregateElement(I);
if (ShMask[I] >= 0) { if (ShMask[I] >= 0 && ShMask[I] < (int) NumElts) {
assert(ShMask[I] < (int)NumElts && "Not expecting narrowing shuffle");
aqjuneUnsubmitted
Not Done
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This seems to be

aqjune: This seems to be
aqjuneUnsubmitted
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Nevermind, please ignore this comment.

aqjune: Nevermind, please ignore this comment.
Constant *NewCElt = NewVecC[ShMask[I]]; Constant *NewCElt = NewVecC[ShMask[I]];
// Bail out if: // Bail out if:
// 1. The constant vector contains a constant expression. // 1. The constant vector contains a constant expression.
// 2. The shuffle needs an element of the constant vector that can't // 2. The shuffle needs an element of the constant vector that can't
// be mapped to a new constant vector. // be mapped to a new constant vector.
// 3. This is a widening shuffle that copies elements of V1 into the // 3. This is a widening shuffle that copies elements of V1 into the
// extended elements (extending with undef is allowed). // extended elements (extending with undef is allowed).
if (!CElt || (!isa<UndefValue>(NewCElt) && NewCElt != CElt) || if (!CElt || (!isa<UndefValue>(NewCElt) && NewCElt != CElt) ||
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines if (Value *V = simplifyGEPInst(GEPEltType, PtrOp, Indices, GEP.isInBounds(),
SQ.getWithInstruction(&GEP))) SQ.getWithInstruction(&GEP)))
return replaceInstUsesWith(GEP, V); return replaceInstUsesWith(GEP, V);
// For vector geps, use the generic demanded vector support. // For vector geps, use the generic demanded vector support.
// Skip if GEP return type is scalable. The number of elements is unknown at // Skip if GEP return type is scalable. The number of elements is unknown at
// compile-time. // compile-time.
if (auto *GEPFVTy = dyn_cast<FixedVectorType>(GEPType)) { if (auto *GEPFVTy = dyn_cast<FixedVectorType>(GEPType)) {
auto VWidth = GEPFVTy->getNumElements(); auto VWidth = GEPFVTy->getNumElements();
APInt UndefElts(VWidth, 0); APInt PoisonElts(VWidth, 0);
APInt AllOnesEltMask(APInt::getAllOnes(VWidth)); APInt AllOnesEltMask(APInt::getAllOnes(VWidth));
if (Value *V = SimplifyDemandedVectorElts(&GEP, AllOnesEltMask, if (Value *V = SimplifyDemandedVectorElts(&GEP, AllOnesEltMask,
UndefElts)) { PoisonElts)) {
if (V != &GEP) if (V != &GEP)
return replaceInstUsesWith(GEP, V); return replaceInstUsesWith(GEP, V);
return &GEP; return &GEP;
} }
// TODO: 1) Scalarize splat operands, 2) scalarize entire instruction if // TODO: 1) Scalarize splat operands, 2) scalarize entire instruction if
// possible (decide on canonical form for pointer broadcast), 3) exploit // possible (decide on canonical form for pointer broadcast), 3) exploit
// undef elements to decrease demanded bits // undef elements to decrease demanded bits
▲ Show 20 Lines • Show All 2,329 Lines • Show Last 20 Lines

llvm/test/Transforms/InstCombine/AArch64/demandelts.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -passes=instcombine -mtriple aarch64 < %s | FileCheck %s ; RUN: opt -S -passes=instcombine -mtriple aarch64 < %s | FileCheck %s
define <2 x float> @fcvtxn(<2 x double> %d1) { define <2 x float> @fcvtxn(<2 x double> %d1) {
; CHECK-LABEL: @fcvtxn( ; CHECK-LABEL: @fcvtxn(
; CHECK-NEXT: [[I:%.*]] = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> [[D1:%.*]]) ; CHECK-NEXT: [[I:%.*]] = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> [[D1:%.*]])
; CHECK-NEXT: [[S:%.*]] = shufflevector <2 x float> [[I]], <2 x float> undef, <2 x i32> <i32 0, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <2 x float> [[I]], <2 x float> poison, <2 x i32> <i32 0, i32 poison>
; CHECK-NEXT: ret <2 x float> [[S]] ; CHECK-NEXT: ret <2 x float> [[S]]
; ;
%a = shufflevector <2 x double> %d1, <2 x double> undef, <2 x i32> <i32 0, i32 0> %a = shufflevector <2 x double> %d1, <2 x double> undef, <2 x i32> <i32 0, i32 0>
%i = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %a) %i = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %a)
%s = shufflevector <2 x float> %i, <2 x float> undef, <2 x i32> <i32 0, i32 undef> %s = shufflevector <2 x float> %i, <2 x float> undef, <2 x i32> <i32 0, i32 undef>
ret <2 x float> %s ret <2 x float> %s
} }
define <4 x i16> @rshrn(<2 x i32> %d1, <2 x i32> %d2) { define <4 x i16> @rshrn(<2 x i32> %d1, <2 x i32> %d2) {
; CHECK-LABEL: @rshrn( ; CHECK-LABEL: @rshrn(
; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[A]], i32 9) ; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[A]], i32 9)
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i16> [[S]] ; CHECK-NEXT: ret <4 x i16> [[S]]
; ;
%a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%i = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %a, i32 9) %i = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %a, i32 9)
%s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @sqrshrn(<2 x i32> %d1, <2 x i32> %d2) { define <4 x i16> @sqrshrn(<2 x i32> %d1, <2 x i32> %d2) {
; CHECK-LABEL: @sqrshrn( ; CHECK-LABEL: @sqrshrn(
; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> [[A]], i32 9) ; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> [[A]], i32 9)
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i16> [[S]] ; CHECK-NEXT: ret <4 x i16> [[S]]
; ;
%a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%i = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %a, i32 9) %i = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %a, i32 9)
%s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @sqrshrun(<2 x i32> %d1, <2 x i32> %d2) { define <4 x i16> @sqrshrun(<2 x i32> %d1, <2 x i32> %d2) {
; CHECK-LABEL: @sqrshrun( ; CHECK-LABEL: @sqrshrun(
; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> [[A]], i32 9) ; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> [[A]], i32 9)
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i16> [[S]] ; CHECK-NEXT: ret <4 x i16> [[S]]
; ;
%a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%i = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %a, i32 9) %i = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %a, i32 9)
%s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @sqshrn(<2 x i32> %d1, <2 x i32> %d2) { define <4 x i16> @sqshrn(<2 x i32> %d1, <2 x i32> %d2) {
; CHECK-LABEL: @sqshrn( ; CHECK-LABEL: @sqshrn(
; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[A]], i32 9) ; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[A]], i32 9)
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i16> [[S]] ; CHECK-NEXT: ret <4 x i16> [[S]]
; ;
%a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%i = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %a, i32 9) %i = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %a, i32 9)
%s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @sqshrun(<2 x i32> %d1, <2 x i32> %d2) { define <4 x i16> @sqshrun(<2 x i32> %d1, <2 x i32> %d2) {
; CHECK-LABEL: @sqshrun( ; CHECK-LABEL: @sqshrun(
; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> [[A]], i32 9) ; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> [[A]], i32 9)
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i16> [[S]] ; CHECK-NEXT: ret <4 x i16> [[S]]
; ;
%a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%i = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %a, i32 9) %i = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %a, i32 9)
%s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @sqxtn(<2 x i32> %d1, <2 x i32> %d2) { define <4 x i16> @sqxtn(<2 x i32> %d1, <2 x i32> %d2) {
; CHECK-LABEL: @sqxtn( ; CHECK-LABEL: @sqxtn(
; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> [[A]]) ; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> [[A]])
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i16> [[S]] ; CHECK-NEXT: ret <4 x i16> [[S]]
; ;
%a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%i = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %a) %i = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %a)
%s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @sqxtun(<2 x i32> %d1, <2 x i32> %d2) { define <4 x i16> @sqxtun(<2 x i32> %d1, <2 x i32> %d2) {
; CHECK-LABEL: @sqxtun( ; CHECK-LABEL: @sqxtun(
; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> [[A]]) ; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> [[A]])
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i16> [[S]] ; CHECK-NEXT: ret <4 x i16> [[S]]
; ;
%a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%i = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %a) %i = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %a)
%s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @uqrshrn(<2 x i32> %d1, <2 x i32> %d2) { define <4 x i16> @uqrshrn(<2 x i32> %d1, <2 x i32> %d2) {
; CHECK-LABEL: @uqrshrn( ; CHECK-LABEL: @uqrshrn(
; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> [[A]], i32 9) ; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> [[A]], i32 9)
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i16> [[S]] ; CHECK-NEXT: ret <4 x i16> [[S]]
; ;
%a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%i = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %a, i32 9) %i = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %a, i32 9)
%s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @uqshrn(<2 x i32> %d1, <2 x i32> %d2) { define <4 x i16> @uqshrn(<2 x i32> %d1, <2 x i32> %d2) {
; CHECK-LABEL: @uqshrn( ; CHECK-LABEL: @uqshrn(
; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[A]], i32 9) ; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[A]], i32 9)
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i16> [[S]] ; CHECK-NEXT: ret <4 x i16> [[S]]
; ;
%a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%i = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %a, i32 9) %i = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %a, i32 9)
%s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @uqxtn(<2 x i32> %d1, <2 x i32> %d2) { define <4 x i16> @uqxtn(<2 x i32> %d1, <2 x i32> %d2) {
; CHECK-LABEL: @uqxtn( ; CHECK-LABEL: @uqxtn(
; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[A:%.*]] = shufflevector <2 x i32> [[D1:%.*]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> [[A]]) ; CHECK-NEXT: [[I:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> [[A]])
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i16> [[I]], <4 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i16> [[S]] ; CHECK-NEXT: ret <4 x i16> [[S]]
; ;
%a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %a = shufflevector <2 x i32> %d1, <2 x i32> %d2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%i = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %a) %i = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %a)
%s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %s = shufflevector <4 x i16> %i, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i16> %s ret <4 x i16> %s
} }
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llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts-inseltpoison.ll

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%ins1 = insertvalue { float, float, float } %ins0, float %elt1, 1 %ins1 = insertvalue { float, float, float } %ins0, float %elt1, 1
%ins2 = insertvalue { float, float, float } %ins1, float %elt2, 2 %ins2 = insertvalue { float, float, float } %ins1, float %elt2, 2
ret { float, float, float } %ins2 ret { float, float, float } %ins2
} }
define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_3(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 { define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_3(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_3( ; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_3(
; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false) ; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> undef, <2 x i32> <i32 0, i32 2> ; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 poison, i32 1> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 poison, i32 1>
; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]] ; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]]
; CHECK-NEXT: ret <2 x float> [[RET]] ; CHECK-NEXT: ret <2 x float> [[RET]]
; ;
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
%elt0 = extractelement <4 x float> %data, i32 0 %elt0 = extractelement <4 x float> %data, i32 0
%elt2 = extractelement <4 x float> %data, i32 2 %elt2 = extractelement <4 x float> %data, i32 2
%ins0 = insertelement <2 x float> poison, float %elt0, i32 0 %ins0 = insertelement <2 x float> poison, float %elt0, i32 0
%ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1 %ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1
%shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 4, i32 1> %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 4, i32 1>
%ret = fadd <2 x float> %ins1, %shuf %ret = fadd <2 x float> %ins1, %shuf
ret <2 x float> %ret ret <2 x float> %ret
} }
define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_4(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 { define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_4(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_4( ; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_4(
; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false) ; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> undef, <2 x i32> <i32 0, i32 2> ; CHECK-NEXT: [[A:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <4 x i32> <i32 poison, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 1, i32 poison> ; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x float> [[A]], <4 x float> <float poison, float undef, float poison, float poison>, <2 x i32> <i32 1, i32 5>
; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]] ; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]]
; CHECK-NEXT: ret <2 x float> [[RET]] ; CHECK-NEXT: ret <2 x float> [[RET]]
; ;
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
%elt0 = extractelement <4 x float> %data, i32 0 %elt0 = extractelement <4 x float> %data, i32 0
%elt2 = extractelement <4 x float> %data, i32 2 %elt2 = extractelement <4 x float> %data, i32 2
%ins0 = insertelement <2 x float> poison, float %elt0, i32 0 %ins0 = insertelement <2 x float> poison, float %elt0, i32 0
%ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1 %ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1
%shuf = shufflevector <4 x float> undef, <4 x float> %data, <2 x i32> <i32 5, i32 1> %shuf = shufflevector <4 x float> undef, <4 x float> %data, <2 x i32> <i32 5, i32 1>
%ret = fadd <2 x float> %ins1, %shuf %ret = fadd <2 x float> %ins1, %shuf
ret <2 x float> %ret ret <2 x float> %ret
} }
define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_5(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 { define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_5(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_5( ; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_5(
; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false) ; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> undef, <2 x i32> <i32 2, i32 2> ; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 2, i32 2>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 0, i32 1> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]] ; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]]
; CHECK-NEXT: ret <2 x float> [[RET]] ; CHECK-NEXT: ret <2 x float> [[RET]]
; ;
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
%elt2 = extractelement <4 x float> %data, i32 2 %elt2 = extractelement <4 x float> %data, i32 2
%ins0 = insertelement <2 x float> poison, float %elt2, i32 0 %ins0 = insertelement <2 x float> poison, float %elt2, i32 0
%ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1 %ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1
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%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 7, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0) %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 7, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
%elt0 = extractelement <4 x float> %data, i32 0 %elt0 = extractelement <4 x float> %data, i32 0
ret float %elt0 ret float %elt0
} }
define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 { define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
; CHECK-LABEL: @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32( ; CHECK-LABEL: @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(
; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0) ; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0)
; CHECK-NEXT: [[SHUF:%.*]] = insertelement <2 x float> undef, float [[DATA]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[DATA]], i64 0
; CHECK-NEXT: ret <2 x float> [[SHUF]] ; CHECK-NEXT: ret <2 x float> [[TMP1]]
; ;
%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0) %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
%shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 0, i32 1> %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 0, i32 1>
ret <2 x float> %shuf ret <2 x float> %shuf
} }
define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0011_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 { define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0011_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
; CHECK-LABEL: @extract_elt0_elt1_dmask_0011_image_sample_1d_v4f32_f32( ; CHECK-LABEL: @extract_elt0_elt1_dmask_0011_image_sample_1d_v4f32_f32(
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%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 5, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0) %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 5, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
%shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 0, i32 1> %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 0, i32 1>
ret <2 x float> %shuf ret <2 x float> %shuf
} }
define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 { define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32( ; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(
; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0) ; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0)
; CHECK-NEXT: [[SHUF:%.*]] = insertelement <3 x float> undef, float [[DATA]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x float> <float poison, float undef, float undef>, float [[DATA]], i64 0
; CHECK-NEXT: ret <3 x float> [[SHUF]] ; CHECK-NEXT: ret <3 x float> [[TMP1]]
; ;
%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0) %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
%shuf = shufflevector <4 x float> %data, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2> %shuf = shufflevector <4 x float> %data, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
ret <3 x float> %shuf ret <3 x float> %shuf
} }
define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0011_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 { define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0011_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0011_image_sample_1d_v4f32_f32( ; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0011_image_sample_1d_v4f32_f32(
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llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-demanded-vector-elts.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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%ins1 = insertvalue { float, float, float } %ins0, float %elt1, 1 %ins1 = insertvalue { float, float, float } %ins0, float %elt1, 1
%ins2 = insertvalue { float, float, float } %ins1, float %elt2, 2 %ins2 = insertvalue { float, float, float } %ins1, float %elt2, 2
ret { float, float, float } %ins2 ret { float, float, float } %ins2
} }
define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_3(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 { define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_3(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_3( ; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_3(
; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false) ; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> undef, <2 x i32> <i32 0, i32 2> ; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 poison, i32 1> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 poison, i32 1>
; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]] ; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]]
; CHECK-NEXT: ret <2 x float> [[RET]] ; CHECK-NEXT: ret <2 x float> [[RET]]
; ;
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
%elt0 = extractelement <4 x float> %data, i32 0 %elt0 = extractelement <4 x float> %data, i32 0
%elt2 = extractelement <4 x float> %data, i32 2 %elt2 = extractelement <4 x float> %data, i32 2
%ins0 = insertelement <2 x float> undef, float %elt0, i32 0 %ins0 = insertelement <2 x float> undef, float %elt0, i32 0
%ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1 %ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1
%shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 4, i32 1> %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 4, i32 1>
%ret = fadd <2 x float> %ins1, %shuf %ret = fadd <2 x float> %ins1, %shuf
ret <2 x float> %ret ret <2 x float> %ret
} }
define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_4(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 { define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_4(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_4( ; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_4(
; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false) ; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> undef, <2 x i32> <i32 0, i32 2> ; CHECK-NEXT: [[A:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <4 x i32> <i32 poison, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 1, i32 poison> ; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x float> [[A]], <4 x float> <float poison, float undef, float poison, float poison>, <2 x i32> <i32 1, i32 5>
; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]] ; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]]
; CHECK-NEXT: ret <2 x float> [[RET]] ; CHECK-NEXT: ret <2 x float> [[RET]]
; ;
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
%elt0 = extractelement <4 x float> %data, i32 0 %elt0 = extractelement <4 x float> %data, i32 0
%elt2 = extractelement <4 x float> %data, i32 2 %elt2 = extractelement <4 x float> %data, i32 2
%ins0 = insertelement <2 x float> undef, float %elt0, i32 0 %ins0 = insertelement <2 x float> undef, float %elt0, i32 0
%ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1 %ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1
%shuf = shufflevector <4 x float> undef, <4 x float> %data, <2 x i32> <i32 5, i32 1> %shuf = shufflevector <4 x float> undef, <4 x float> %data, <2 x i32> <i32 5, i32 1>
%ret = fadd <2 x float> %ins1, %shuf %ret = fadd <2 x float> %ins1, %shuf
ret <2 x float> %ret ret <2 x float> %ret
} }
define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_5(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 { define amdgpu_ps <2 x float> @extract_elt0_elt1_elt2_buffer_load_v4f32_5(<4 x i32> inreg %rsrc, i32 %idx, i32 %ofs) #0 {
; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_5( ; CHECK-LABEL: @extract_elt0_elt1_elt2_buffer_load_v4f32_5(
; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false) ; CHECK-NEXT: [[DATA:%.*]] = call <3 x float> @llvm.amdgcn.buffer.load.v3f32(<4 x i32> [[RSRC:%.*]], i32 [[IDX:%.*]], i32 [[OFS:%.*]], i1 false, i1 false)
; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> undef, <2 x i32> <i32 2, i32 2> ; CHECK-NEXT: [[INS1:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 2, i32 2>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 0, i32 1> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x float> [[DATA]], <3 x float> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]] ; CHECK-NEXT: [[RET:%.*]] = fadd <2 x float> [[INS1]], [[SHUF]]
; CHECK-NEXT: ret <2 x float> [[RET]] ; CHECK-NEXT: ret <2 x float> [[RET]]
; ;
%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false) %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 false)
%elt2 = extractelement <4 x float> %data, i32 2 %elt2 = extractelement <4 x float> %data, i32 2
%ins0 = insertelement <2 x float> undef, float %elt2, i32 0 %ins0 = insertelement <2 x float> undef, float %elt2, i32 0
%ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1 %ins1 = insertelement <2 x float> %ins0, float %elt2, i32 1
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%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 7, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0) %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 7, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
%elt0 = extractelement <4 x float> %data, i32 0 %elt0 = extractelement <4 x float> %data, i32 0
ret float %elt0 ret float %elt0
} }
define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 { define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
; CHECK-LABEL: @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32( ; CHECK-LABEL: @extract_elt0_elt1_dmask_0001_image_sample_1d_v4f32_f32(
; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0) ; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0)
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> undef, float [[DATA]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[DATA]], i64 0
; CHECK-NEXT: ret <2 x float> [[TMP1]] ; CHECK-NEXT: ret <2 x float> [[TMP1]]
; ;
%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0) %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
%shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 0, i32 1> %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 0, i32 1>
ret <2 x float> %shuf ret <2 x float> %shuf
} }
define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0011_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 { define amdgpu_ps <2 x float> @extract_elt0_elt1_dmask_0011_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
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%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 5, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0) %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 5, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
%shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 0, i32 1> %shuf = shufflevector <4 x float> %data, <4 x float> poison, <2 x i32> <i32 0, i32 1>
ret <2 x float> %shuf ret <2 x float> %shuf
} }
define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 { define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32( ; CHECK-LABEL: @extract_elt0_elt1_elt2_dmask_0001_image_sample_1d_v4f32_f32(
; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0) ; CHECK-NEXT: [[DATA:%.*]] = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float [[S:%.*]], <8 x i32> [[SAMPLER:%.*]], <4 x i32> [[RSRC:%.*]], i1 false, i32 0, i32 0)
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x float> undef, float [[DATA]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x float> <float poison, float undef, float undef>, float [[DATA]], i64 0
; CHECK-NEXT: ret <3 x float> [[TMP1]] ; CHECK-NEXT: ret <3 x float> [[TMP1]]
; ;
%data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0) %data = call <4 x float> @llvm.amdgcn.image.sample.1d.v4f32.f32(i32 1, float %s, <8 x i32> %sampler, <4 x i32> %rsrc, i1 false, i32 0, i32 0)
%shuf = shufflevector <4 x float> %data, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2> %shuf = shufflevector <4 x float> %data, <4 x float> poison, <3 x i32> <i32 0, i32 1, i32 2>
ret <3 x float> %shuf ret <3 x float> %shuf
} }
define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0011_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 { define amdgpu_ps <3 x float> @extract_elt0_elt1_elt2_dmask_0011_image_sample_1d_v4f32_f32(float %s, <8 x i32> inreg %sampler, <4 x i32> inreg %rsrc) #0 {
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llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-simplify-image-buffer-stores.ll

Show All 34 Lines;
%newvdata1 = insertelement <4 x float> undef, float 0.0, i32 0 %newvdata1 = insertelement <4 x float> undef, float 0.0, i32 0
%newvdata2 = insertelement <4 x float> %newvdata1, float %vdata1, i32 1 %newvdata2 = insertelement <4 x float> %newvdata1, float %vdata1, i32 1
%newvdata3 = insertelement <4 x float> %newvdata2, float %vdata2, i32 2 %newvdata3 = insertelement <4 x float> %newvdata2, float %vdata2, i32 2
%newvdata4 = insertelement <4 x float> %newvdata3, float 0.0, i32 3 %newvdata4 = insertelement <4 x float> %newvdata3, float 0.0, i32 3
call void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float> %newvdata4, i32 7, i32 %s, i32 0, <8 x i32> %rsrc, i32 0, i32 0) call void @llvm.amdgcn.image.store.mip.1d.v4f32.i32(<4 x float> %newvdata4, i32 7, i32 %s, i32 0, <8 x i32> %rsrc, i32 0, i32 0)
ret void ret void
} }
define amdgpu_ps void @buffer_store_format_insert_zeros_at_end(<4 x i32> inreg %a, float %vdata1, i32 %b) { define amdgpu_ps void @buffer_store_insert_zeros_at_end(<4 x i32> inreg %a, float %vdata1, i32 %b) {
; GCN-LABEL: @buffer_store_format_insert_zeros_at_end( ; GCN-LABEL: @buffer_store_insert_zeros_at_end(
; GCN-NEXT: [[TMP1:%.*]] = insertelement <2 x float> undef, float [[VDATA1:%.*]], i64 0 ; GCN-NEXT: [[TMP1:%.*]] = insertelement <2 x float> poison, float [[VDATA1:%.*]], i64 0
; GCN-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer ; GCN-NEXT: [[TMP2:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
; GCN-NEXT: call void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float> [[TMP2]], <4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 0, i1 false, i1 false) ; GCN-NEXT: call void @llvm.amdgcn.buffer.store.format.v2f32(<2 x float> [[TMP2]], <4 x i32> [[A:%.*]], i32 [[B:%.*]], i32 0, i1 false, i1 false)
; GCN-NEXT: ret void ; GCN-NEXT: ret void
; ;
%newvdata1 = insertelement <4 x float> undef, float %vdata1, i32 0 %newvdata1 = insertelement <4 x float> undef, float %vdata1, i32 0
%newvdata2 = insertelement <4 x float> %newvdata1, float %vdata1, i32 1 %newvdata2 = insertelement <4 x float> %newvdata1, float %vdata1, i32 1
%newvdata3 = insertelement <4 x float> %newvdata2, float 0.0, i32 2 %newvdata3 = insertelement <4 x float> %newvdata2, float 0.0, i32 2
%newvdata4 = insertelement <4 x float> %newvdata3, float 0.0, i32 3 %newvdata4 = insertelement <4 x float> %newvdata3, float 0.0, i32 3
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llvm/test/Transforms/InstCombine/X86/clmulqdq.ll

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%1 = insertelement <2 x i64> %a0, i64 1, i64 1 %1 = insertelement <2 x i64> %a0, i64 1, i64 1
%2 = insertelement <2 x i64> %a1, i64 1, i64 1 %2 = insertelement <2 x i64> %a1, i64 1, i64 1
%3 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %2, i8 17) %3 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %1, <2 x i64> %2, i8 17)
ret <2 x i64> %3 ret <2 x i64> %3
} }
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_0() { define <2 x i64> @test_demanded_elts_pclmulqdq_undef_0() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_0( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_0(
; CHECK-NEXT: ret <2 x i64> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 poison>, <2 x i64> <i64 undef, i64 poison>, i8 0)
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
; ;
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 1>, <2 x i64> <i64 undef, i64 1>, i8 0) %1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 1>, <2 x i64> <i64 undef, i64 1>, i8 0)
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_1() { define <2 x i64> @test_demanded_elts_pclmulqdq_undef_1() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_1( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_1(
; CHECK-NEXT: ret <2 x i64> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 poison, i64 undef>, <2 x i64> <i64 undef, i64 poison>, i8 1)
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
; ;
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 1, i64 undef>, <2 x i64> <i64 undef, i64 1>, i8 1) %1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 1, i64 undef>, <2 x i64> <i64 undef, i64 1>, i8 1)
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_16() { define <2 x i64> @test_demanded_elts_pclmulqdq_undef_16() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_16( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_16(
; CHECK-NEXT: ret <2 x i64> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 poison>, <2 x i64> <i64 poison, i64 undef>, i8 16)
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
; ;
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 1>, <2 x i64> <i64 1, i64 undef>, i8 16) %1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 undef, i64 1>, <2 x i64> <i64 1, i64 undef>, i8 16)
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <2 x i64> @test_demanded_elts_pclmulqdq_undef_17() { define <2 x i64> @test_demanded_elts_pclmulqdq_undef_17() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_17( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_undef_17(
; CHECK-NEXT: ret <2 x i64> zeroinitializer ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 poison, i64 undef>, <2 x i64> <i64 poison, i64 undef>, i8 17)
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
; ;
%1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 1, i64 undef>, <2 x i64> <i64 1, i64 undef>, i8 17) %1 = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> <i64 1, i64 undef>, <2 x i64> <i64 1, i64 undef>, i8 17)
ret <2 x i64> %1 ret <2 x i64> %1
} }
define <4 x i64> @test_demanded_elts_pclmulqdq_256_0(<4 x i64> %a0, <4 x i64> %a1) { define <4 x i64> @test_demanded_elts_pclmulqdq_256_0(<4 x i64> %a0, <4 x i64> %a1) {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_0( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_0(
; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]], i8 0) ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> [[A0:%.*]], <4 x i64> [[A1:%.*]], i8 0)
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%3 = insertelement <4 x i64> %1, i64 1, i64 3 %3 = insertelement <4 x i64> %1, i64 1, i64 3
%4 = insertelement <4 x i64> %2, i64 1, i64 3 %4 = insertelement <4 x i64> %2, i64 1, i64 3
%res = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %3, <4 x i64> %4, i8 17) %res = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %3, <4 x i64> %4, i8 17)
ret <4 x i64> %res ret <4 x i64> %res
} }
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_0() { define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_0() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_0( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_0(
; CHECK-NEXT: ret <4 x i64> zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, <4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, i8 0)
; CHECK-NEXT: ret <4 x i64> [[RES]]
; ;
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, <4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, i8 0) %1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, <4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, i8 0)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_1() { define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_1() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_1( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_1(
; CHECK-NEXT: ret <4 x i64> zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, <4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, i8 1)
; CHECK-NEXT: ret <4 x i64> [[RES]]
; ;
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, <4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, i8 1) %1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, <4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, i8 1)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_16() { define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_16() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_16( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_16(
; CHECK-NEXT: ret <4 x i64> zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 poison, i64 undef, i64 poison>, <4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, i8 16)
; CHECK-NEXT: ret <4 x i64> [[RES]]
; ;
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, <4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, i8 16) %1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 undef, i64 1, i64 undef, i64 1>, <4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, i8 16)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_17() { define <4 x i64> @test_demanded_elts_pclmulqdq_256_undef_17() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_17( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_256_undef_17(
; CHECK-NEXT: ret <4 x i64> zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, <4 x i64> <i64 poison, i64 undef, i64 poison, i64 undef>, i8 17)
; CHECK-NEXT: ret <4 x i64> [[RES]]
; ;
%1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, <4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, i8 17) %1 = call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, <4 x i64> <i64 1, i64 undef, i64 1, i64 undef>, i8 17)
ret <4 x i64> %1 ret <4 x i64> %1
} }
define <8 x i64> @test_demanded_elts_pclmulqdq_512_0(<8 x i64> %a0, <8 x i64> %a1) { define <8 x i64> @test_demanded_elts_pclmulqdq_512_0(<8 x i64> %a0, <8 x i64> %a1) {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_0( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_0(
; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1:%.*]], i8 0) ; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> [[A0:%.*]], <8 x i64> [[A1:%.*]], i8 0)
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%7 = insertelement <8 x i64> %5, i64 1, i64 7 %7 = insertelement <8 x i64> %5, i64 1, i64 7
%8 = insertelement <8 x i64> %6, i64 1, i64 7 %8 = insertelement <8 x i64> %6, i64 1, i64 7
%res = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %7, <8 x i64> %8, i8 17) %res = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %7, <8 x i64> %8, i8 17)
ret <8 x i64> %res ret <8 x i64> %res
} }
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_0() { define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_0() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_0( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_0(
; CHECK-NEXT: ret <8 x i64> zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, <8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, i8 0)
; CHECK-NEXT: ret <8 x i64> [[RES]]
; ;
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, <8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, i8 0) %1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, <8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, i8 0)
ret <8 x i64> %1 ret <8 x i64> %1
} }
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_1() { define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_1() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_1( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_1(
; CHECK-NEXT: ret <8 x i64> zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, <8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, i8 1)
; CHECK-NEXT: ret <8 x i64> [[RES]]
; ;
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, <8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, i8 1) %1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, <8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, i8 1)
ret <8 x i64> %1 ret <8 x i64> %1
} }
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_16() { define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_16() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_16( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_16(
; CHECK-NEXT: ret <8 x i64> zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison>, <8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, i8 16)
; CHECK-NEXT: ret <8 x i64> [[RES]]
; ;
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, <8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, i8 16) %1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1>, <8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, i8 16)
ret <8 x i64> %1 ret <8 x i64> %1
} }
define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_17() { define <8 x i64> @test_demanded_elts_pclmulqdq_512_undef_17() {
; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_17( ; CHECK-LABEL: @test_demanded_elts_pclmulqdq_512_undef_17(
; CHECK-NEXT: ret <8 x i64> zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, <8 x i64> <i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef, i64 poison, i64 undef>, i8 17)
; CHECK-NEXT: ret <8 x i64> [[RES]]
; ;
%1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, <8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, i8 17) %1 = call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, <8 x i64> <i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef, i64 1, i64 undef>, i8 17)
ret <8 x i64> %1 ret <8 x i64> %1
} }

llvm/test/Transforms/InstCombine/X86/x86-addsub.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s ; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>)
declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>)
declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>)
declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>)
declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #0 declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8 immarg) #0
; ;
; Demanded Elts ; Demanded Elts
; ;
define double @elts_addsub_v2f64(<2 x double> %0, <2 x double> %1) { define double @elts_addsub_v2f64(<2 x double> %0, <2 x double> %1) {
; CHECK-LABEL: @elts_addsub_v2f64( ; CHECK-LABEL: @elts_addsub_v2f64(
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1:%.*]], <2 x double> undef, <2 x i32> <i32 1, i32 poison> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1:%.*]], <2 x double> poison, <2 x i32> <i32 1, i32 poison>
; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> [[TMP0:%.*]], [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> [[TMP0:%.*]], [[TMP3]]
; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i64 0 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i64 0
; CHECK-NEXT: ret double [[TMP5]] ; CHECK-NEXT: ret double [[TMP5]]
; ;
%3 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 0, i32 0> %3 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 0, i32 0>
%4 = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> <i32 1, i32 1> %4 = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> <i32 1, i32 1>
%5 = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %3, <2 x double> %4) %5 = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %3, <2 x double> %4)
%6 = extractelement <2 x double> %5, i32 0 %6 = extractelement <2 x double> %5, i32 0
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%6 = extractelement <8 x float> %5, i32 0 %6 = extractelement <8 x float> %5, i32 0
%7 = extractelement <8 x float> %5, i32 4 %7 = extractelement <8 x float> %5, i32 4
%8 = fadd float %6, %7 %8 = fadd float %6, %7
ret float %8 ret float %8
} }
define void @PR46277(float %0, float %1, float %2, float %3, <4 x float> %4, ptr %5) { define void @PR46277(float %0, float %1, float %2, float %3, <4 x float> %4, ptr %5) {
; CHECK-LABEL: @PR46277( ; CHECK-LABEL: @PR46277(
; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> undef, float [[TMP0:%.*]], i64 0 ; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> poison, float [[TMP0:%.*]], i64 0
; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[TMP1:%.*]], i64 1 ; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> [[TMP7]], float [[TMP1:%.*]], i64 1
; CHECK-NEXT: [[TMP9:%.*]] = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> [[TMP8]], <4 x float> [[TMP4:%.*]]) ; CHECK-NEXT: [[TMP9:%.*]] = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> [[TMP8]], <4 x float> [[TMP4:%.*]])
; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x float> [[TMP9]], i64 0 ; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x float> [[TMP9]], i64 0
; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds float, ptr [[TMP5:%.*]], i64 1 ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds float, ptr [[TMP5:%.*]], i64 1
; CHECK-NEXT: store float [[TMP10]], ptr [[TMP5]], align 4 ; CHECK-NEXT: store float [[TMP10]], ptr [[TMP5]], align 4
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x float> [[TMP9]], i64 1 ; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x float> [[TMP9]], i64 1
; CHECK-NEXT: store float [[TMP12]], ptr [[TMP11]], align 4 ; CHECK-NEXT: store float [[TMP12]], ptr [[TMP11]], align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
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%t2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %t1, <2 x double> %x, i8 6) %t2 = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %t1, <2 x double> %x, i8 6)
%vecext = extractelement <2 x double> %t2, i32 0 %vecext = extractelement <2 x double> %t2, i32 0
ret double %vecext ret double %vecext
} }
define double @PR48476_fadd_fsub(<2 x double> %x) { define double @PR48476_fadd_fsub(<2 x double> %x) {
; CHECK-LABEL: @PR48476_fadd_fsub( ; CHECK-LABEL: @PR48476_fadd_fsub(
; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x double> [[X:%.*]], <double poison, double 0.000000e+00> ; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x double> [[X:%.*]], <double poison, double 0.000000e+00>
; CHECK-NEXT: [[S:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> undef, <2 x i32> <i32 1, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <2 x double> [[TMP1]], <2 x double> poison, <2 x i32> <i32 1, i32 poison>
; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> [[S]], [[X]] ; CHECK-NEXT: [[TMP2:%.*]] = fsub <2 x double> [[S]], [[X]]
; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <2 x double> [[TMP2]], i64 0 ; CHECK-NEXT: [[VECEXT:%.*]] = extractelement <2 x double> [[TMP2]], i64 0
; CHECK-NEXT: ret double [[VECEXT]] ; CHECK-NEXT: ret double [[VECEXT]]
; ;
%t1 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> zeroinitializer, <2 x double> %x) %t1 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> zeroinitializer, <2 x double> %x)
%s = shufflevector <2 x double> %t1, <2 x double> undef, <2 x i32> <i32 1, i32 0> %s = shufflevector <2 x double> %t1, <2 x double> undef, <2 x i32> <i32 1, i32 0>
%t2 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %s, <2 x double> %x) %t2 = call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %s, <2 x double> %x)
%vecext = extractelement <2 x double> %t2, i32 0 %vecext = extractelement <2 x double> %t2, i32 0
ret double %vecext ret double %vecext
} }

llvm/test/Transforms/InstCombine/X86/x86-avx2.ll

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%a = tail call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>) %a = tail call <8 x float> @llvm.x86.avx2.permps(<8 x float> %a0, <8 x i32> <i32 undef, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>)
ret <8 x float> %a ret <8 x float> %a
} }
; Verify simplify demanded elts. ; Verify simplify demanded elts.
define <8 x i32> @elts_test_vpermd(<8 x i32> %a0, i32 %a1) { define <8 x i32> @elts_test_vpermd(<8 x i32> %a0, i32 %a1) {
; CHECK-LABEL: @elts_test_vpermd( ; CHECK-LABEL: @elts_test_vpermd(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> undef, <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> poison, <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
; CHECK-NEXT: ret <8 x i32> [[TMP1]] ; CHECK-NEXT: ret <8 x i32> [[TMP1]]
; ;
%1 = insertelement <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, i32 %a1, i32 0 %1 = insertelement <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, i32 %a1, i32 0
%2 = tail call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> %1) %2 = tail call <8 x i32> @llvm.x86.avx2.permd(<8 x i32> %a0, <8 x i32> %1)
%3 = shufflevector <8 x i32> %2, <8 x i32> undef, <8 x i32> <i32 undef, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %3 = shufflevector <8 x i32> %2, <8 x i32> undef, <8 x i32> <i32 undef, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i32> %3 ret <8 x i32> %3
} }
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llvm/test/Transforms/InstCombine/X86/x86-avx512-inseltpoison.ll

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%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x float> @test_add_ss_round(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_add_ss_round(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_add_ss_round( ; CHECK-LABEL: @test_add_ss_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8) %4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
ret <4 x float> %4 ret <4 x float> %4
} }
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%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_add_sd_round(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_add_sd_round(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_add_sd_round( ; CHECK-LABEL: @test_add_sd_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8) %2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_add_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_add_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
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%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x float> @test_sub_ss_round(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_sub_ss_round(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_sub_ss_round( ; CHECK-LABEL: @test_sub_ss_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8) %4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
ret <4 x float> %4 ret <4 x float> %4
} }
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%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_sub_sd_round(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_sub_sd_round(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_sub_sd_round( ; CHECK-LABEL: @test_sub_sd_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8) %2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_sub_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_sub_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
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%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x float> @test_mul_ss_round(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_mul_ss_round(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_mul_ss_round( ; CHECK-LABEL: @test_mul_ss_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8) %4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
ret <4 x float> %4 ret <4 x float> %4
} }
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%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_mul_sd_round(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_mul_sd_round(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_mul_sd_round( ; CHECK-LABEL: @test_mul_sd_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8) %2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_mul_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_mul_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
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%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x float> @test_div_ss_round(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_div_ss_round(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_div_ss_round( ; CHECK-LABEL: @test_div_ss_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8) %4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
ret <4 x float> %4 ret <4 x float> %4
} }
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%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_div_sd_round(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_div_sd_round(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_div_sd_round( ; CHECK-LABEL: @test_div_sd_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8) %2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_div_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_div_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
Show All 39 Lines;
ret double %6 ret double %6
} }
declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
define <4 x float> @test_max_ss(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_max_ss(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_max_ss( ; CHECK-LABEL: @test_max_ss(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
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ret float %10 ret float %10
} }
declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
define <2 x double> @test_max_sd(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_max_sd(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_max_sd( ; CHECK-LABEL: @test_max_sd(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_max_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_max_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
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ret double %6 ret double %6
} }
declare <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) declare <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
define <4 x float> @test_min_ss(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_min_ss(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_min_ss( ; CHECK-LABEL: @test_min_ss(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
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ret float %10 ret float %10
} }
declare <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) declare <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
define <2 x double> @test_min_sd(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_min_sd(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_min_sd( ; CHECK-LABEL: @test_min_sd(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_min_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_min_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
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llvm/test/Transforms/InstCombine/X86/x86-avx512.ll

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%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x float> @test_add_ss_round(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_add_ss_round(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_add_ss_round( ; CHECK-LABEL: @test_add_ss_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8) %4 = tail call <4 x float> @llvm.x86.avx512.mask.add.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
ret <4 x float> %4 ret <4 x float> %4
} }
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%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_add_sd_round(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_add_sd_round(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_add_sd_round( ; CHECK-LABEL: @test_add_sd_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8) %2 = tail call <2 x double> @llvm.x86.avx512.mask.add.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_add_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_add_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
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%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x float> @test_sub_ss_round(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_sub_ss_round(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_sub_ss_round( ; CHECK-LABEL: @test_sub_ss_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8) %4 = tail call <4 x float> @llvm.x86.avx512.mask.sub.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
ret <4 x float> %4 ret <4 x float> %4
} }
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%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_sub_sd_round(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_sub_sd_round(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_sub_sd_round( ; CHECK-LABEL: @test_sub_sd_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8) %2 = tail call <2 x double> @llvm.x86.avx512.mask.sub.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_sub_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_sub_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
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%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x float> @test_mul_ss_round(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_mul_ss_round(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_mul_ss_round( ; CHECK-LABEL: @test_mul_ss_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8) %4 = tail call <4 x float> @llvm.x86.avx512.mask.mul.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
ret <4 x float> %4 ret <4 x float> %4
} }
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%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_mul_sd_round(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_mul_sd_round(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_mul_sd_round( ; CHECK-LABEL: @test_mul_sd_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8) %2 = tail call <2 x double> @llvm.x86.avx512.mask.mul.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_mul_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_mul_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
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%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
define <4 x float> @test_div_ss_round(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_div_ss_round(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_div_ss_round( ; CHECK-LABEL: @test_div_ss_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8) %4 = tail call <4 x float> @llvm.x86.avx512.mask.div.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 8)
ret <4 x float> %4 ret <4 x float> %4
} }
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%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_div_sd_round(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_div_sd_round(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_div_sd_round( ; CHECK-LABEL: @test_div_sd_round(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 8) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 8)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8) %2 = tail call <2 x double> @llvm.x86.avx512.mask.div.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 8)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_div_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_div_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
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ret double %6 ret double %6
} }
declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) declare <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
define <4 x float> @test_max_ss(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_max_ss(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_max_ss( ; CHECK-LABEL: @test_max_ss(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.max.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
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ret float %10 ret float %10
} }
declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) declare <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
define <2 x double> @test_max_sd(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_max_sd(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_max_sd( ; CHECK-LABEL: @test_max_sd(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.max.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_max_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_max_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
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ret double %6 ret double %6
} }
declare <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32) declare <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float>, <4 x float>, <4 x float>, i8, i32)
define <4 x float> @test_min_ss(<4 x float> %a, <4 x float> %b) { define <4 x float> @test_min_ss(<4 x float> %a, <4 x float> %b) {
; ;
; CHECK-LABEL: @test_min_ss( ; CHECK-LABEL: @test_min_ss(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> undef, i8 -1, i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> <float undef, float poison, float poison, float poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1 %1 = insertelement <4 x float> %b, float 1.000000e+00, i32 1
%2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2 %2 = insertelement <4 x float> %1, float 2.000000e+00, i32 2
%3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3 %3 = insertelement <4 x float> %2, float 3.000000e+00, i32 3
%4 = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4) %4 = tail call <4 x float> @llvm.x86.avx512.mask.min.ss.round(<4 x float> %a, <4 x float> %3, <4 x float> undef, i8 -1, i32 4)
ret <4 x float> %4 ret <4 x float> %4
} }
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ret float %10 ret float %10
} }
declare <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32) declare <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double>, <2 x double>, <2 x double>, i8, i32)
define <2 x double> @test_min_sd(<2 x double> %a, <2 x double> %b) { define <2 x double> @test_min_sd(<2 x double> %a, <2 x double> %b) {
; ;
; CHECK-LABEL: @test_min_sd( ; CHECK-LABEL: @test_min_sd(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> undef, i8 -1, i32 4) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> <double undef, double poison>, i8 -1, i32 4)
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1 %1 = insertelement <2 x double> %b, double 1.000000e+00, i32 1
%2 = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4) %2 = tail call <2 x double> @llvm.x86.avx512.mask.min.sd.round(<2 x double> %a, <2 x double> %1, <2 x double> undef, i8 -1, i32 4)
ret <2 x double> %2 ret <2 x double> %2
} }
define <2 x double> @test_min_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) { define <2 x double> @test_min_sd_mask(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 %mask) {
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llvm/test/Transforms/InstCombine/X86/x86-muldq.ll

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} }
; ;
; PMULUDQ/PMULDQ - only the even elements (0, 2, 4, 6) of the vXi32 inputs are required. ; PMULUDQ/PMULDQ - only the even elements (0, 2, 4, 6) of the vXi32 inputs are required.
; ;
define <2 x i64> @test_demanded_elts_pmuludq_128(<4 x i32> %a0, <4 x i32> %a1) { define <2 x i64> @test_demanded_elts_pmuludq_128(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuludq_128( ; CHECK-LABEL: @test_demanded_elts_pmuludq_128(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[A1:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[A1:%.*]], <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <2 x i64>
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to <2 x i64> ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to <2 x i64>
; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP3]], <i64 4294967295, i64 poison> ; CHECK-NEXT: [[TMP5:%.*]] = and <2 x i64> [[TMP3]], <i64 4294967295, i64 poison>
; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i64> [[TMP4]], <i64 4294967295, i64 poison> ; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i64> [[TMP4]], <i64 4294967295, i64 poison>
; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <2 x i64> [[TMP5]], [[TMP6]] ; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <2 x i64> [[TMP5]], [[TMP6]]
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i64> [[TMP7]], <2 x i64> undef, <2 x i32> zeroinitializer ; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i64> [[TMP7]], <2 x i64> undef, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i64> [[TMP8]] ; CHECK-NEXT: ret <2 x i64> [[TMP8]]
; ;
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> %1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
%2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3> %2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
%3 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %1, <4 x i32> %2) %3 = call <2 x i64> @llvm.x86.sse2.pmulu.dq(<4 x i32> %1, <4 x i32> %2)
%4 = shufflevector <2 x i64> %3, <2 x i64> undef, <2 x i32> zeroinitializer %4 = shufflevector <2 x i64> %3, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %4 ret <2 x i64> %4
} }
define <4 x i64> @test_demanded_elts_pmuludq_256(<8 x i32> %a0, <8 x i32> %a1) { define <4 x i64> @test_demanded_elts_pmuludq_256(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuludq_256( ; CHECK-LABEL: @test_demanded_elts_pmuludq_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> poison, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[A1:%.*]], <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[A1:%.*]], <8 x i32> poison, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to <4 x i64> ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to <4 x i64>
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to <4 x i64> ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to <4 x i64>
; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i64> [[TMP3]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> ; CHECK-NEXT: [[TMP5:%.*]] = and <4 x i64> [[TMP3]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
; CHECK-NEXT: [[TMP6:%.*]] = and <4 x i64> [[TMP4]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> ; CHECK-NEXT: [[TMP6:%.*]] = and <4 x i64> [[TMP4]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <4 x i64> [[TMP5]], [[TMP6]] ; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <4 x i64> [[TMP5]], [[TMP6]]
; CHECK-NEXT: ret <4 x i64> [[TMP7]] ; CHECK-NEXT: ret <4 x i64> [[TMP7]]
; ;
%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> %1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
%2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7> %2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
%3 = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> %1, <8 x i32> %2) %3 = call <4 x i64> @llvm.x86.avx2.pmulu.dq(<8 x i32> %1, <8 x i32> %2)
ret <4 x i64> %3 ret <4 x i64> %3
} }
define <8 x i64> @test_demanded_elts_pmuludq_512(<16 x i32> %a0, <16 x i32> %a1) { define <8 x i64> @test_demanded_elts_pmuludq_512(<16 x i32> %a0, <16 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuludq_512( ; CHECK-LABEL: @test_demanded_elts_pmuludq_512(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> poison, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[A1:%.*]], <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[A1:%.*]], <16 x i32> poison, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to <8 x i64> ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to <8 x i64>
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to <8 x i64> ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to <8 x i64>
; CHECK-NEXT: [[TMP5:%.*]] = and <8 x i64> [[TMP3]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> ; CHECK-NEXT: [[TMP5:%.*]] = and <8 x i64> [[TMP3]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
; CHECK-NEXT: [[TMP6:%.*]] = and <8 x i64> [[TMP4]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> ; CHECK-NEXT: [[TMP6:%.*]] = and <8 x i64> [[TMP4]], <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <8 x i64> [[TMP5]], [[TMP6]] ; CHECK-NEXT: [[TMP7:%.*]] = mul nuw <8 x i64> [[TMP5]], [[TMP6]]
; CHECK-NEXT: ret <8 x i64> [[TMP7]] ; CHECK-NEXT: ret <8 x i64> [[TMP7]]
; ;
%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14> %1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
%2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15> %2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
%3 = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %1, <16 x i32> %2) %3 = call <8 x i64> @llvm.x86.avx512.pmulu.dq.512(<16 x i32> %1, <16 x i32> %2)
ret <8 x i64> %3 ret <8 x i64> %3
} }
define <2 x i64> @test_demanded_elts_pmuldq_128(<4 x i32> %a0, <4 x i32> %a1) { define <2 x i64> @test_demanded_elts_pmuldq_128(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuldq_128( ; CHECK-LABEL: @test_demanded_elts_pmuldq_128(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A0:%.*]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[A1:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[A1:%.*]], <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <2 x i64>
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to <2 x i64> ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to <2 x i64>
; CHECK-NEXT: [[TMP5:%.*]] = shl <2 x i64> [[TMP3]], <i64 32, i64 32> ; CHECK-NEXT: [[TMP5:%.*]] = shl <2 x i64> [[TMP3]], <i64 32, i64 32>
; CHECK-NEXT: [[TMP6:%.*]] = ashr exact <2 x i64> [[TMP5]], <i64 32, i64 32> ; CHECK-NEXT: [[TMP6:%.*]] = ashr exact <2 x i64> [[TMP5]], <i64 32, i64 32>
; CHECK-NEXT: [[TMP7:%.*]] = shl <2 x i64> [[TMP4]], <i64 32, i64 32> ; CHECK-NEXT: [[TMP7:%.*]] = shl <2 x i64> [[TMP4]], <i64 32, i64 32>
; CHECK-NEXT: [[TMP8:%.*]] = ashr exact <2 x i64> [[TMP7]], <i64 32, i64 32> ; CHECK-NEXT: [[TMP8:%.*]] = ashr exact <2 x i64> [[TMP7]], <i64 32, i64 32>
; CHECK-NEXT: [[TMP9:%.*]] = mul nsw <2 x i64> [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP9:%.*]] = mul nsw <2 x i64> [[TMP6]], [[TMP8]]
; CHECK-NEXT: ret <2 x i64> [[TMP9]] ; CHECK-NEXT: ret <2 x i64> [[TMP9]]
; ;
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2> %1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
%2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3> %2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
%3 = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %1, <4 x i32> %2) %3 = call <2 x i64> @llvm.x86.sse41.pmuldq(<4 x i32> %1, <4 x i32> %2)
ret <2 x i64> %3 ret <2 x i64> %3
} }
define <4 x i64> @test_demanded_elts_pmuldq_256(<8 x i32> %a0, <8 x i32> %a1) { define <4 x i64> @test_demanded_elts_pmuldq_256(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuldq_256( ; CHECK-LABEL: @test_demanded_elts_pmuldq_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A0:%.*]], <8 x i32> poison, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[A1:%.*]], <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i32> [[A1:%.*]], <8 x i32> poison, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to <4 x i64> ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i32> [[TMP1]] to <4 x i64>
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to <4 x i64> ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to <4 x i64>
; CHECK-NEXT: [[TMP5:%.*]] = shl <4 x i64> [[TMP3]], <i64 32, i64 32, i64 32, i64 32> ; CHECK-NEXT: [[TMP5:%.*]] = shl <4 x i64> [[TMP3]], <i64 32, i64 32, i64 32, i64 32>
; CHECK-NEXT: [[TMP6:%.*]] = ashr exact <4 x i64> [[TMP5]], <i64 32, i64 32, i64 32, i64 32> ; CHECK-NEXT: [[TMP6:%.*]] = ashr exact <4 x i64> [[TMP5]], <i64 32, i64 32, i64 32, i64 32>
; CHECK-NEXT: [[TMP7:%.*]] = shl <4 x i64> [[TMP4]], <i64 32, i64 32, i64 32, i64 32> ; CHECK-NEXT: [[TMP7:%.*]] = shl <4 x i64> [[TMP4]], <i64 32, i64 32, i64 32, i64 32>
; CHECK-NEXT: [[TMP8:%.*]] = ashr exact <4 x i64> [[TMP7]], <i64 32, i64 32, i64 32, i64 32> ; CHECK-NEXT: [[TMP8:%.*]] = ashr exact <4 x i64> [[TMP7]], <i64 32, i64 32, i64 32, i64 32>
; CHECK-NEXT: [[TMP9:%.*]] = mul nsw <4 x i64> [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP9:%.*]] = mul nsw <4 x i64> [[TMP6]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i64> [[TMP9]], <4 x i64> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> ; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x i64> [[TMP9]], <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 3, i32 3>
; CHECK-NEXT: ret <4 x i64> [[TMP10]] ; CHECK-NEXT: ret <4 x i64> [[TMP10]]
; ;
%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> %1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6>
%2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7> %2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7>
%3 = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> %1, <8 x i32> %2) %3 = call <4 x i64> @llvm.x86.avx2.pmul.dq(<8 x i32> %1, <8 x i32> %2)
%4 = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3> %4 = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> <i32 0, i32 0, i32 3, i32 3>
ret <4 x i64> %4 ret <4 x i64> %4
} }
define <8 x i64> @test_demanded_elts_pmuldq_512(<16 x i32> %a0, <16 x i32> %a1) { define <8 x i64> @test_demanded_elts_pmuldq_512(<16 x i32> %a0, <16 x i32> %a1) {
; CHECK-LABEL: @test_demanded_elts_pmuldq_512( ; CHECK-LABEL: @test_demanded_elts_pmuldq_512(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A0:%.*]], <16 x i32> poison, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[A1:%.*]], <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[A1:%.*]], <16 x i32> poison, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to <8 x i64> ; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i32> [[TMP1]] to <8 x i64>
; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to <8 x i64> ; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i32> [[TMP2]] to <8 x i64>
; CHECK-NEXT: [[TMP5:%.*]] = shl <8 x i64> [[TMP3]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32> ; CHECK-NEXT: [[TMP5:%.*]] = shl <8 x i64> [[TMP3]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
; CHECK-NEXT: [[TMP6:%.*]] = ashr exact <8 x i64> [[TMP5]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32> ; CHECK-NEXT: [[TMP6:%.*]] = ashr exact <8 x i64> [[TMP5]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
; CHECK-NEXT: [[TMP7:%.*]] = shl <8 x i64> [[TMP4]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32> ; CHECK-NEXT: [[TMP7:%.*]] = shl <8 x i64> [[TMP4]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
; CHECK-NEXT: [[TMP8:%.*]] = ashr exact <8 x i64> [[TMP7]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32> ; CHECK-NEXT: [[TMP8:%.*]] = ashr exact <8 x i64> [[TMP7]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
; CHECK-NEXT: [[TMP9:%.*]] = mul nsw <8 x i64> [[TMP6]], [[TMP8]] ; CHECK-NEXT: [[TMP9:%.*]] = mul nsw <8 x i64> [[TMP6]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i64> [[TMP9]], <8 x i64> undef, <8 x i32> <i32 0, i32 0, i32 3, i32 3, i32 4, i32 4, i32 7, i32 7> ; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <8 x i64> [[TMP9]], <8 x i64> poison, <8 x i32> <i32 0, i32 0, i32 3, i32 3, i32 4, i32 4, i32 7, i32 7>
; CHECK-NEXT: ret <8 x i64> [[TMP10]] ; CHECK-NEXT: ret <8 x i64> [[TMP10]]
; ;
%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14> %1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6, i32 8, i32 8, i32 10, i32 10, i32 12, i32 12, i32 14, i32 14>
%2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15> %2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15, i32 15>
%3 = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %1, <16 x i32> %2) %3 = call <8 x i64> @llvm.x86.avx512.pmul.dq.512(<16 x i32> %1, <16 x i32> %2)
%4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> <i32 0, i32 0, i32 3, i32 3, i32 4, i32 4, i32 7, i32 7> %4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> <i32 0, i32 0, i32 3, i32 3, i32 4, i32 4, i32 7, i32 7>
ret <8 x i64> %4 ret <8 x i64> %4
} }
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llvm/test/Transforms/InstCombine/X86/x86-pack-inseltpoison.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s ; RUN: opt < %s -passes=instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s
; ;
; UNDEF Elts ; UNDEF Elts
; ;
define <8 x i16> @poison_packssdw_128() { define <8 x i16> @poison_packssdw_128() {
; CHECK-LABEL: @poison_packssdw_128( ; CHECK-LABEL: @poison_packssdw_128(
; CHECK-NEXT: ret <8 x i16> undef ; CHECK-NEXT: ret <8 x i16> poison
; ;
%1 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> poison, <4 x i32> poison) %1 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> poison, <4 x i32> poison)
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <8 x i16> @poison_packusdw_128() { define <8 x i16> @poison_packusdw_128() {
; CHECK-LABEL: @poison_packusdw_128( ; CHECK-LABEL: @poison_packusdw_128(
; CHECK-NEXT: ret <8 x i16> undef ; CHECK-NEXT: ret <8 x i16> poison
; ;
%1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> poison, <4 x i32> poison) %1 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> poison, <4 x i32> poison)
ret <8 x i16> %1 ret <8 x i16> %1
} }
define <16 x i8> @poison_packsswb_128() { define <16 x i8> @poison_packsswb_128() {
; CHECK-LABEL: @poison_packsswb_128( ; CHECK-LABEL: @poison_packsswb_128(
; CHECK-NEXT: ret <16 x i8> undef ; CHECK-NEXT: ret <16 x i8> poison
; ;
%1 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> poison, <8 x i16> poison) %1 = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> poison, <8 x i16> poison)
ret <16 x i8> %1 ret <16 x i8> %1
} }
define <16 x i8> @poison_packuswb_128() { define <16 x i8> @poison_packuswb_128() {
; CHECK-LABEL: @poison_packuswb_128( ; CHECK-LABEL: @poison_packuswb_128(
; CHECK-NEXT: ret <16 x i8> undef ; CHECK-NEXT: ret <16 x i8> poison
; ;
%1 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> poison, <8 x i16> poison) %1 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> poison, <8 x i16> poison)
ret <16 x i8> %1 ret <16 x i8> %1
} }
define <16 x i16> @poison_packssdw_256() { define <16 x i16> @poison_packssdw_256() {
; CHECK-LABEL: @poison_packssdw_256( ; CHECK-LABEL: @poison_packssdw_256(
; CHECK-NEXT: ret <16 x i16> undef ; CHECK-NEXT: ret <16 x i16> poison
; ;
%1 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> poison, <8 x i32> poison) %1 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> poison, <8 x i32> poison)
ret <16 x i16> %1 ret <16 x i16> %1
} }
define <16 x i16> @poison_packusdw_256() { define <16 x i16> @poison_packusdw_256() {
; CHECK-LABEL: @poison_packusdw_256( ; CHECK-LABEL: @poison_packusdw_256(
; CHECK-NEXT: ret <16 x i16> undef ; CHECK-NEXT: ret <16 x i16> poison
; ;
%1 = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> poison, <8 x i32> poison) %1 = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> poison, <8 x i32> poison)
ret <16 x i16> %1 ret <16 x i16> %1
} }
define <32 x i8> @poison_packsswb_256() { define <32 x i8> @poison_packsswb_256() {
; CHECK-LABEL: @poison_packsswb_256( ; CHECK-LABEL: @poison_packsswb_256(
; CHECK-NEXT: ret <32 x i8> undef ; CHECK-NEXT: ret <32 x i8> poison
; ;
%1 = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> poison, <16 x i16> poison) %1 = call <32 x i8> @llvm.x86.avx2.packsswb(<16 x i16> poison, <16 x i16> poison)
ret <32 x i8> %1 ret <32 x i8> %1
} }
define <32 x i8> @poison_packuswb_256() { define <32 x i8> @poison_packuswb_256() {
; CHECK-LABEL: @poison_packuswb_256( ; CHECK-LABEL: @poison_packuswb_256(
; CHECK-NEXT: ret <32 x i8> undef ; CHECK-NEXT: ret <32 x i8> poison
; ;
%1 = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> poison, <16 x i16> poison) %1 = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> poison, <16 x i16> poison)
ret <32 x i8> %1 ret <32 x i8> %1
} }
define <32 x i16> @poison_packssdw_512() { define <32 x i16> @poison_packssdw_512() {
; CHECK-LABEL: @poison_packssdw_512( ; CHECK-LABEL: @poison_packssdw_512(
; CHECK-NEXT: ret <32 x i16> undef ; CHECK-NEXT: ret <32 x i16> poison
; ;
%1 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> poison, <16 x i32> poison) %1 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> poison, <16 x i32> poison)
ret <32 x i16> %1 ret <32 x i16> %1
} }
define <32 x i16> @poison_packusdw_512() { define <32 x i16> @poison_packusdw_512() {
; CHECK-LABEL: @poison_packusdw_512( ; CHECK-LABEL: @poison_packusdw_512(
; CHECK-NEXT: ret <32 x i16> undef ; CHECK-NEXT: ret <32 x i16> poison
; ;
%1 = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> poison, <16 x i32> poison) %1 = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> poison, <16 x i32> poison)
ret <32 x i16> %1 ret <32 x i16> %1
} }
define <64 x i8> @poison_packsswb_512() { define <64 x i8> @poison_packsswb_512() {
; CHECK-LABEL: @poison_packsswb_512( ; CHECK-LABEL: @poison_packsswb_512(
; CHECK-NEXT: ret <64 x i8> undef ; CHECK-NEXT: ret <64 x i8> poison
; ;
%1 = call <64 x i8> @llvm.x86.avx512.packsswb.512(<32 x i16> poison, <32 x i16> poison) %1 = call <64 x i8> @llvm.x86.avx512.packsswb.512(<32 x i16> poison, <32 x i16> poison)
ret <64 x i8> %1 ret <64 x i8> %1
} }
define <64 x i8> @poison_packuswb_512() { define <64 x i8> @poison_packuswb_512() {
; CHECK-LABEL: @poison_packuswb_512( ; CHECK-LABEL: @poison_packuswb_512(
; CHECK-NEXT: ret <64 x i8> undef ; CHECK-NEXT: ret <64 x i8> poison
; ;
%1 = call <64 x i8> @llvm.x86.avx512.packuswb.512(<32 x i16> poison, <32 x i16> poison) %1 = call <64 x i8> @llvm.x86.avx512.packuswb.512(<32 x i16> poison, <32 x i16> poison)
ret <64 x i8> %1 ret <64 x i8> %1
} }
; ;
; Constant Folding ; Constant Folding
; ;
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
} }
; ;
; Demanded Elts ; Demanded Elts
; ;
define <8 x i16> @elts_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) { define <8 x i16> @elts_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: @elts_packssdw_128( ; CHECK-LABEL: @elts_packssdw_128(
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[A0:%.*]], <4 x i32> undef) ; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[A0:%.*]], <4 x i32> poison)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <8 x i16> [[TMP2]] ; CHECK-NEXT: ret <8 x i16> [[TMP2]]
; ;
%1 = shufflevector <4 x i32> %a0, <4 x i32> poison, <4 x i32> <i32 3, i32 1, i32 poison, i32 poison> %1 = shufflevector <4 x i32> %a0, <4 x i32> poison, <4 x i32> <i32 3, i32 1, i32 poison, i32 poison>
%2 = shufflevector <4 x i32> %a1, <4 x i32> poison, <4 x i32> <i32 poison, i32 2, i32 1, i32 poison> %2 = shufflevector <4 x i32> %a1, <4 x i32> poison, <4 x i32> <i32 poison, i32 2, i32 1, i32 poison>
%3 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %1, <4 x i32> %2) %3 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %1, <4 x i32> %2)
%4 = shufflevector <8 x i16> %3, <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 7, i32 7, i32 7, i32 7> %4 = shufflevector <8 x i16> %3, <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 7, i32 7, i32 7, i32 7>
ret <8 x i16> %4 ret <8 x i16> %4
Show All 31 Lines;
%2 = insertelement <8 x i16> poison, i16 0, i32 0 %2 = insertelement <8 x i16> poison, i16 0, i32 0
%3 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %1, <8 x i16> %2) %3 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %1, <8 x i16> %2)
%4 = shufflevector <16 x i8> %3, <16 x i8> poison, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15> %4 = shufflevector <16 x i8> %3, <16 x i8> poison, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i16> @elts_packssdw_256(<8 x i32> %a0, <8 x i32> %a1) { define <16 x i16> @elts_packssdw_256(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-LABEL: @elts_packssdw_256( ; CHECK-LABEL: @elts_packssdw_256(
; CHECK-NEXT: [[TMP1:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[A0:%.*]], <8 x i32> undef) ; CHECK-NEXT: [[TMP1:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[A0:%.*]], <8 x i32> poison)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> poison, <16 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 8, i32 poison, i32 poison, i32 11, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> poison, <16 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 8, i32 poison, i32 poison, i32 11, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <16 x i16> [[TMP2]] ; CHECK-NEXT: ret <16 x i16> [[TMP2]]
; ;
%1 = shufflevector <8 x i32> %a0, <8 x i32> poison, <8 x i32> <i32 1, i32 0, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %1 = shufflevector <8 x i32> %a0, <8 x i32> poison, <8 x i32> <i32 1, i32 0, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%2 = shufflevector <8 x i32> %a1, <8 x i32> poison, <8 x i32> <i32 poison, i32 2, i32 1, i32 poison, i32 poison, i32 6, i32 5, i32 poison> %2 = shufflevector <8 x i32> %a1, <8 x i32> poison, <8 x i32> <i32 poison, i32 2, i32 1, i32 poison, i32 poison, i32 6, i32 5, i32 poison>
%3 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %1, <8 x i32> %2) %3 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %1, <8 x i32> %2)
%4 = shufflevector <16 x i16> %3, <16 x i16> poison, <16 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 4, i32 poison, i32 poison, i32 7, i32 8, i32 poison, i32 poison, i32 11, i32 12, i32 poison, i32 poison, i32 15> %4 = shufflevector <16 x i16> %3, <16 x i16> poison, <16 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 4, i32 poison, i32 poison, i32 7, i32 8, i32 poison, i32 poison, i32 11, i32 12, i32 poison, i32 poison, i32 15>
ret <16 x i16> %4 ret <16 x i16> %4
Show All 32 Lines;
%2 = insertelement <16 x i16> poison, i16 0, i32 0 %2 = insertelement <16 x i16> poison, i16 0, i32 0
%3 = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %1, <16 x i16> %2) %3 = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %1, <16 x i16> %2)
%4 = shufflevector <32 x i8> %3, <32 x i8> poison, <32 x i32> zeroinitializer %4 = shufflevector <32 x i8> %3, <32 x i8> poison, <32 x i32> zeroinitializer
ret <32 x i8> %4 ret <32 x i8> %4
} }
define <32 x i16> @elts_packssdw_512(<16 x i32> %a0, <16 x i32> %a1) { define <32 x i16> @elts_packssdw_512(<16 x i32> %a0, <16 x i32> %a1) {
; CHECK-LABEL: @elts_packssdw_512( ; CHECK-LABEL: @elts_packssdw_512(
; CHECK-NEXT: [[TMP1:%.*]] = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> [[A0:%.*]], <16 x i32> undef) ; CHECK-NEXT: [[TMP1:%.*]] = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> [[A0:%.*]], <16 x i32> poison)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <32 x i16> [[TMP1]], <32 x i16> poison, <32 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 8, i32 poison, i32 poison, i32 11, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 18, i32 19, i32 poison, i32 poison, i32 poison, i32 poison, i32 24, i32 poison, i32 poison, i32 27, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <32 x i16> [[TMP1]], <32 x i16> poison, <32 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 8, i32 poison, i32 poison, i32 11, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 18, i32 19, i32 poison, i32 poison, i32 poison, i32 poison, i32 24, i32 poison, i32 poison, i32 27, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <32 x i16> [[TMP2]] ; CHECK-NEXT: ret <32 x i16> [[TMP2]]
; ;
%1 = shufflevector <16 x i32> %a0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %1 = shufflevector <16 x i32> %a0, <16 x i32> poison, <16 x i32> <i32 1, i32 0, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%2 = shufflevector <16 x i32> %a1, <16 x i32> poison, <16 x i32> <i32 poison, i32 2, i32 1, i32 poison, i32 poison, i32 6, i32 5, i32 poison, i32 poison, i32 10, i32 9, i32 poison, i32 poison, i32 14, i32 13, i32 poison> %2 = shufflevector <16 x i32> %a1, <16 x i32> poison, <16 x i32> <i32 poison, i32 2, i32 1, i32 poison, i32 poison, i32 6, i32 5, i32 poison, i32 poison, i32 10, i32 9, i32 poison, i32 poison, i32 14, i32 13, i32 poison>
%3 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> %1, <16 x i32> %2) %3 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> %1, <16 x i32> %2)
%4 = shufflevector <32 x i16> %3, <32 x i16> poison, <32 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 4, i32 poison, i32 poison, i32 7, i32 8, i32 poison, i32 poison, i32 11, i32 12, i32 poison, i32 poison, i32 15, i32 poison, i32 poison, i32 18, i32 19, i32 20, i32 poison, i32 poison, i32 23, i32 24, i32 poison, i32 poison, i32 27, i32 28, i32 poison, i32 poison, i32 31> %4 = shufflevector <32 x i16> %3, <32 x i16> poison, <32 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 4, i32 poison, i32 poison, i32 7, i32 8, i32 poison, i32 poison, i32 11, i32 12, i32 poison, i32 poison, i32 15, i32 poison, i32 poison, i32 18, i32 19, i32 20, i32 poison, i32 poison, i32 23, i32 24, i32 poison, i32 poison, i32 27, i32 28, i32 poison, i32 poison, i32 31>
ret <32 x i16> %4 ret <32 x i16> %4
▲ Show 20 Lines • Show All 320 Lines • Show Last 20 Lines

llvm/test/Transforms/InstCombine/X86/x86-pack.ll

Show First 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
} }
; ;
; Demanded Elts ; Demanded Elts
; ;
define <8 x i16> @elts_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) { define <8 x i16> @elts_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: @elts_packssdw_128( ; CHECK-LABEL: @elts_packssdw_128(
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[A0:%.*]], <4 x i32> undef) ; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> [[A0:%.*]], <4 x i32> poison)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <8 x i16> [[TMP2]] ; CHECK-NEXT: ret <8 x i16> [[TMP2]]
; ;
%1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 undef, i32 undef> %1 = shufflevector <4 x i32> %a0, <4 x i32> undef, <4 x i32> <i32 3, i32 1, i32 undef, i32 undef>
%2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 1, i32 undef> %2 = shufflevector <4 x i32> %a1, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 1, i32 undef>
%3 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %1, <4 x i32> %2) %3 = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %1, <4 x i32> %2)
%4 = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 7, i32 7, i32 7, i32 7> %4 = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 7, i32 7, i32 7, i32 7>
ret <8 x i16> %4 ret <8 x i16> %4
} }
define <8 x i16> @elts_packusdw_128(<4 x i32> %a0, <4 x i32> %a1) { define <8 x i16> @elts_packusdw_128(<4 x i32> %a0, <4 x i32> %a1) {
; CHECK-LABEL: @elts_packusdw_128( ; CHECK-LABEL: @elts_packusdw_128(
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> [[A0:%.*]], <4 x i32> [[A1:%.*]])
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 poison> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 poison>
; CHECK-NEXT: ret <8 x i16> [[TMP2]] ; CHECK-NEXT: ret <8 x i16> [[TMP2]]
; ;
%1 = insertelement <4 x i32> %a0, i32 0, i32 0 %1 = insertelement <4 x i32> %a0, i32 0, i32 0
%2 = insertelement <4 x i32> %a1, i32 0, i32 3 %2 = insertelement <4 x i32> %a1, i32 0, i32 3
%3 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %1, <4 x i32> %2) %3 = call <8 x i16> @llvm.x86.sse41.packusdw(<4 x i32> %1, <4 x i32> %2)
%4 = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> <i32 undef, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 undef> %4 = shufflevector <8 x i16> %3, <8 x i16> undef, <8 x i32> <i32 undef, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 undef>
ret <8 x i16> %4 ret <8 x i16> %4
} }
Show All 17 Lines;
%2 = insertelement <8 x i16> undef, i16 0, i32 0 %2 = insertelement <8 x i16> undef, i16 0, i32 0
%3 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %1, <8 x i16> %2) %3 = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %1, <8 x i16> %2)
%4 = shufflevector <16 x i8> %3, <16 x i8> undef, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15> %4 = shufflevector <16 x i8> %3, <16 x i8> undef, <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <16 x i16> @elts_packssdw_256(<8 x i32> %a0, <8 x i32> %a1) { define <16 x i16> @elts_packssdw_256(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-LABEL: @elts_packssdw_256( ; CHECK-LABEL: @elts_packssdw_256(
; CHECK-NEXT: [[TMP1:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[A0:%.*]], <8 x i32> undef) ; CHECK-NEXT: [[TMP1:%.*]] = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> [[A0:%.*]], <8 x i32> poison)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> undef, <16 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 8, i32 poison, i32 poison, i32 11, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i16> [[TMP1]], <16 x i16> poison, <16 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 8, i32 poison, i32 poison, i32 11, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <16 x i16> [[TMP2]] ; CHECK-NEXT: ret <16 x i16> [[TMP2]]
; ;
%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 undef, i32 2, i32 1, i32 undef, i32 undef, i32 6, i32 5, i32 undef> %2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 undef, i32 2, i32 1, i32 undef, i32 undef, i32 6, i32 5, i32 undef>
%3 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %1, <8 x i32> %2) %3 = call <16 x i16> @llvm.x86.avx2.packssdw(<8 x i32> %1, <8 x i32> %2)
%4 = shufflevector <16 x i16> %3, <16 x i16> undef, <16 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 undef, i32 undef, i32 11, i32 12, i32 undef, i32 undef, i32 15> %4 = shufflevector <16 x i16> %3, <16 x i16> undef, <16 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 undef, i32 undef, i32 11, i32 12, i32 undef, i32 undef, i32 15>
ret <16 x i16> %4 ret <16 x i16> %4
} }
define <16 x i16> @elts_packusdw_256(<8 x i32> %a0, <8 x i32> %a1) { define <16 x i16> @elts_packusdw_256(<8 x i32> %a0, <8 x i32> %a1) {
; CHECK-LABEL: @elts_packusdw_256( ; CHECK-LABEL: @elts_packusdw_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A1:%.*]], <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A1:%.*]], <8 x i32> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> poison, <8 x i32> [[TMP1]]) ; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> poison, <8 x i32> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i16> [[TMP2]], <16 x i16> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <16 x i16> [[TMP2]], <16 x i16> poison, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <16 x i16> [[TMP3]] ; CHECK-NEXT: ret <16 x i16> [[TMP3]]
; ;
%1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> %1 = shufflevector <8 x i32> %a0, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %2 = shufflevector <8 x i32> %a1, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%3 = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> %1, <8 x i32> %2) %3 = call <16 x i16> @llvm.x86.avx2.packusdw(<8 x i32> %1, <8 x i32> %2)
%4 = shufflevector <16 x i16> %3, <16 x i16> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef> %4 = shufflevector <16 x i16> %3, <16 x i16> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef>
ret <16 x i16> %4 ret <16 x i16> %4
} }
Show All 17 Lines;
%2 = insertelement <16 x i16> undef, i16 0, i32 0 %2 = insertelement <16 x i16> undef, i16 0, i32 0
%3 = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %1, <16 x i16> %2) %3 = call <32 x i8> @llvm.x86.avx2.packuswb(<16 x i16> %1, <16 x i16> %2)
%4 = shufflevector <32 x i8> %3, <32 x i8> undef, <32 x i32> zeroinitializer %4 = shufflevector <32 x i8> %3, <32 x i8> undef, <32 x i32> zeroinitializer
ret <32 x i8> %4 ret <32 x i8> %4
} }
define <32 x i16> @elts_packssdw_512(<16 x i32> %a0, <16 x i32> %a1) { define <32 x i16> @elts_packssdw_512(<16 x i32> %a0, <16 x i32> %a1) {
; CHECK-LABEL: @elts_packssdw_512( ; CHECK-LABEL: @elts_packssdw_512(
; CHECK-NEXT: [[TMP1:%.*]] = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> [[A0:%.*]], <16 x i32> undef) ; CHECK-NEXT: [[TMP1:%.*]] = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> [[A0:%.*]], <16 x i32> poison)
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <32 x i16> [[TMP1]], <32 x i16> undef, <32 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 8, i32 poison, i32 poison, i32 11, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 18, i32 19, i32 poison, i32 poison, i32 poison, i32 poison, i32 24, i32 poison, i32 poison, i32 27, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <32 x i16> [[TMP1]], <32 x i16> poison, <32 x i32> <i32 poison, i32 poison, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 8, i32 poison, i32 poison, i32 11, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 18, i32 19, i32 poison, i32 poison, i32 poison, i32 poison, i32 24, i32 poison, i32 poison, i32 27, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <32 x i16> [[TMP2]] ; CHECK-NEXT: ret <32 x i16> [[TMP2]]
; ;
%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 1, i32 0, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 1, i32 0, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 undef, i32 2, i32 1, i32 undef, i32 undef, i32 6, i32 5, i32 undef, i32 undef, i32 10, i32 9, i32 undef, i32 undef, i32 14, i32 13, i32 undef> %2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 undef, i32 2, i32 1, i32 undef, i32 undef, i32 6, i32 5, i32 undef, i32 undef, i32 10, i32 9, i32 undef, i32 undef, i32 14, i32 13, i32 undef>
%3 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> %1, <16 x i32> %2) %3 = call <32 x i16> @llvm.x86.avx512.packssdw.512(<16 x i32> %1, <16 x i32> %2)
%4 = shufflevector <32 x i16> %3, <32 x i16> undef, <32 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 undef, i32 undef, i32 11, i32 12, i32 undef, i32 undef, i32 15, i32 undef, i32 undef, i32 18, i32 19, i32 20, i32 undef, i32 undef, i32 23, i32 24, i32 undef, i32 undef, i32 27, i32 28, i32 undef, i32 undef, i32 31> %4 = shufflevector <32 x i16> %3, <32 x i16> undef, <32 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 undef, i32 undef, i32 11, i32 12, i32 undef, i32 undef, i32 15, i32 undef, i32 undef, i32 18, i32 19, i32 20, i32 undef, i32 undef, i32 23, i32 24, i32 undef, i32 undef, i32 27, i32 28, i32 undef, i32 undef, i32 31>
ret <32 x i16> %4 ret <32 x i16> %4
} }
define <32 x i16> @elts_packusdw_512(<16 x i32> %a0, <16 x i32> %a1) { define <32 x i16> @elts_packusdw_512(<16 x i32> %a0, <16 x i32> %a1) {
; CHECK-LABEL: @elts_packusdw_512( ; CHECK-LABEL: @elts_packusdw_512(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A1:%.*]], <16 x i32> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i32> [[A1:%.*]], <16 x i32> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
; CHECK-NEXT: [[TMP2:%.*]] = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> poison, <16 x i32> [[TMP1]]) ; CHECK-NEXT: [[TMP2:%.*]] = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> poison, <16 x i32> [[TMP1]])
; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <32 x i16> [[TMP2]], <32 x i16> undef, <32 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 20, i32 21, i32 22, i32 23, i32 poison, i32 poison, i32 poison, i32 poison, i32 28, i32 29, i32 30, i32 31, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <32 x i16> [[TMP2]], <32 x i16> poison, <32 x i32> <i32 4, i32 5, i32 6, i32 7, i32 poison, i32 poison, i32 poison, i32 poison, i32 12, i32 13, i32 14, i32 15, i32 poison, i32 poison, i32 poison, i32 poison, i32 20, i32 21, i32 22, i32 23, i32 poison, i32 poison, i32 poison, i32 poison, i32 28, i32 29, i32 30, i32 31, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <32 x i16> [[TMP3]] ; CHECK-NEXT: ret <32 x i16> [[TMP3]]
; ;
%1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %1 = shufflevector <16 x i32> %a0, <16 x i32> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> %2 = shufflevector <16 x i32> %a1, <16 x i32> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
%3 = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> %1, <16 x i32> %2) %3 = call <32 x i16> @llvm.x86.avx512.packusdw.512(<16 x i32> %1, <16 x i32> %2)
%4 = shufflevector <32 x i16> %3, <32 x i16> undef, <32 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef> %4 = shufflevector <32 x i16> %3, <32 x i16> undef, <32 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 20, i32 21, i32 22, i32 23, i32 undef, i32 undef, i32 undef, i32 undef, i32 28, i32 29, i32 30, i32 31, i32 undef, i32 undef, i32 undef, i32 undef>
ret <32 x i16> %4 ret <32 x i16> %4
} }
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llvm/test/Transforms/InstCombine/X86/x86-pshufb-inseltpoison.ll

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; CHECK-NEXT: ret <64 x i8> [[TMP1]] ; CHECK-NEXT: ret <64 x i8> [[TMP1]]
; ;
%1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 0, i8 -128, i8 poison, i8 -128, i8 1, i8 -128, i8 poison, i8 -128, i8 2, i8 -128, i8 poison, i8 -128, i8 3, i8 -128, i8 poison, i8 -128, i8 0, i8 -128, i8 poison, i8 -128, i8 1, i8 -128, i8 poison, i8 -128, i8 2, i8 -128, i8 poison, i8 -128, i8 3, i8 -128, i8 poison, i8 -128, i8 0, i8 -128, i8 poison, i8 -128, i8 1, i8 -128, i8 poison, i8 -128, i8 2, i8 -128, i8 poison, i8 -128, i8 3, i8 -128, i8 poison, i8 -128, i8 0, i8 -128, i8 poison, i8 -128, i8 1, i8 -128, i8 poison, i8 -128, i8 2, i8 -128, i8 poison, i8 -128, i8 3, i8 -128, i8 poison, i8 -128>) %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 0, i8 -128, i8 poison, i8 -128, i8 1, i8 -128, i8 poison, i8 -128, i8 2, i8 -128, i8 poison, i8 -128, i8 3, i8 -128, i8 poison, i8 -128, i8 0, i8 -128, i8 poison, i8 -128, i8 1, i8 -128, i8 poison, i8 -128, i8 2, i8 -128, i8 poison, i8 -128, i8 3, i8 -128, i8 poison, i8 -128, i8 0, i8 -128, i8 poison, i8 -128, i8 1, i8 -128, i8 poison, i8 -128, i8 2, i8 -128, i8 poison, i8 -128, i8 3, i8 -128, i8 poison, i8 -128, i8 0, i8 -128, i8 poison, i8 -128, i8 1, i8 -128, i8 poison, i8 -128, i8 2, i8 -128, i8 poison, i8 -128, i8 3, i8 -128, i8 poison, i8 -128>)
ret <64 x i8> %1 ret <64 x i8> %1
} }
define <16 x i8> @fold_with_allpoison_elts(<16 x i8> %InVec) { define <16 x i8> @fold_with_allpoison_elts(<16 x i8> %InVec) {
; CHECK-LABEL: @fold_with_allpoison_elts( ; CHECK-LABEL: @fold_with_allpoison_elts(
; CHECK-NEXT: ret <16 x i8> undef ; CHECK-NEXT: ret <16 x i8> poison
; ;
%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> poison) %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> poison)
ret <16 x i8> %1 ret <16 x i8> %1
} }
define <32 x i8> @fold_with_allpoison_elts_avx2(<32 x i8> %InVec) { define <32 x i8> @fold_with_allpoison_elts_avx2(<32 x i8> %InVec) {
; CHECK-LABEL: @fold_with_allpoison_elts_avx2( ; CHECK-LABEL: @fold_with_allpoison_elts_avx2(
; CHECK-NEXT: ret <32 x i8> undef ; CHECK-NEXT: ret <32 x i8> poison
; ;
%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> poison) %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> poison)
ret <32 x i8> %1 ret <32 x i8> %1
} }
define <64 x i8> @fold_with_allpoison_elts_avx512(<64 x i8> %InVec) { define <64 x i8> @fold_with_allpoison_elts_avx512(<64 x i8> %InVec) {
; CHECK-LABEL: @fold_with_allpoison_elts_avx512( ; CHECK-LABEL: @fold_with_allpoison_elts_avx512(
; CHECK-NEXT: ret <64 x i8> undef ; CHECK-NEXT: ret <64 x i8> poison
; ;
%1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> poison) %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> poison)
ret <64 x i8> %1 ret <64 x i8> %1
} }
; Demanded elts tests. ; Demanded elts tests.
define <16 x i8> @demanded_elts_insertion(<16 x i8> %InVec, <16 x i8> %BaseMask, i8 %M0, i8 %M15) { define <16 x i8> @demanded_elts_insertion(<16 x i8> %InVec, <16 x i8> %BaseMask, i8 %M0, i8 %M15) {
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llvm/test/Transforms/InstCombine/X86/x86-pshufb.ll

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; CHECK-NEXT: ret <64 x i8> [[TMP1]] ; CHECK-NEXT: ret <64 x i8> [[TMP1]]
; ;
%1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128, i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128, i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128, i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128>) %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> <i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128, i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128, i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128, i8 0, i8 -128, i8 undef, i8 -128, i8 1, i8 -128, i8 undef, i8 -128, i8 2, i8 -128, i8 undef, i8 -128, i8 3, i8 -128, i8 undef, i8 -128>)
ret <64 x i8> %1 ret <64 x i8> %1
} }
define <16 x i8> @fold_with_allundef_elts(<16 x i8> %InVec) { define <16 x i8> @fold_with_allundef_elts(<16 x i8> %InVec) {
; CHECK-LABEL: @fold_with_allundef_elts( ; CHECK-LABEL: @fold_with_allundef_elts(
; CHECK-NEXT: ret <16 x i8> undef ; CHECK-NEXT: ret <16 x i8> poison
; ;
%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> undef) %1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> undef)
ret <16 x i8> %1 ret <16 x i8> %1
} }
define <32 x i8> @fold_with_allundef_elts_avx2(<32 x i8> %InVec) { define <32 x i8> @fold_with_allundef_elts_avx2(<32 x i8> %InVec) {
; CHECK-LABEL: @fold_with_allundef_elts_avx2( ; CHECK-LABEL: @fold_with_allundef_elts_avx2(
; CHECK-NEXT: ret <32 x i8> undef ; CHECK-NEXT: ret <32 x i8> poison
; ;
%1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> undef) %1 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> undef)
ret <32 x i8> %1 ret <32 x i8> %1
} }
define <64 x i8> @fold_with_allundef_elts_avx512(<64 x i8> %InVec) { define <64 x i8> @fold_with_allundef_elts_avx512(<64 x i8> %InVec) {
; CHECK-LABEL: @fold_with_allundef_elts_avx512( ; CHECK-LABEL: @fold_with_allundef_elts_avx512(
; CHECK-NEXT: ret <64 x i8> undef ; CHECK-NEXT: ret <64 x i8> poison
; ;
%1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> undef) %1 = tail call <64 x i8> @llvm.x86.avx512.pshuf.b.512(<64 x i8> %InVec, <64 x i8> undef)
ret <64 x i8> %1 ret <64 x i8> %1
} }
; Demanded elts tests. ; Demanded elts tests.
define <16 x i8> @demanded_elts_insertion(<16 x i8> %InVec, <16 x i8> %BaseMask, i8 %M0, i8 %M15) { define <16 x i8> @demanded_elts_insertion(<16 x i8> %InVec, <16 x i8> %BaseMask, i8 %M0, i8 %M15) {
; CHECK-LABEL: @demanded_elts_insertion( ; CHECK-LABEL: @demanded_elts_insertion(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> [[INVEC:%.*]], <16 x i8> [[BASEMASK:%.*]]) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> [[INVEC:%.*]], <16 x i8> [[BASEMASK:%.*]])
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> undef, <16 x i32> <i32 poison, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 poison> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 poison, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 poison>
; CHECK-NEXT: ret <16 x i8> [[TMP2]] ; CHECK-NEXT: ret <16 x i8> [[TMP2]]
; ;
%1 = insertelement <16 x i8> %BaseMask, i8 %M0, i32 0 %1 = insertelement <16 x i8> %BaseMask, i8 %M0, i32 0
%2 = insertelement <16 x i8> %1, i8 %M15, i32 15 %2 = insertelement <16 x i8> %1, i8 %M15, i32 15
%3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> %2) %3 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %InVec, <16 x i8> %2)
%4 = shufflevector <16 x i8> %3, <16 x i8> undef, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 undef> %4 = shufflevector <16 x i8> %3, <16 x i8> undef, <16 x i32> <i32 undef, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 undef>
ret <16 x i8> %4 ret <16 x i8> %4
} }
define <32 x i8> @demanded_elts_insertion_avx2(<32 x i8> %InVec, <32 x i8> %BaseMask, i8 %M0, i8 %M22) { define <32 x i8> @demanded_elts_insertion_avx2(<32 x i8> %InVec, <32 x i8> %BaseMask, i8 %M0, i8 %M22) {
; CHECK-LABEL: @demanded_elts_insertion_avx2( ; CHECK-LABEL: @demanded_elts_insertion_avx2(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> [[INVEC:%.*]], <32 x i8> [[BASEMASK:%.*]]) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> [[INVEC:%.*]], <32 x i8> [[BASEMASK:%.*]])
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <32 x i8> [[TMP1]], <32 x i8> undef, <32 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 poison, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <32 x i8> [[TMP1]], <32 x i8> poison, <32 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 poison, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
; CHECK-NEXT: ret <32 x i8> [[TMP2]] ; CHECK-NEXT: ret <32 x i8> [[TMP2]]
; ;
%1 = insertelement <32 x i8> %BaseMask, i8 %M0, i32 0 %1 = insertelement <32 x i8> %BaseMask, i8 %M0, i32 0
%2 = insertelement <32 x i8> %1, i8 %M22, i32 22 %2 = insertelement <32 x i8> %1, i8 %M22, i32 22
%3 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> %2) %3 = tail call <32 x i8> @llvm.x86.avx2.pshuf.b(<32 x i8> %InVec, <32 x i8> %2)
%4 = shufflevector <32 x i8> %3, <32 x i8> undef, <32 x i32> <i32 undef, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 undef, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31> %4 = shufflevector <32 x i8> %3, <32 x i8> undef, <32 x i32> <i32 undef, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 undef, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
ret <32 x i8> %4 ret <32 x i8> %4
} }
Show All 18 Lines

llvm/test/Transforms/InstCombine/X86/x86-sse4a-inseltpoison.ll

Show First 20 Lines • Show All 316 Lines • ▼ Show 20 Lines;
%1 = shufflevector <2 x i64> %x, <2 x i64> poison, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %x, <2 x i64> poison, <2 x i32> <i32 0, i32 0>
%2 = shufflevector <16 x i8> %y, <16 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> %2 = shufflevector <16 x i8> %y, <16 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
%3 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %1, <16 x i8> %2) nounwind %3 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %1, <16 x i8> %2) nounwind
ret <2 x i64> %3 ret <2 x i64> %3
} }
define <2 x i64> @test_extrq_ret(<2 x i64> %x, <16 x i8> %y) { define <2 x i64> @test_extrq_ret(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_ret( ; CHECK-LABEL: @test_extrq_ret(
; CHECK-NEXT: ret <2 x i64> undef ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> [[X:%.*]], <16 x i8> [[Y:%.*]]) [[ATTR1]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
; ;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %y) nounwind %1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %y) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> poison, <2 x i32> <i32 1, i32 1> %2 = shufflevector <2 x i64> %1, <2 x i64> poison, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <2 x i64> @test_extrqi_arg0(<2 x i64> %x) { define <2 x i64> @test_extrqi_arg0(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_arg0( ; CHECK-LABEL: @test_extrqi_arg0(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> [[X:%.*]], i8 3, i8 2) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> [[X:%.*]], i8 3, i8 2)
; CHECK-NEXT: ret <2 x i64> [[TMP1]] ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
; ;
%1 = shufflevector <2 x i64> %x, <2 x i64> poison, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %x, <2 x i64> poison, <2 x i32> <i32 0, i32 0>
%2 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %1, i8 3, i8 2) %2 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %1, i8 3, i8 2)
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <2 x i64> @test_extrqi_ret(<2 x i64> %x) { define <2 x i64> @test_extrqi_ret(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_ret( ; CHECK-LABEL: @test_extrqi_ret(
; CHECK-NEXT: ret <2 x i64> undef ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> [[X:%.*]], i8 3, i8 2) [[ATTR1]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
; ;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2) nounwind %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> poison, <2 x i32> <i32 1, i32 1> %2 = shufflevector <2 x i64> %1, <2 x i64> poison, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <2 x i64> @test_insertq_arg0(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @test_insertq_arg0(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertq_arg0( ; CHECK-LABEL: @test_insertq_arg0(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]]) [[ATTR1]] ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]]) [[ATTR1]]
; CHECK-NEXT: ret <2 x i64> [[TMP1]] ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
; ;
%1 = shufflevector <2 x i64> %x, <2 x i64> poison, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %x, <2 x i64> poison, <2 x i32> <i32 0, i32 0>
%2 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %1, <2 x i64> %y) nounwind %2 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %1, <2 x i64> %y) nounwind
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <2 x i64> @test_insertq_ret(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @test_insertq_ret(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertq_ret( ; CHECK-LABEL: @test_insertq_ret(
; CHECK-NEXT: ret <2 x i64> undef ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]]) [[ATTR1]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
; ;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> poison, <2 x i32> <i32 1, i32 1> %2 = shufflevector <2 x i64> %1, <2 x i64> poison, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <2 x i64> @test_insertqi_arg0(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @test_insertqi_arg0(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertqi_arg0( ; CHECK-LABEL: @test_insertqi_arg0(
Show All 23 Lines;
%1 = shufflevector <2 x i64> %x, <2 x i64> poison, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %x, <2 x i64> poison, <2 x i32> <i32 0, i32 0>
%2 = shufflevector <2 x i64> %y, <2 x i64> poison, <2 x i32> <i32 0, i32 0> %2 = shufflevector <2 x i64> %y, <2 x i64> poison, <2 x i32> <i32 0, i32 0>
%3 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %2, i8 3, i8 2) nounwind %3 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %2, i8 3, i8 2) nounwind
ret <2 x i64> %3 ret <2 x i64> %3
} }
define <2 x i64> @test_insertqi_ret(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @test_insertqi_ret(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertqi_ret( ; CHECK-LABEL: @test_insertqi_ret(
; CHECK-NEXT: ret <2 x i64> undef ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]], i8 3, i8 2) [[ATTR1]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
; ;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 3, i8 2) nounwind %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 3, i8 2) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> poison, <2 x i32> <i32 1, i32 1> %2 = shufflevector <2 x i64> %1, <2 x i64> poison, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2 ret <2 x i64> %2
} }
; CHECK: declare <2 x i64> @llvm.x86.sse4a.extrq ; CHECK: declare <2 x i64> @llvm.x86.sse4a.extrq
declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
Show All 9 Lines

llvm/test/Transforms/InstCombine/X86/x86-sse4a.ll

Show First 20 Lines • Show All 316 Lines • ▼ Show 20 Lines;
%1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = shufflevector <16 x i8> %y, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0> %2 = shufflevector <16 x i8> %y, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
%3 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %1, <16 x i8> %2) nounwind %3 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %1, <16 x i8> %2) nounwind
ret <2 x i64> %3 ret <2 x i64> %3
} }
define <2 x i64> @test_extrq_ret(<2 x i64> %x, <16 x i8> %y) { define <2 x i64> @test_extrq_ret(<2 x i64> %x, <16 x i8> %y) {
; CHECK-LABEL: @test_extrq_ret( ; CHECK-LABEL: @test_extrq_ret(
; CHECK-NEXT: ret <2 x i64> undef ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> [[X:%.*]], <16 x i8> [[Y:%.*]]) [[ATTR1]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
; ;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %y) nounwind %1 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %y) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1> %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <2 x i64> @test_extrqi_arg0(<2 x i64> %x) { define <2 x i64> @test_extrqi_arg0(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_arg0( ; CHECK-LABEL: @test_extrqi_arg0(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> [[X:%.*]], i8 3, i8 2) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> [[X:%.*]], i8 3, i8 2)
; CHECK-NEXT: ret <2 x i64> [[TMP1]] ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
; ;
%1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %1, i8 3, i8 2) %2 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %1, i8 3, i8 2)
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <2 x i64> @test_extrqi_ret(<2 x i64> %x) { define <2 x i64> @test_extrqi_ret(<2 x i64> %x) {
; CHECK-LABEL: @test_extrqi_ret( ; CHECK-LABEL: @test_extrqi_ret(
; CHECK-NEXT: ret <2 x i64> undef ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> [[X:%.*]], i8 3, i8 2) [[ATTR1]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
; ;
%1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2) nounwind %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1> %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <2 x i64> @test_insertq_arg0(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @test_insertq_arg0(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertq_arg0( ; CHECK-LABEL: @test_insertq_arg0(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]]) [[ATTR1]] ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]]) [[ATTR1]]
; CHECK-NEXT: ret <2 x i64> [[TMP1]] ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
; ;
%1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %1, <2 x i64> %y) nounwind %2 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %1, <2 x i64> %y) nounwind
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <2 x i64> @test_insertq_ret(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @test_insertq_ret(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertq_ret( ; CHECK-LABEL: @test_insertq_ret(
; CHECK-NEXT: ret <2 x i64> undef ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]]) [[ATTR1]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
; ;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1> %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2 ret <2 x i64> %2
} }
define <2 x i64> @test_insertqi_arg0(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @test_insertqi_arg0(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertqi_arg0( ; CHECK-LABEL: @test_insertqi_arg0(
Show All 23 Lines;
%1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %1 = shufflevector <2 x i64> %x, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%2 = shufflevector <2 x i64> %y, <2 x i64> undef, <2 x i32> <i32 0, i32 0> %2 = shufflevector <2 x i64> %y, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%3 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %2, i8 3, i8 2) nounwind %3 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %1, <2 x i64> %2, i8 3, i8 2) nounwind
ret <2 x i64> %3 ret <2 x i64> %3
} }
define <2 x i64> @test_insertqi_ret(<2 x i64> %x, <2 x i64> %y) { define <2 x i64> @test_insertqi_ret(<2 x i64> %x, <2 x i64> %y) {
; CHECK-LABEL: @test_insertqi_ret( ; CHECK-LABEL: @test_insertqi_ret(
; CHECK-NEXT: ret <2 x i64> undef ; CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]], i8 3, i8 2) [[ATTR1]]
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: ret <2 x i64> [[TMP2]]
; ;
%1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 3, i8 2) nounwind %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 3, i8 2) nounwind
%2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1> %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> <i32 1, i32 1>
ret <2 x i64> %2 ret <2 x i64> %2
} }
; CHECK: declare <2 x i64> @llvm.x86.sse4a.extrq ; CHECK: declare <2 x i64> @llvm.x86.sse4a.extrq
declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
Show All 9 Lines

llvm/test/Transforms/InstCombine/X86/x86-vector-shifts.ll

Show First 20 Lines • Show All 2,957 Lines • ▼ Show 20 Lines;
%1 = and <4 x i32> %a, <i32 31, i32 31, i32 31, i32 31> %1 = and <4 x i32> %a, <i32 31, i32 31, i32 31, i32 31>
%2 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> %1) %2 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> %1)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define <4 x i32> @avx2_psrav_d_128_masked_shuffle(<4 x i32> %v, <4 x i32> %a) { define <4 x i32> @avx2_psrav_d_128_masked_shuffle(<4 x i32> %v, <4 x i32> %a) {
; CHECK-LABEL: @avx2_psrav_d_128_masked_shuffle( ; CHECK-LABEL: @avx2_psrav_d_128_masked_shuffle(
; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 poison, i32 poison, i32 15, i32 31> ; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], <i32 poison, i32 poison, i32 15, i32 31>
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[V:%.*]], [[TMP2]] ; CHECK-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[V:%.*]], [[TMP2]]
; CHECK-NEXT: ret <4 x i32> [[TMP3]] ; CHECK-NEXT: ret <4 x i32> [[TMP3]]
; ;
%1 = and <4 x i32> %a, <i32 undef, i32 undef, i32 15, i32 31> %1 = and <4 x i32> %a, <i32 undef, i32 undef, i32 15, i32 31>
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3> %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
%3 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> %2) %3 = tail call <4 x i32> @llvm.x86.avx2.psrav.d(<4 x i32> %v, <4 x i32> %2)
ret <4 x i32> %3 ret <4 x i32> %3
} }
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llvm/test/Transforms/InstCombine/X86/x86-vpermil.ll

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%a = tail call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> %v, <8 x i64> <i64 undef, i64 1, i64 2, i64 undef, i64 undef, i64 1, i64 2, i64 undef>) %a = tail call <8 x double> @llvm.x86.avx512.vpermilvar.pd.512(<8 x double> %v, <8 x i64> <i64 undef, i64 1, i64 2, i64 undef, i64 undef, i64 1, i64 2, i64 undef>)
ret <8 x double> %a ret <8 x double> %a
} }
; Simplify demanded elts ; Simplify demanded elts
define <4 x float> @elts_test_vpermilvar_ps(<4 x float> %a0, i32 %a1) { define <4 x float> @elts_test_vpermilvar_ps(<4 x float> %a0, i32 %a1) {
; CHECK-LABEL: @elts_test_vpermilvar_ps( ; CHECK-LABEL: @elts_test_vpermilvar_ps(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[A0:%.*]], <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 poison> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[A0:%.*]], <4 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
; CHECK-NEXT: ret <4 x float> [[TMP1]] ; CHECK-NEXT: ret <4 x float> [[TMP1]]
; ;
%1 = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %a1, i32 3 %1 = insertelement <4 x i32> <i32 0, i32 1, i32 2, i32 3>, i32 %a1, i32 3
%2 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %1) %2 = tail call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %1)
%3 = shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> %3 = shufflevector <4 x float> %2, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
ret <4 x float> %3 ret <4 x float> %3
} }
define <8 x float> @elts_test_vpermilvar_ps_256(<8 x float> %a0, <8 x i32> %a1) { define <8 x float> @elts_test_vpermilvar_ps_256(<8 x float> %a0, <8 x i32> %a1) {
; CHECK-LABEL: @elts_test_vpermilvar_ps_256( ; CHECK-LABEL: @elts_test_vpermilvar_ps_256(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A0:%.*]], <8 x float> poison, <8 x i32> <i32 poison, i32 0, i32 poison, i32 1, i32 poison, i32 6, i32 poison, i32 7> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A0:%.*]], <8 x float> poison, <8 x i32> <i32 poison, i32 0, i32 poison, i32 1, i32 poison, i32 6, i32 poison, i32 7>
; CHECK-NEXT: ret <8 x float> [[TMP1]] ; CHECK-NEXT: ret <8 x float> [[TMP1]]
; ;
%1 = shufflevector <8 x i32> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 2, i32 1, i32 0>, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> %1 = shufflevector <8 x i32> %a1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 3, i32 2, i32 1, i32 0>, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11>
%2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> %1) %2 = tail call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> %1)
%3 = shufflevector <8 x float> %2, <8 x float> undef, <8 x i32> <i32 undef, i32 1, i32 undef, i32 3, i32 undef, i32 5, i32 undef, i32 7> %3 = shufflevector <8 x float> %2, <8 x float> undef, <8 x i32> <i32 undef, i32 1, i32 undef, i32 3, i32 undef, i32 5, i32 undef, i32 7>
ret <8 x float> %3 ret <8 x float> %3
} }
define <16 x float> @elts_test_vpermilvar_ps_512(<16 x float> %a0, <16 x i32> %a1, i32 %a2) { define <16 x float> @elts_test_vpermilvar_ps_512(<16 x float> %a0, <16 x i32> %a1, i32 %a2) {
; CHECK-LABEL: @elts_test_vpermilvar_ps_512( ; CHECK-LABEL: @elts_test_vpermilvar_ps_512(
; CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[A0:%.*]], <16 x i32> [[A1:%.*]]) ; CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> [[A0:%.*]], <16 x i32> [[A1:%.*]])
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x float> [[TMP1]], <16 x float> undef, <16 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x float> [[TMP1]], <16 x float> poison, <16 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: ret <16 x float> [[TMP2]] ; CHECK-NEXT: ret <16 x float> [[TMP2]]
; ;
%1 = insertelement <16 x i32> %a1, i32 %a2, i32 0 %1 = insertelement <16 x i32> %a1, i32 %a2, i32 0
%2 = tail call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> %a0, <16 x i32> %1) %2 = tail call <16 x float> @llvm.x86.avx512.vpermilvar.ps.512(<16 x float> %a0, <16 x i32> %1)
%3 = shufflevector <16 x float> %2, <16 x float> undef, <16 x i32> <i32 undef, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %3 = shufflevector <16 x float> %2, <16 x float> undef, <16 x i32> <i32 undef, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x float> %3 ret <16 x float> %3
} }
define <2 x double> @elts_test_vpermilvar_pd(<2 x double> %a0, i64 %a1) { define <2 x double> @elts_test_vpermilvar_pd(<2 x double> %a0, i64 %a1) {
; CHECK-LABEL: @elts_test_vpermilvar_pd( ; CHECK-LABEL: @elts_test_vpermilvar_pd(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[A0:%.*]], <2 x double> undef, <2 x i32> <i32 0, i32 poison> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x double> [[A0:%.*]], <2 x double> poison, <2 x i32> <i32 0, i32 poison>
; CHECK-NEXT: ret <2 x double> [[TMP1]] ; CHECK-NEXT: ret <2 x double> [[TMP1]]
; ;
%1 = insertelement <2 x i64> <i64 0, i64 2>, i64 %a1, i32 1 %1 = insertelement <2 x i64> <i64 0, i64 2>, i64 %a1, i32 1
%2 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> %1) %2 = tail call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> %1)
%3 = shufflevector <2 x double> %2, <2 x double> undef, <2 x i32> <i32 0, i32 undef> %3 = shufflevector <2 x double> %2, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
ret <2 x double> %3 ret <2 x double> %3
} }
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llvm/test/Transforms/InstCombine/assume.ll

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ret void ret void
} }
; This would crash. ; This would crash.
; Does it ever make sense to peek through a bitcast of the icmp operand? ; Does it ever make sense to peek through a bitcast of the icmp operand?
define i32 @PR40940(<4 x i8> %x) { define i32 @PR40940(<4 x i8> %x) {
; CHECK-LABEL: @PR40940( ; CHECK-LABEL: @PR40940(
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> poison, <4 x i32> <i32 1, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[T2:%.*]] = bitcast <4 x i8> [[SHUF]] to i32 ; CHECK-NEXT: [[T2:%.*]] = bitcast <4 x i8> [[SHUF]] to i32
; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 65536 ; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 65536
; CHECK-NEXT: call void @llvm.assume(i1 [[T3]]) ; CHECK-NEXT: call void @llvm.assume(i1 [[T3]])
; CHECK-NEXT: ret i32 [[T2]] ; CHECK-NEXT: ret i32 [[T2]]
; ;
%shuf = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 3> %shuf = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 1, i32 1, i32 2, i32 3>
%t2 = bitcast <4 x i8> %shuf to i32 %t2 = bitcast <4 x i8> %shuf to i32
%t3 = icmp ult i32 %t2, 65536 %t3 = icmp ult i32 %t2, 65536
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llvm/test/Transforms/InstCombine/bitcast-vec-canon-inseltpoison.ll

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%i = insertelement <3 x i64> poison, i64 %xb, i32 %idx %i = insertelement <3 x i64> poison, i64 %xb, i32 %idx
ret <3 x i64> %i ret <3 x i64> %i
} }
; Reduce number of casts ; Reduce number of casts
define <2 x i64> @PR45748(double %x, double %y) { define <2 x i64> @PR45748(double %x, double %y) {
; CHECK-LABEL: @PR45748( ; CHECK-LABEL: @PR45748(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[Y:%.*]], i64 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[Y:%.*]], i64 1
; CHECK-NEXT: [[I1:%.*]] = bitcast <2 x double> [[TMP2]] to <2 x i64> ; CHECK-NEXT: [[I1:%.*]] = bitcast <2 x double> [[TMP2]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[I1]] ; CHECK-NEXT: ret <2 x i64> [[I1]]
; ;
%xb = bitcast double %x to i64 %xb = bitcast double %x to i64
%i0 = insertelement <2 x i64> poison, i64 %xb, i32 0 %i0 = insertelement <2 x i64> poison, i64 %xb, i32 0
%yb = bitcast double %y to i64 %yb = bitcast double %y to i64
%i1 = insertelement <2 x i64> %i0, i64 %yb, i32 1 %i1 = insertelement <2 x i64> %i0, i64 %yb, i32 1
ret <2 x i64> %i1 ret <2 x i64> %i1
} }

llvm/test/Transforms/InstCombine/bitcast-vec-canon.ll

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%i = insertelement <3 x i64> undef, i64 %xb, i32 %idx %i = insertelement <3 x i64> undef, i64 %xb, i32 %idx
ret <3 x i64> %i ret <3 x i64> %i
} }
; Reduce number of casts ; Reduce number of casts
define <2 x i64> @PR45748(double %x, double %y) { define <2 x i64> @PR45748(double %x, double %y) {
; CHECK-LABEL: @PR45748( ; CHECK-LABEL: @PR45748(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[X:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[Y:%.*]], i64 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[Y:%.*]], i64 1
; CHECK-NEXT: [[I1:%.*]] = bitcast <2 x double> [[TMP2]] to <2 x i64> ; CHECK-NEXT: [[I1:%.*]] = bitcast <2 x double> [[TMP2]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[I1]] ; CHECK-NEXT: ret <2 x i64> [[I1]]
; ;
%xb = bitcast double %x to i64 %xb = bitcast double %x to i64
%i0 = insertelement <2 x i64> undef, i64 %xb, i32 0 %i0 = insertelement <2 x i64> undef, i64 %xb, i32 0
%yb = bitcast double %y to i64 %yb = bitcast double %y to i64
%i1 = insertelement <2 x i64> %i0, i64 %yb, i32 1 %i1 = insertelement <2 x i64> %i0, i64 %yb, i32 1
ret <2 x i64> %i1 ret <2 x i64> %i1
} }

llvm/test/Transforms/InstCombine/bitreverse.ll

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%bitreverse = shufflevector <4 x i1> %cast1, <4 x i1> undef, <4 x i32> <i32 poison, i32 2, i32 1, i32 0> %bitreverse = shufflevector <4 x i1> %cast1, <4 x i1> undef, <4 x i32> <i32 poison, i32 2, i32 1, i32 0>
%cast2 = bitcast <4 x i1> %bitreverse to i4 %cast2 = bitcast <4 x i1> %bitreverse to i4
ret i4 %cast2 ret i4 %cast2
} }
; Negative tests - not reverse ; Negative tests - not reverse
define i4 @shuf_4bits_not_reverse(<4 x i1> %x) { define i4 @shuf_4bits_not_reverse(<4 x i1> %x) {
; CHECK-LABEL: @shuf_4bits_not_reverse( ; CHECK-LABEL: @shuf_4bits_not_reverse(
; CHECK-NEXT: [[BITREVERSE:%.*]] = shufflevector <4 x i1> [[X:%.*]], <4 x i1> undef, <4 x i32> <i32 3, i32 1, i32 2, i32 0> ; CHECK-NEXT: [[BITREVERSE:%.*]] = shufflevector <4 x i1> [[X:%.*]], <4 x i1> poison, <4 x i32> <i32 3, i32 1, i32 2, i32 0>
; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i1> [[BITREVERSE]] to i4 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i1> [[BITREVERSE]] to i4
; CHECK-NEXT: ret i4 [[CAST]] ; CHECK-NEXT: ret i4 [[CAST]]
; ;
%bitreverse = shufflevector <4 x i1> %x, <4 x i1> undef, <4 x i32> <i32 3, i32 1, i32 2, i32 0> %bitreverse = shufflevector <4 x i1> %x, <4 x i1> undef, <4 x i32> <i32 3, i32 1, i32 2, i32 0>
%cast = bitcast <4 x i1> %bitreverse to i4 %cast = bitcast <4 x i1> %bitreverse to i4
ret i4 %cast ret i4 %cast
} }
; Negative test - extra use ; Negative test - extra use
declare void @use(<4 x i1>) declare void @use(<4 x i1>)
define i4 @shuf_4bits_extra_use(<4 x i1> %x) { define i4 @shuf_4bits_extra_use(<4 x i1> %x) {
; CHECK-LABEL: @shuf_4bits_extra_use( ; CHECK-LABEL: @shuf_4bits_extra_use(
; CHECK-NEXT: [[BITREVERSE:%.*]] = shufflevector <4 x i1> [[X:%.*]], <4 x i1> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[BITREVERSE:%.*]] = shufflevector <4 x i1> [[X:%.*]], <4 x i1> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: call void @use(<4 x i1> [[BITREVERSE]]) ; CHECK-NEXT: call void @use(<4 x i1> [[BITREVERSE]])
; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i1> [[BITREVERSE]] to i4 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i1> [[BITREVERSE]] to i4
; CHECK-NEXT: ret i4 [[CAST]] ; CHECK-NEXT: ret i4 [[CAST]]
; ;
%bitreverse = shufflevector <4 x i1> %x, <4 x i1> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %bitreverse = shufflevector <4 x i1> %x, <4 x i1> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
call void @use(<4 x i1> %bitreverse) call void @use(<4 x i1> %bitreverse)
%cast = bitcast <4 x i1> %bitreverse to i4 %cast = bitcast <4 x i1> %bitreverse to i4
ret i4 %cast ret i4 %cast
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llvm/test/Transforms/InstCombine/broadcast.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=instcombine -S < %s | FileCheck %s ; RUN: opt -passes=instcombine -S < %s | FileCheck %s
define <4 x float> @good1(float %arg) { define <4 x float> @good1(float %arg) {
; CHECK-LABEL: @good1( ; CHECK-LABEL: @good1(
; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i64 0 ; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i64 0
; CHECK-NEXT: [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[T6:%.*]] = shufflevector <4 x float> [[T]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x float> [[T6]] ; CHECK-NEXT: ret <4 x float> [[T6]]
; ;
%t = insertelement <4 x float> undef, float %arg, i32 0 %t = insertelement <4 x float> undef, float %arg, i32 0
%t4 = insertelement <4 x float> %t, float %arg, i32 1 %t4 = insertelement <4 x float> %t, float %arg, i32 1
%t5 = insertelement <4 x float> %t4, float %arg, i32 2 %t5 = insertelement <4 x float> %t4, float %arg, i32 2
%t6 = insertelement <4 x float> %t5, float %arg, i32 3 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
ret <4 x float> %t6 ret <4 x float> %t6
} }
define <4 x float> @good2(float %arg) { define <4 x float> @good2(float %arg) {
; CHECK-LABEL: @good2( ; CHECK-LABEL: @good2(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i64 0
; CHECK-NEXT: [[T6:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[T6:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x float> [[T6]] ; CHECK-NEXT: ret <4 x float> [[T6]]
; ;
%t = insertelement <4 x float> undef, float %arg, i32 1 %t = insertelement <4 x float> undef, float %arg, i32 1
%t4 = insertelement <4 x float> %t, float %arg, i32 2 %t4 = insertelement <4 x float> %t, float %arg, i32 2
%t5 = insertelement <4 x float> %t4, float %arg, i32 0 %t5 = insertelement <4 x float> %t4, float %arg, i32 0
%t6 = insertelement <4 x float> %t5, float %arg, i32 3 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
ret <4 x float> %t6 ret <4 x float> %t6
Show All 24 Lines;
%t5 = insertelement <4 x float> %t4, float %arg, i32 2 %t5 = insertelement <4 x float> %t4, float %arg, i32 2
%t6 = insertelement <4 x float> %t5, float %arg, i32 3 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
%t7 = fadd <4 x float> %t6, %t6 %t7 = fadd <4 x float> %t6, %t6
ret <4 x float> %t7 ret <4 x float> %t7
} }
define <4 x float> @good5(float %v) { define <4 x float> @good5(float %v) {
; CHECK-LABEL: @good5( ; CHECK-LABEL: @good5(
; CHECK-NEXT: [[INS1:%.*]] = insertelement <4 x float> undef, float [[V:%.*]], i64 0 ; CHECK-NEXT: [[INS1:%.*]] = insertelement <4 x float> <float poison, float undef, float undef, float undef>, float [[V:%.*]], i64 0
; CHECK-NEXT: [[A1:%.*]] = fadd <4 x float> [[INS1]], [[INS1]] ; CHECK-NEXT: [[A1:%.*]] = fadd <4 x float> [[INS1]], [[INS1]]
; CHECK-NEXT: [[INS4:%.*]] = shufflevector <4 x float> [[INS1]], <4 x float> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[INS4:%.*]] = shufflevector <4 x float> [[INS1]], <4 x float> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[RES:%.*]] = fadd <4 x float> [[A1]], [[INS4]] ; CHECK-NEXT: [[RES:%.*]] = fadd <4 x float> [[A1]], [[INS4]]
; CHECK-NEXT: ret <4 x float> [[RES]] ; CHECK-NEXT: ret <4 x float> [[RES]]
; ;
%ins1 = insertelement <4 x float> undef, float %v, i32 0 %ins1 = insertelement <4 x float> undef, float %v, i32 0
%a1 = fadd <4 x float> %ins1, %ins1 %a1 = fadd <4 x float> %ins1, %ins1
%ins2 = insertelement<4 x float> %ins1, float %v, i32 1 %ins2 = insertelement<4 x float> %ins1, float %v, i32 1
%ins3 = insertelement<4 x float> %ins2, float %v, i32 2 %ins3 = insertelement<4 x float> %ins2, float %v, i32 2
%ins4 = insertelement<4 x float> %ins3, float %v, i32 3 %ins4 = insertelement<4 x float> %ins3, float %v, i32 3
%res = fadd <4 x float> %a1, %ins4 %res = fadd <4 x float> %a1, %ins4
ret <4 x float> %res ret <4 x float> %res
} }
; The insert is changed to allow the canonical shuffle-splat pattern from element 0. ; The insert is changed to allow the canonical shuffle-splat pattern from element 0.
define <4 x float> @splat_undef1(float %arg) { define <4 x float> @splat_undef1(float %arg) {
; CHECK-LABEL: @splat_undef1( ; CHECK-LABEL: @splat_undef1(
; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i64 1 ; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> <float undef, float poison, float poison, float poison>, float [[ARG:%.*]], i64 1
; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG:%.*]], i64 2 ; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG:%.*]], i64 2
; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG:%.*]], i64 3 ; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG:%.*]], i64 3
; CHECK-NEXT: ret <4 x float> [[T6]] ; CHECK-NEXT: ret <4 x float> [[T6]]
; ;
%t = insertelement <4 x float> undef, float %arg, i32 1 %t = insertelement <4 x float> undef, float %arg, i32 1
%t4 = insertelement <4 x float> %t, float %arg, i32 1 %t4 = insertelement <4 x float> %t, float %arg, i32 1
%t5 = insertelement <4 x float> %t4, float %arg, i32 2 %t5 = insertelement <4 x float> %t4, float %arg, i32 2
%t6 = insertelement <4 x float> %t5, float %arg, i32 3 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
ret <4 x float> %t6 ret <4 x float> %t6
} }
; Re-uses the existing first insertelement. ; Re-uses the existing first insertelement.
define <4 x float> @splat_undef2(float %arg) { define <4 x float> @splat_undef2(float %arg) {
; CHECK-LABEL: @splat_undef2( ; CHECK-LABEL: @splat_undef2(
; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i64 0 ; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> <float poison, float undef, float poison, float poison>, float [[ARG:%.*]], i64 0
; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T]], float [[ARG:%.*]], i64 2 ; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T]], float [[ARG:%.*]], i64 2
; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG:%.*]], i64 3 ; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG:%.*]], i64 3
; CHECK-NEXT: ret <4 x float> [[T6]] ; CHECK-NEXT: ret <4 x float> [[T6]]
; ;
%t = insertelement <4 x float> undef, float %arg, i32 0 %t = insertelement <4 x float> undef, float %arg, i32 0
%t5 = insertelement <4 x float> %t, float %arg, i32 2 %t5 = insertelement <4 x float> %t, float %arg, i32 2
%t6 = insertelement <4 x float> %t5, float %arg, i32 3 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
ret <4 x float> %t6 ret <4 x float> %t6
} }
define <4 x float> @bad3(float %arg, float %arg2) { define <4 x float> @bad3(float %arg, float %arg2) {
; CHECK-LABEL: @bad3( ; CHECK-LABEL: @bad3(
; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i64 0 ; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> poison, float [[ARG:%.*]], i64 0
; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> [[T]], float [[ARG2:%.*]], i64 1 ; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> [[T]], float [[ARG2:%.*]], i64 1
; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG]], i64 2 ; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG]], i64 2
; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3 ; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3
; CHECK-NEXT: ret <4 x float> [[T6]] ; CHECK-NEXT: ret <4 x float> [[T6]]
; ;
%t = insertelement <4 x float> undef, float %arg, i32 0 %t = insertelement <4 x float> undef, float %arg, i32 0
%t4 = insertelement <4 x float> %t, float %arg2, i32 1 %t4 = insertelement <4 x float> %t, float %arg2, i32 1
%t5 = insertelement <4 x float> %t4, float %arg, i32 2 %t5 = insertelement <4 x float> %t4, float %arg, i32 2
%t6 = insertelement <4 x float> %t5, float %arg, i32 3 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
ret <4 x float> %t6 ret <4 x float> %t6
} }
define <1 x float> @bad4(float %arg) { define <1 x float> @bad4(float %arg) {
; CHECK-LABEL: @bad4( ; CHECK-LABEL: @bad4(
; CHECK-NEXT: [[T:%.*]] = insertelement <1 x float> undef, float [[ARG:%.*]], i64 0 ; CHECK-NEXT: [[T:%.*]] = insertelement <1 x float> poison, float [[ARG:%.*]], i64 0
; CHECK-NEXT: ret <1 x float> [[T]] ; CHECK-NEXT: ret <1 x float> [[T]]
; ;
%t = insertelement <1 x float> undef, float %arg, i32 0 %t = insertelement <1 x float> undef, float %arg, i32 0
ret <1 x float> %t ret <1 x float> %t
} }
; Multiple undef elements are ok. ; Multiple undef elements are ok.
; TODO: Multiple uses triggers the transform at %t4, but we should sink/scalarize/CSE the splats? ; TODO: Multiple uses triggers the transform at %t4, but we should sink/scalarize/CSE the splats?
define <4 x float> @splat_undef3(float %arg) { define <4 x float> @splat_undef3(float %arg) {
; CHECK-LABEL: @splat_undef3( ; CHECK-LABEL: @splat_undef3(
; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i64 0 ; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> <float poison, float poison, float undef, float undef>, float [[ARG:%.*]], i64 0
; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> [[T]], float [[ARG:%.*]], i64 1 ; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> [[T]], float [[ARG:%.*]], i64 1
; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG:%.*]], i64 2 ; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG:%.*]], i64 2
; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG:%.*]], i64 3 ; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG:%.*]], i64 3
; CHECK-NEXT: [[T7:%.*]] = fadd <4 x float> [[T6]], [[T4]] ; CHECK-NEXT: [[T7:%.*]] = fadd <4 x float> [[T6]], [[T4]]
; CHECK-NEXT: ret <4 x float> [[T7]] ; CHECK-NEXT: ret <4 x float> [[T7]]
; ;
%t = insertelement <4 x float> undef, float %arg, i32 0 %t = insertelement <4 x float> undef, float %arg, i32 0
%t4 = insertelement <4 x float> %t, float %arg, i32 1 %t4 = insertelement <4 x float> %t, float %arg, i32 1
%t5 = insertelement <4 x float> %t4, float %arg, i32 2 %t5 = insertelement <4 x float> %t4, float %arg, i32 2
%t6 = insertelement <4 x float> %t5, float %arg, i32 3 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
%t7 = fadd <4 x float> %t6, %t4 %t7 = fadd <4 x float> %t6, %t4
ret <4 x float> %t7 ret <4 x float> %t7
} }
define <4 x float> @bad6(float %arg, i32 %k) { define <4 x float> @bad6(float %arg, i32 %k) {
; CHECK-LABEL: @bad6( ; CHECK-LABEL: @bad6(
; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> undef, float [[ARG:%.*]], i64 0 ; CHECK-NEXT: [[T:%.*]] = insertelement <4 x float> <float poison, float poison, float undef, float poison>, float [[ARG:%.*]], i64 0
; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> [[T]], float [[ARG]], i64 1 ; CHECK-NEXT: [[T4:%.*]] = insertelement <4 x float> [[T]], float [[ARG]], i64 1
; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG]], i32 [[K:%.*]] ; CHECK-NEXT: [[T5:%.*]] = insertelement <4 x float> [[T4]], float [[ARG]], i32 [[K:%.*]]
; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3 ; CHECK-NEXT: [[T6:%.*]] = insertelement <4 x float> [[T5]], float [[ARG]], i64 3
; CHECK-NEXT: ret <4 x float> [[T6]] ; CHECK-NEXT: ret <4 x float> [[T6]]
; ;
%t = insertelement <4 x float> undef, float %arg, i32 0 %t = insertelement <4 x float> undef, float %arg, i32 0
%t4 = insertelement <4 x float> %t, float %arg, i32 1 %t4 = insertelement <4 x float> %t, float %arg, i32 1
%t5 = insertelement <4 x float> %t4, float %arg, i32 %k %t5 = insertelement <4 x float> %t4, float %arg, i32 %k
%t6 = insertelement <4 x float> %t5, float %arg, i32 3 %t6 = insertelement <4 x float> %t5, float %arg, i32 3
ret <4 x float> %t6 ret <4 x float> %t6
} }
define <4 x float> @bad7(float %v) { define <4 x float> @bad7(float %v) {
; CHECK-LABEL: @bad7( ; CHECK-LABEL: @bad7(
; CHECK-NEXT: [[INS1:%.*]] = insertelement <4 x float> undef, float [[V:%.*]], i64 1 ; CHECK-NEXT: [[INS1:%.*]] = insertelement <4 x float> <float undef, float poison, float undef, float undef>, float [[V:%.*]], i64 1
; CHECK-NEXT: [[A1:%.*]] = fadd <4 x float> [[INS1]], [[INS1]] ; CHECK-NEXT: [[A1:%.*]] = fadd <4 x float> [[INS1]], [[INS1]]
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[INS1]], float [[V]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[INS1]], float [[V]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[V]], i64 2 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x float> [[TMP1]], float [[V]], i64 2
; CHECK-NEXT: [[INS4:%.*]] = insertelement <4 x float> [[TMP2]], float [[V]], i64 3 ; CHECK-NEXT: [[INS4:%.*]] = insertelement <4 x float> [[TMP2]], float [[V]], i64 3
; CHECK-NEXT: [[RES:%.*]] = fadd <4 x float> [[A1]], [[INS4]] ; CHECK-NEXT: [[RES:%.*]] = fadd <4 x float> [[A1]], [[INS4]]
; CHECK-NEXT: ret <4 x float> [[RES]] ; CHECK-NEXT: ret <4 x float> [[RES]]
; ;
%ins1 = insertelement <4 x float> undef, float %v, i32 1 %ins1 = insertelement <4 x float> undef, float %v, i32 1
%a1 = fadd <4 x float> %ins1, %ins1 %a1 = fadd <4 x float> %ins1, %ins1
%ins2 = insertelement<4 x float> %ins1, float %v, i32 2 %ins2 = insertelement<4 x float> %ins1, float %v, i32 2
%ins3 = insertelement<4 x float> %ins2, float %v, i32 3 %ins3 = insertelement<4 x float> %ins2, float %v, i32 3
%ins4 = insertelement<4 x float> %ins3, float %v, i32 0 %ins4 = insertelement<4 x float> %ins3, float %v, i32 0
%res = fadd <4 x float> %a1, %ins4 %res = fadd <4 x float> %a1, %ins4
ret <4 x float> %res ret <4 x float> %res
} }

llvm/test/Transforms/InstCombine/bswap.ll

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ret i32 %cast2 ret i32 %cast2
} }
; Negative test - extra use ; Negative test - extra use
declare void @use(<4 x i8>) declare void @use(<4 x i8>)
define i32 @shuf_4bytes_extra_use(<4 x i8> %x) { define i32 @shuf_4bytes_extra_use(<4 x i8> %x) {
; CHECK-LABEL: @shuf_4bytes_extra_use( ; CHECK-LABEL: @shuf_4bytes_extra_use(
; CHECK-NEXT: [[BSWAP:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[BSWAP:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: call void @use(<4 x i8> [[BSWAP]]) ; CHECK-NEXT: call void @use(<4 x i8> [[BSWAP]])
; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[BSWAP]] to i32 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[BSWAP]] to i32
; CHECK-NEXT: ret i32 [[CAST]] ; CHECK-NEXT: ret i32 [[CAST]]
; ;
%bswap = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %bswap = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
call void @use(<4 x i8> %bswap) call void @use(<4 x i8> %bswap)
%cast = bitcast <4 x i8> %bswap to i32 %cast = bitcast <4 x i8> %bswap to i32
ret i32 %cast ret i32 %cast
} }
; Negative test - scalar type is not in the data layout ; Negative test - scalar type is not in the data layout
define i128 @shuf_16bytes(<16 x i8> %x) { define i128 @shuf_16bytes(<16 x i8> %x) {
; CHECK-LABEL: @shuf_16bytes( ; CHECK-LABEL: @shuf_16bytes(
; CHECK-NEXT: [[BSWAP:%.*]] = shufflevector <16 x i8> [[X:%.*]], <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[BSWAP:%.*]] = shufflevector <16 x i8> [[X:%.*]], <16 x i8> poison, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[CAST:%.*]] = bitcast <16 x i8> [[BSWAP]] to i128 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <16 x i8> [[BSWAP]] to i128
; CHECK-NEXT: ret i128 [[CAST]] ; CHECK-NEXT: ret i128 [[CAST]]
; ;
%bswap = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %bswap = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%cast = bitcast <16 x i8> %bswap to i128 %cast = bitcast <16 x i8> %bswap to i128
ret i128 %cast ret i128 %cast
} }
; Negative test - don't touch widening shuffles (for now) ; Negative test - don't touch widening shuffles (for now)
define i32 @shuf_2bytes_widening(<2 x i8> %x) { define i32 @shuf_2bytes_widening(<2 x i8> %x) {
; CHECK-LABEL: @shuf_2bytes_widening( ; CHECK-LABEL: @shuf_2bytes_widening(
; CHECK-NEXT: [[BSWAP:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison> ; CHECK-NEXT: [[BSWAP:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> poison, <4 x i32> <i32 1, i32 0, i32 poison, i32 poison>
; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[BSWAP]] to i32 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[BSWAP]] to i32
; CHECK-NEXT: ret i32 [[CAST]] ; CHECK-NEXT: ret i32 [[CAST]]
; ;
%bswap = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 1, i32 0, i32 undef, i32 undef> %bswap = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 1, i32 0, i32 undef, i32 undef>
%cast = bitcast <4 x i8> %bswap to i32 %cast = bitcast <4 x i8> %bswap to i32
ret i32 %cast ret i32 %cast
} }
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llvm/test/Transforms/InstCombine/extractelement.ll

Show First 20 Lines • Show All 139 Lines • ▼ Show 20 Lines
} }
; Partial negative test for the above fold, extra uses are not allowed if shift is needed. ; Partial negative test for the above fold, extra uses are not allowed if shift is needed.
declare void @use(<8 x i8>) declare void @use(<8 x i8>)
define i8 @bitcasted_inselt_wide_source_uses(i32 %x) { define i8 @bitcasted_inselt_wide_source_uses(i32 %x) {
; ANYLE-LABEL: @bitcasted_inselt_wide_source_uses( ; ANYLE-LABEL: @bitcasted_inselt_wide_source_uses(
; ANYLE-NEXT: [[I:%.*]] = insertelement <2 x i32> undef, i32 [[X:%.*]], i64 0 ; ANYLE-NEXT: [[I:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[X:%.*]], i64 0
; ANYLE-NEXT: [[B:%.*]] = bitcast <2 x i32> [[I]] to <8 x i8> ; ANYLE-NEXT: [[B:%.*]] = bitcast <2 x i32> [[I]] to <8 x i8>
; ANYLE-NEXT: call void @use(<8 x i8> [[B]]) ; ANYLE-NEXT: call void @use(<8 x i8> [[B]])
; ANYLE-NEXT: [[R:%.*]] = extractelement <8 x i8> [[B]], i64 3 ; ANYLE-NEXT: [[R:%.*]] = extractelement <8 x i8> [[B]], i64 3
; ANYLE-NEXT: ret i8 [[R]] ; ANYLE-NEXT: ret i8 [[R]]
; ;
; ANYBE-LABEL: @bitcasted_inselt_wide_source_uses( ; ANYBE-LABEL: @bitcasted_inselt_wide_source_uses(
; ANYBE-NEXT: [[I:%.*]] = insertelement <2 x i32> undef, i32 [[X:%.*]], i64 0 ; ANYBE-NEXT: [[I:%.*]] = insertelement <2 x i32> <i32 poison, i32 undef>, i32 [[X:%.*]], i64 0
; ANYBE-NEXT: [[B:%.*]] = bitcast <2 x i32> [[I]] to <8 x i8> ; ANYBE-NEXT: [[B:%.*]] = bitcast <2 x i32> [[I]] to <8 x i8>
; ANYBE-NEXT: call void @use(<8 x i8> [[B]]) ; ANYBE-NEXT: call void @use(<8 x i8> [[B]])
; ANYBE-NEXT: [[R:%.*]] = trunc i32 [[X]] to i8 ; ANYBE-NEXT: [[R:%.*]] = trunc i32 [[X]] to i8
; ANYBE-NEXT: ret i8 [[R]] ; ANYBE-NEXT: ret i8 [[R]]
; ;
%i = insertelement <2 x i32> undef, i32 %x, i32 0 %i = insertelement <2 x i32> undef, i32 %x, i32 0
%b = bitcast <2 x i32> %i to <8 x i8> %b = bitcast <2 x i32> %i to <8 x i8>
call void @use(<8 x i8> %b) call void @use(<8 x i8> %b)
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ret float %r ret float %r
} }
declare void @use_v2i128(<2 x i128>) declare void @use_v2i128(<2 x i128>)
declare void @use_v8f32(<8 x float>) declare void @use_v8f32(<8 x float>)
define float @bitcasted_inselt_to_FP_uses(i128 %x) { define float @bitcasted_inselt_to_FP_uses(i128 %x) {
; ANY-LABEL: @bitcasted_inselt_to_FP_uses( ; ANY-LABEL: @bitcasted_inselt_to_FP_uses(
; ANY-NEXT: [[I:%.*]] = insertelement <2 x i128> undef, i128 [[X:%.*]], i64 0 ; ANY-NEXT: [[I:%.*]] = insertelement <2 x i128> <i128 poison, i128 undef>, i128 [[X:%.*]], i64 0
; ANY-NEXT: call void @use_v2i128(<2 x i128> [[I]]) ; ANY-NEXT: call void @use_v2i128(<2 x i128> [[I]])
; ANY-NEXT: [[B:%.*]] = bitcast <2 x i128> [[I]] to <8 x float> ; ANY-NEXT: [[B:%.*]] = bitcast <2 x i128> [[I]] to <8 x float>
; ANY-NEXT: [[R:%.*]] = extractelement <8 x float> [[B]], i64 1 ; ANY-NEXT: [[R:%.*]] = extractelement <8 x float> [[B]], i64 1
; ANY-NEXT: ret float [[R]] ; ANY-NEXT: ret float [[R]]
; ;
%i = insertelement <2 x i128> undef, i128 %x, i32 0 %i = insertelement <2 x i128> undef, i128 %x, i32 0
call void @use_v2i128(<2 x i128> %i) call void @use_v2i128(<2 x i128> %i)
%b = bitcast <2 x i128> %i to <8 x float> %b = bitcast <2 x i128> %i to <8 x float>
%r = extractelement <8 x float> %b, i32 1 %r = extractelement <8 x float> %b, i32 1
ret float %r ret float %r
} }
define float @bitcasted_inselt_to_FP_uses2(i128 %x) { define float @bitcasted_inselt_to_FP_uses2(i128 %x) {
; ANY-LABEL: @bitcasted_inselt_to_FP_uses2( ; ANY-LABEL: @bitcasted_inselt_to_FP_uses2(
; ANY-NEXT: [[I:%.*]] = insertelement <2 x i128> undef, i128 [[X:%.*]], i64 0 ; ANY-NEXT: [[I:%.*]] = insertelement <2 x i128> <i128 poison, i128 undef>, i128 [[X:%.*]], i64 0
; ANY-NEXT: [[B:%.*]] = bitcast <2 x i128> [[I]] to <8 x float> ; ANY-NEXT: [[B:%.*]] = bitcast <2 x i128> [[I]] to <8 x float>
; ANY-NEXT: call void @use_v8f32(<8 x float> [[B]]) ; ANY-NEXT: call void @use_v8f32(<8 x float> [[B]])
; ANY-NEXT: [[R:%.*]] = extractelement <8 x float> [[B]], i64 1 ; ANY-NEXT: [[R:%.*]] = extractelement <8 x float> [[B]], i64 1
; ANY-NEXT: ret float [[R]] ; ANY-NEXT: ret float [[R]]
; ;
%i = insertelement <2 x i128> undef, i128 %x, i32 0 %i = insertelement <2 x i128> undef, i128 %x, i32 0
%b = bitcast <2 x i128> %i to <8 x float> %b = bitcast <2 x i128> %i to <8 x float>
call void @use_v8f32(<8 x float> %b) call void @use_v8f32(<8 x float> %b)
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ret i32 %r ret i32 %r
} }
declare void @use_v2f64(<2 x double>) declare void @use_v2f64(<2 x double>)
declare void @use_v8i16(<8 x i16>) declare void @use_v8i16(<8 x i16>)
define i16 @bitcasted_inselt_from_FP_uses(double %x) { define i16 @bitcasted_inselt_from_FP_uses(double %x) {
; ANY-LABEL: @bitcasted_inselt_from_FP_uses( ; ANY-LABEL: @bitcasted_inselt_from_FP_uses(
; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i64 0 ; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[X:%.*]], i64 0
; ANY-NEXT: call void @use_v2f64(<2 x double> [[I]]) ; ANY-NEXT: call void @use_v2f64(<2 x double> [[I]])
; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <8 x i16> ; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <8 x i16>
; ANY-NEXT: [[R:%.*]] = extractelement <8 x i16> [[B]], i64 1 ; ANY-NEXT: [[R:%.*]] = extractelement <8 x i16> [[B]], i64 1
; ANY-NEXT: ret i16 [[R]] ; ANY-NEXT: ret i16 [[R]]
; ;
%i = insertelement <2 x double> undef, double %x, i32 0 %i = insertelement <2 x double> undef, double %x, i32 0
call void @use_v2f64(<2 x double> %i) call void @use_v2f64(<2 x double> %i)
%b = bitcast <2 x double> %i to <8 x i16> %b = bitcast <2 x double> %i to <8 x i16>
%r = extractelement <8 x i16> %b, i32 1 %r = extractelement <8 x i16> %b, i32 1
ret i16 %r ret i16 %r
} }
define i16 @bitcasted_inselt_from_FP_uses2(double %x) { define i16 @bitcasted_inselt_from_FP_uses2(double %x) {
; ANY-LABEL: @bitcasted_inselt_from_FP_uses2( ; ANY-LABEL: @bitcasted_inselt_from_FP_uses2(
; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i64 0 ; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[X:%.*]], i64 0
; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <8 x i16> ; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <8 x i16>
; ANY-NEXT: call void @use_v8i16(<8 x i16> [[B]]) ; ANY-NEXT: call void @use_v8i16(<8 x i16> [[B]])
; ANY-NEXT: [[R:%.*]] = extractelement <8 x i16> [[B]], i64 1 ; ANY-NEXT: [[R:%.*]] = extractelement <8 x i16> [[B]], i64 1
; ANY-NEXT: ret i16 [[R]] ; ANY-NEXT: ret i16 [[R]]
; ;
%i = insertelement <2 x double> undef, double %x, i32 0 %i = insertelement <2 x double> undef, double %x, i32 0
%b = bitcast <2 x double> %i to <8 x i16> %b = bitcast <2 x double> %i to <8 x i16>
call void @use_v8i16(<8 x i16> %b) call void @use_v8i16(<8 x i16> %b)
%r = extractelement <8 x i16> %b, i32 1 %r = extractelement <8 x i16> %b, i32 1
ret i16 %r ret i16 %r
} }
define float @bitcasted_inselt_to_and_from_FP(double %x) { define float @bitcasted_inselt_to_and_from_FP(double %x) {
; ANY-LABEL: @bitcasted_inselt_to_and_from_FP( ; ANY-LABEL: @bitcasted_inselt_to_and_from_FP(
; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i64 0 ; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> poison, double [[X:%.*]], i64 0
; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <4 x float> ; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <4 x float>
; ANY-NEXT: [[R:%.*]] = extractelement <4 x float> [[B]], i64 1 ; ANY-NEXT: [[R:%.*]] = extractelement <4 x float> [[B]], i64 1
; ANY-NEXT: ret float [[R]] ; ANY-NEXT: ret float [[R]]
; ;
%i = insertelement <2 x double> undef, double %x, i32 0 %i = insertelement <2 x double> undef, double %x, i32 0
%b = bitcast <2 x double> %i to <4 x float> %b = bitcast <2 x double> %i to <4 x float>
%r = extractelement <4 x float> %b, i32 1 %r = extractelement <4 x float> %b, i32 1
ret float %r ret float %r
} }
define float @bitcasted_inselt_to_and_from_FP_uses(double %x) { define float @bitcasted_inselt_to_and_from_FP_uses(double %x) {
; ANY-LABEL: @bitcasted_inselt_to_and_from_FP_uses( ; ANY-LABEL: @bitcasted_inselt_to_and_from_FP_uses(
; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i64 0 ; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[X:%.*]], i64 0
; ANY-NEXT: call void @use_v2f64(<2 x double> [[I]]) ; ANY-NEXT: call void @use_v2f64(<2 x double> [[I]])
; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <4 x float> ; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <4 x float>
; ANY-NEXT: [[R:%.*]] = extractelement <4 x float> [[B]], i64 1 ; ANY-NEXT: [[R:%.*]] = extractelement <4 x float> [[B]], i64 1
; ANY-NEXT: ret float [[R]] ; ANY-NEXT: ret float [[R]]
; ;
%i = insertelement <2 x double> undef, double %x, i32 0 %i = insertelement <2 x double> undef, double %x, i32 0
call void @use_v2f64(<2 x double> %i) call void @use_v2f64(<2 x double> %i)
%b = bitcast <2 x double> %i to <4 x float> %b = bitcast <2 x double> %i to <4 x float>
%r = extractelement <4 x float> %b, i32 1 %r = extractelement <4 x float> %b, i32 1
ret float %r ret float %r
} }
declare void @use_v4f32(<4 x float>) declare void @use_v4f32(<4 x float>)
define float @bitcasted_inselt_to_and_from_FP_uses2(double %x) { define float @bitcasted_inselt_to_and_from_FP_uses2(double %x) {
; ANY-LABEL: @bitcasted_inselt_to_and_from_FP_uses2( ; ANY-LABEL: @bitcasted_inselt_to_and_from_FP_uses2(
; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> undef, double [[X:%.*]], i64 0 ; ANY-NEXT: [[I:%.*]] = insertelement <2 x double> <double poison, double undef>, double [[X:%.*]], i64 0
; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <4 x float> ; ANY-NEXT: [[B:%.*]] = bitcast <2 x double> [[I]] to <4 x float>
; ANY-NEXT: call void @use_v4f32(<4 x float> [[B]]) ; ANY-NEXT: call void @use_v4f32(<4 x float> [[B]])
; ANY-NEXT: [[R:%.*]] = extractelement <4 x float> [[B]], i64 1 ; ANY-NEXT: [[R:%.*]] = extractelement <4 x float> [[B]], i64 1
; ANY-NEXT: ret float [[R]] ; ANY-NEXT: ret float [[R]]
; ;
%i = insertelement <2 x double> undef, double %x, i32 0 %i = insertelement <2 x double> undef, double %x, i32 0
%b = bitcast <2 x double> %i to <4 x float> %b = bitcast <2 x double> %i to <4 x float>
call void @use_v4f32(<4 x float> %b) call void @use_v4f32(<4 x float> %b)
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llvm/test/Transforms/InstCombine/icmp-bc-vec.ll

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%cast = bitcast <4 x i8> %vec to i32 %cast = bitcast <4 x i8> %vec to i32
%cond = icmp eq i32 %cast, 1212696648 %cond = icmp eq i32 %cast, 1212696648
ret i1 %cond ret i1 %cond
} }
; Make sure we don't try to fold if the shufflemask has differing element values ; Make sure we don't try to fold if the shufflemask has differing element values
define i1 @test_i8_pattern_3(<4 x i8> %invec) { define i1 @test_i8_pattern_3(<4 x i8> %invec) {
; CHECK-LABEL: @test_i8_pattern_3( ; CHECK-LABEL: @test_i8_pattern_3(
; CHECK-NEXT: [[VEC:%.*]] = shufflevector <4 x i8> [[INVEC:%.*]], <4 x i8> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> ; CHECK-NEXT: [[VEC:%.*]] = shufflevector <4 x i8> [[INVEC:%.*]], <4 x i8> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[CAST]], 1212696648 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[CAST]], 1212696648
; CHECK-NEXT: ret i1 [[COND]] ; CHECK-NEXT: ret i1 [[COND]]
; ;
%vec = shufflevector <4 x i8> %invec, <4 x i8> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> %vec = shufflevector <4 x i8> %invec, <4 x i8> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
%cast = bitcast <4 x i8> %vec to i32 %cast = bitcast <4 x i8> %vec to i32
%cond = icmp eq i32 %cast, 1212696648 %cond = icmp eq i32 %cast, 1212696648
ret i1 %cond ret i1 %cond
} }
; Make sure we don't try to fold if the compared-to constant isn't a splatted value ; Make sure we don't try to fold if the compared-to constant isn't a splatted value
define i1 @test_i8_nopattern(i8 %val) { define i1 @test_i8_nopattern(i8 %val) {
; CHECK-LABEL: @test_i8_nopattern( ; CHECK-LABEL: @test_i8_nopattern(
; CHECK-NEXT: [[INSVEC:%.*]] = insertelement <4 x i8> undef, i8 [[VAL:%.*]], i64 0 ; CHECK-NEXT: [[INSVEC:%.*]] = insertelement <4 x i8> poison, i8 [[VAL:%.*]], i64 0
; CHECK-NEXT: [[VEC:%.*]] = shufflevector <4 x i8> [[INSVEC]], <4 x i8> undef, <4 x i32> zeroinitializer ; CHECK-NEXT: [[VEC:%.*]] = shufflevector <4 x i8> [[INSVEC]], <4 x i8> undef, <4 x i32> zeroinitializer
; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[CAST]], 1212696647 ; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[CAST]], 1212696647
; CHECK-NEXT: ret i1 [[COND]] ; CHECK-NEXT: ret i1 [[COND]]
; ;
%insvec = insertelement <4 x i8> undef, i8 %val, i32 0 %insvec = insertelement <4 x i8> undef, i8 %val, i32 0
%vec = shufflevector <4 x i8> %insvec, <4 x i8> undef, <4 x i32> zeroinitializer %vec = shufflevector <4 x i8> %insvec, <4 x i8> undef, <4 x i32> zeroinitializer
%cast = bitcast <4 x i8> %vec to i32 %cast = bitcast <4 x i8> %vec to i32
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llvm/test/Transforms/InstCombine/icmp-vec.ll

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%cmp = fcmp oeq <5 x float> %shufx, %shufy %cmp = fcmp oeq <5 x float> %shufx, %shufy
ret <5 x i1> %cmp ret <5 x i1> %cmp
} }
declare void @use_v4i8(<4 x i8>) declare void @use_v4i8(<4 x i8>)
define <4 x i1> @same_shuffle_inputs_icmp_extra_use1(<4 x i8> %x, <4 x i8> %y) { define <4 x i1> @same_shuffle_inputs_icmp_extra_use1(<4 x i8> %x, <4 x i8> %y) {
; CHECK-LABEL: @same_shuffle_inputs_icmp_extra_use1( ; CHECK-LABEL: @same_shuffle_inputs_icmp_extra_use1(
; CHECK-NEXT: [[SHUFX:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> ; CHECK-NEXT: [[SHUFX:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i8> [[X]], [[Y:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt <4 x i8> [[X]], [[Y:%.*]]
; CHECK-NEXT: [[CMP:%.*]] = shufflevector <4 x i1> [[TMP1]], <4 x i1> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3> ; CHECK-NEXT: [[CMP:%.*]] = shufflevector <4 x i1> [[TMP1]], <4 x i1> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
; CHECK-NEXT: call void @use_v4i8(<4 x i8> [[SHUFX]]) ; CHECK-NEXT: call void @use_v4i8(<4 x i8> [[SHUFX]])
; CHECK-NEXT: ret <4 x i1> [[CMP]] ; CHECK-NEXT: ret <4 x i1> [[CMP]]
; ;
%shufx = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > %shufx = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >
%shufy = shufflevector <4 x i8> %y, <4 x i8> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 > %shufy = shufflevector <4 x i8> %y, <4 x i8> undef, <4 x i32> < i32 3, i32 3, i32 3, i32 3 >
%cmp = icmp ugt <4 x i8> %shufx, %shufy %cmp = icmp ugt <4 x i8> %shufx, %shufy
call void @use_v4i8(<4 x i8> %shufx) call void @use_v4i8(<4 x i8> %shufx)
ret <4 x i1> %cmp ret <4 x i1> %cmp
} }
declare void @use_v2i8(<2 x i8>) declare void @use_v2i8(<2 x i8>)
define <2 x i1> @same_shuffle_inputs_icmp_extra_use2(<4 x i8> %x, <4 x i8> %y) { define <2 x i1> @same_shuffle_inputs_icmp_extra_use2(<4 x i8> %x, <4 x i8> %y) {
; CHECK-LABEL: @same_shuffle_inputs_icmp_extra_use2( ; CHECK-LABEL: @same_shuffle_inputs_icmp_extra_use2(
; CHECK-NEXT: [[SHUFY:%.*]] = shufflevector <4 x i8> [[Y:%.*]], <4 x i8> undef, <2 x i32> <i32 3, i32 2> ; CHECK-NEXT: [[SHUFY:%.*]] = shufflevector <4 x i8> [[Y:%.*]], <4 x i8> poison, <2 x i32> <i32 3, i32 2>
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i8> [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <4 x i8> [[X:%.*]], [[Y]]
; CHECK-NEXT: [[CMP:%.*]] = shufflevector <4 x i1> [[TMP1]], <4 x i1> poison, <2 x i32> <i32 3, i32 2> ; CHECK-NEXT: [[CMP:%.*]] = shufflevector <4 x i1> [[TMP1]], <4 x i1> poison, <2 x i32> <i32 3, i32 2>
; CHECK-NEXT: call void @use_v2i8(<2 x i8> [[SHUFY]]) ; CHECK-NEXT: call void @use_v2i8(<2 x i8> [[SHUFY]])
; CHECK-NEXT: ret <2 x i1> [[CMP]] ; CHECK-NEXT: ret <2 x i1> [[CMP]]
; ;
%shufx = shufflevector <4 x i8> %x, <4 x i8> undef, <2 x i32> < i32 3, i32 2 > %shufx = shufflevector <4 x i8> %x, <4 x i8> undef, <2 x i32> < i32 3, i32 2 >
%shufy = shufflevector <4 x i8> %y, <4 x i8> undef, <2 x i32> < i32 3, i32 2 > %shufy = shufflevector <4 x i8> %y, <4 x i8> undef, <2 x i32> < i32 3, i32 2 >
%cmp = icmp eq <2 x i8> %shufx, %shufy %cmp = icmp eq <2 x i8> %shufx, %shufy
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%cmp = fcmp oeq <4 x float> %splatx, <float 42.0, float 42.0, float undef, float 42.0> %cmp = fcmp oeq <4 x float> %splatx, <float 42.0, float 42.0, float undef, float 42.0>
ret <4 x i1> %cmp ret <4 x i1> %cmp
} }
; Negative test ; Negative test
define <4 x i1> @splat_icmp_extra_use(<4 x i8> %x) { define <4 x i1> @splat_icmp_extra_use(<4 x i8> %x) {
; CHECK-LABEL: @splat_icmp_extra_use( ; CHECK-LABEL: @splat_icmp_extra_use(
; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> ; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
; CHECK-NEXT: call void @use_v4i8(<4 x i8> [[SPLATX]]) ; CHECK-NEXT: call void @use_v4i8(<4 x i8> [[SPLATX]])
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <4 x i8> [[SPLATX]], <i8 42, i8 42, i8 42, i8 42> ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <4 x i8> [[SPLATX]], <i8 42, i8 42, i8 42, i8 42>
; CHECK-NEXT: ret <4 x i1> [[CMP]] ; CHECK-NEXT: ret <4 x i1> [[CMP]]
; ;
%splatx = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %splatx = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
call void @use_v4i8(<4 x i8> %splatx) call void @use_v4i8(<4 x i8> %splatx)
%cmp = icmp sgt <4 x i8> %splatx, <i8 42, i8 42, i8 42, i8 42> %cmp = icmp sgt <4 x i8> %splatx, <i8 42, i8 42, i8 42, i8 42>
ret <4 x i1> %cmp ret <4 x i1> %cmp
} }
; Negative test ; Negative test
define <4 x i1> @not_splat_icmp(<4 x i8> %x) { define <4 x i1> @not_splat_icmp(<4 x i8> %x) {
; CHECK-LABEL: @not_splat_icmp( ; CHECK-LABEL: @not_splat_icmp(
; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 3> ; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 3, i32 3>
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <4 x i8> [[SPLATX]], <i8 42, i8 42, i8 42, i8 42> ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <4 x i8> [[SPLATX]], <i8 42, i8 42, i8 42, i8 42>
; CHECK-NEXT: ret <4 x i1> [[CMP]] ; CHECK-NEXT: ret <4 x i1> [[CMP]]
; ;
%splatx = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 3> %splatx = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 3>
%cmp = icmp sgt <4 x i8> %splatx, <i8 42, i8 42, i8 42, i8 42> %cmp = icmp sgt <4 x i8> %splatx, <i8 42, i8 42, i8 42, i8 42>
ret <4 x i1> %cmp ret <4 x i1> %cmp
} }
; Negative test ; Negative test
define <4 x i1> @not_splat_icmp2(<4 x i8> %x) { define <4 x i1> @not_splat_icmp2(<4 x i8> %x) {
; CHECK-LABEL: @not_splat_icmp2( ; CHECK-LABEL: @not_splat_icmp2(
; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2> ; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> poison, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <4 x i8> [[SPLATX]], <i8 43, i8 42, i8 42, i8 42> ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <4 x i8> [[SPLATX]], <i8 43, i8 42, i8 42, i8 42>
; CHECK-NEXT: ret <4 x i1> [[CMP]] ; CHECK-NEXT: ret <4 x i1> [[CMP]]
; ;
%splatx = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2> %splatx = shufflevector <4 x i8> %x, <4 x i8> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
%cmp = icmp sgt <4 x i8> %splatx, <i8 43, i8 42, i8 42, i8 42> %cmp = icmp sgt <4 x i8> %splatx, <i8 43, i8 42, i8 42, i8 42>
ret <4 x i1> %cmp ret <4 x i1> %cmp
} }
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llvm/test/Transforms/InstCombine/inselt-binop.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -passes=instcombine %s | FileCheck %s ; RUN: opt -S -passes=instcombine %s | FileCheck %s
define <2 x i8> @add_constant(i8 %x) { define <2 x i8> @add_constant(i8 %x) {
; CHECK-LABEL: @add_constant( ; CHECK-LABEL: @add_constant(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 undef> ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = add <2 x i8> %ins, <i8 42, i8 undef> %bo = add <2 x i8> %ins, <i8 42, i8 undef>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @add_constant_not_undef_lane(i8 %x) { define <2 x i8> @add_constant_not_undef_lane(i8 %x) {
; CHECK-LABEL: @add_constant_not_undef_lane( ; CHECK-LABEL: @add_constant_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 -42> ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 42, i8 -42>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = add <2 x i8> %ins, <i8 42, i8 -42> %bo = add <2 x i8> %ins, <i8 42, i8 -42>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
; IR flags are not required, but they should propagate. ; IR flags are not required, but they should propagate.
define <2 x i8> @sub_constant_op0(i8 %x) { define <2 x i8> @sub_constant_op0(i8 %x) {
; CHECK-LABEL: @sub_constant_op0( ; CHECK-LABEL: @sub_constant_op0(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = sub nuw nsw <2 x i8> <i8 undef, i8 -42>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = sub nuw nsw <2 x i8> <i8 undef, i8 -42>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = sub nsw nuw <2 x i8> <i8 undef, i8 -42>, %ins %bo = sub nsw nuw <2 x i8> <i8 undef, i8 -42>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @sub_constant_op0_not_undef_lane(i8 %x) { define <2 x i8> @sub_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @sub_constant_op0_not_undef_lane( ; CHECK-LABEL: @sub_constant_op0_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = sub nuw <2 x i8> <i8 42, i8 -42>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = sub nuw <2 x i8> <i8 42, i8 -42>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = sub nuw <2 x i8> <i8 42, i8 -42>, %ins %bo = sub nuw <2 x i8> <i8 42, i8 -42>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @sub_constant_op1(i8 %x) { define <2 x i8> @sub_constant_op1(i8 %x) {
; CHECK-LABEL: @sub_constant_op1( ; CHECK-LABEL: @sub_constant_op1(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 -42, i8 undef> ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 -42, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = sub nuw <2 x i8> %ins, <i8 42, i8 undef> %bo = sub nuw <2 x i8> %ins, <i8 42, i8 undef>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @sub_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @sub_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @sub_constant_op1_not_undef_lane( ; CHECK-LABEL: @sub_constant_op1_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 -42, i8 42> ; CHECK-NEXT: [[BO:%.*]] = add <2 x i8> [[INS]], <i8 -42, i8 42>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = sub nuw <2 x i8> %ins, <i8 42, i8 -42> %bo = sub nuw <2 x i8> %ins, <i8 42, i8 -42>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <3 x i8> @mul_constant(i8 %x) { define <3 x i8> @mul_constant(i8 %x) {
; CHECK-LABEL: @mul_constant( ; CHECK-LABEL: @mul_constant(
; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x i8> undef, i8 [[X:%.*]], i64 2 ; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x i8> <i8 undef, i8 undef, i8 poison>, i8 [[X:%.*]], i64 2
; CHECK-NEXT: [[BO:%.*]] = mul <3 x i8> [[INS]], <i8 undef, i8 undef, i8 -42> ; CHECK-NEXT: [[BO:%.*]] = mul <3 x i8> [[INS]], <i8 undef, i8 undef, i8 -42>
; CHECK-NEXT: ret <3 x i8> [[BO]] ; CHECK-NEXT: ret <3 x i8> [[BO]]
; ;
%ins = insertelement <3 x i8> undef, i8 %x, i32 2 %ins = insertelement <3 x i8> undef, i8 %x, i32 2
%bo = mul <3 x i8> %ins, <i8 undef, i8 undef, i8 -42> %bo = mul <3 x i8> %ins, <i8 undef, i8 undef, i8 -42>
ret <3 x i8> %bo ret <3 x i8> %bo
} }
define <3 x i8> @mul_constant_not_undef_lane(i8 %x) { define <3 x i8> @mul_constant_not_undef_lane(i8 %x) {
; CHECK-LABEL: @mul_constant_not_undef_lane( ; CHECK-LABEL: @mul_constant_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x i8> undef, i8 [[X:%.*]], i64 2 ; CHECK-NEXT: [[INS:%.*]] = insertelement <3 x i8> <i8 undef, i8 undef, i8 poison>, i8 [[X:%.*]], i64 2
; CHECK-NEXT: [[BO:%.*]] = mul <3 x i8> [[INS]], <i8 42, i8 undef, i8 -42> ; CHECK-NEXT: [[BO:%.*]] = mul <3 x i8> [[INS]], <i8 42, i8 undef, i8 -42>
; CHECK-NEXT: ret <3 x i8> [[BO]] ; CHECK-NEXT: ret <3 x i8> [[BO]]
; ;
%ins = insertelement <3 x i8> undef, i8 %x, i32 2 %ins = insertelement <3 x i8> undef, i8 %x, i32 2
%bo = mul <3 x i8> %ins, <i8 42, i8 undef, i8 -42> %bo = mul <3 x i8> %ins, <i8 42, i8 undef, i8 -42>
ret <3 x i8> %bo ret <3 x i8> %bo
} }
define <2 x i8> @shl_constant_op0(i8 %x) { define <2 x i8> @shl_constant_op0(i8 %x) {
; CHECK-LABEL: @shl_constant_op0( ; CHECK-LABEL: @shl_constant_op0(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = shl <2 x i8> <i8 undef, i8 2>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = shl <2 x i8> <i8 undef, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = shl <2 x i8> <i8 undef, i8 2>, %ins %bo = shl <2 x i8> <i8 undef, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @shl_constant_op0_not_undef_lane(i8 %x) { define <2 x i8> @shl_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @shl_constant_op0_not_undef_lane( ; CHECK-LABEL: @shl_constant_op0_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = shl <2 x i8> <i8 5, i8 2>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = shl <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = shl <2 x i8> <i8 5, i8 2>, %ins %bo = shl <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @shl_constant_op1(i8 %x) { define <2 x i8> @shl_constant_op1(i8 %x) {
; CHECK-LABEL: @shl_constant_op1( ; CHECK-LABEL: @shl_constant_op1(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = shl nuw <2 x i8> [[INS]], <i8 5, i8 undef> ; CHECK-NEXT: [[BO:%.*]] = shl nuw <2 x i8> [[INS]], <i8 5, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = shl nuw <2 x i8> %ins, <i8 5, i8 undef> %bo = shl nuw <2 x i8> %ins, <i8 5, i8 undef>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @shl_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @shl_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @shl_constant_op1_not_undef_lane( ; CHECK-LABEL: @shl_constant_op1_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = shl nuw <2 x i8> [[INS]], <i8 5, i8 2> ; CHECK-NEXT: [[BO:%.*]] = shl nuw <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = shl nuw <2 x i8> %ins, <i8 5, i8 2> %bo = shl nuw <2 x i8> %ins, <i8 5, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @ashr_constant_op0(i8 %x) { define <2 x i8> @ashr_constant_op0(i8 %x) {
; CHECK-LABEL: @ashr_constant_op0( ; CHECK-LABEL: @ashr_constant_op0(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = ashr exact <2 x i8> <i8 undef, i8 2>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = ashr exact <2 x i8> <i8 undef, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = ashr exact <2 x i8> <i8 undef, i8 2>, %ins %bo = ashr exact <2 x i8> <i8 undef, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @ashr_constant_op0_not_undef_lane(i8 %x) { define <2 x i8> @ashr_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @ashr_constant_op0_not_undef_lane( ; CHECK-LABEL: @ashr_constant_op0_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = lshr exact <2 x i8> <i8 5, i8 2>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = lshr exact <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = ashr exact <2 x i8> <i8 5, i8 2>, %ins %bo = ashr exact <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @ashr_constant_op1(i8 %x) { define <2 x i8> @ashr_constant_op1(i8 %x) {
; CHECK-LABEL: @ashr_constant_op1( ; CHECK-LABEL: @ashr_constant_op1(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = ashr <2 x i8> [[INS]], <i8 5, i8 undef> ; CHECK-NEXT: [[BO:%.*]] = ashr <2 x i8> [[INS]], <i8 5, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = ashr <2 x i8> %ins, <i8 5, i8 undef> %bo = ashr <2 x i8> %ins, <i8 5, i8 undef>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @ashr_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @ashr_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @ashr_constant_op1_not_undef_lane( ; CHECK-LABEL: @ashr_constant_op1_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = ashr <2 x i8> [[INS]], <i8 5, i8 2> ; CHECK-NEXT: [[BO:%.*]] = ashr <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = ashr <2 x i8> %ins, <i8 5, i8 2> %bo = ashr <2 x i8> %ins, <i8 5, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @lshr_constant_op0(i8 %x) { define <2 x i8> @lshr_constant_op0(i8 %x) {
; CHECK-LABEL: @lshr_constant_op0( ; CHECK-LABEL: @lshr_constant_op0(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 undef>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 undef>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = lshr <2 x i8> <i8 5, i8 undef>, %ins %bo = lshr <2 x i8> <i8 5, i8 undef>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @lshr_constant_op0_not_undef_lane(i8 %x) { define <2 x i8> @lshr_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @lshr_constant_op0_not_undef_lane( ; CHECK-LABEL: @lshr_constant_op0_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 2>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = lshr <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = lshr <2 x i8> <i8 5, i8 2>, %ins %bo = lshr <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @lshr_constant_op1(i8 %x) { define <2 x i8> @lshr_constant_op1(i8 %x) {
; CHECK-LABEL: @lshr_constant_op1( ; CHECK-LABEL: @lshr_constant_op1(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = lshr exact <2 x i8> [[INS]], <i8 undef, i8 2> ; CHECK-NEXT: [[BO:%.*]] = lshr exact <2 x i8> [[INS]], <i8 undef, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = lshr exact <2 x i8> %ins, <i8 undef, i8 2> %bo = lshr exact <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @lshr_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @lshr_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @lshr_constant_op1_not_undef_lane( ; CHECK-LABEL: @lshr_constant_op1_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = lshr exact <2 x i8> [[INS]], <i8 5, i8 2> ; CHECK-NEXT: [[BO:%.*]] = lshr exact <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = lshr exact <2 x i8> %ins, <i8 5, i8 2> %bo = lshr exact <2 x i8> %ins, <i8 5, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @urem_constant_op0(i8 %x) { define <2 x i8> @urem_constant_op0(i8 %x) {
; CHECK-LABEL: @urem_constant_op0( ; CHECK-LABEL: @urem_constant_op0(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> <i8 5, i8 undef>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> <i8 5, i8 undef>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = urem <2 x i8> <i8 5, i8 undef>, %ins %bo = urem <2 x i8> <i8 5, i8 undef>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @urem_constant_op0_not_undef_lane(i8 %x) { define <2 x i8> @urem_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @urem_constant_op0_not_undef_lane( ; CHECK-LABEL: @urem_constant_op0_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> <i8 5, i8 2>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = urem <2 x i8> <i8 5, i8 2>, %ins %bo = urem <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @urem_constant_op1(i8 %x) { define <2 x i8> @urem_constant_op1(i8 %x) {
; CHECK-LABEL: @urem_constant_op1( ; CHECK-LABEL: @urem_constant_op1(
; CHECK-NEXT: ret <2 x i8> poison ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = urem <2 x i8> %ins, <i8 undef, i8 2> %bo = urem <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @urem_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @urem_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @urem_constant_op1_not_undef_lane( ; CHECK-LABEL: @urem_constant_op1_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> [[INS]], <i8 5, i8 2> ; CHECK-NEXT: [[BO:%.*]] = urem <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = urem <2 x i8> %ins, <i8 5, i8 2> %bo = urem <2 x i8> %ins, <i8 5, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @srem_constant_op0(i8 %x) { define <2 x i8> @srem_constant_op0(i8 %x) {
; CHECK-LABEL: @srem_constant_op0( ; CHECK-LABEL: @srem_constant_op0(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = srem <2 x i8> <i8 5, i8 undef>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = srem <2 x i8> <i8 5, i8 undef>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = srem <2 x i8> <i8 5, i8 undef>, %ins %bo = srem <2 x i8> <i8 5, i8 undef>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @srem_constant_op0_not_undef_lane(i8 %x) { define <2 x i8> @srem_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @srem_constant_op0_not_undef_lane( ; CHECK-LABEL: @srem_constant_op0_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = srem <2 x i8> <i8 5, i8 2>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = srem <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = srem <2 x i8> <i8 5, i8 2>, %ins %bo = srem <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @srem_constant_op1(i8 %x) { define <2 x i8> @srem_constant_op1(i8 %x) {
; CHECK-LABEL: @srem_constant_op1( ; CHECK-LABEL: @srem_constant_op1(
; CHECK-NEXT: ret <2 x i8> poison ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = srem <2 x i8> %ins, <i8 undef, i8 2> %bo = srem <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @srem_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @srem_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @srem_constant_op1_not_undef_lane( ; CHECK-LABEL: @srem_constant_op1_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = srem <2 x i8> [[INS]], <i8 5, i8 2> ; CHECK-NEXT: [[BO:%.*]] = srem <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = srem <2 x i8> %ins, <i8 5, i8 2> %bo = srem <2 x i8> %ins, <i8 5, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @udiv_constant_op0(i8 %x) { define <2 x i8> @udiv_constant_op0(i8 %x) {
; CHECK-LABEL: @udiv_constant_op0( ; CHECK-LABEL: @udiv_constant_op0(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = udiv exact <2 x i8> <i8 5, i8 undef>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = udiv exact <2 x i8> <i8 5, i8 undef>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = udiv exact <2 x i8> <i8 5, i8 undef>, %ins %bo = udiv exact <2 x i8> <i8 5, i8 undef>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @udiv_constant_op0_not_undef_lane(i8 %x) { define <2 x i8> @udiv_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @udiv_constant_op0_not_undef_lane( ; CHECK-LABEL: @udiv_constant_op0_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = udiv exact <2 x i8> <i8 5, i8 2>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = udiv exact <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = udiv exact <2 x i8> <i8 5, i8 2>, %ins %bo = udiv exact <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @udiv_constant_op1(i8 %x) { define <2 x i8> @udiv_constant_op1(i8 %x) {
; CHECK-LABEL: @udiv_constant_op1( ; CHECK-LABEL: @udiv_constant_op1(
; CHECK-NEXT: ret <2 x i8> poison ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = udiv <2 x i8> %ins, <i8 undef, i8 2> %bo = udiv <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @udiv_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @udiv_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @udiv_constant_op1_not_undef_lane( ; CHECK-LABEL: @udiv_constant_op1_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = udiv <2 x i8> [[INS]], <i8 5, i8 2> ; CHECK-NEXT: [[BO:%.*]] = udiv <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = udiv <2 x i8> %ins, <i8 5, i8 2> %bo = udiv <2 x i8> %ins, <i8 5, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @sdiv_constant_op0(i8 %x) { define <2 x i8> @sdiv_constant_op0(i8 %x) {
; CHECK-LABEL: @sdiv_constant_op0( ; CHECK-LABEL: @sdiv_constant_op0(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = sdiv <2 x i8> <i8 5, i8 undef>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = sdiv <2 x i8> <i8 5, i8 undef>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = sdiv <2 x i8> <i8 5, i8 undef>, %ins %bo = sdiv <2 x i8> <i8 5, i8 undef>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @sdiv_constant_op0_not_undef_lane(i8 %x) { define <2 x i8> @sdiv_constant_op0_not_undef_lane(i8 %x) {
; CHECK-LABEL: @sdiv_constant_op0_not_undef_lane( ; CHECK-LABEL: @sdiv_constant_op0_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = sdiv <2 x i8> <i8 5, i8 2>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = sdiv <2 x i8> <i8 5, i8 2>, [[INS]]
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = sdiv <2 x i8> <i8 5, i8 2>, %ins %bo = sdiv <2 x i8> <i8 5, i8 2>, %ins
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @sdiv_constant_op1(i8 %x) { define <2 x i8> @sdiv_constant_op1(i8 %x) {
; CHECK-LABEL: @sdiv_constant_op1( ; CHECK-LABEL: @sdiv_constant_op1(
; CHECK-NEXT: ret <2 x i8> poison ; CHECK-NEXT: ret <2 x i8> poison
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = sdiv exact <2 x i8> %ins, <i8 undef, i8 2> %bo = sdiv exact <2 x i8> %ins, <i8 undef, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @sdiv_constant_op1_not_undef_lane(i8 %x) { define <2 x i8> @sdiv_constant_op1_not_undef_lane(i8 %x) {
; CHECK-LABEL: @sdiv_constant_op1_not_undef_lane( ; CHECK-LABEL: @sdiv_constant_op1_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = sdiv exact <2 x i8> [[INS]], <i8 5, i8 2> ; CHECK-NEXT: [[BO:%.*]] = sdiv exact <2 x i8> [[INS]], <i8 5, i8 2>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = sdiv exact <2 x i8> %ins, <i8 5, i8 2> %bo = sdiv exact <2 x i8> %ins, <i8 5, i8 2>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @and_constant(i8 %x) { define <2 x i8> @and_constant(i8 %x) {
; CHECK-LABEL: @and_constant( ; CHECK-LABEL: @and_constant(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = and <2 x i8> [[INS]], <i8 42, i8 undef> ; CHECK-NEXT: [[BO:%.*]] = and <2 x i8> [[INS]], <i8 42, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = and <2 x i8> %ins, <i8 42, i8 undef> %bo = and <2 x i8> %ins, <i8 42, i8 undef>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @and_constant_not_undef_lane(i8 %x) { define <2 x i8> @and_constant_not_undef_lane(i8 %x) {
; CHECK-LABEL: @and_constant_not_undef_lane( ; CHECK-LABEL: @and_constant_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = and <2 x i8> [[INS]], <i8 42, i8 -42> ; CHECK-NEXT: [[BO:%.*]] = and <2 x i8> [[INS]], <i8 42, i8 -42>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = and <2 x i8> %ins, <i8 42, i8 -42> %bo = and <2 x i8> %ins, <i8 42, i8 -42>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @or_constant(i8 %x) { define <2 x i8> @or_constant(i8 %x) {
; CHECK-LABEL: @or_constant( ; CHECK-LABEL: @or_constant(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = or <2 x i8> [[INS]], <i8 undef, i8 -42> ; CHECK-NEXT: [[BO:%.*]] = or <2 x i8> [[INS]], <i8 undef, i8 -42>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = or <2 x i8> %ins, <i8 undef, i8 -42> %bo = or <2 x i8> %ins, <i8 undef, i8 -42>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @or_constant_not_undef_lane(i8 %x) { define <2 x i8> @or_constant_not_undef_lane(i8 %x) {
; CHECK-LABEL: @or_constant_not_undef_lane( ; CHECK-LABEL: @or_constant_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 undef, i8 poison>, i8 [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = or <2 x i8> [[INS]], <i8 42, i8 -42> ; CHECK-NEXT: [[BO:%.*]] = or <2 x i8> [[INS]], <i8 42, i8 -42>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 1 %ins = insertelement <2 x i8> undef, i8 %x, i32 1
%bo = or <2 x i8> %ins, <i8 42, i8 -42> %bo = or <2 x i8> %ins, <i8 42, i8 -42>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @xor_constant(i8 %x) { define <2 x i8> @xor_constant(i8 %x) {
; CHECK-LABEL: @xor_constant( ; CHECK-LABEL: @xor_constant(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = xor <2 x i8> [[INS]], <i8 42, i8 undef> ; CHECK-NEXT: [[BO:%.*]] = xor <2 x i8> [[INS]], <i8 42, i8 undef>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = xor <2 x i8> %ins, <i8 42, i8 undef> %bo = xor <2 x i8> %ins, <i8 42, i8 undef>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x i8> @xor_constant_not_undef_lane(i8 %x) { define <2 x i8> @xor_constant_not_undef_lane(i8 %x) {
; CHECK-LABEL: @xor_constant_not_undef_lane( ; CHECK-LABEL: @xor_constant_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x i8> <i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = xor <2 x i8> [[INS]], <i8 42, i8 -42> ; CHECK-NEXT: [[BO:%.*]] = xor <2 x i8> [[INS]], <i8 42, i8 -42>
; CHECK-NEXT: ret <2 x i8> [[BO]] ; CHECK-NEXT: ret <2 x i8> [[BO]]
; ;
%ins = insertelement <2 x i8> undef, i8 %x, i32 0 %ins = insertelement <2 x i8> undef, i8 %x, i32 0
%bo = xor <2 x i8> %ins, <i8 42, i8 -42> %bo = xor <2 x i8> %ins, <i8 42, i8 -42>
ret <2 x i8> %bo ret <2 x i8> %bo
} }
define <2 x float> @fadd_constant(float %x) { define <2 x float> @fadd_constant(float %x) {
; CHECK-LABEL: @fadd_constant( ; CHECK-LABEL: @fadd_constant(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float 4.200000e+01, float undef> ; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float 4.200000e+01, float undef>
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 0 %ins = insertelement <2 x float> undef, float %x, i32 0
%bo = fadd <2 x float> %ins, <float 42.0, float undef> %bo = fadd <2 x float> %ins, <float 42.0, float undef>
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @fadd_constant_not_undef_lane(float %x) { define <2 x float> @fadd_constant_not_undef_lane(float %x) {
; CHECK-LABEL: @fadd_constant_not_undef_lane( ; CHECK-LABEL: @fadd_constant_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01> ; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 1 %ins = insertelement <2 x float> undef, float %x, i32 1
%bo = fadd <2 x float> %ins, <float 42.0, float -42.0> %bo = fadd <2 x float> %ins, <float 42.0, float -42.0>
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @fsub_constant_op0(float %x) { define <2 x float> @fsub_constant_op0(float %x) {
; CHECK-LABEL: @fsub_constant_op0( ; CHECK-LABEL: @fsub_constant_op0(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fsub fast <2 x float> <float 4.200000e+01, float undef>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = fsub fast <2 x float> <float 4.200000e+01, float undef>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 0 %ins = insertelement <2 x float> undef, float %x, i32 0
%bo = fsub fast <2 x float> <float 42.0, float undef>, %ins %bo = fsub fast <2 x float> <float 42.0, float undef>, %ins
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @fsub_constant_op0_not_undef_lane(float %x) { define <2 x float> @fsub_constant_op0_not_undef_lane(float %x) {
; CHECK-LABEL: @fsub_constant_op0_not_undef_lane( ; CHECK-LABEL: @fsub_constant_op0_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = fsub nsz <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = fsub nsz <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 1 %ins = insertelement <2 x float> undef, float %x, i32 1
%bo = fsub nsz <2 x float> <float 42.0, float -42.0>, %ins %bo = fsub nsz <2 x float> <float 42.0, float -42.0>, %ins
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @fsub_constant_op1(float %x) { define <2 x float> @fsub_constant_op1(float %x) {
; CHECK-LABEL: @fsub_constant_op1( ; CHECK-LABEL: @fsub_constant_op1(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float undef, float -4.200000e+01> ; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float undef, float -4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 1 %ins = insertelement <2 x float> undef, float %x, i32 1
%bo = fsub <2 x float> %ins, <float undef, float 42.0> %bo = fsub <2 x float> %ins, <float undef, float 42.0>
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @fsub_constant_op1_not_undef_lane(float %x) { define <2 x float> @fsub_constant_op1_not_undef_lane(float %x) {
; CHECK-LABEL: @fsub_constant_op1_not_undef_lane( ; CHECK-LABEL: @fsub_constant_op1_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float -4.200000e+01, float 4.200000e+01> ; CHECK-NEXT: [[BO:%.*]] = fadd <2 x float> [[INS]], <float -4.200000e+01, float 4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 0 %ins = insertelement <2 x float> undef, float %x, i32 0
%bo = fsub <2 x float> %ins, <float 42.0, float -42.0> %bo = fsub <2 x float> %ins, <float 42.0, float -42.0>
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @fmul_constant(float %x) { define <2 x float> @fmul_constant(float %x) {
; CHECK-LABEL: @fmul_constant( ; CHECK-LABEL: @fmul_constant(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fmul reassoc <2 x float> [[INS]], <float 4.200000e+01, float undef> ; CHECK-NEXT: [[BO:%.*]] = fmul reassoc <2 x float> [[INS]], <float 4.200000e+01, float undef>
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 0 %ins = insertelement <2 x float> undef, float %x, i32 0
%bo = fmul reassoc <2 x float> %ins, <float 42.0, float undef> %bo = fmul reassoc <2 x float> %ins, <float 42.0, float undef>
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @fmul_constant_not_undef_lane(float %x) { define <2 x float> @fmul_constant_not_undef_lane(float %x) {
; CHECK-LABEL: @fmul_constant_not_undef_lane( ; CHECK-LABEL: @fmul_constant_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = fmul <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01> ; CHECK-NEXT: [[BO:%.*]] = fmul <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 1 %ins = insertelement <2 x float> undef, float %x, i32 1
%bo = fmul <2 x float> %ins, <float 42.0, float -42.0> %bo = fmul <2 x float> %ins, <float 42.0, float -42.0>
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @fdiv_constant_op0(float %x) { define <2 x float> @fdiv_constant_op0(float %x) {
; CHECK-LABEL: @fdiv_constant_op0( ; CHECK-LABEL: @fdiv_constant_op0(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = fdiv nnan <2 x float> <float undef, float 4.200000e+01>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = fdiv nnan <2 x float> <float undef, float 4.200000e+01>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 1 %ins = insertelement <2 x float> undef, float %x, i32 1
%bo = fdiv nnan <2 x float> <float undef, float 42.0>, %ins %bo = fdiv nnan <2 x float> <float undef, float 42.0>, %ins
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @fdiv_constant_op0_not_undef_lane(float %x) { define <2 x float> @fdiv_constant_op0_not_undef_lane(float %x) {
; CHECK-LABEL: @fdiv_constant_op0_not_undef_lane( ; CHECK-LABEL: @fdiv_constant_op0_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fdiv ninf <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = fdiv ninf <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 0 %ins = insertelement <2 x float> undef, float %x, i32 0
%bo = fdiv ninf <2 x float> <float 42.0, float -42.0>, %ins %bo = fdiv ninf <2 x float> <float 42.0, float -42.0>, %ins
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @fdiv_constant_op1(float %x) { define <2 x float> @fdiv_constant_op1(float %x) {
; CHECK-LABEL: @fdiv_constant_op1( ; CHECK-LABEL: @fdiv_constant_op1(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fdiv <2 x float> [[INS]], <float 4.200000e+01, float undef> ; CHECK-NEXT: [[BO:%.*]] = fdiv <2 x float> [[INS]], <float 4.200000e+01, float undef>
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 0 %ins = insertelement <2 x float> undef, float %x, i32 0
%bo = fdiv <2 x float> %ins, <float 42.0, float undef> %bo = fdiv <2 x float> %ins, <float 42.0, float undef>
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @fdiv_constant_op1_not_undef_lane(float %x) { define <2 x float> @fdiv_constant_op1_not_undef_lane(float %x) {
; CHECK-LABEL: @fdiv_constant_op1_not_undef_lane( ; CHECK-LABEL: @fdiv_constant_op1_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = fdiv <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01> ; CHECK-NEXT: [[BO:%.*]] = fdiv <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 0 %ins = insertelement <2 x float> undef, float %x, i32 0
%bo = fdiv <2 x float> %ins, <float 42.0, float -42.0> %bo = fdiv <2 x float> %ins, <float 42.0, float -42.0>
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @frem_constant_op0(float %x) { define <2 x float> @frem_constant_op0(float %x) {
; CHECK-LABEL: @frem_constant_op0( ; CHECK-LABEL: @frem_constant_op0(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = frem fast <2 x float> <float 4.200000e+01, float undef>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = frem fast <2 x float> <float 4.200000e+01, float undef>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 0 %ins = insertelement <2 x float> undef, float %x, i32 0
%bo = frem fast <2 x float> <float 42.0, float undef>, %ins %bo = frem fast <2 x float> <float 42.0, float undef>, %ins
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @frem_constant_op0_not_undef_lane(float %x) { define <2 x float> @frem_constant_op0_not_undef_lane(float %x) {
; CHECK-LABEL: @frem_constant_op0_not_undef_lane( ; CHECK-LABEL: @frem_constant_op0_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = frem <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]] ; CHECK-NEXT: [[BO:%.*]] = frem <2 x float> <float 4.200000e+01, float -4.200000e+01>, [[INS]]
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 1 %ins = insertelement <2 x float> undef, float %x, i32 1
%bo = frem <2 x float> <float 42.0, float -42.0>, %ins %bo = frem <2 x float> <float 42.0, float -42.0>, %ins
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @frem_constant_op1(float %x) { define <2 x float> @frem_constant_op1(float %x) {
; CHECK-LABEL: @frem_constant_op1( ; CHECK-LABEL: @frem_constant_op1(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 1 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[X:%.*]], i64 1
; CHECK-NEXT: [[BO:%.*]] = frem ninf <2 x float> [[INS]], <float undef, float 4.200000e+01> ; CHECK-NEXT: [[BO:%.*]] = frem ninf <2 x float> [[INS]], <float undef, float 4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 1 %ins = insertelement <2 x float> undef, float %x, i32 1
%bo = frem ninf <2 x float> %ins, <float undef, float 42.0> %bo = frem ninf <2 x float> %ins, <float undef, float 42.0>
ret <2 x float> %bo ret <2 x float> %bo
} }
define <2 x float> @frem_constant_op1_not_undef_lane(float %x) { define <2 x float> @frem_constant_op1_not_undef_lane(float %x) {
; CHECK-LABEL: @frem_constant_op1_not_undef_lane( ; CHECK-LABEL: @frem_constant_op1_not_undef_lane(
; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[INS:%.*]] = insertelement <2 x float> <float poison, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: [[BO:%.*]] = frem nnan <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01> ; CHECK-NEXT: [[BO:%.*]] = frem nnan <2 x float> [[INS]], <float 4.200000e+01, float -4.200000e+01>
; CHECK-NEXT: ret <2 x float> [[BO]] ; CHECK-NEXT: ret <2 x float> [[BO]]
; ;
%ins = insertelement <2 x float> undef, float %x, i32 0 %ins = insertelement <2 x float> undef, float %x, i32 0
%bo = frem nnan <2 x float> %ins, <float 42.0, float -42.0> %bo = frem nnan <2 x float> %ins, <float 42.0, float -42.0>
ret <2 x float> %bo ret <2 x float> %bo
} }

llvm/test/Transforms/InstCombine/insert-const-shuf.ll

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%add = fadd <3 x float> %shuf, %ins %add = fadd <3 x float> %shuf, %ins
ret <3 x float> %add ret <3 x float> %add
} }
; The inserted scalar constant index is out-of-bounds for the shuffle vector constant. ; The inserted scalar constant index is out-of-bounds for the shuffle vector constant.
define <5 x i8> @longerMask(<3 x i8> %x) { define <5 x i8> @longerMask(<3 x i8> %x) {
; CHECK-LABEL: @longerMask( ; CHECK-LABEL: @longerMask(
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> <i8 poison, i8 1, i8 poison>, <5 x i32> <i32 2, i32 1, i32 4, i32 poison, i32 poison> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> <i8 undef, i8 1, i8 poison>, <5 x i32> <i32 2, i32 1, i32 4, i32 3, i32 poison>
; CHECK-NEXT: [[INS:%.*]] = insertelement <5 x i8> [[SHUF]], i8 42, i64 4 ; CHECK-NEXT: [[INS:%.*]] = insertelement <5 x i8> [[SHUF]], i8 42, i64 4
; CHECK-NEXT: ret <5 x i8> [[INS]] ; CHECK-NEXT: ret <5 x i8> [[INS]]
; ;
%shuf = shufflevector <3 x i8> %x, <3 x i8> <i8 undef, i8 1, i8 2>, <5 x i32> <i32 2, i32 1, i32 4, i32 3, i32 0> %shuf = shufflevector <3 x i8> %x, <3 x i8> <i8 undef, i8 1, i8 2>, <5 x i32> <i32 2, i32 1, i32 4, i32 3, i32 0>
%ins = insertelement <5 x i8> %shuf, i8 42, i17 4 %ins = insertelement <5 x i8> %shuf, i8 42, i17 4
ret <5 x i8> %ins ret <5 x i8> %ins
} }
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llvm/test/Transforms/InstCombine/insert-extract-shuffle-inseltpoison.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -passes=instcombine %s | FileCheck %s ; RUN: opt -S -passes=instcombine %s | FileCheck %s
define <1 x i8> @test1(<8 x i8> %in) { define <1 x i8> @test1(<8 x i8> %in) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: [[VEC:%.*]] = shufflevector <8 x i8> [[IN:%.*]], <8 x i8> undef, <1 x i32> <i32 5> ; CHECK-NEXT: [[VEC:%.*]] = shufflevector <8 x i8> [[IN:%.*]], <8 x i8> poison, <1 x i32> <i32 5>
; CHECK-NEXT: ret <1 x i8> [[VEC]] ; CHECK-NEXT: ret <1 x i8> [[VEC]]
; ;
%val = extractelement <8 x i8> %in, i32 5 %val = extractelement <8 x i8> %in, i32 5
%vec = insertelement <1 x i8> poison, i8 %val, i32 0 %vec = insertelement <1 x i8> poison, i8 %val, i32 0
ret <1 x i8> %vec ret <1 x i8> %vec
} }
define <4 x i16> @test2(<8 x i16> %in, <8 x i16> %in2) { define <4 x i16> @test2(<8 x i16> %in, <8 x i16> %in2) {
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; ;
%xv = insertelement <4 x float> %q, float %x, i32 2 %xv = insertelement <4 x float> %q, float %x, i32 2
%r = shufflevector <4 x float> %y, <4 x float> %xv, <5 x i32> <i32 0, i32 6, i32 2, i32 undef, i32 undef> %r = shufflevector <4 x float> %y, <4 x float> %xv, <5 x i32> <i32 0, i32 6, i32 2, i32 undef, i32 undef>
ret <5 x float> %r ret <5 x float> %r
} }
define <4 x float> @insert_nonzero_index_splat(float %x) { define <4 x float> @insert_nonzero_index_splat(float %x) {
; CHECK-LABEL: @insert_nonzero_index_splat( ; CHECK-LABEL: @insert_nonzero_index_splat(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i64 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 poison> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 poison>
; CHECK-NEXT: ret <4 x float> [[SPLAT]] ; CHECK-NEXT: ret <4 x float> [[SPLAT]]
; ;
%xv = insertelement <4 x float> poison, float %x, i32 2 %xv = insertelement <4 x float> poison, float %x, i32 2
%splat = shufflevector <4 x float> %xv, <4 x float> poison, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> poison, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef>
ret <4 x float> %splat ret <4 x float> %splat
} }
define <3 x double> @insert_nonzero_index_splat_narrow(double %x) { define <3 x double> @insert_nonzero_index_splat_narrow(double %x) {
; CHECK-LABEL: @insert_nonzero_index_splat_narrow( ; CHECK-LABEL: @insert_nonzero_index_splat_narrow(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x double> undef, double [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x double> poison, double [[X:%.*]], i64 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <3 x double> [[TMP1]], <3 x double> poison, <3 x i32> <i32 0, i32 poison, i32 0> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <3 x double> [[TMP1]], <3 x double> poison, <3 x i32> <i32 0, i32 poison, i32 0>
; CHECK-NEXT: ret <3 x double> [[SPLAT]] ; CHECK-NEXT: ret <3 x double> [[SPLAT]]
; ;
%xv = insertelement <4 x double> poison, double %x, i32 3 %xv = insertelement <4 x double> poison, double %x, i32 3
%splat = shufflevector <4 x double> %xv, <4 x double> poison, <3 x i32> <i32 3, i32 undef, i32 3> %splat = shufflevector <4 x double> %xv, <4 x double> poison, <3 x i32> <i32 3, i32 undef, i32 3>
ret <3 x double> %splat ret <3 x double> %splat
} }
define <5 x i7> @insert_nonzero_index_splat_widen(i7 %x) { define <5 x i7> @insert_nonzero_index_splat_widen(i7 %x) {
; CHECK-LABEL: @insert_nonzero_index_splat_widen( ; CHECK-LABEL: @insert_nonzero_index_splat_widen(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x i7> undef, i7 [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x i7> poison, i7 [[X:%.*]], i64 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <5 x i7> [[TMP1]], <5 x i7> poison, <5 x i32> <i32 poison, i32 0, i32 0, i32 poison, i32 0> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <5 x i7> [[TMP1]], <5 x i7> poison, <5 x i32> <i32 poison, i32 0, i32 0, i32 poison, i32 0>
; CHECK-NEXT: ret <5 x i7> [[SPLAT]] ; CHECK-NEXT: ret <5 x i7> [[SPLAT]]
; ;
%xv = insertelement <4 x i7> poison, i7 %x, i32 1 %xv = insertelement <4 x i7> poison, i7 %x, i32 1
%splat = shufflevector <4 x i7> %xv, <4 x i7> poison, <5 x i32> <i32 undef, i32 1, i32 1, i32 undef, i32 1> %splat = shufflevector <4 x i7> %xv, <4 x i7> poison, <5 x i32> <i32 undef, i32 1, i32 1, i32 undef, i32 1>
ret <5 x i7> %splat ret <5 x i7> %splat
} }
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llvm/test/Transforms/InstCombine/insert-extract-shuffle.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -passes=instcombine %s | FileCheck %s ; RUN: opt -S -passes=instcombine %s | FileCheck %s
define <1 x i8> @test1(<8 x i8> %in) { define <1 x i8> @test1(<8 x i8> %in) {
; CHECK-LABEL: @test1( ; CHECK-LABEL: @test1(
; CHECK-NEXT: [[VEC:%.*]] = shufflevector <8 x i8> [[IN:%.*]], <8 x i8> undef, <1 x i32> <i32 5> ; CHECK-NEXT: [[VEC:%.*]] = shufflevector <8 x i8> [[IN:%.*]], <8 x i8> poison, <1 x i32> <i32 5>
; CHECK-NEXT: ret <1 x i8> [[VEC]] ; CHECK-NEXT: ret <1 x i8> [[VEC]]
; ;
%val = extractelement <8 x i8> %in, i32 5 %val = extractelement <8 x i8> %in, i32 5
%vec = insertelement <1 x i8> undef, i8 %val, i32 0 %vec = insertelement <1 x i8> undef, i8 %val, i32 0
ret <1 x i8> %vec ret <1 x i8> %vec
} }
define <4 x i16> @test2(<8 x i16> %in, <8 x i16> %in2) { define <4 x i16> @test2(<8 x i16> %in, <8 x i16> %in2) {
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} }
; PR34724: https://bugs.llvm.org/show_bug.cgi?id=34724 ; PR34724: https://bugs.llvm.org/show_bug.cgi?id=34724
define <4 x float> @collectShuffleElts(<2 x float> %x, float %y) { define <4 x float> @collectShuffleElts(<2 x float> %x, float %y) {
; CHECK-LABEL: @collectShuffleElts( ; CHECK-LABEL: @collectShuffleElts(
; CHECK-NEXT: [[X0:%.*]] = extractelement <2 x float> [[X:%.*]], i64 0 ; CHECK-NEXT: [[X0:%.*]] = extractelement <2 x float> [[X:%.*]], i64 0
; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x float> [[X]], i64 1 ; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x float> [[X]], i64 1
; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x float> undef, float [[X0]], i64 1 ; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x float> <float undef, float poison, float poison, float poison>, float [[X0]], i64 1
; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[X1]], i64 2 ; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[X1]], i64 2
; CHECK-NEXT: [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[Y:%.*]], i64 3 ; CHECK-NEXT: [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[Y:%.*]], i64 3
; CHECK-NEXT: ret <4 x float> [[V3]] ; CHECK-NEXT: ret <4 x float> [[V3]]
; ;
%x0 = extractelement <2 x float> %x, i32 0 %x0 = extractelement <2 x float> %x, i32 0
%x1 = extractelement <2 x float> %x, i32 1 %x1 = extractelement <2 x float> %x, i32 1
%v1 = insertelement <4 x float> undef, float %x0, i32 1 %v1 = insertelement <4 x float> undef, float %x0, i32 1
%v2 = insertelement <4 x float> %v1, float %x1, i32 2 %v2 = insertelement <4 x float> %v1, float %x1, i32 2
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
; ;
%xv = insertelement <4 x float> %q, float %x, i32 2 %xv = insertelement <4 x float> %q, float %x, i32 2
%r = shufflevector <4 x float> %y, <4 x float> %xv, <5 x i32> <i32 0, i32 6, i32 2, i32 undef, i32 undef> %r = shufflevector <4 x float> %y, <4 x float> %xv, <5 x i32> <i32 0, i32 6, i32 2, i32 undef, i32 undef>
ret <5 x float> %r ret <5 x float> %r
} }
define <4 x float> @insert_nonzero_index_splat(float %x) { define <4 x float> @insert_nonzero_index_splat(float %x) {
; CHECK-LABEL: @insert_nonzero_index_splat( ; CHECK-LABEL: @insert_nonzero_index_splat(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i64 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 poison> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 poison>
; CHECK-NEXT: ret <4 x float> [[SPLAT]] ; CHECK-NEXT: ret <4 x float> [[SPLAT]]
; ;
%xv = insertelement <4 x float> undef, float %x, i32 2 %xv = insertelement <4 x float> undef, float %x, i32 2
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef>
ret <4 x float> %splat ret <4 x float> %splat
} }
define <3 x double> @insert_nonzero_index_splat_narrow(double %x) { define <3 x double> @insert_nonzero_index_splat_narrow(double %x) {
; CHECK-LABEL: @insert_nonzero_index_splat_narrow( ; CHECK-LABEL: @insert_nonzero_index_splat_narrow(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x double> undef, double [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x double> poison, double [[X:%.*]], i64 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <3 x double> [[TMP1]], <3 x double> poison, <3 x i32> <i32 0, i32 poison, i32 0> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <3 x double> [[TMP1]], <3 x double> poison, <3 x i32> <i32 0, i32 poison, i32 0>
; CHECK-NEXT: ret <3 x double> [[SPLAT]] ; CHECK-NEXT: ret <3 x double> [[SPLAT]]
; ;
%xv = insertelement <4 x double> undef, double %x, i32 3 %xv = insertelement <4 x double> undef, double %x, i32 3
%splat = shufflevector <4 x double> %xv, <4 x double> undef, <3 x i32> <i32 3, i32 undef, i32 3> %splat = shufflevector <4 x double> %xv, <4 x double> undef, <3 x i32> <i32 3, i32 undef, i32 3>
ret <3 x double> %splat ret <3 x double> %splat
} }
define <5 x i7> @insert_nonzero_index_splat_widen(i7 %x) { define <5 x i7> @insert_nonzero_index_splat_widen(i7 %x) {
; CHECK-LABEL: @insert_nonzero_index_splat_widen( ; CHECK-LABEL: @insert_nonzero_index_splat_widen(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x i7> undef, i7 [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <5 x i7> poison, i7 [[X:%.*]], i64 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <5 x i7> [[TMP1]], <5 x i7> poison, <5 x i32> <i32 poison, i32 0, i32 0, i32 poison, i32 0> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <5 x i7> [[TMP1]], <5 x i7> poison, <5 x i32> <i32 poison, i32 0, i32 0, i32 poison, i32 0>
; CHECK-NEXT: ret <5 x i7> [[SPLAT]] ; CHECK-NEXT: ret <5 x i7> [[SPLAT]]
; ;
%xv = insertelement <4 x i7> undef, i7 %x, i32 1 %xv = insertelement <4 x i7> undef, i7 %x, i32 1
%splat = shufflevector <4 x i7> %xv, <4 x i7> undef, <5 x i32> <i32 undef, i32 1, i32 1, i32 undef, i32 1> %splat = shufflevector <4 x i7> %xv, <4 x i7> undef, <5 x i32> <i32 undef, i32 1, i32 1, i32 undef, i32 1>
ret <5 x i7> %splat ret <5 x i7> %splat
} }
; Negative test - don't increase instruction count ; Negative test - don't increase instruction count
define <4 x float> @insert_nonzero_index_splat_extra_use(float %x) { define <4 x float> @insert_nonzero_index_splat_extra_use(float %x) {
; CHECK-LABEL: @insert_nonzero_index_splat_extra_use( ; CHECK-LABEL: @insert_nonzero_index_splat_extra_use(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i64 2 ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> <float undef, float undef, float poison, float undef>, float [[X:%.*]], i64 2
; CHECK-NEXT: call void @use(<4 x float> [[XV]]) ; CHECK-NEXT: call void @use(<4 x float> [[XV]])
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 poison, i32 2, i32 2, i32 poison> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 2, i32 2, i32 poison>
; CHECK-NEXT: ret <4 x float> [[SPLAT]] ; CHECK-NEXT: ret <4 x float> [[SPLAT]]
; ;
%xv = insertelement <4 x float> undef, float %x, i32 2 %xv = insertelement <4 x float> undef, float %x, i32 2
call void @use(<4 x float> %xv) call void @use(<4 x float> %xv)
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 2, i32 undef>
ret <4 x float> %splat ret <4 x float> %splat
} }
; Negative test - non-undef base vector ; Negative test - non-undef base vector
define <4 x float> @insert_nonzero_index_splat_wrong_base(float %x, <4 x float> %y) { define <4 x float> @insert_nonzero_index_splat_wrong_base(float %x, <4 x float> %y) {
; CHECK-LABEL: @insert_nonzero_index_splat_wrong_base( ; CHECK-LABEL: @insert_nonzero_index_splat_wrong_base(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> [[Y:%.*]], float [[X:%.*]], i64 2 ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> [[Y:%.*]], float [[X:%.*]], i64 2
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 poison, i32 2, i32 3, i32 poison> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 2, i32 3, i32 poison>
; CHECK-NEXT: ret <4 x float> [[SPLAT]] ; CHECK-NEXT: ret <4 x float> [[SPLAT]]
; ;
%xv = insertelement <4 x float> %y, float %x, i32 2 %xv = insertelement <4 x float> %y, float %x, i32 2
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 3, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 3, i32 undef>
ret <4 x float> %splat ret <4 x float> %splat
} }
; Negative test - non-constant insert index ; Negative test - non-constant insert index
define <4 x float> @insert_nonzero_index_splat_wrong_index(float %x, i32 %index) { define <4 x float> @insert_nonzero_index_splat_wrong_index(float %x, i32 %index) {
; CHECK-LABEL: @insert_nonzero_index_splat_wrong_index( ; CHECK-LABEL: @insert_nonzero_index_splat_wrong_index(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i32 [[INDEX:%.*]] ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> <float poison, float undef, float poison, float poison>, float [[X:%.*]], i32 [[INDEX:%.*]]
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 poison, i32 1, i32 1, i32 poison> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 1, i32 1, i32 poison>
; CHECK-NEXT: ret <4 x float> [[SPLAT]] ; CHECK-NEXT: ret <4 x float> [[SPLAT]]
; ;
%xv = insertelement <4 x float> undef, float %x, i32 %index %xv = insertelement <4 x float> undef, float %x, i32 %index
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
ret <4 x float> %splat ret <4 x float> %splat
} }
define <4 x float> @insert_in_splat(float %x) { define <4 x float> @insert_in_splat(float %x) {
; CHECK-LABEL: @insert_in_splat( ; CHECK-LABEL: @insert_in_splat(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i64 0
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 0>
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%xv = insertelement <4 x float> undef, float %x, i32 0 %xv = insertelement <4 x float> undef, float %x, i32 0
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
%r = insertelement <4 x float> %splat, float %x, i32 3 %r = insertelement <4 x float> %splat, float %x, i32 3
ret <4 x float> %r ret <4 x float> %r
} }
define <4 x float> @insert_in_splat_extra_uses(float %x) { define <4 x float> @insert_in_splat_extra_uses(float %x) {
; CHECK-LABEL: @insert_in_splat_extra_uses( ; CHECK-LABEL: @insert_in_splat_extra_uses(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> <float poison, float undef, float undef, float undef>, float [[X:%.*]], i64 0
; CHECK-NEXT: call void @use(<4 x float> [[XV]]) ; CHECK-NEXT: call void @use(<4 x float> [[XV]])
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 poison, i32 0, i32 0, i32 poison> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 poison>
; CHECK-NEXT: call void @use(<4 x float> [[SPLAT]]) ; CHECK-NEXT: call void @use(<4 x float> [[SPLAT]])
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 0>
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%xv = insertelement <4 x float> undef, float %x, i32 0 %xv = insertelement <4 x float> undef, float %x, i32 0
call void @use(<4 x float> %xv) call void @use(<4 x float> %xv)
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
call void @use(<4 x float> %splat) call void @use(<4 x float> %splat)
%r = insertelement <4 x float> %splat, float %x, i32 3 %r = insertelement <4 x float> %splat, float %x, i32 3
ret <4 x float> %r ret <4 x float> %r
} }
; Negative test - not a constant index insert ; Negative test - not a constant index insert
define <4 x float> @insert_in_splat_variable_index(float %x, i32 %y) { define <4 x float> @insert_in_splat_variable_index(float %x, i32 %y) {
; CHECK-LABEL: @insert_in_splat_variable_index( ; CHECK-LABEL: @insert_in_splat_variable_index(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i64 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 poison, i32 0, i32 0, i32 poison> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 poison>
; CHECK-NEXT: [[R:%.*]] = insertelement <4 x float> [[SPLAT]], float [[X]], i32 [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = insertelement <4 x float> [[SPLAT]], float [[X]], i32 [[Y:%.*]]
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%xv = insertelement <4 x float> undef, float %x, i32 0 %xv = insertelement <4 x float> undef, float %x, i32 0
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 undef>
%r = insertelement <4 x float> %splat, float %x, i32 %y %r = insertelement <4 x float> %splat, float %x, i32 %y
ret <4 x float> %r ret <4 x float> %r
} }
; Negative test - not a splat shuffle ; Negative test - not a splat shuffle
define <4 x float> @insert_in_nonsplat(float %x, <4 x float> %y) { define <4 x float> @insert_in_nonsplat(float %x, <4 x float> %y) {
; CHECK-LABEL: @insert_in_nonsplat( ; CHECK-LABEL: @insert_in_nonsplat(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> undef, float [[X:%.*]], i64 0 ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> poison, float [[X:%.*]], i64 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> [[Y:%.*]], <4 x i32> <i32 poison, i32 0, i32 4, i32 poison> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> [[Y:%.*]], <4 x i32> <i32 poison, i32 0, i32 4, i32 poison>
; CHECK-NEXT: [[R:%.*]] = insertelement <4 x float> [[SPLAT]], float [[X]], i64 3 ; CHECK-NEXT: [[R:%.*]] = insertelement <4 x float> [[SPLAT]], float [[X]], i64 3
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%xv = insertelement <4 x float> undef, float %x, i32 0 %xv = insertelement <4 x float> undef, float %x, i32 0
%splat = shufflevector <4 x float> %xv, <4 x float> %y, <4 x i32> <i32 undef, i32 0, i32 4, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> %y, <4 x i32> <i32 undef, i32 0, i32 4, i32 undef>
%r = insertelement <4 x float> %splat, float %x, i32 3 %r = insertelement <4 x float> %splat, float %x, i32 3
ret <4 x float> %r ret <4 x float> %r
} }
; Negative test - not a splat shuffle ; Negative test - not a splat shuffle
define <4 x float> @insert_in_nonsplat2(float %x, <4 x float> %y) { define <4 x float> @insert_in_nonsplat2(float %x, <4 x float> %y) {
; CHECK-LABEL: @insert_in_nonsplat2( ; CHECK-LABEL: @insert_in_nonsplat2(
; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> [[Y:%.*]], float [[X:%.*]], i64 0 ; CHECK-NEXT: [[XV:%.*]] = insertelement <4 x float> [[Y:%.*]], float [[X:%.*]], i64 0
; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> undef, <4 x i32> <i32 poison, i32 0, i32 1, i32 poison> ; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[XV]], <4 x float> poison, <4 x i32> <i32 poison, i32 0, i32 1, i32 poison>
; CHECK-NEXT: [[R:%.*]] = insertelement <4 x float> [[SPLAT]], float [[X]], i64 3 ; CHECK-NEXT: [[R:%.*]] = insertelement <4 x float> [[SPLAT]], float [[X]], i64 3
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%xv = insertelement <4 x float> %y, float %x, i32 0 %xv = insertelement <4 x float> %y, float %x, i32 0
%splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef> %splat = shufflevector <4 x float> %xv, <4 x float> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
%r = insertelement <4 x float> %splat, float %x, i32 3 %r = insertelement <4 x float> %splat, float %x, i32 3
ret <4 x float> %r ret <4 x float> %r
} }
define <4 x i8> @shuf_identity_padding(<2 x i8> %x, i8 %y) { define <4 x i8> @shuf_identity_padding(<2 x i8> %x, i8 %y) {
; CHECK-LABEL: @shuf_identity_padding( ; CHECK-LABEL: @shuf_identity_padding(
; CHECK-NEXT: [[V1:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[V1:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i64 2 ; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i64 2
; CHECK-NEXT: ret <4 x i8> [[V2]] ; CHECK-NEXT: ret <4 x i8> [[V2]]
; ;
%v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%x1 = extractelement <2 x i8> %x, i32 1 %x1 = extractelement <2 x i8> %x, i32 1
%v1 = insertelement <4 x i8> %v0, i8 %x1, i32 1 %v1 = insertelement <4 x i8> %v0, i8 %x1, i32 1
%v2 = insertelement <4 x i8> %v1, i8 %y, i32 2 %v2 = insertelement <4 x i8> %v1, i8 %y, i32 2
ret <4 x i8> %v2 ret <4 x i8> %v2
} }
define <3 x i8> @shuf_identity_extract(<4 x i8> %x, i8 %y) { define <3 x i8> @shuf_identity_extract(<4 x i8> %x, i8 %y) {
; CHECK-LABEL: @shuf_identity_extract( ; CHECK-LABEL: @shuf_identity_extract(
; CHECK-NEXT: [[V1:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 poison> ; CHECK-NEXT: [[V1:%.*]] = shufflevector <4 x i8> [[X:%.*]], <4 x i8> poison, <3 x i32> <i32 0, i32 1, i32 poison>
; CHECK-NEXT: [[V2:%.*]] = insertelement <3 x i8> [[V1]], i8 [[Y:%.*]], i64 2 ; CHECK-NEXT: [[V2:%.*]] = insertelement <3 x i8> [[V1]], i8 [[Y:%.*]], i64 2
; CHECK-NEXT: ret <3 x i8> [[V2]] ; CHECK-NEXT: ret <3 x i8> [[V2]]
; ;
%v0 = shufflevector <4 x i8> %x, <4 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 undef> %v0 = shufflevector <4 x i8> %x, <4 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 undef>
%x1 = extractelement <4 x i8> %x, i32 1 %x1 = extractelement <4 x i8> %x, i32 1
%v1 = insertelement <3 x i8> %v0, i8 %x1, i32 1 %v1 = insertelement <3 x i8> %v0, i8 %x1, i32 1
%v2 = insertelement <3 x i8> %v1, i8 %y, i32 2 %v2 = insertelement <3 x i8> %v1, i8 %y, i32 2
ret <3 x i8> %v2 ret <3 x i8> %v2
} }
define <4 x float> @shuf_identity_extract_extra_use(<6 x float> %x, float %y) { define <4 x float> @shuf_identity_extract_extra_use(<6 x float> %x, float %y) {
; CHECK-LABEL: @shuf_identity_extract_extra_use( ; CHECK-LABEL: @shuf_identity_extract_extra_use(
; CHECK-NEXT: [[V0:%.*]] = shufflevector <6 x float> [[X:%.*]], <6 x float> undef, <4 x i32> <i32 0, i32 poison, i32 poison, i32 3> ; CHECK-NEXT: [[V0:%.*]] = shufflevector <6 x float> [[X:%.*]], <6 x float> poison, <4 x i32> <i32 0, i32 poison, i32 poison, i32 3>
; CHECK-NEXT: call void @use(<4 x float> [[V0]]) ; CHECK-NEXT: call void @use(<4 x float> [[V0]])
; CHECK-NEXT: [[V1:%.*]] = shufflevector <6 x float> [[X]], <6 x float> undef, <4 x i32> <i32 0, i32 poison, i32 2, i32 3> ; CHECK-NEXT: [[V1:%.*]] = shufflevector <6 x float> [[X]], <6 x float> poison, <4 x i32> <i32 0, i32 poison, i32 2, i32 3>
; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[Y:%.*]], i64 1 ; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[Y:%.*]], i64 1
; CHECK-NEXT: ret <4 x float> [[V2]] ; CHECK-NEXT: ret <4 x float> [[V2]]
; ;
%v0 = shufflevector <6 x float> %x, <6 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 3> %v0 = shufflevector <6 x float> %x, <6 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 3>
call void @use(<4 x float> %v0) call void @use(<4 x float> %v0)
%x1 = extractelement <6 x float> %x, i32 2 %x1 = extractelement <6 x float> %x, i32 2
%v1 = insertelement <4 x float> %v0, float %x1, i32 2 %v1 = insertelement <4 x float> %v0, float %x1, i32 2
%v2 = insertelement <4 x float> %v1, float %y, i32 1 %v2 = insertelement <4 x float> %v1, float %y, i32 1
ret <4 x float> %v2 ret <4 x float> %v2
} }
; Negative test - can't map variable index to shuffle mask. ; Negative test - can't map variable index to shuffle mask.
define <4 x i8> @shuf_identity_padding_variable_index(<2 x i8> %x, i8 %y, i32 %index) { define <4 x i8> @shuf_identity_padding_variable_index(<2 x i8> %x, i8 %y, i32 %index) {
; CHECK-LABEL: @shuf_identity_padding_variable_index( ; CHECK-LABEL: @shuf_identity_padding_variable_index(
; CHECK-NEXT: [[V0:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[V0:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x i8> [[X]], i32 [[INDEX:%.*]] ; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x i8> [[X]], i32 [[INDEX:%.*]]
; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x i8> [[V0]], i8 [[X1]], i32 [[INDEX]] ; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x i8> [[V0]], i8 [[X1]], i32 [[INDEX]]
; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i64 2 ; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i64 2
; CHECK-NEXT: ret <4 x i8> [[V2]] ; CHECK-NEXT: ret <4 x i8> [[V2]]
; ;
%v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%x1 = extractelement <2 x i8> %x, i32 %index %x1 = extractelement <2 x i8> %x, i32 %index
%v1 = insertelement <4 x i8> %v0, i8 %x1, i32 %index %v1 = insertelement <4 x i8> %v0, i8 %x1, i32 %index
%v2 = insertelement <4 x i8> %v1, i8 %y, i32 2 %v2 = insertelement <4 x i8> %v1, i8 %y, i32 2
ret <4 x i8> %v2 ret <4 x i8> %v2
} }
; Negative test - don't create arbitrary shuffle masks. ; Negative test - don't create arbitrary shuffle masks.
define <4 x i8> @shuf_identity_padding_wrong_source_vec(<2 x i8> %x, i8 %y, <2 x i8> %other) { define <4 x i8> @shuf_identity_padding_wrong_source_vec(<2 x i8> %x, i8 %y, <2 x i8> %other) {
; CHECK-LABEL: @shuf_identity_padding_wrong_source_vec( ; CHECK-LABEL: @shuf_identity_padding_wrong_source_vec(
; CHECK-NEXT: [[V0:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[V0:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> poison, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x i8> [[OTHER:%.*]], i64 1 ; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x i8> [[OTHER:%.*]], i64 1
; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x i8> [[V0]], i8 [[X1]], i64 1 ; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x i8> [[V0]], i8 [[X1]], i64 1
; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i64 2 ; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i64 2
; CHECK-NEXT: ret <4 x i8> [[V2]] ; CHECK-NEXT: ret <4 x i8> [[V2]]
; ;
%v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%x1 = extractelement <2 x i8> %other, i32 1 %x1 = extractelement <2 x i8> %other, i32 1
%v1 = insertelement <4 x i8> %v0, i8 %x1, i32 1 %v1 = insertelement <4 x i8> %v0, i8 %x1, i32 1
%v2 = insertelement <4 x i8> %v1, i8 %y, i32 2 %v2 = insertelement <4 x i8> %v1, i8 %y, i32 2
ret <4 x i8> %v2 ret <4 x i8> %v2
} }
; Negative test - don't create arbitrary shuffle masks. ; Negative test - don't create arbitrary shuffle masks.
define <4 x i8> @shuf_identity_padding_wrong_index(<2 x i8> %x, i8 %y) { define <4 x i8> @shuf_identity_padding_wrong_index(<2 x i8> %x, i8 %y) {
; CHECK-LABEL: @shuf_identity_padding_wrong_index( ; CHECK-LABEL: @shuf_identity_padding_wrong_index(
; CHECK-NEXT: [[V0:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[V0:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x i8> [[X]], i64 1 ; CHECK-NEXT: [[X1:%.*]] = extractelement <2 x i8> [[X]], i64 1
; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x i8> [[V0]], i8 [[X1]], i64 2 ; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x i8> [[V0]], i8 [[X1]], i64 2
; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i64 3 ; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x i8> [[V1]], i8 [[Y:%.*]], i64 3
; CHECK-NEXT: ret <4 x i8> [[V2]] ; CHECK-NEXT: ret <4 x i8> [[V2]]
; ;
%v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %v0 = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%x1 = extractelement <2 x i8> %x, i32 1 %x1 = extractelement <2 x i8> %x, i32 1
%v1 = insertelement <4 x i8> %v0, i8 %x1, i32 2 %v1 = insertelement <4 x i8> %v0, i8 %x1, i32 2
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llvm/test/Transforms/InstCombine/logical-select.ll

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%or = or <2 x i64> %and2, %and1 %or = or <2 x i64> %and2, %and1
ret <2 x i64> %or ret <2 x i64> %or
} }
define <4 x i32> @computesignbits_through_shuffles(<4 x float> %x, <4 x float> %y, <4 x float> %z) { define <4 x i32> @computesignbits_through_shuffles(<4 x float> %x, <4 x float> %y, <4 x float> %z) {
; CHECK-LABEL: @computesignbits_through_shuffles( ; CHECK-LABEL: @computesignbits_through_shuffles(
; CHECK-NEXT: [[CMP:%.*]] = fcmp ole <4 x float> [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = fcmp ole <4 x float> [[X:%.*]], [[Y:%.*]]
; CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32> ; CHECK-NEXT: [[SEXT:%.*]] = sext <4 x i1> [[CMP]] to <4 x i32>
; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x i32> [[SEXT]], <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x i32> [[SEXT]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
; CHECK-NEXT: [[S2:%.*]] = shufflevector <4 x i32> [[SEXT]], <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3> ; CHECK-NEXT: [[S2:%.*]] = shufflevector <4 x i32> [[SEXT]], <4 x i32> poison, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
; CHECK-NEXT: [[SHUF_OR1:%.*]] = or <4 x i32> [[S1]], [[S2]] ; CHECK-NEXT: [[SHUF_OR1:%.*]] = or <4 x i32> [[S1]], [[S2]]
; CHECK-NEXT: [[S3:%.*]] = shufflevector <4 x i32> [[SHUF_OR1]], <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1> ; CHECK-NEXT: [[S3:%.*]] = shufflevector <4 x i32> [[SHUF_OR1]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
; CHECK-NEXT: [[S4:%.*]] = shufflevector <4 x i32> [[SHUF_OR1]], <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3> ; CHECK-NEXT: [[S4:%.*]] = shufflevector <4 x i32> [[SHUF_OR1]], <4 x i32> poison, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
; CHECK-NEXT: [[SHUF_OR2:%.*]] = or <4 x i32> [[S3]], [[S4]] ; CHECK-NEXT: [[SHUF_OR2:%.*]] = or <4 x i32> [[S3]], [[S4]]
; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[SHUF_OR2]] to <4 x i1> ; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i32> [[SHUF_OR2]] to <4 x i1>
; CHECK-NEXT: [[SEL_V:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[Z:%.*]], <4 x float> [[X]] ; CHECK-NEXT: [[SEL_V:%.*]] = select <4 x i1> [[TMP1]], <4 x float> [[Z:%.*]], <4 x float> [[X]]
; CHECK-NEXT: [[SEL:%.*]] = bitcast <4 x float> [[SEL_V]] to <4 x i32> ; CHECK-NEXT: [[SEL:%.*]] = bitcast <4 x float> [[SEL_V]] to <4 x i32>
; CHECK-NEXT: ret <4 x i32> [[SEL]] ; CHECK-NEXT: ret <4 x i32> [[SEL]]
; ;
%cmp = fcmp ole <4 x float> %x, %y %cmp = fcmp ole <4 x float> %x, %y
%sext = sext <4 x i1> %cmp to <4 x i32> %sext = sext <4 x i1> %cmp to <4 x i32>
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llvm/test/Transforms/InstCombine/masked_intrinsics-inseltpoison.ll

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%ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1 %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
%res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 2, <2 x i1> <i1 true, i1 false>, <2 x double> %ptv2) %res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 2, <2 x i1> <i1 true, i1 false>, <2 x double> %ptv2)
ret <2 x double> %res ret <2 x double> %res
} }
define double @load_all(ptr %base, double %pt) { define double @load_all(ptr %base, double %pt) {
; CHECK-LABEL: @load_all( ; CHECK-LABEL: @load_all(
; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[BASE:%.*]], <4 x i64> <i64 0, i64 poison, i64 2, i64 3> ; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[BASE:%.*]], <4 x i64> <i64 0, i64 poison, i64 2, i64 3>
; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> [[PTRS]], i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x double> undef) ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> [[PTRS]], i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x double> poison)
; CHECK-NEXT: [[ELT:%.*]] = extractelement <4 x double> [[RES]], i64 2 ; CHECK-NEXT: [[ELT:%.*]] = extractelement <4 x double> [[RES]], i64 2
; CHECK-NEXT: ret double [[ELT]] ; CHECK-NEXT: ret double [[ELT]]
; ;
%ptrs = getelementptr double, ptr %base, <4 x i64> <i64 0, i64 1, i64 2, i64 3> %ptrs = getelementptr double, ptr %base, <4 x i64> <i64 0, i64 1, i64 2, i64 3>
%res = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x double> undef) %res = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x double> undef)
%elt = extractelement <4 x double> %res, i64 2 %elt = extractelement <4 x double> %res, i64 2
ret double %elt ret double %elt
} }
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llvm/test/Transforms/InstCombine/masked_intrinsics.ll

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%ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1 %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
%res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 2, <2 x i1> <i1 true, i1 false>, <2 x double> %ptv2) %res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 2, <2 x i1> <i1 true, i1 false>, <2 x double> %ptv2)
ret <2 x double> %res ret <2 x double> %res
} }
define double @load_all(ptr %base, double %pt) { define double @load_all(ptr %base, double %pt) {
; CHECK-LABEL: @load_all( ; CHECK-LABEL: @load_all(
; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[BASE:%.*]], <4 x i64> <i64 0, i64 poison, i64 2, i64 3> ; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[BASE:%.*]], <4 x i64> <i64 0, i64 poison, i64 2, i64 3>
; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> [[PTRS]], i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x double> undef) ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> [[PTRS]], i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x double> poison)
; CHECK-NEXT: [[ELT:%.*]] = extractelement <4 x double> [[RES]], i64 2 ; CHECK-NEXT: [[ELT:%.*]] = extractelement <4 x double> [[RES]], i64 2
; CHECK-NEXT: ret double [[ELT]] ; CHECK-NEXT: ret double [[ELT]]
; ;
%ptrs = getelementptr double, ptr %base, <4 x i64> <i64 0, i64 1, i64 2, i64 3> %ptrs = getelementptr double, ptr %base, <4 x i64> <i64 0, i64 1, i64 2, i64 3>
%res = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x double> undef) %res = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x double> undef)
%elt = extractelement <4 x double> %res, i64 2 %elt = extractelement <4 x double> %res, i64 2
ret double %elt ret double %elt
} }
define <2 x double> @load_generic(ptr %ptr, double %pt, <2 x i1> %mask) { define <2 x double> @load_generic(ptr %ptr, double %pt, <2 x i1> %mask) {
; CHECK-LABEL: @load_generic( ; CHECK-LABEL: @load_generic(
; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> undef, double [[PT:%.*]], i64 0 ; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0(ptr [[PTR:%.*]], i32 4, <2 x i1> [[MASK:%.*]], <2 x double> [[PTV2]]) ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0(ptr [[PTR:%.*]], i32 4, <2 x i1> [[MASK:%.*]], <2 x double> [[PTV2]])
; CHECK-NEXT: ret <2 x double> [[RES]] ; CHECK-NEXT: ret <2 x double> [[RES]]
; ;
%ptv1 = insertelement <2 x double> undef, double %pt, i64 0 %ptv1 = insertelement <2 x double> undef, double %pt, i64 0
%ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1 %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
%res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2) %res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2)
ret <2 x double> %res ret <2 x double> %res
} }
define <2 x double> @load_speculative(ptr dereferenceable(16) align 4 %ptr, double %pt, <2 x i1> %mask) nofree nosync { define <2 x double> @load_speculative(ptr dereferenceable(16) align 4 %ptr, double %pt, <2 x i1> %mask) nofree nosync {
; CHECK-LABEL: @load_speculative( ; CHECK-LABEL: @load_speculative(
; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> undef, double [[PT:%.*]], i64 0 ; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[UNMASKEDLOAD:%.*]] = load <2 x double>, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: [[UNMASKEDLOAD:%.*]] = load <2 x double>, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]] ; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
; CHECK-NEXT: ret <2 x double> [[RES]] ; CHECK-NEXT: ret <2 x double> [[RES]]
; ;
%ptv1 = insertelement <2 x double> undef, double %pt, i64 0 %ptv1 = insertelement <2 x double> undef, double %pt, i64 0
%ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1 %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
%res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2) %res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2)
ret <2 x double> %res ret <2 x double> %res
} }
define <2 x double> @load_speculative_less_aligned(ptr dereferenceable(16) %ptr, double %pt, <2 x i1> %mask) nofree nosync { define <2 x double> @load_speculative_less_aligned(ptr dereferenceable(16) %ptr, double %pt, <2 x i1> %mask) nofree nosync {
; CHECK-LABEL: @load_speculative_less_aligned( ; CHECK-LABEL: @load_speculative_less_aligned(
; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> undef, double [[PT:%.*]], i64 0 ; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[UNMASKEDLOAD:%.*]] = load <2 x double>, ptr [[PTR:%.*]], align 4 ; CHECK-NEXT: [[UNMASKEDLOAD:%.*]] = load <2 x double>, ptr [[PTR:%.*]], align 4
; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]] ; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[MASK:%.*]], <2 x double> [[UNMASKEDLOAD]], <2 x double> [[PTV2]]
; CHECK-NEXT: ret <2 x double> [[RES]] ; CHECK-NEXT: ret <2 x double> [[RES]]
; ;
%ptv1 = insertelement <2 x double> undef, double %pt, i64 0 %ptv1 = insertelement <2 x double> undef, double %pt, i64 0
%ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1 %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
%res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2) %res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2)
ret <2 x double> %res ret <2 x double> %res
} }
; Can't speculate since only half of required size is known deref ; Can't speculate since only half of required size is known deref
define <2 x double> @load_spec_neg_size(ptr dereferenceable(8) %ptr, double %pt, <2 x i1> %mask) nofree nosync { define <2 x double> @load_spec_neg_size(ptr dereferenceable(8) %ptr, double %pt, <2 x i1> %mask) nofree nosync {
; CHECK-LABEL: @load_spec_neg_size( ; CHECK-LABEL: @load_spec_neg_size(
; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> undef, double [[PT:%.*]], i64 0 ; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0(ptr nonnull [[PTR:%.*]], i32 4, <2 x i1> [[MASK:%.*]], <2 x double> [[PTV2]]) ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0(ptr nonnull [[PTR:%.*]], i32 4, <2 x i1> [[MASK:%.*]], <2 x double> [[PTV2]])
; CHECK-NEXT: ret <2 x double> [[RES]] ; CHECK-NEXT: ret <2 x double> [[RES]]
; ;
%ptv1 = insertelement <2 x double> undef, double %pt, i64 0 %ptv1 = insertelement <2 x double> undef, double %pt, i64 0
%ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1 %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
%res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2) %res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %ptr, i32 4, <2 x i1> %mask, <2 x double> %ptv2)
ret <2 x double> %res ret <2 x double> %res
} }
; Can only speculate one lane (but it's the only one active) ; Can only speculate one lane (but it's the only one active)
define <2 x double> @load_spec_lan0(ptr dereferenceable(8) %ptr, double %pt, <2 x i1> %mask) nofree nosync { define <2 x double> @load_spec_lan0(ptr dereferenceable(8) %ptr, double %pt, <2 x i1> %mask) nofree nosync {
; CHECK-LABEL: @load_spec_lan0( ; CHECK-LABEL: @load_spec_lan0(
; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> undef, double [[PT:%.*]], i64 0 ; CHECK-NEXT: [[PTV1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[PTV2:%.*]] = shufflevector <2 x double> [[PTV1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[MASK2:%.*]] = insertelement <2 x i1> [[MASK:%.*]], i1 false, i64 1 ; CHECK-NEXT: [[MASK2:%.*]] = insertelement <2 x i1> [[MASK:%.*]], i1 false, i64 1
; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0(ptr nonnull [[PTR:%.*]], i32 4, <2 x i1> [[MASK2]], <2 x double> [[PTV2]]) ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.masked.load.v2f64.p0(ptr nonnull [[PTR:%.*]], i32 4, <2 x i1> [[MASK2]], <2 x double> [[PTV2]])
; CHECK-NEXT: ret <2 x double> [[RES]] ; CHECK-NEXT: ret <2 x double> [[RES]]
; ;
%ptv1 = insertelement <2 x double> undef, double %pt, i64 0 %ptv1 = insertelement <2 x double> undef, double %pt, i64 0
%ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1 %ptv2 = insertelement <2 x double> %ptv1, double %pt, i64 1
%mask2 = insertelement <2 x i1> %mask, i1 false, i64 1 %mask2 = insertelement <2 x i1> %mask, i1 false, i64 1
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; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
call void @llvm.masked.store.v2f64.p0(<2 x double> %val, ptr %ptr, i32 4, <2 x i1> <i1 1, i1 1>) call void @llvm.masked.store.v2f64.p0(<2 x double> %val, ptr %ptr, i32 4, <2 x i1> <i1 1, i1 1>)
ret void ret void
} }
define void @store_demandedelts(ptr %ptr, double %val) { define void @store_demandedelts(ptr %ptr, double %val) {
; CHECK-LABEL: @store_demandedelts( ; CHECK-LABEL: @store_demandedelts(
; CHECK-NEXT: [[VALVEC1:%.*]] = insertelement <2 x double> undef, double [[VAL:%.*]], i64 0 ; CHECK-NEXT: [[VALVEC1:%.*]] = insertelement <2 x double> poison, double [[VAL:%.*]], i64 0
; CHECK-NEXT: call void @llvm.masked.store.v2f64.p0(<2 x double> [[VALVEC1]], ptr [[PTR:%.*]], i32 4, <2 x i1> <i1 true, i1 false>) ; CHECK-NEXT: call void @llvm.masked.store.v2f64.p0(<2 x double> [[VALVEC1]], ptr [[PTR:%.*]], i32 4, <2 x i1> <i1 true, i1 false>)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%valvec1 = insertelement <2 x double> undef, double %val, i32 0 %valvec1 = insertelement <2 x double> undef, double %val, i32 0
%valvec2 = insertelement <2 x double> %valvec1, double %val, i32 1 %valvec2 = insertelement <2 x double> %valvec1, double %val, i32 1
call void @llvm.masked.store.v2f64.p0(<2 x double> %valvec2, ptr %ptr, i32 4, <2 x i1> <i1 true, i1 false>) call void @llvm.masked.store.v2f64.p0(<2 x double> %valvec2, ptr %ptr, i32 4, <2 x i1> <i1 true, i1 false>)
ret void ret void
} }
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; ;
%res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> <i1 true, i1 true>, <2 x double> %passthru) %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> <i1 true, i1 true>, <2 x double> %passthru)
ret <2 x double> %res ret <2 x double> %res
} }
define <4 x double> @gather_lane2(ptr %base, double %pt) { define <4 x double> @gather_lane2(ptr %base, double %pt) {
; CHECK-LABEL: @gather_lane2( ; CHECK-LABEL: @gather_lane2(
; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[BASE:%.*]], <4 x i64> <i64 poison, i64 poison, i64 2, i64 poison> ; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[BASE:%.*]], <4 x i64> <i64 poison, i64 poison, i64 2, i64 poison>
; CHECK-NEXT: [[PT_V1:%.*]] = insertelement <4 x double> undef, double [[PT:%.*]], i64 0 ; CHECK-NEXT: [[PT_V1:%.*]] = insertelement <4 x double> poison, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PT_V2:%.*]] = shufflevector <4 x double> [[PT_V1]], <4 x double> undef, <4 x i32> <i32 0, i32 0, i32 poison, i32 0> ; CHECK-NEXT: [[PT_V2:%.*]] = shufflevector <4 x double> [[PT_V1]], <4 x double> poison, <4 x i32> <i32 0, i32 0, i32 poison, i32 0>
; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> [[PTRS]], i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> [[PT_V2]]) ; CHECK-NEXT: [[RES:%.*]] = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> [[PTRS]], i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> [[PT_V2]])
; CHECK-NEXT: ret <4 x double> [[RES]] ; CHECK-NEXT: ret <4 x double> [[RES]]
; ;
%ptrs = getelementptr double, ptr %base, <4 x i64> <i64 0, i64 1, i64 2, i64 3> %ptrs = getelementptr double, ptr %base, <4 x i64> <i64 0, i64 1, i64 2, i64 3>
%pt_v1 = insertelement <4 x double> undef, double %pt, i64 0 %pt_v1 = insertelement <4 x double> undef, double %pt, i64 0
%pt_v2 = shufflevector <4 x double> %pt_v1, <4 x double> undef, <4 x i32> zeroinitializer %pt_v2 = shufflevector <4 x double> %pt_v1, <4 x double> undef, <4 x i32> zeroinitializer
%res = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> %pt_v2) %res = call <4 x double> @llvm.masked.gather.v4f64.v4p0(<4 x ptr> %ptrs, i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> %pt_v2)
ret <4 x double> %res ret <4 x double> %res
} }
define <2 x double> @gather_lane0_maybe(ptr %base, double %pt, <2 x i1> %mask) { define <2 x double> @gather_lane0_maybe(ptr %base, double %pt, <2 x i1> %mask) {
; CHECK-LABEL: @gather_lane0_maybe( ; CHECK-LABEL: @gather_lane0_maybe(
; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[BASE:%.*]], <2 x i64> <i64 0, i64 1> ; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[BASE:%.*]], <2 x i64> <i64 0, i64 1>
; CHECK-NEXT: [[PT_V1:%.*]] = insertelement <2 x double> undef, double [[PT:%.*]], i64 0 ; CHECK-NEXT: [[PT_V1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PT_V2:%.*]] = shufflevector <2 x double> [[PT_V1]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[PT_V2:%.*]] = shufflevector <2 x double> [[PT_V1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[MASK2:%.*]] = insertelement <2 x i1> [[MASK:%.*]], i1 false, i64 1 ; CHECK-NEXT: [[MASK2:%.*]] = insertelement <2 x i1> [[MASK:%.*]], i1 false, i64 1
; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> [[PTRS]], i32 4, <2 x i1> [[MASK2]], <2 x double> [[PT_V2]]) ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> [[PTRS]], i32 4, <2 x i1> [[MASK2]], <2 x double> [[PT_V2]])
; CHECK-NEXT: ret <2 x double> [[RES]] ; CHECK-NEXT: ret <2 x double> [[RES]]
; ;
%ptrs = getelementptr double, ptr %base, <2 x i64> <i64 0, i64 1> %ptrs = getelementptr double, ptr %base, <2 x i64> <i64 0, i64 1>
%pt_v1 = insertelement <2 x double> undef, double %pt, i64 0 %pt_v1 = insertelement <2 x double> undef, double %pt, i64 0
%pt_v2 = insertelement <2 x double> %pt_v1, double %pt, i64 1 %pt_v2 = insertelement <2 x double> %pt_v1, double %pt, i64 1
%mask2 = insertelement <2 x i1> %mask, i1 false, i64 1 %mask2 = insertelement <2 x i1> %mask, i1 false, i64 1
%res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask2, <2 x double> %pt_v2) %res = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> %ptrs, i32 4, <2 x i1> %mask2, <2 x double> %pt_v2)
ret <2 x double> %res ret <2 x double> %res
} }
define <2 x double> @gather_lane0_maybe_spec(ptr %base, double %pt, <2 x i1> %mask) { define <2 x double> @gather_lane0_maybe_spec(ptr %base, double %pt, <2 x i1> %mask) {
; CHECK-LABEL: @gather_lane0_maybe_spec( ; CHECK-LABEL: @gather_lane0_maybe_spec(
; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[BASE:%.*]], <2 x i64> <i64 0, i64 1> ; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[BASE:%.*]], <2 x i64> <i64 0, i64 1>
; CHECK-NEXT: [[PT_V1:%.*]] = insertelement <2 x double> undef, double [[PT:%.*]], i64 0 ; CHECK-NEXT: [[PT_V1:%.*]] = insertelement <2 x double> poison, double [[PT:%.*]], i64 0
; CHECK-NEXT: [[PT_V2:%.*]] = shufflevector <2 x double> [[PT_V1]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[PT_V2:%.*]] = shufflevector <2 x double> [[PT_V1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[MASK2:%.*]] = insertelement <2 x i1> [[MASK:%.*]], i1 false, i64 1 ; CHECK-NEXT: [[MASK2:%.*]] = insertelement <2 x i1> [[MASK:%.*]], i1 false, i64 1
; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> [[PTRS]], i32 4, <2 x i1> [[MASK2]], <2 x double> [[PT_V2]]) ; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.masked.gather.v2f64.v2p0(<2 x ptr> [[PTRS]], i32 4, <2 x i1> [[MASK2]], <2 x double> [[PT_V2]])
; CHECK-NEXT: ret <2 x double> [[RES]] ; CHECK-NEXT: ret <2 x double> [[RES]]
; ;
%ptrs = getelementptr double, ptr %base, <2 x i64> <i64 0, i64 1> %ptrs = getelementptr double, ptr %base, <2 x i64> <i64 0, i64 1>
%pt_v1 = insertelement <2 x double> undef, double %pt, i64 0 %pt_v1 = insertelement <2 x double> undef, double %pt, i64 0
%pt_v2 = insertelement <2 x double> %pt_v1, double %pt, i64 1 %pt_v2 = insertelement <2 x double> %pt_v1, double %pt, i64 1
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; ;
call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> %val, <2 x ptr> %ptrs, i32 8, <2 x i1> zeroinitializer) call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> %val, <2 x ptr> %ptrs, i32 8, <2 x i1> zeroinitializer)
ret void ret void
} }
define void @scatter_demandedelts(ptr %ptr, double %val) { define void @scatter_demandedelts(ptr %ptr, double %val) {
; CHECK-LABEL: @scatter_demandedelts( ; CHECK-LABEL: @scatter_demandedelts(
; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[PTR:%.*]], <2 x i64> <i64 0, i64 poison> ; CHECK-NEXT: [[PTRS:%.*]] = getelementptr double, ptr [[PTR:%.*]], <2 x i64> <i64 0, i64 poison>
; CHECK-NEXT: [[VALVEC1:%.*]] = insertelement <2 x double> undef, double [[VAL:%.*]], i64 0 ; CHECK-NEXT: [[VALVEC1:%.*]] = insertelement <2 x double> poison, double [[VAL:%.*]], i64 0
; CHECK-NEXT: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> [[VALVEC1]], <2 x ptr> [[PTRS]], i32 8, <2 x i1> <i1 true, i1 false>) ; CHECK-NEXT: call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> [[VALVEC1]], <2 x ptr> [[PTRS]], i32 8, <2 x i1> <i1 true, i1 false>)
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
%ptrs = getelementptr double, ptr %ptr, <2 x i64> <i64 0, i64 1> %ptrs = getelementptr double, ptr %ptr, <2 x i64> <i64 0, i64 1>
%valvec1 = insertelement <2 x double> undef, double %val, i32 0 %valvec1 = insertelement <2 x double> undef, double %val, i32 0
%valvec2 = insertelement <2 x double> %valvec1, double %val, i32 1 %valvec2 = insertelement <2 x double> %valvec1, double %val, i32 1
call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> %valvec2, <2 x ptr> %ptrs, i32 8, <2 x i1> <i1 true, i1 false>) call void @llvm.masked.scatter.v2f64.v2p0(<2 x double> %valvec2, <2 x ptr> %ptrs, i32 8, <2 x i1> <i1 true, i1 false>)
ret void ret void
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} }
; Negative gather tests ; Negative gather tests
;; Vector of pointers is not a splat. ;; Vector of pointers is not a splat.
define <2 x i64> @negative_gather_v2i64_non_uniform_ptrs_all_active_mask(<2 x ptr> %inVal, ptr %src ) { define <2 x i64> @negative_gather_v2i64_non_uniform_ptrs_all_active_mask(<2 x ptr> %inVal, ptr %src ) {
; CHECK-LABEL: @negative_gather_v2i64_non_uniform_ptrs_all_active_mask( ; CHECK-LABEL: @negative_gather_v2i64_non_uniform_ptrs_all_active_mask(
; CHECK-NEXT: [[INSERT_VALUE:%.*]] = insertelement <2 x ptr> [[INVAL:%.*]], ptr [[SRC:%.*]], i64 1 ; CHECK-NEXT: [[INSERT_VALUE:%.*]] = insertelement <2 x ptr> [[INVAL:%.*]], ptr [[SRC:%.*]], i64 1
; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> [[INSERT_VALUE]], i32 8, <2 x i1> <i1 true, i1 true>, <2 x i64> undef) ; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.masked.gather.v2i64.v2p0(<2 x ptr> [[INSERT_VALUE]], i32 8, <2 x i1> <i1 true, i1 true>, <2 x i64> poison)
; CHECK-NEXT: ret <2 x i64> [[RES]] ; CHECK-NEXT: ret <2 x i64> [[RES]]
; ;
%insert.value = insertelement <2 x ptr> %inVal, ptr %src, i32 1 %insert.value = insertelement <2 x ptr> %inVal, ptr %src, i32 1
%res = call <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr> %insert.value, i32 8, <2 x i1><i1 1, i1 1>, <2 x i64> undef) %res = call <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr> %insert.value, i32 8, <2 x i1><i1 1, i1 1>, <2 x i64> undef)
ret <2 x i64> %res ret <2 x i64> %res
} }
;; Unknown mask value ;; Unknown mask value
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llvm/test/Transforms/InstCombine/matrix-multiplication-negation.ll

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store <3 x double> %b.neg, ptr %b_loc store <3 x double> %b.neg, ptr %b_loc
ret <9 x double> %res ret <9 x double> %res
} }
define <12 x double> @fneg_with_multiple_uses(<15 x double> %a, <20 x double> %b){ define <12 x double> @fneg_with_multiple_uses(<15 x double> %a, <20 x double> %b){
; CHECK-LABEL: @fneg_with_multiple_uses( ; CHECK-LABEL: @fneg_with_multiple_uses(
; CHECK-NEXT: [[A_NEG:%.*]] = fneg <15 x double> [[A:%.*]] ; CHECK-NEXT: [[A_NEG:%.*]] = fneg <15 x double> [[A:%.*]]
; CHECK-NEXT: [[RES:%.*]] = tail call <12 x double> @llvm.matrix.multiply.v12f64.v15f64.v20f64(<15 x double> [[A_NEG]], <20 x double> [[B:%.*]], i32 3, i32 5, i32 4) ; CHECK-NEXT: [[RES:%.*]] = tail call <12 x double> @llvm.matrix.multiply.v12f64.v15f64.v20f64(<15 x double> [[A_NEG]], <20 x double> [[B:%.*]], i32 3, i32 5, i32 4)
; CHECK-NEXT: [[RES_2:%.*]] = shufflevector <15 x double> [[A_NEG]], <15 x double> undef, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> ; CHECK-NEXT: [[RES_2:%.*]] = shufflevector <15 x double> [[A_NEG]], <15 x double> poison, <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
; CHECK-NEXT: [[RES_3:%.*]] = fadd <12 x double> [[RES_2]], [[RES]] ; CHECK-NEXT: [[RES_3:%.*]] = fadd <12 x double> [[RES_2]], [[RES]]
; CHECK-NEXT: ret <12 x double> [[RES_3]] ; CHECK-NEXT: ret <12 x double> [[RES_3]]
; ;
%a.neg = fneg <15 x double> %a %a.neg = fneg <15 x double> %a
%res = tail call <12 x double> @llvm.matrix.multiply.v12f64.v15f64.v20f64(<15 x double> %a.neg, <20 x double> %b, i32 3, i32 5, i32 4) %res = tail call <12 x double> @llvm.matrix.multiply.v12f64.v15f64.v20f64(<15 x double> %a.neg, <20 x double> %b, i32 3, i32 5, i32 4)
%res.2 = shufflevector <15 x double> %a.neg, <15 x double> undef, %res.2 = shufflevector <15 x double> %a.neg, <15 x double> undef,
<12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> <12 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
%res.3 = fadd <12 x double> %res.2, %res %res.3 = fadd <12 x double> %res.2, %res
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llvm/test/Transforms/InstCombine/nsw.ll

Show First 20 Lines • Show All 96 Lines • ▼ Show 20 Lines;
%y = add nsw i8 %B, 10 %y = add nsw i8 %B, 10
%add = add nsw i8 %x, %y %add = add nsw i8 %x, %y
ret i8 %add ret i8 %add
} }
define <3 x i32> @shl_nuw_nsw_shuffle_splat_vec(<2 x i8> %x) { define <3 x i32> @shl_nuw_nsw_shuffle_splat_vec(<2 x i8> %x) {
; CHECK-LABEL: @shl_nuw_nsw_shuffle_splat_vec( ; CHECK-LABEL: @shl_nuw_nsw_shuffle_splat_vec(
; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32> ; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i32> [[T2]], <2 x i32> poison, <3 x i32> <i32 1, i32 0, i32 1>
; CHECK-NEXT: [[T3:%.*]] = shl nuw nsw <3 x i32> [[SHUF]], <i32 17, i32 17, i32 17> ; CHECK-NEXT: [[T3:%.*]] = shl nuw nsw <3 x i32> [[SHUF]], <i32 17, i32 17, i32 17>
; CHECK-NEXT: ret <3 x i32> [[T3]] ; CHECK-NEXT: ret <3 x i32> [[T3]]
; ;
%t2 = zext <2 x i8> %x to <2 x i32> %t2 = zext <2 x i8> %x to <2 x i32>
%shuf = shufflevector <2 x i32> %t2, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1> %shuf = shufflevector <2 x i32> %t2, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
%t3 = shl <3 x i32> %shuf, <i32 17, i32 17, i32 17> %t3 = shl <3 x i32> %shuf, <i32 17, i32 17, i32 17>
ret <3 x i32> %t3 ret <3 x i32> %t3
} }
; Negative test - if the shuffle mask contains an undef, we bail out to ; Negative test - if the shuffle mask contains an undef, we bail out to
; avoid propagating information that may not be used consistently by callers. ; avoid propagating information that may not be used consistently by callers.
define <3 x i32> @shl_nuw_nsw_shuffle_undef_elt_splat_vec(<2 x i8> %x) { define <3 x i32> @shl_nuw_nsw_shuffle_undef_elt_splat_vec(<2 x i8> %x) {
; CHECK-LABEL: @shl_nuw_nsw_shuffle_undef_elt_splat_vec( ; CHECK-LABEL: @shl_nuw_nsw_shuffle_undef_elt_splat_vec(
; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32> ; CHECK-NEXT: [[T2:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i32> [[T2]], <2 x i32> undef, <3 x i32> <i32 1, i32 poison, i32 0> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i32> [[T2]], <2 x i32> poison, <3 x i32> <i32 1, i32 poison, i32 0>
; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[SHUF]], <i32 17, i32 17, i32 17> ; CHECK-NEXT: [[T3:%.*]] = shl <3 x i32> [[SHUF]], <i32 17, i32 17, i32 17>
; CHECK-NEXT: ret <3 x i32> [[T3]] ; CHECK-NEXT: ret <3 x i32> [[T3]]
; ;
%t2 = zext <2 x i8> %x to <2 x i32> %t2 = zext <2 x i8> %x to <2 x i32>
%shuf = shufflevector <2 x i32> %t2, <2 x i32> undef, <3 x i32> <i32 1, i32 undef, i32 0> %shuf = shufflevector <2 x i32> %t2, <2 x i32> undef, <3 x i32> <i32 1, i32 undef, i32 0>
%t3 = shl <3 x i32> %shuf, <i32 17, i32 17, i32 17> %t3 = shl <3 x i32> %shuf, <i32 17, i32 17, i32 17>
ret <3 x i32> %t3 ret <3 x i32> %t3
} }
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llvm/test/Transforms/InstCombine/pr38984.ll

Show All 19 Linesentry:
ret <4 x i1> %4 ret <4 x i1> %4
} }
; The "compare base pointers" optimization should not kick in for vector icmp. ; The "compare base pointers" optimization should not kick in for vector icmp.
define <4 x i1> @PR38984_2() { define <4 x i1> @PR38984_2() {
; CHECK-LABEL: @PR38984_2( ; CHECK-LABEL: @PR38984_2(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @offsets, align 2 ; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @offsets, align 2
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> undef, i16 [[TMP0]], i64 3 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> <i16 undef, i16 undef, i16 undef, i16 poison>, i16 [[TMP0]], i64 3
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i16, ptr getelementptr inbounds ([21 x i16], ptr @a, i16 1, i16 0), <4 x i16> [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i16, ptr getelementptr inbounds ([21 x i16], ptr @a, i16 1, i16 0), <4 x i16> [[TMP1]]
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i16, ptr null, <4 x i16> [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i16, ptr null, <4 x i16> [[TMP1]]
; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x ptr> [[TMP2]], [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = icmp eq <4 x ptr> [[TMP2]], [[TMP3]]
; CHECK-NEXT: ret <4 x i1> [[TMP4]] ; CHECK-NEXT: ret <4 x i1> [[TMP4]]
; ;
entry: entry:
%0 = load i16, ptr @offsets %0 = load i16, ptr @offsets
%1 = insertelement <4 x i16> undef, i16 %0, i32 3 %1 = insertelement <4 x i16> undef, i16 %0, i32 3
%2 = getelementptr i16, ptr getelementptr ([21 x i16], ptr @a, i64 1, i32 0), <4 x i16> %1 %2 = getelementptr i16, ptr getelementptr ([21 x i16], ptr @a, i64 1, i32 0), <4 x i16> %1
%3 = getelementptr i16, ptr null, <4 x i16> %1 %3 = getelementptr i16, ptr null, <4 x i16> %1
%4 = icmp eq <4 x ptr> %2, %3 %4 = icmp eq <4 x ptr> %2, %3
ret <4 x i1> %4 ret <4 x i1> %4
} }

llvm/test/Transforms/InstCombine/select-binop-cmp.ll

Show First 20 Lines • Show All 565 Lines • ▼ Show 20 Lines;
%C = select <2 x i1> %A, <2 x i8> %B, <2 x i8> %y %C = select <2 x i1> %A, <2 x i8> %B, <2 x i8> %y
ret <2 x i8> %C ret <2 x i8> %C
} }
; Value equivalence substitution is all-or-nothing, so needs a scalar compare. ; Value equivalence substitution is all-or-nothing, so needs a scalar compare.
define <2 x i32> @vec_select_no_equivalence(<2 x i32> %x) { define <2 x i32> @vec_select_no_equivalence(<2 x i32> %x) {
; CHECK-LABEL: @vec_select_no_equivalence( ; CHECK-LABEL: @vec_select_no_equivalence(
; CHECK-NEXT: [[X10:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> undef, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[X10:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[COND:%.*]] = icmp eq <2 x i32> [[X]], zeroinitializer ; CHECK-NEXT: [[COND:%.*]] = icmp eq <2 x i32> [[X]], zeroinitializer
; CHECK-NEXT: [[S:%.*]] = select <2 x i1> [[COND]], <2 x i32> [[X10]], <2 x i32> [[X]] ; CHECK-NEXT: [[S:%.*]] = select <2 x i1> [[COND]], <2 x i32> [[X10]], <2 x i32> [[X]]
; CHECK-NEXT: ret <2 x i32> [[S]] ; CHECK-NEXT: ret <2 x i32> [[S]]
; ;
%x10 = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> <i32 1, i32 0> %x10 = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
%cond = icmp eq <2 x i32> %x, zeroinitializer %cond = icmp eq <2 x i32> %x, zeroinitializer
%s = select <2 x i1> %cond, <2 x i32> %x10, <2 x i32> %x %s = select <2 x i1> %cond, <2 x i32> %x10, <2 x i32> %x
ret <2 x i32> %s ret <2 x i32> %s
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llvm/test/Transforms/InstCombine/select-extractelement-inseltpoison.ll

Show All 15 Lines;
ret float %extract ret float %extract
} }
; Multiple extractelements ; Multiple extractelements
define <2 x float> @extract_two_select(<4 x float> %a, <4 x float> %b, i32 %c) #0 { define <2 x float> @extract_two_select(<4 x float> %a, <4 x float> %b, i32 %c) #0 {
; CHECK-LABEL: @extract_two_select( ; CHECK-LABEL: @extract_two_select(
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[C:%.*]], 0 ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[C:%.*]], 0
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]]
; CHECK-NEXT: [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> undef, <2 x i32> <i32 1, i32 2> ; CHECK-NEXT: [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> poison, <2 x i32> <i32 1, i32 2>
; CHECK-NEXT: ret <2 x float> [[BUILD2]] ; CHECK-NEXT: ret <2 x float> [[BUILD2]]
; ;
%cmp = icmp ne i32 %c, 0 %cmp = icmp ne i32 %c, 0
%sel = select i1 %cmp, <4 x float> %a, <4 x float> %b %sel = select i1 %cmp, <4 x float> %a, <4 x float> %b
%extract1 = extractelement <4 x float> %sel, i32 1 %extract1 = extractelement <4 x float> %sel, i32 1
%extract2 = extractelement <4 x float> %sel, i32 2 %extract2 = extractelement <4 x float> %sel, i32 2
%build1 = insertelement <2 x float> poison, float %extract1, i32 0 %build1 = insertelement <2 x float> poison, float %extract1, i32 0
%build2 = insertelement <2 x float> %build1, float %extract2, i32 1 %build2 = insertelement <2 x float> %build1, float %extract2, i32 1
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ret float %extract ret float %extract
} }
; Multiple extractelements from a vector select ; Multiple extractelements from a vector select
define <2 x float> @extract_two_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 { define <2 x float> @extract_two_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
; CHECK-LABEL: @extract_two_vselect( ; CHECK-LABEL: @extract_two_vselect(
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq <4 x i32> [[C:%.*]], zeroinitializer ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq <4 x i32> [[C:%.*]], zeroinitializer
; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]] ; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]]
; CHECK-NEXT: [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> undef, <2 x i32> <i32 1, i32 2> ; CHECK-NEXT: [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> poison, <2 x i32> <i32 1, i32 2>
; CHECK-NEXT: ret <2 x float> [[BUILD2]] ; CHECK-NEXT: ret <2 x float> [[BUILD2]]
; ;
%cmp = icmp ne <4 x i32> %c, zeroinitializer %cmp = icmp ne <4 x i32> %c, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x float> %a, <4 x float> %b %sel = select <4 x i1> %cmp, <4 x float> %a, <4 x float> %b
%extract1 = extractelement <4 x float> %sel, i32 1 %extract1 = extractelement <4 x float> %sel, i32 1
%extract2 = extractelement <4 x float> %sel, i32 2 %extract2 = extractelement <4 x float> %sel, i32 2
%build1 = insertelement <2 x float> poison, float %extract1, i32 0 %build1 = insertelement <2 x float> poison, float %extract1, i32 0
%build2 = insertelement <2 x float> %build1, float %extract2, i32 1 %build2 = insertelement <2 x float> %build1, float %extract2, i32 1
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%a.sink3 = select i1 %tobool11, <4 x float> %a, <4 x float> %b %a.sink3 = select i1 %tobool11, <4 x float> %a, <4 x float> %b
%10 = extractelement <4 x float> %a.sink3, i32 3 %10 = extractelement <4 x float> %a.sink3, i32 3
%11 = insertelement <4 x float> %8, float %10, i32 3 %11 = insertelement <4 x float> %8, float %10, i32 3
ret <4 x float> %11 ret <4 x float> %11
} }
define <4 x i32> @extract_cond(<4 x i32> %x, <4 x i32> %y, <4 x i1> %condv) { define <4 x i32> @extract_cond(<4 x i32> %x, <4 x i32> %y, <4 x i1> %condv) {
; CHECK-LABEL: @extract_cond( ; CHECK-LABEL: @extract_cond(
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i1> [[CONDV:%.*]], <4 x i1> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> ; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i1> [[CONDV:%.*]], <4 x i1> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[DOTSPLAT]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[DOTSPLAT]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]
; CHECK-NEXT: ret <4 x i32> [[R]] ; CHECK-NEXT: ret <4 x i32> [[R]]
; ;
%cond = extractelement <4 x i1> %condv, i32 3 %cond = extractelement <4 x i1> %condv, i32 3
%r = select i1 %cond, <4 x i32> %x, <4 x i32> %y %r = select i1 %cond, <4 x i32> %x, <4 x i32> %y
ret <4 x i32> %r ret <4 x i32> %r
} }
Show All 37 Lines;
%r = select i1 %cond, <4 x i32> %x, <4 x i32> %y %r = select i1 %cond, <4 x i32> %x, <4 x i32> %y
ret <4 x i32> %r ret <4 x i32> %r
} }
; IR shuffle can alter the number of elements in the vector, so this is ok. ; IR shuffle can alter the number of elements in the vector, so this is ok.
define <4 x i32> @extract_cond_type_mismatch(<4 x i32> %x, <4 x i32> %y, <5 x i1> %condv) { define <4 x i32> @extract_cond_type_mismatch(<4 x i32> %x, <4 x i32> %y, <5 x i1> %condv) {
; CHECK-LABEL: @extract_cond_type_mismatch( ; CHECK-LABEL: @extract_cond_type_mismatch(
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <5 x i1> [[CONDV:%.*]], <5 x i1> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <5 x i1> [[CONDV:%.*]], <5 x i1> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[DOTSPLAT]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[DOTSPLAT]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]
; CHECK-NEXT: ret <4 x i32> [[R]] ; CHECK-NEXT: ret <4 x i32> [[R]]
; ;
%cond = extractelement <5 x i1> %condv, i32 1 %cond = extractelement <5 x i1> %condv, i32 1
%r = select i1 %cond, <4 x i32> %x, <4 x i32> %y %r = select i1 %cond, <4 x i32> %x, <4 x i32> %y
ret <4 x i32> %r ret <4 x i32> %r
} }
attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }

llvm/test/Transforms/InstCombine/select-extractelement.ll

Show All 15 Lines;
ret float %extract ret float %extract
} }
; Multiple extractelements ; Multiple extractelements
define <2 x float> @extract_two_select(<4 x float> %a, <4 x float> %b, i32 %c) #0 { define <2 x float> @extract_two_select(<4 x float> %a, <4 x float> %b, i32 %c) #0 {
; CHECK-LABEL: @extract_two_select( ; CHECK-LABEL: @extract_two_select(
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[C:%.*]], 0 ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[C:%.*]], 0
; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]]
; CHECK-NEXT: [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> undef, <2 x i32> <i32 1, i32 2> ; CHECK-NEXT: [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> poison, <2 x i32> <i32 1, i32 2>
; CHECK-NEXT: ret <2 x float> [[BUILD2]] ; CHECK-NEXT: ret <2 x float> [[BUILD2]]
; ;
%cmp = icmp ne i32 %c, 0 %cmp = icmp ne i32 %c, 0
%sel = select i1 %cmp, <4 x float> %a, <4 x float> %b %sel = select i1 %cmp, <4 x float> %a, <4 x float> %b
%extract1 = extractelement <4 x float> %sel, i32 1 %extract1 = extractelement <4 x float> %sel, i32 1
%extract2 = extractelement <4 x float> %sel, i32 2 %extract2 = extractelement <4 x float> %sel, i32 2
%build1 = insertelement <2 x float> undef, float %extract1, i32 0 %build1 = insertelement <2 x float> undef, float %extract1, i32 0
%build2 = insertelement <2 x float> %build1, float %extract2, i32 1 %build2 = insertelement <2 x float> %build1, float %extract2, i32 1
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ret float %extract ret float %extract
} }
; Multiple extractelements from a vector select ; Multiple extractelements from a vector select
define <2 x float> @extract_two_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 { define <2 x float> @extract_two_vselect(<4 x float> %a, <4 x float> %b, <4 x i32> %c) #0 {
; CHECK-LABEL: @extract_two_vselect( ; CHECK-LABEL: @extract_two_vselect(
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq <4 x i32> [[C:%.*]], zeroinitializer ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq <4 x i32> [[C:%.*]], zeroinitializer
; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]] ; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[CMP_NOT]], <4 x float> [[B:%.*]], <4 x float> [[A:%.*]]
; CHECK-NEXT: [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> undef, <2 x i32> <i32 1, i32 2> ; CHECK-NEXT: [[BUILD2:%.*]] = shufflevector <4 x float> [[SEL]], <4 x float> poison, <2 x i32> <i32 1, i32 2>
; CHECK-NEXT: ret <2 x float> [[BUILD2]] ; CHECK-NEXT: ret <2 x float> [[BUILD2]]
; ;
%cmp = icmp ne <4 x i32> %c, zeroinitializer %cmp = icmp ne <4 x i32> %c, zeroinitializer
%sel = select <4 x i1> %cmp, <4 x float> %a, <4 x float> %b %sel = select <4 x i1> %cmp, <4 x float> %a, <4 x float> %b
%extract1 = extractelement <4 x float> %sel, i32 1 %extract1 = extractelement <4 x float> %sel, i32 1
%extract2 = extractelement <4 x float> %sel, i32 2 %extract2 = extractelement <4 x float> %sel, i32 2
%build1 = insertelement <2 x float> undef, float %extract1, i32 0 %build1 = insertelement <2 x float> undef, float %extract1, i32 0
%build2 = insertelement <2 x float> %build1, float %extract2, i32 1 %build2 = insertelement <2 x float> %build1, float %extract2, i32 1
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Linesentry:
%a.sink3 = select i1 %tobool11, <4 x float> %a, <4 x float> %b %a.sink3 = select i1 %tobool11, <4 x float> %a, <4 x float> %b
%10 = extractelement <4 x float> %a.sink3, i32 3 %10 = extractelement <4 x float> %a.sink3, i32 3
%11 = insertelement <4 x float> %8, float %10, i32 3 %11 = insertelement <4 x float> %8, float %10, i32 3
ret <4 x float> %11 ret <4 x float> %11
} }
define <4 x i32> @extract_cond(<4 x i32> %x, <4 x i32> %y, <4 x i1> %condv) { define <4 x i32> @extract_cond(<4 x i32> %x, <4 x i32> %y, <4 x i1> %condv) {
; CHECK-LABEL: @extract_cond( ; CHECK-LABEL: @extract_cond(
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i1> [[CONDV:%.*]], <4 x i1> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> ; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <4 x i1> [[CONDV:%.*]], <4 x i1> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[DOTSPLAT]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[DOTSPLAT]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]
; CHECK-NEXT: ret <4 x i32> [[R]] ; CHECK-NEXT: ret <4 x i32> [[R]]
; ;
%cond = extractelement <4 x i1> %condv, i32 3 %cond = extractelement <4 x i1> %condv, i32 3
%r = select i1 %cond, <4 x i32> %x, <4 x i32> %y %r = select i1 %cond, <4 x i32> %x, <4 x i32> %y
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @splat_cond(<4 x i32> %x, <4 x i32> %y, <4 x i1> %condv) { define <4 x i32> @splat_cond(<4 x i32> %x, <4 x i32> %y, <4 x i1> %condv) {
; CHECK-LABEL: @splat_cond( ; CHECK-LABEL: @splat_cond(
; CHECK-NEXT: [[SPLATCOND:%.*]] = shufflevector <4 x i1> [[CONDV:%.*]], <4 x i1> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> ; CHECK-NEXT: [[SPLATCOND:%.*]] = shufflevector <4 x i1> [[CONDV:%.*]], <4 x i1> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[SPLATCOND]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[SPLATCOND]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]
; CHECK-NEXT: ret <4 x i32> [[R]] ; CHECK-NEXT: ret <4 x i32> [[R]]
; ;
%splatcond = shufflevector <4 x i1> %condv, <4 x i1> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3> %splatcond = shufflevector <4 x i1> %condv, <4 x i1> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
%r = select <4 x i1> %splatcond, <4 x i32> %x, <4 x i32> %y %r = select <4 x i1> %splatcond, <4 x i32> %x, <4 x i32> %y
ret <4 x i32> %r ret <4 x i32> %r
} }
Show All 26 Lines;
%r = select i1 %cond, <4 x i32> %x, <4 x i32> %y %r = select i1 %cond, <4 x i32> %x, <4 x i32> %y
ret <4 x i32> %r ret <4 x i32> %r
} }
; IR shuffle can alter the number of elements in the vector, so this is ok. ; IR shuffle can alter the number of elements in the vector, so this is ok.
define <4 x i32> @extract_cond_type_mismatch(<4 x i32> %x, <4 x i32> %y, <5 x i1> %condv) { define <4 x i32> @extract_cond_type_mismatch(<4 x i32> %x, <4 x i32> %y, <5 x i1> %condv) {
; CHECK-LABEL: @extract_cond_type_mismatch( ; CHECK-LABEL: @extract_cond_type_mismatch(
; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <5 x i1> [[CONDV:%.*]], <5 x i1> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <5 x i1> [[CONDV:%.*]], <5 x i1> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[DOTSPLAT]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[DOTSPLAT]], <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]]
; CHECK-NEXT: ret <4 x i32> [[R]] ; CHECK-NEXT: ret <4 x i32> [[R]]
; ;
%cond = extractelement <5 x i1> %condv, i32 1 %cond = extractelement <5 x i1> %condv, i32 1
%r = select i1 %cond, <4 x i32> %x, <4 x i32> %y %r = select i1 %cond, <4 x i32> %x, <4 x i32> %y
ret <4 x i32> %r ret <4 x i32> %r
} }
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llvm/test/Transforms/InstCombine/shift-add.ll

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%C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16> %C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
%D = lshr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C %D = lshr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
ret <4 x i32> %D ret <4 x i32> %D
} }
define <4 x i32> @shl_C1_add_A_C2_v4i32_splat(i16 %I) { define <4 x i32> @shl_C1_add_A_C2_v4i32_splat(i16 %I) {
; CHECK-LABEL: @shl_C1_add_A_C2_v4i32_splat( ; CHECK-LABEL: @shl_C1_add_A_C2_v4i32_splat(
; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32 ; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32
; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i64 0 ; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0
; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer ; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
; CHECK-NEXT: [[E:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 poison, i32 -458752>, [[C]] ; CHECK-NEXT: [[E:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 poison, i32 -458752>, [[C]]
; CHECK-NEXT: ret <4 x i32> [[E]] ; CHECK-NEXT: ret <4 x i32> [[E]]
; ;
%A = zext i16 %I to i32 %A = zext i16 %I to i32
%B = insertelement <4 x i32> undef, i32 %A, i32 0 %B = insertelement <4 x i32> undef, i32 %A, i32 0
%C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer %C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
%D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16> %D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
%E = shl <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D %E = shl <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D
ret <4 x i32> %E ret <4 x i32> %E
} }
define <4 x i32> @ashr_C1_add_A_C2_v4i32_splat(i16 %I) { define <4 x i32> @ashr_C1_add_A_C2_v4i32_splat(i16 %I) {
; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32_splat( ; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32_splat(
; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32 ; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32
; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i64 0 ; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0
; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer ; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
; CHECK-NEXT: [[E:%.*]] = ashr <4 x i32> <i32 6, i32 1, i32 poison, i32 -1>, [[C]] ; CHECK-NEXT: [[E:%.*]] = ashr <4 x i32> <i32 6, i32 1, i32 poison, i32 -1>, [[C]]
; CHECK-NEXT: ret <4 x i32> [[E]] ; CHECK-NEXT: ret <4 x i32> [[E]]
; ;
%A = zext i16 %I to i32 %A = zext i16 %I to i32
%B = insertelement <4 x i32> undef, i32 %A, i32 0 %B = insertelement <4 x i32> undef, i32 %A, i32 0
%C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer %C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
%D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16> %D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
%E = ashr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D %E = ashr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D
ret <4 x i32> %E ret <4 x i32> %E
} }
define <4 x i32> @lshr_C1_add_A_C2_v4i32_splat(i16 %I) { define <4 x i32> @lshr_C1_add_A_C2_v4i32_splat(i16 %I) {
; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32_splat( ; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32_splat(
; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32 ; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32
; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i64 0 ; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0
; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer ; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
; CHECK-NEXT: [[E:%.*]] = lshr <4 x i32> <i32 6, i32 1, i32 poison, i32 65535>, [[C]] ; CHECK-NEXT: [[E:%.*]] = lshr <4 x i32> <i32 6, i32 1, i32 poison, i32 65535>, [[C]]
; CHECK-NEXT: ret <4 x i32> [[E]] ; CHECK-NEXT: ret <4 x i32> [[E]]
; ;
%A = zext i16 %I to i32 %A = zext i16 %I to i32
%B = insertelement <4 x i32> undef, i32 %A, i32 0 %B = insertelement <4 x i32> undef, i32 %A, i32 0
%C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer %C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
%D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16> %D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
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; CHECK-NEXT: [[TMP10:%.*]] = zext i1 [[ADD_NARROWED_OVERFLOW]] to i64 ; CHECK-NEXT: [[TMP10:%.*]] = zext i1 [[ADD_NARROWED_OVERFLOW]] to i64
; CHECK-NEXT: [[TMP11:%.*]] = add nuw nsw i64 [[TMP9]], [[TMP10]] ; CHECK-NEXT: [[TMP11:%.*]] = add nuw nsw i64 [[TMP9]], [[TMP10]]
; CHECK-NEXT: [[TMP12:%.*]] = extractelement <3 x i32> [[TMP0]], i64 2 ; CHECK-NEXT: [[TMP12:%.*]] = extractelement <3 x i32> [[TMP0]], i64 2
; CHECK-NEXT: [[TMP13:%.*]] = extractelement <3 x i32> [[TMP1]], i64 2 ; CHECK-NEXT: [[TMP13:%.*]] = extractelement <3 x i32> [[TMP1]], i64 2
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], [[TMP12]] ; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], [[TMP12]]
; CHECK-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP11]], 32 ; CHECK-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP11]], 32
; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32 ; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32
; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP14]], [[TMP16]] ; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP14]], [[TMP16]]
; CHECK-NEXT: [[TMP18:%.*]] = insertelement <3 x i32> undef, i32 [[ADD_NARROWED]], i64 0 ; CHECK-NEXT: [[TMP18:%.*]] = insertelement <3 x i32> poison, i32 [[ADD_NARROWED]], i64 0
; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP11]] to i32 ; CHECK-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP11]] to i32
; CHECK-NEXT: [[TMP20:%.*]] = insertelement <3 x i32> [[TMP18]], i32 [[TMP19]], i64 1 ; CHECK-NEXT: [[TMP20:%.*]] = insertelement <3 x i32> [[TMP18]], i32 [[TMP19]], i64 1
; CHECK-NEXT: [[TMP21:%.*]] = insertelement <3 x i32> [[TMP20]], i32 [[TMP17]], i64 2 ; CHECK-NEXT: [[TMP21:%.*]] = insertelement <3 x i32> [[TMP20]], i32 [[TMP17]], i64 2
; CHECK-NEXT: ret <3 x i32> [[TMP21]] ; CHECK-NEXT: ret <3 x i32> [[TMP21]]
; ;
%3 = extractelement <3 x i32> %0, i64 0 %3 = extractelement <3 x i32> %0, i64 0
%4 = zext i32 %3 to i64 %4 = zext i32 %3 to i64
%5 = extractelement <3 x i32> %1, i64 0 %5 = extractelement <3 x i32> %1, i64 0
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llvm/test/Transforms/InstCombine/shuffle-cast.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=instcombine -S -data-layout="e" | FileCheck %s --check-prefixes=ANY,LE ; RUN: opt < %s -passes=instcombine -S -data-layout="e" | FileCheck %s --check-prefixes=ANY,LE
; RUN: opt < %s -passes=instcombine -S -data-layout="E" | FileCheck %s --check-prefixes=ANY,BE ; RUN: opt < %s -passes=instcombine -S -data-layout="E" | FileCheck %s --check-prefixes=ANY,BE
define <4 x i16> @trunc_little_endian(<4 x i32> %x) { define <4 x i16> @trunc_little_endian(<4 x i32> %x) {
; LE-LABEL: @trunc_little_endian( ; LE-LABEL: @trunc_little_endian(
; LE-NEXT: [[R:%.*]] = trunc <4 x i32> [[X:%.*]] to <4 x i16> ; LE-NEXT: [[R:%.*]] = trunc <4 x i32> [[X:%.*]] to <4 x i16>
; LE-NEXT: ret <4 x i16> [[R]] ; LE-NEXT: ret <4 x i16> [[R]]
; ;
; BE-LABEL: @trunc_little_endian( ; BE-LABEL: @trunc_little_endian(
; BE-NEXT: [[B:%.*]] = bitcast <4 x i32> [[X:%.*]] to <8 x i16> ; BE-NEXT: [[B:%.*]] = bitcast <4 x i32> [[X:%.*]] to <8 x i16>
; BE-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> ; BE-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; BE-NEXT: ret <4 x i16> [[R]] ; BE-NEXT: ret <4 x i16> [[R]]
; ;
%b = bitcast <4 x i32> %x to <8 x i16> %b = bitcast <4 x i32> %x to <8 x i16>
%r = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %r = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x i16> %r ret <4 x i16> %r
} }
define <4 x i16> @trunc_big_endian(<4 x i32> %x) { define <4 x i16> @trunc_big_endian(<4 x i32> %x) {
; LE-LABEL: @trunc_big_endian( ; LE-LABEL: @trunc_big_endian(
; LE-NEXT: [[B:%.*]] = bitcast <4 x i32> [[X:%.*]] to <8 x i16> ; LE-NEXT: [[B:%.*]] = bitcast <4 x i32> [[X:%.*]] to <8 x i16>
; LE-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> ; LE-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
; LE-NEXT: ret <4 x i16> [[R]] ; LE-NEXT: ret <4 x i16> [[R]]
; ;
; BE-LABEL: @trunc_big_endian( ; BE-LABEL: @trunc_big_endian(
; BE-NEXT: [[R:%.*]] = trunc <4 x i32> [[X:%.*]] to <4 x i16> ; BE-NEXT: [[R:%.*]] = trunc <4 x i32> [[X:%.*]] to <4 x i16>
; BE-NEXT: ret <4 x i16> [[R]] ; BE-NEXT: ret <4 x i16> [[R]]
; ;
%b = bitcast <4 x i32> %x to <8 x i16> %b = bitcast <4 x i32> %x to <8 x i16>
%r = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> %r = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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; LE-NEXT: [[B:%.*]] = bitcast <2 x i64> [[X:%.*]] to <8 x i16> ; LE-NEXT: [[B:%.*]] = bitcast <2 x i64> [[X:%.*]] to <8 x i16>
; LE-NEXT: call void @use_v8i16(<8 x i16> [[B]]) ; LE-NEXT: call void @use_v8i16(<8 x i16> [[B]])
; LE-NEXT: [[R:%.*]] = trunc <2 x i64> [[X]] to <2 x i16> ; LE-NEXT: [[R:%.*]] = trunc <2 x i64> [[X]] to <2 x i16>
; LE-NEXT: ret <2 x i16> [[R]] ; LE-NEXT: ret <2 x i16> [[R]]
; ;
; BE-LABEL: @trunc_little_endian_extra_use( ; BE-LABEL: @trunc_little_endian_extra_use(
; BE-NEXT: [[B:%.*]] = bitcast <2 x i64> [[X:%.*]] to <8 x i16> ; BE-NEXT: [[B:%.*]] = bitcast <2 x i64> [[X:%.*]] to <8 x i16>
; BE-NEXT: call void @use_v8i16(<8 x i16> [[B]]) ; BE-NEXT: call void @use_v8i16(<8 x i16> [[B]])
; BE-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> undef, <2 x i32> <i32 0, i32 4> ; BE-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <2 x i32> <i32 0, i32 4>
; BE-NEXT: ret <2 x i16> [[R]] ; BE-NEXT: ret <2 x i16> [[R]]
; ;
%b = bitcast <2 x i64> %x to <8 x i16> %b = bitcast <2 x i64> %x to <8 x i16>
call void @use_v8i16(<8 x i16> %b) call void @use_v8i16(<8 x i16> %b)
%r = shufflevector <8 x i16> %b, <8 x i16> undef, <2 x i32> <i32 0, i32 4> %r = shufflevector <8 x i16> %b, <8 x i16> undef, <2 x i32> <i32 0, i32 4>
ret <2 x i16> %r ret <2 x i16> %r
} }
declare void @use_v12i11(<12 x i11>) declare void @use_v12i11(<12 x i11>)
; Weird types are ok. ; Weird types are ok.
define <4 x i11> @trunc_big_endian_extra_use(<4 x i33> %x) { define <4 x i11> @trunc_big_endian_extra_use(<4 x i33> %x) {
; LE-LABEL: @trunc_big_endian_extra_use( ; LE-LABEL: @trunc_big_endian_extra_use(
; LE-NEXT: [[B:%.*]] = bitcast <4 x i33> [[X:%.*]] to <12 x i11> ; LE-NEXT: [[B:%.*]] = bitcast <4 x i33> [[X:%.*]] to <12 x i11>
; LE-NEXT: call void @use_v12i11(<12 x i11> [[B]]) ; LE-NEXT: call void @use_v12i11(<12 x i11> [[B]])
; LE-NEXT: [[R:%.*]] = shufflevector <12 x i11> [[B]], <12 x i11> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> ; LE-NEXT: [[R:%.*]] = shufflevector <12 x i11> [[B]], <12 x i11> poison, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
; LE-NEXT: ret <4 x i11> [[R]] ; LE-NEXT: ret <4 x i11> [[R]]
; ;
; BE-LABEL: @trunc_big_endian_extra_use( ; BE-LABEL: @trunc_big_endian_extra_use(
; BE-NEXT: [[B:%.*]] = bitcast <4 x i33> [[X:%.*]] to <12 x i11> ; BE-NEXT: [[B:%.*]] = bitcast <4 x i33> [[X:%.*]] to <12 x i11>
; BE-NEXT: call void @use_v12i11(<12 x i11> [[B]]) ; BE-NEXT: call void @use_v12i11(<12 x i11> [[B]])
; BE-NEXT: [[R:%.*]] = trunc <4 x i33> [[X]] to <4 x i11> ; BE-NEXT: [[R:%.*]] = trunc <4 x i33> [[X]] to <4 x i11>
; BE-NEXT: ret <4 x i11> [[R]] ; BE-NEXT: ret <4 x i11> [[R]]
; ;
%b = bitcast <4 x i33> %x to <12 x i11> %b = bitcast <4 x i33> %x to <12 x i11>
call void @use_v12i11(<12 x i11> %b) call void @use_v12i11(<12 x i11> %b)
%r = shufflevector <12 x i11> %b, <12 x i11> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11> %r = shufflevector <12 x i11> %b, <12 x i11> undef, <4 x i32> <i32 2, i32 5, i32 8, i32 11>
ret <4 x i11> %r ret <4 x i11> %r
} }
define <4 x i16> @wrong_cast1(i128 %x) { define <4 x i16> @wrong_cast1(i128 %x) {
; ANY-LABEL: @wrong_cast1( ; ANY-LABEL: @wrong_cast1(
; ANY-NEXT: [[B:%.*]] = bitcast i128 [[X:%.*]] to <8 x i16> ; ANY-NEXT: [[B:%.*]] = bitcast i128 [[X:%.*]] to <8 x i16>
; ANY-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> ; ANY-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; ANY-NEXT: ret <4 x i16> [[R]] ; ANY-NEXT: ret <4 x i16> [[R]]
; ;
%b = bitcast i128 %x to <8 x i16> %b = bitcast i128 %x to <8 x i16>
%r = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %r = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x i16> %r ret <4 x i16> %r
} }
define <4 x i16> @wrong_cast2(<4 x float> %x) { define <4 x i16> @wrong_cast2(<4 x float> %x) {
; ANY-LABEL: @wrong_cast2( ; ANY-LABEL: @wrong_cast2(
; ANY-NEXT: [[B:%.*]] = bitcast <4 x float> [[X:%.*]] to <8 x i16> ; ANY-NEXT: [[B:%.*]] = bitcast <4 x float> [[X:%.*]] to <8 x i16>
; ANY-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> ; ANY-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; ANY-NEXT: ret <4 x i16> [[R]] ; ANY-NEXT: ret <4 x i16> [[R]]
; ;
%b = bitcast <4 x float> %x to <8 x i16> %b = bitcast <4 x float> %x to <8 x i16>
%r = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %r = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x i16> %r ret <4 x i16> %r
} }
define <4 x half> @wrong_cast3(<4 x i32> %x) { define <4 x half> @wrong_cast3(<4 x i32> %x) {
; ANY-LABEL: @wrong_cast3( ; ANY-LABEL: @wrong_cast3(
; ANY-NEXT: [[B:%.*]] = bitcast <4 x i32> [[X:%.*]] to <8 x half> ; ANY-NEXT: [[B:%.*]] = bitcast <4 x i32> [[X:%.*]] to <8 x half>
; ANY-NEXT: [[R:%.*]] = shufflevector <8 x half> [[B]], <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> ; ANY-NEXT: [[R:%.*]] = shufflevector <8 x half> [[B]], <8 x half> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; ANY-NEXT: ret <4 x half> [[R]] ; ANY-NEXT: ret <4 x half> [[R]]
; ;
%b = bitcast <4 x i32> %x to <8 x half> %b = bitcast <4 x i32> %x to <8 x half>
%r = shufflevector <8 x half> %b, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> %r = shufflevector <8 x half> %b, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x half> %r ret <4 x half> %r
} }
define <2 x i16> @wrong_shuffle(<4 x i32> %x) { define <2 x i16> @wrong_shuffle(<4 x i32> %x) {
; ANY-LABEL: @wrong_shuffle( ; ANY-LABEL: @wrong_shuffle(
; ANY-NEXT: [[B:%.*]] = bitcast <4 x i32> [[X:%.*]] to <8 x i16> ; ANY-NEXT: [[B:%.*]] = bitcast <4 x i32> [[X:%.*]] to <8 x i16>
; ANY-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> undef, <2 x i32> <i32 0, i32 2> ; ANY-NEXT: [[R:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <2 x i32> <i32 0, i32 2>
; ANY-NEXT: ret <2 x i16> [[R]] ; ANY-NEXT: ret <2 x i16> [[R]]
; ;
%b = bitcast <4 x i32> %x to <8 x i16> %b = bitcast <4 x i32> %x to <8 x i16>
%r = shufflevector <8 x i16> %b, <8 x i16> undef, <2 x i32> <i32 0, i32 2> %r = shufflevector <8 x i16> %b, <8 x i16> undef, <2 x i32> <i32 0, i32 2>
ret <2 x i16> %r ret <2 x i16> %r
} }

llvm/test/Transforms/InstCombine/shuffle-select-narrow.ll

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declare void @use(<4 x i8>) declare void @use(<4 x i8>)
declare void @use_cmp(<4 x i1>) declare void @use_cmp(<4 x i1>)
; Negative test - extra use would require more instructions than we started with. ; Negative test - extra use would require more instructions than we started with.
define <2 x i8> @narrow_shuffle_of_select_use1(<2 x i1> %cmp, <4 x i8> %x, <4 x i8> %y) { define <2 x i8> @narrow_shuffle_of_select_use1(<2 x i1> %cmp, <4 x i8> %x, <4 x i8> %y) {
; CHECK-LABEL: @narrow_shuffle_of_select_use1( ; CHECK-LABEL: @narrow_shuffle_of_select_use1(
; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <2 x i1> [[CMP:%.*]], <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <2 x i1> [[CMP:%.*]], <2 x i1> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[WIDESEL:%.*]] = select <4 x i1> [[WIDECMP]], <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]] ; CHECK-NEXT: [[WIDESEL:%.*]] = select <4 x i1> [[WIDECMP]], <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]]
; CHECK-NEXT: call void @use(<4 x i8> [[WIDESEL]]) ; CHECK-NEXT: call void @use(<4 x i8> [[WIDESEL]])
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[WIDESEL]], <4 x i8> undef, <2 x i32> <i32 0, i32 1> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[WIDESEL]], <4 x i8> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: ret <2 x i8> [[R]] ; CHECK-NEXT: ret <2 x i8> [[R]]
; ;
%widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%widesel = select <4 x i1> %widecmp, <4 x i8> %x, <4 x i8> %y %widesel = select <4 x i1> %widecmp, <4 x i8> %x, <4 x i8> %y
call void @use(<4 x i8> %widesel) call void @use(<4 x i8> %widesel)
%r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <2 x i32> <i32 0, i32 1> %r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
ret <2 x i8> %r ret <2 x i8> %r
} }
; Negative test - extra use would require more instructions than we started with. ; Negative test - extra use would require more instructions than we started with.
define <2 x i8> @narrow_shuffle_of_select_use2(<2 x i1> %cmp, <4 x i8> %x, <4 x i8> %y) { define <2 x i8> @narrow_shuffle_of_select_use2(<2 x i1> %cmp, <4 x i8> %x, <4 x i8> %y) {
; CHECK-LABEL: @narrow_shuffle_of_select_use2( ; CHECK-LABEL: @narrow_shuffle_of_select_use2(
; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <2 x i1> [[CMP:%.*]], <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <2 x i1> [[CMP:%.*]], <2 x i1> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: call void @use_cmp(<4 x i1> [[WIDECMP]]) ; CHECK-NEXT: call void @use_cmp(<4 x i1> [[WIDECMP]])
; CHECK-NEXT: [[WIDESEL:%.*]] = select <4 x i1> [[WIDECMP]], <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]] ; CHECK-NEXT: [[WIDESEL:%.*]] = select <4 x i1> [[WIDECMP]], <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[WIDESEL]], <4 x i8> undef, <2 x i32> <i32 0, i32 1> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[WIDESEL]], <4 x i8> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: ret <2 x i8> [[R]] ; CHECK-NEXT: ret <2 x i8> [[R]]
; ;
%widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
call void @use_cmp(<4 x i1> %widecmp) call void @use_cmp(<4 x i1> %widecmp)
%widesel = select <4 x i1> %widecmp, <4 x i8> %x, <4 x i8> %y %widesel = select <4 x i1> %widecmp, <4 x i8> %x, <4 x i8> %y
%r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <2 x i32> <i32 0, i32 1> %r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <2 x i32> <i32 0, i32 1>
ret <2 x i8> %r ret <2 x i8> %r
} }
; Negative test - mismatched types would require extra shuffling. ; Negative test - mismatched types would require extra shuffling.
define <3 x i8> @narrow_shuffle_of_select_mismatch_types1(<2 x i1> %cmp, <4 x i8> %x, <4 x i8> %y) { define <3 x i8> @narrow_shuffle_of_select_mismatch_types1(<2 x i1> %cmp, <4 x i8> %x, <4 x i8> %y) {
; CHECK-LABEL: @narrow_shuffle_of_select_mismatch_types1( ; CHECK-LABEL: @narrow_shuffle_of_select_mismatch_types1(
; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <2 x i1> [[CMP:%.*]], <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <2 x i1> [[CMP:%.*]], <2 x i1> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[WIDESEL:%.*]] = select <4 x i1> [[WIDECMP]], <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]] ; CHECK-NEXT: [[WIDESEL:%.*]] = select <4 x i1> [[WIDECMP]], <4 x i8> [[X:%.*]], <4 x i8> [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[WIDESEL]], <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[WIDESEL]], <4 x i8> poison, <3 x i32> <i32 0, i32 1, i32 2>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %widecmp = shufflevector <2 x i1> %cmp, <2 x i1> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%widesel = select <4 x i1> %widecmp, <4 x i8> %x, <4 x i8> %y %widesel = select <4 x i1> %widecmp, <4 x i8> %x, <4 x i8> %y
%r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> %r = shufflevector <4 x i8> %widesel, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
ret <3 x i8> %r ret <3 x i8> %r
} }
; Negative test - mismatched types would require extra shuffling. ; Negative test - mismatched types would require extra shuffling.
define <3 x i8> @narrow_shuffle_of_select_mismatch_types2(<4 x i1> %cmp, <6 x i8> %x, <6 x i8> %y) { define <3 x i8> @narrow_shuffle_of_select_mismatch_types2(<4 x i1> %cmp, <6 x i8> %x, <6 x i8> %y) {
; CHECK-LABEL: @narrow_shuffle_of_select_mismatch_types2( ; CHECK-LABEL: @narrow_shuffle_of_select_mismatch_types2(
; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> undef, <6 x i32> <i32 0, i32 1, i32 2, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[WIDECMP:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> poison, <6 x i32> <i32 0, i32 1, i32 2, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[WIDESEL:%.*]] = select <6 x i1> [[WIDECMP]], <6 x i8> [[X:%.*]], <6 x i8> [[Y:%.*]] ; CHECK-NEXT: [[WIDESEL:%.*]] = select <6 x i1> [[WIDECMP]], <6 x i8> [[X:%.*]], <6 x i8> [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <6 x i8> [[WIDESEL]], <6 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> ; CHECK-NEXT: [[R:%.*]] = shufflevector <6 x i8> [[WIDESEL]], <6 x i8> poison, <3 x i32> <i32 0, i32 1, i32 2>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%widecmp = shufflevector <4 x i1> %cmp, <4 x i1> undef, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef> %widecmp = shufflevector <4 x i1> %cmp, <4 x i1> undef, <6 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef>
%widesel = select <6 x i1> %widecmp, <6 x i8> %x, <6 x i8> %y %widesel = select <6 x i1> %widecmp, <6 x i8> %x, <6 x i8> %y
%r = shufflevector <6 x i8> %widesel, <6 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> %r = shufflevector <6 x i8> %widesel, <6 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2>
ret <3 x i8> %r ret <3 x i8> %r
} }
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llvm/test/Transforms/InstCombine/shuffle_select.ll

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%t3 = shufflevector <4 x i8> %t1, <4 x i8> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3> %t3 = shufflevector <4 x i8> %t1, <4 x i8> %t2, <4 x i32> <i32 4, i32 5, i32 2, i32 3>
ret <4 x i8> %t3 ret <4 x i8> %t3
} }
; The undef operand is used to simplify the shuffle mask, but don't assert that too soon. ; The undef operand is used to simplify the shuffle mask, but don't assert that too soon.
define <4 x i32> @PR41419(<4 x i32> %v) { define <4 x i32> @PR41419(<4 x i32> %v) {
; CHECK-LABEL: @PR41419( ; CHECK-LABEL: @PR41419(
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V:%.*]], <4 x i32> undef, <4 x i32> <i32 poison, i32 poison, i32 2, i32 poison> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[V:%.*]], <4 x i32> <i32 undef, i32 undef, i32 poison, i32 undef>, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
; CHECK-NEXT: ret <4 x i32> [[S]] ; CHECK-NEXT: ret <4 x i32> [[S]]
; ;
%s = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 4, i32 5, i32 2, i32 7> %s = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 4, i32 5, i32 2, i32 7>
ret <4 x i32> %s ret <4 x i32> %s
} }
; The shuffle masks in the next 4 tests are identical to make it easier ; The shuffle masks in the next 4 tests are identical to make it easier
; to see that we are choosing the correct elements in the new shuffle. ; to see that we are choosing the correct elements in the new shuffle.
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llvm/test/Transforms/InstCombine/shufflevec-bitcast.ll

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store float %f, ptr %o2, align 4 store float %f, ptr %o2, align 4
ret void ret void
} }
; Shuffle-of-bitcast-splat --> splat-bitcast ; Shuffle-of-bitcast-splat --> splat-bitcast
define <4 x i16> @splat_bitcast_operand(<8 x i8> %x) { define <4 x i16> @splat_bitcast_operand(<8 x i8> %x) {
; CHECK-LABEL: @splat_bitcast_operand( ; CHECK-LABEL: @splat_bitcast_operand(
; CHECK-NEXT: [[S1:%.*]] = shufflevector <8 x i8> [[X:%.*]], <8 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <8 x i8> [[X:%.*]], <8 x i8> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[S2:%.*]] = bitcast <8 x i8> [[S1]] to <4 x i16> ; CHECK-NEXT: [[S2:%.*]] = bitcast <8 x i8> [[S1]] to <4 x i16>
; CHECK-NEXT: ret <4 x i16> [[S2]] ; CHECK-NEXT: ret <4 x i16> [[S2]]
; ;
%s1 = shufflevector <8 x i8> %x, <8 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %s1 = shufflevector <8 x i8> %x, <8 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%bc = bitcast <8 x i8> %s1 to <4 x i16> %bc = bitcast <8 x i8> %s1 to <4 x i16>
%s2 = shufflevector <4 x i16> %bc, <4 x i16> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 0> %s2 = shufflevector <4 x i16> %bc, <4 x i16> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 0>
ret <4 x i16> %s2 ret <4 x i16> %s2
} }
; Shuffle-of-bitcast-splat --> splat-bitcast ; Shuffle-of-bitcast-splat --> splat-bitcast
define <4 x i16> @splat_bitcast_operand_uses(<8 x i8> %x) { define <4 x i16> @splat_bitcast_operand_uses(<8 x i8> %x) {
; CHECK-LABEL: @splat_bitcast_operand_uses( ; CHECK-LABEL: @splat_bitcast_operand_uses(
; CHECK-NEXT: [[S1:%.*]] = shufflevector <8 x i8> [[X:%.*]], <8 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <8 x i8> [[X:%.*]], <8 x i8> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[BC:%.*]] = bitcast <8 x i8> [[S1]] to <4 x i16> ; CHECK-NEXT: [[BC:%.*]] = bitcast <8 x i8> [[S1]] to <4 x i16>
; CHECK-NEXT: call void @use(<4 x i16> [[BC]]) ; CHECK-NEXT: call void @use(<4 x i16> [[BC]])
; CHECK-NEXT: [[S2:%.*]] = bitcast <8 x i8> [[S1]] to <4 x i16> ; CHECK-NEXT: [[S2:%.*]] = bitcast <8 x i8> [[S1]] to <4 x i16>
; CHECK-NEXT: ret <4 x i16> [[S2]] ; CHECK-NEXT: ret <4 x i16> [[S2]]
; ;
%s1 = shufflevector <8 x i8> %x, <8 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %s1 = shufflevector <8 x i8> %x, <8 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%bc = bitcast <8 x i8> %s1 to <4 x i16> %bc = bitcast <8 x i8> %s1 to <4 x i16>
call void @use(<4 x i16> %bc) call void @use(<4 x i16> %bc)
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%s2 = shufflevector <4 x i32> %bc, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %s2 = shufflevector <4 x i32> %bc, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
ret <4 x i32> %s2 ret <4 x i32> %s2
} }
; TODO: Could allow fold for length-changing shuffles. ; TODO: Could allow fold for length-changing shuffles.
define <5 x i16> @splat_bitcast_operand_change_type(<8 x i8> %x) { define <5 x i16> @splat_bitcast_operand_change_type(<8 x i8> %x) {
; CHECK-LABEL: @splat_bitcast_operand_change_type( ; CHECK-LABEL: @splat_bitcast_operand_change_type(
; CHECK-NEXT: [[S1:%.*]] = shufflevector <8 x i8> [[X:%.*]], <8 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <8 x i8> [[X:%.*]], <8 x i8> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[BC:%.*]] = bitcast <8 x i8> [[S1]] to <4 x i16> ; CHECK-NEXT: [[BC:%.*]] = bitcast <8 x i8> [[S1]] to <4 x i16>
; CHECK-NEXT: [[S2:%.*]] = shufflevector <4 x i16> [[BC]], <4 x i16> undef, <5 x i32> <i32 0, i32 2, i32 1, i32 0, i32 3> ; CHECK-NEXT: [[S2:%.*]] = shufflevector <4 x i16> [[BC]], <4 x i16> poison, <5 x i32> <i32 0, i32 2, i32 1, i32 0, i32 3>
; CHECK-NEXT: ret <5 x i16> [[S2]] ; CHECK-NEXT: ret <5 x i16> [[S2]]
; ;
%s1 = shufflevector <8 x i8> %x, <8 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %s1 = shufflevector <8 x i8> %x, <8 x i8> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%bc = bitcast <8 x i8> %s1 to <4 x i16> %bc = bitcast <8 x i8> %s1 to <4 x i16>
%s2 = shufflevector <4 x i16> %bc, <4 x i16> undef, <5 x i32> <i32 0, i32 2, i32 1, i32 0, i32 3> %s2 = shufflevector <4 x i16> %bc, <4 x i16> undef, <5 x i32> <i32 0, i32 2, i32 1, i32 0, i32 3>
ret <5 x i16> %s2 ret <5 x i16> %s2
} }
; Shuffle-of-bitcast-splat --> splat-bitcast ; Shuffle-of-bitcast-splat --> splat-bitcast
define <4 x i16> @splat_bitcast_operand_wider_src_elt(<2 x i32> %x) { define <4 x i16> @splat_bitcast_operand_wider_src_elt(<2 x i32> %x) {
; CHECK-LABEL: @splat_bitcast_operand_wider_src_elt( ; CHECK-LABEL: @splat_bitcast_operand_wider_src_elt(
; CHECK-NEXT: [[S1:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[S2:%.*]] = bitcast <2 x i32> [[S1]] to <4 x i16> ; CHECK-NEXT: [[S2:%.*]] = bitcast <2 x i32> [[S1]] to <4 x i16>
; CHECK-NEXT: ret <4 x i16> [[S2]] ; CHECK-NEXT: ret <4 x i16> [[S2]]
; ;
%s1 = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> <i32 1, i32 1> %s1 = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
%bc = bitcast <2 x i32> %s1 to <4 x i16> %bc = bitcast <2 x i32> %s1 to <4 x i16>
%s2 = shufflevector <4 x i16> %bc, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> %s2 = shufflevector <4 x i16> %bc, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
ret <4 x i16> %s2 ret <4 x i16> %s2
} }
; Shuffle-of-bitcast-splat --> splat-bitcast ; Shuffle-of-bitcast-splat --> splat-bitcast
define <4 x i16> @splat_bitcast_operand_wider_src_elt_uses(<2 x i32> %x) { define <4 x i16> @splat_bitcast_operand_wider_src_elt_uses(<2 x i32> %x) {
; CHECK-LABEL: @splat_bitcast_operand_wider_src_elt_uses( ; CHECK-LABEL: @splat_bitcast_operand_wider_src_elt_uses(
; CHECK-NEXT: [[S1:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[BC:%.*]] = bitcast <2 x i32> [[S1]] to <4 x i16> ; CHECK-NEXT: [[BC:%.*]] = bitcast <2 x i32> [[S1]] to <4 x i16>
; CHECK-NEXT: call void @use(<4 x i16> [[BC]]) ; CHECK-NEXT: call void @use(<4 x i16> [[BC]])
; CHECK-NEXT: [[S2:%.*]] = bitcast <2 x i32> [[S1]] to <4 x i16> ; CHECK-NEXT: [[S2:%.*]] = bitcast <2 x i32> [[S1]] to <4 x i16>
; CHECK-NEXT: ret <4 x i16> [[S2]] ; CHECK-NEXT: ret <4 x i16> [[S2]]
; ;
%s1 = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> <i32 1, i32 1> %s1 = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
%bc = bitcast <2 x i32> %s1 to <4 x i16> %bc = bitcast <2 x i32> %s1 to <4 x i16>
call void @use(<4 x i16> %bc) call void @use(<4 x i16> %bc)
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%s2 = shufflevector <16 x i8> %bc, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> %s2 = shufflevector <16 x i8> %bc, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
ret <16 x i8> %s2 ret <16 x i8> %s2
} }
; Negative test - the 2nd mask can't be widened ; Negative test - the 2nd mask can't be widened
define <16 x i8> @shuf_bitcast_operand_cannot_widen(<4 x i32> %x) { define <16 x i8> @shuf_bitcast_operand_cannot_widen(<4 x i32> %x) {
; CHECK-LABEL: @shuf_bitcast_operand_cannot_widen( ; CHECK-LABEL: @shuf_bitcast_operand_cannot_widen(
; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[S1]] to <16 x i8> ; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[S1]] to <16 x i8>
; CHECK-NEXT: [[S2:%.*]] = shufflevector <16 x i8> [[BC]], <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 12, i32 13, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[S2:%.*]] = shufflevector <16 x i8> [[BC]], <16 x i8> poison, <16 x i32> <i32 12, i32 13, i32 12, i32 13, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: ret <16 x i8> [[S2]] ; CHECK-NEXT: ret <16 x i8> [[S2]]
; ;
%s1 = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %s1 = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%bc = bitcast <4 x i32> %s1 to <16 x i8> %bc = bitcast <4 x i32> %s1 to <16 x i8>
%s2 = shufflevector <16 x i8> %bc, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 12, i32 13, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> %s2 = shufflevector <16 x i8> %bc, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 12, i32 13, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
ret <16 x i8> %s2 ret <16 x i8> %s2
} }
; Negative test - the 2nd mask can't be widened ; Negative test - the 2nd mask can't be widened
define <16 x i8> @shuf_bitcast_operand_cannot_widen_undef(<4 x i32> %x) { define <16 x i8> @shuf_bitcast_operand_cannot_widen_undef(<4 x i32> %x) {
; CHECK-LABEL: @shuf_bitcast_operand_cannot_widen_undef( ; CHECK-LABEL: @shuf_bitcast_operand_cannot_widen_undef(
; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[S1]] to <16 x i8> ; CHECK-NEXT: [[BC:%.*]] = bitcast <4 x i32> [[S1]] to <16 x i8>
; CHECK-NEXT: [[S2:%.*]] = shufflevector <16 x i8> [[BC]], <16 x i8> undef, <16 x i32> <i32 12, i32 poison, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[S2:%.*]] = shufflevector <16 x i8> [[BC]], <16 x i8> poison, <16 x i32> <i32 12, i32 poison, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: ret <16 x i8> [[S2]] ; CHECK-NEXT: ret <16 x i8> [[S2]]
; ;
%s1 = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> %s1 = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
%bc = bitcast <4 x i32> %s1 to <16 x i8> %bc = bitcast <4 x i32> %s1 to <16 x i8>
%s2 = shufflevector <16 x i8> %bc, <16 x i8> undef, <16 x i32> <i32 12, i32 undef, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> %s2 = shufflevector <16 x i8> %bc, <16 x i8> undef, <16 x i32> <i32 12, i32 undef, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
ret <16 x i8> %s2 ret <16 x i8> %s2
} }
Show All 36 Lines;
ret <2 x i4> %r ret <2 x i4> %r
} }
; negative test - but demanded elements reduces this. ; negative test - but demanded elements reduces this.
define <2 x i4> @shuf_bitcast_insert_wrong_index(<2 x i8> %v, i8 %x) { define <2 x i4> @shuf_bitcast_insert_wrong_index(<2 x i8> %v, i8 %x) {
; CHECK-LABEL: @shuf_bitcast_insert_wrong_index( ; CHECK-LABEL: @shuf_bitcast_insert_wrong_index(
; CHECK-NEXT: [[B:%.*]] = bitcast <2 x i8> [[V:%.*]] to <4 x i4> ; CHECK-NEXT: [[B:%.*]] = bitcast <2 x i8> [[V:%.*]] to <4 x i4>
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i4> [[B]], <4 x i4> undef, <2 x i32> <i32 0, i32 1> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i4> [[B]], <4 x i4> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: ret <2 x i4> [[R]] ; CHECK-NEXT: ret <2 x i4> [[R]]
; ;
%i = insertelement <2 x i8> %v, i8 %x, i32 1 %i = insertelement <2 x i8> %v, i8 %x, i32 1
%b = bitcast <2 x i8> %i to <4 x i4> %b = bitcast <2 x i8> %i to <4 x i4>
%r = shufflevector <4 x i4> %b, <4 x i4> undef, <2 x i32> <i32 0, i32 1> %r = shufflevector <4 x i4> %b, <4 x i4> undef, <2 x i32> <i32 0, i32 1>
ret <2 x i4> %r ret <2 x i4> %r
} }
; negative test ; negative test
define <3 x i4> @shuf_bitcast_wrong_size(<2 x i8> %v, i8 %x) { define <3 x i4> @shuf_bitcast_wrong_size(<2 x i8> %v, i8 %x) {
; CHECK-LABEL: @shuf_bitcast_wrong_size( ; CHECK-LABEL: @shuf_bitcast_wrong_size(
; CHECK-NEXT: [[I:%.*]] = insertelement <2 x i8> [[V:%.*]], i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[I:%.*]] = insertelement <2 x i8> [[V:%.*]], i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[B:%.*]] = bitcast <2 x i8> [[I]] to <4 x i4> ; CHECK-NEXT: [[B:%.*]] = bitcast <2 x i8> [[I]] to <4 x i4>
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i4> [[B]], <4 x i4> undef, <3 x i32> <i32 0, i32 1, i32 2> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i4> [[B]], <4 x i4> poison, <3 x i32> <i32 0, i32 1, i32 2>
; CHECK-NEXT: ret <3 x i4> [[R]] ; CHECK-NEXT: ret <3 x i4> [[R]]
; ;
%i = insertelement <2 x i8> %v, i8 %x, i32 0 %i = insertelement <2 x i8> %v, i8 %x, i32 0
%b = bitcast <2 x i8> %i to <4 x i4> %b = bitcast <2 x i8> %i to <4 x i4>
%r = shufflevector <4 x i4> %b, <4 x i4> undef, <3 x i32> <i32 0, i32 1, i32 2> %r = shufflevector <4 x i4> %b, <4 x i4> undef, <3 x i32> <i32 0, i32 1, i32 2>
ret <3 x i4> %r ret <3 x i4> %r
} }

llvm/test/Transforms/InstCombine/shufflevector-div-rem-inseltpoison.ll

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines;
%t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op %t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op
ret <2 x i16> %t2 ret <2 x i16> %t2
} }
; For fdiv we do not need to worry about div by undef. Verify that the ; For fdiv we do not need to worry about div by undef. Verify that the
; shufflevector is eliminated here. ; shufflevector is eliminated here.
define <2 x float> @test_fdiv(float %a, float %b, i1 %cmp) { define <2 x float> @test_fdiv(float %a, float %b, i1 %cmp) {
; CHECK-LABEL: @test_fdiv( ; CHECK-LABEL: @test_fdiv(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> undef, float [[A:%.*]], i64 1 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[A:%.*]], i64 1
; CHECK-NEXT: [[SPLAT_OP:%.*]] = fdiv <2 x float> [[TMP1]], <float undef, float 3.000000e+00> ; CHECK-NEXT: [[SPLAT_OP:%.*]] = fdiv <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]] ; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x float> [[T2]] ; CHECK-NEXT: ret <2 x float> [[T2]]
; ;
%splatinsert = insertelement <2 x float> poison, float %a, i32 0 %splatinsert = insertelement <2 x float> poison, float %a, i32 0
%denom = insertelement <2 x float> <float 3.0, float undef>, float 1.0, i32 1 %denom = insertelement <2 x float> <float 3.0, float undef>, float 1.0, i32 1
%t1 = fdiv <2 x float> %splatinsert, %denom %t1 = fdiv <2 x float> %splatinsert, %denom
%splat.op = shufflevector <2 x float> %t1, <2 x float> poison, <2 x i32> <i32 undef, i32 0> %splat.op = shufflevector <2 x float> %t1, <2 x float> poison, <2 x i32> <i32 undef, i32 0>
%t2 = select i1 %cmp, <2 x float> <float 77.0, float 99.0>, <2 x float> %splat.op %t2 = select i1 %cmp, <2 x float> <float 77.0, float 99.0>, <2 x float> %splat.op
ret <2 x float> %t2 ret <2 x float> %t2
} }
; For frem we do not need to worry about div by undef. Verify that the ; For frem we do not need to worry about div by undef. Verify that the
; shufflevector is eliminated here. ; shufflevector is eliminated here.
define <2 x float> @test_frem(float %a, float %b, i1 %cmp) { define <2 x float> @test_frem(float %a, float %b, i1 %cmp) {
; CHECK-LABEL: @test_frem( ; CHECK-LABEL: @test_frem(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> undef, float [[A:%.*]], i64 1 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[A:%.*]], i64 1
; CHECK-NEXT: [[SPLAT_OP:%.*]] = frem <2 x float> [[TMP1]], <float undef, float 3.000000e+00> ; CHECK-NEXT: [[SPLAT_OP:%.*]] = frem <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]] ; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x float> [[T2]] ; CHECK-NEXT: ret <2 x float> [[T2]]
; ;
%splatinsert = insertelement <2 x float> poison, float %a, i32 0 %splatinsert = insertelement <2 x float> poison, float %a, i32 0
%denom = insertelement <2 x float> <float 3.0, float undef>, float 1.0, i32 1 %denom = insertelement <2 x float> <float 3.0, float undef>, float 1.0, i32 1
%t1 = frem <2 x float> %splatinsert, %denom %t1 = frem <2 x float> %splatinsert, %denom
%splat.op = shufflevector <2 x float> %t1, <2 x float> poison, <2 x i32> <i32 undef, i32 0> %splat.op = shufflevector <2 x float> %t1, <2 x float> poison, <2 x i32> <i32 undef, i32 0>
%t2 = select i1 %cmp, <2 x float> <float 77.0, float 99.0>, <2 x float> %splat.op %t2 = select i1 %cmp, <2 x float> <float 77.0, float 99.0>, <2 x float> %splat.op
ret <2 x float> %t2 ret <2 x float> %t2
} }

llvm/test/Transforms/InstCombine/shufflevector-div-rem.ll

Show All 20 Lines
} }
; This is basically a reduced version of test_srem_orig (based on what the ; This is basically a reduced version of test_srem_orig (based on what the
; code would look like after a few iterations of instcombine, just before we ; code would look like after a few iterations of instcombine, just before we
; try to transform the shufflevector by doing ; try to transform the shufflevector by doing
; "evaluateInDifferentElementOrder". ; "evaluateInDifferentElementOrder".
define <2 x i16> @test_srem(i16 %a, i1 %cmp) { define <2 x i16> @test_srem(i16 %a, i1 %cmp) {
; CHECK-LABEL: @test_srem( ; CHECK-LABEL: @test_srem(
; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> undef, i16 [[A:%.*]], i64 0 ; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> <i16 poison, i16 undef>, i16 [[A:%.*]], i64 0
; CHECK-NEXT: [[T1:%.*]] = srem <2 x i16> [[SPLATINSERT]], <i16 2, i16 1> ; CHECK-NEXT: [[T1:%.*]] = srem <2 x i16> [[SPLATINSERT]], <i16 2, i16 1>
; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> undef, <2 x i32> <i32 poison, i32 0> ; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> poison, <2 x i32> <i32 poison, i32 0>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]] ; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x i16> [[T2]] ; CHECK-NEXT: ret <2 x i16> [[T2]]
; ;
%splatinsert = insertelement <2 x i16> undef, i16 %a, i32 0 %splatinsert = insertelement <2 x i16> undef, i16 %a, i32 0
%t1 = srem <2 x i16> %splatinsert, <i16 2, i16 1> %t1 = srem <2 x i16> %splatinsert, <i16 2, i16 1>
%splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0> %splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
%t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op %t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op
ret <2 x i16> %t2 ret <2 x i16> %t2
} }
define <2 x i16> @test_urem(i16 %a, i1 %cmp) { define <2 x i16> @test_urem(i16 %a, i1 %cmp) {
; CHECK-LABEL: @test_urem( ; CHECK-LABEL: @test_urem(
; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> undef, i16 [[A:%.*]], i64 0 ; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> <i16 poison, i16 undef>, i16 [[A:%.*]], i64 0
; CHECK-NEXT: [[T1:%.*]] = urem <2 x i16> [[SPLATINSERT]], <i16 3, i16 1> ; CHECK-NEXT: [[T1:%.*]] = urem <2 x i16> [[SPLATINSERT]], <i16 3, i16 1>
; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> undef, <2 x i32> <i32 poison, i32 0> ; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> poison, <2 x i32> <i32 poison, i32 0>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]] ; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x i16> [[T2]] ; CHECK-NEXT: ret <2 x i16> [[T2]]
; ;
%splatinsert = insertelement <2 x i16> undef, i16 %a, i32 0 %splatinsert = insertelement <2 x i16> undef, i16 %a, i32 0
%t1 = urem <2 x i16> %splatinsert, <i16 3, i16 1> %t1 = urem <2 x i16> %splatinsert, <i16 3, i16 1>
%splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0> %splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
%t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op %t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op
ret <2 x i16> %t2 ret <2 x i16> %t2
} }
define <2 x i16> @test_sdiv(i16 %a, i1 %cmp) { define <2 x i16> @test_sdiv(i16 %a, i1 %cmp) {
; CHECK-LABEL: @test_sdiv( ; CHECK-LABEL: @test_sdiv(
; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> undef, i16 [[A:%.*]], i64 0 ; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> <i16 poison, i16 undef>, i16 [[A:%.*]], i64 0
; CHECK-NEXT: [[T1:%.*]] = sdiv <2 x i16> [[SPLATINSERT]], <i16 2, i16 1> ; CHECK-NEXT: [[T1:%.*]] = sdiv <2 x i16> [[SPLATINSERT]], <i16 2, i16 1>
; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> undef, <2 x i32> <i32 poison, i32 0> ; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> poison, <2 x i32> <i32 poison, i32 0>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]] ; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x i16> [[T2]] ; CHECK-NEXT: ret <2 x i16> [[T2]]
; ;
%splatinsert = insertelement <2 x i16> undef, i16 %a, i32 0 %splatinsert = insertelement <2 x i16> undef, i16 %a, i32 0
%t1 = sdiv <2 x i16> %splatinsert, <i16 2, i16 1> %t1 = sdiv <2 x i16> %splatinsert, <i16 2, i16 1>
%splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0> %splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
%t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op %t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op
ret <2 x i16> %t2 ret <2 x i16> %t2
} }
define <2 x i16> @test_udiv(i16 %a, i1 %cmp) { define <2 x i16> @test_udiv(i16 %a, i1 %cmp) {
; CHECK-LABEL: @test_udiv( ; CHECK-LABEL: @test_udiv(
; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> undef, i16 [[A:%.*]], i64 0 ; CHECK-NEXT: [[SPLATINSERT:%.*]] = insertelement <2 x i16> <i16 poison, i16 undef>, i16 [[A:%.*]], i64 0
; CHECK-NEXT: [[T1:%.*]] = udiv <2 x i16> [[SPLATINSERT]], <i16 3, i16 1> ; CHECK-NEXT: [[T1:%.*]] = udiv <2 x i16> [[SPLATINSERT]], <i16 3, i16 1>
; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> undef, <2 x i32> <i32 poison, i32 0> ; CHECK-NEXT: [[SPLAT_OP:%.*]] = shufflevector <2 x i16> [[T1]], <2 x i16> poison, <2 x i32> <i32 poison, i32 0>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]] ; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x i16> <i16 77, i16 99>, <2 x i16> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x i16> [[T2]] ; CHECK-NEXT: ret <2 x i16> [[T2]]
; ;
%splatinsert = insertelement <2 x i16> undef, i16 %a, i32 0 %splatinsert = insertelement <2 x i16> undef, i16 %a, i32 0
%t1 = udiv <2 x i16> %splatinsert, <i16 3, i16 1> %t1 = udiv <2 x i16> %splatinsert, <i16 3, i16 1>
%splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0> %splat.op = shufflevector <2 x i16> %t1, <2 x i16> undef, <2 x i32> <i32 undef, i32 0>
%t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op %t2 = select i1 %cmp, <2 x i16> <i16 77, i16 99>, <2 x i16> %splat.op
ret <2 x i16> %t2 ret <2 x i16> %t2
} }
; For fdiv we do not need to worry about div by undef. Verify that the ; For fdiv we do not need to worry about div by undef. Verify that the
; shufflevector is eliminated here. ; shufflevector is eliminated here.
define <2 x float> @test_fdiv(float %a, float %b, i1 %cmp) { define <2 x float> @test_fdiv(float %a, float %b, i1 %cmp) {
; CHECK-LABEL: @test_fdiv( ; CHECK-LABEL: @test_fdiv(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> undef, float [[A:%.*]], i64 1 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[A:%.*]], i64 1
; CHECK-NEXT: [[SPLAT_OP:%.*]] = fdiv <2 x float> [[TMP1]], <float undef, float 3.000000e+00> ; CHECK-NEXT: [[SPLAT_OP:%.*]] = fdiv <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]] ; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x float> [[T2]] ; CHECK-NEXT: ret <2 x float> [[T2]]
; ;
%splatinsert = insertelement <2 x float> undef, float %a, i32 0 %splatinsert = insertelement <2 x float> undef, float %a, i32 0
%denom = insertelement <2 x float> <float 3.0, float undef>, float 1.0, i32 1 %denom = insertelement <2 x float> <float 3.0, float undef>, float 1.0, i32 1
%t1 = fdiv <2 x float> %splatinsert, %denom %t1 = fdiv <2 x float> %splatinsert, %denom
%splat.op = shufflevector <2 x float> %t1, <2 x float> undef, <2 x i32> <i32 undef, i32 0> %splat.op = shufflevector <2 x float> %t1, <2 x float> undef, <2 x i32> <i32 undef, i32 0>
%t2 = select i1 %cmp, <2 x float> <float 77.0, float 99.0>, <2 x float> %splat.op %t2 = select i1 %cmp, <2 x float> <float 77.0, float 99.0>, <2 x float> %splat.op
ret <2 x float> %t2 ret <2 x float> %t2
} }
; For frem we do not need to worry about div by undef. Verify that the ; For frem we do not need to worry about div by undef. Verify that the
; shufflevector is eliminated here. ; shufflevector is eliminated here.
define <2 x float> @test_frem(float %a, float %b, i1 %cmp) { define <2 x float> @test_frem(float %a, float %b, i1 %cmp) {
; CHECK-LABEL: @test_frem( ; CHECK-LABEL: @test_frem(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> undef, float [[A:%.*]], i64 1 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x float> <float undef, float poison>, float [[A:%.*]], i64 1
; CHECK-NEXT: [[SPLAT_OP:%.*]] = frem <2 x float> [[TMP1]], <float undef, float 3.000000e+00> ; CHECK-NEXT: [[SPLAT_OP:%.*]] = frem <2 x float> [[TMP1]], <float undef, float 3.000000e+00>
; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]] ; CHECK-NEXT: [[T2:%.*]] = select i1 [[CMP:%.*]], <2 x float> <float 7.700000e+01, float 9.900000e+01>, <2 x float> [[SPLAT_OP]]
; CHECK-NEXT: ret <2 x float> [[T2]] ; CHECK-NEXT: ret <2 x float> [[T2]]
; ;
%splatinsert = insertelement <2 x float> undef, float %a, i32 0 %splatinsert = insertelement <2 x float> undef, float %a, i32 0
%denom = insertelement <2 x float> <float 3.0, float undef>, float 1.0, i32 1 %denom = insertelement <2 x float> <float 3.0, float undef>, float 1.0, i32 1
%t1 = frem <2 x float> %splatinsert, %denom %t1 = frem <2 x float> %splatinsert, %denom
%splat.op = shufflevector <2 x float> %t1, <2 x float> undef, <2 x i32> <i32 undef, i32 0> %splat.op = shufflevector <2 x float> %t1, <2 x float> undef, <2 x i32> <i32 undef, i32 0>
%t2 = select i1 %cmp, <2 x float> <float 77.0, float 99.0>, <2 x float> %splat.op %t2 = select i1 %cmp, <2 x float> <float 77.0, float 99.0>, <2 x float> %splat.op
ret <2 x float> %t2 ret <2 x float> %t2
} }

llvm/test/Transforms/InstCombine/sub-of-negatible.ll

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%t0 = zext i2 %y to i8 %t0 = zext i2 %y to i8
%t1 = sub i8 %x, %t0 %t1 = sub i8 %x, %t0
ret i8 %t1 ret i8 %t1
} }
define <2 x i4> @negate_shufflevector_oneinput_reverse(<2 x i4> %x, <2 x i4> %y) { define <2 x i4> @negate_shufflevector_oneinput_reverse(<2 x i4> %x, <2 x i4> %y) {
; CHECK-LABEL: @negate_shufflevector_oneinput_reverse( ; CHECK-LABEL: @negate_shufflevector_oneinput_reverse(
; CHECK-NEXT: [[T0_NEG:%.*]] = shl <2 x i4> <i4 6, i4 -5>, [[X:%.*]] ; CHECK-NEXT: [[T0_NEG:%.*]] = shl <2 x i4> <i4 6, i4 -5>, [[X:%.*]]
; CHECK-NEXT: [[T1_NEG:%.*]] = shufflevector <2 x i4> [[T0_NEG]], <2 x i4> undef, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[T1_NEG:%.*]] = shufflevector <2 x i4> [[T0_NEG]], <2 x i4> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[T2:%.*]] = add <2 x i4> [[T1_NEG]], [[Y:%.*]] ; CHECK-NEXT: [[T2:%.*]] = add <2 x i4> [[T1_NEG]], [[Y:%.*]]
; CHECK-NEXT: ret <2 x i4> [[T2]] ; CHECK-NEXT: ret <2 x i4> [[T2]]
; ;
%t0 = shl <2 x i4> <i4 -6, i4 5>, %x %t0 = shl <2 x i4> <i4 -6, i4 5>, %x
%t1 = shufflevector <2 x i4> %t0, <2 x i4> undef, <2 x i32> <i32 1, i32 0> %t1 = shufflevector <2 x i4> %t0, <2 x i4> undef, <2 x i32> <i32 1, i32 0>
%t2 = sub <2 x i4> %y, %t1 %t2 = sub <2 x i4> %y, %t1
ret <2 x i4> %t2 ret <2 x i4> %t2
} }
define <2 x i4> @negate_shufflevector_oneinput_second_lane_is_undef(<2 x i4> %x, <2 x i4> %y) { define <2 x i4> @negate_shufflevector_oneinput_second_lane_is_undef(<2 x i4> %x, <2 x i4> %y) {
; CHECK-LABEL: @negate_shufflevector_oneinput_second_lane_is_undef( ; CHECK-LABEL: @negate_shufflevector_oneinput_second_lane_is_undef(
; CHECK-NEXT: [[T0_NEG:%.*]] = shl <2 x i4> <i4 6, i4 -5>, [[X:%.*]] ; CHECK-NEXT: [[T0_NEG:%.*]] = shl <2 x i4> <i4 6, i4 -5>, [[X:%.*]]
; CHECK-NEXT: [[T1_NEG:%.*]] = shufflevector <2 x i4> [[T0_NEG]], <2 x i4> undef, <2 x i32> <i32 0, i32 poison> ; CHECK-NEXT: [[T1_NEG:%.*]] = insertelement <2 x i4> [[T0_NEG]], i4 undef, i64 1
; CHECK-NEXT: [[T2:%.*]] = add <2 x i4> [[T1_NEG]], [[Y:%.*]] ; CHECK-NEXT: [[T2:%.*]] = add <2 x i4> [[T1_NEG]], [[Y:%.*]]
; CHECK-NEXT: ret <2 x i4> [[T2]] ; CHECK-NEXT: ret <2 x i4> [[T2]]
; ;
%t0 = shl <2 x i4> <i4 -6, i4 5>, %x %t0 = shl <2 x i4> <i4 -6, i4 5>, %x
%t1 = shufflevector <2 x i4> %t0, <2 x i4> undef, <2 x i32> <i32 0, i32 2> %t1 = shufflevector <2 x i4> %t0, <2 x i4> undef, <2 x i32> <i32 0, i32 2>
%t2 = sub <2 x i4> %y, %t1 %t2 = sub <2 x i4> %y, %t1
ret <2 x i4> %t2 ret <2 x i4> %t2
} }
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%t1 = xor <2 x i4> %y, <i4 -1, i4 -1> %t1 = xor <2 x i4> %y, <i4 -1, i4 -1>
%t2 = shufflevector <2 x i4> %t0, <2 x i4> %t1, <2 x i32> <i32 0, i32 3> %t2 = shufflevector <2 x i4> %t0, <2 x i4> %t1, <2 x i32> <i32 0, i32 3>
%t3 = sub <2 x i4> %z, %t2 %t3 = sub <2 x i4> %z, %t2
ret <2 x i4> %t3 ret <2 x i4> %t3
} }
define <2 x i4> @negate_shufflevector_oneinput_extrause(<2 x i4> %x, <2 x i4> %y) { define <2 x i4> @negate_shufflevector_oneinput_extrause(<2 x i4> %x, <2 x i4> %y) {
; CHECK-LABEL: @negate_shufflevector_oneinput_extrause( ; CHECK-LABEL: @negate_shufflevector_oneinput_extrause(
; CHECK-NEXT: [[T0:%.*]] = shl <2 x i4> <i4 -6, i4 5>, [[X:%.*]] ; CHECK-NEXT: [[T0:%.*]] = shl <2 x i4> <i4 -6, i4 5>, [[X:%.*]]
; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x i4> [[T0]], <2 x i4> undef, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x i4> [[T0]], <2 x i4> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: call void @use_v2i4(<2 x i4> [[T1]]) ; CHECK-NEXT: call void @use_v2i4(<2 x i4> [[T1]])
; CHECK-NEXT: [[T2:%.*]] = sub <2 x i4> [[Y:%.*]], [[T1]] ; CHECK-NEXT: [[T2:%.*]] = sub <2 x i4> [[Y:%.*]], [[T1]]
; CHECK-NEXT: ret <2 x i4> [[T2]] ; CHECK-NEXT: ret <2 x i4> [[T2]]
; ;
%t0 = shl <2 x i4> <i4 -6, i4 5>, %x %t0 = shl <2 x i4> <i4 -6, i4 5>, %x
%t1 = shufflevector <2 x i4> %t0, <2 x i4> undef, <2 x i32> <i32 1, i32 0> %t1 = shufflevector <2 x i4> %t0, <2 x i4> undef, <2 x i32> <i32 1, i32 0>
call void @use_v2i4(<2 x i4> %t1) call void @use_v2i4(<2 x i4> %t1)
%t2 = sub <2 x i4> %y, %t1 %t2 = sub <2 x i4> %y, %t1
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llvm/test/Transforms/InstCombine/trunc-extractelement-inseltpoison.ll

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; LE-LABEL: @PR45314( ; LE-LABEL: @PR45314(
; LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i64> [[X:%.*]] to <8 x i32> ; LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i64> [[X:%.*]] to <8 x i32>
; LE-NEXT: [[S:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer ; LE-NEXT: [[S:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> zeroinitializer
; LE-NEXT: [[B:%.*]] = bitcast <8 x i32> [[S]] to <4 x i64> ; LE-NEXT: [[B:%.*]] = bitcast <8 x i32> [[S]] to <4 x i64>
; LE-NEXT: ret <4 x i64> [[B]] ; LE-NEXT: ret <4 x i64> [[B]]
; ;
; BE-LABEL: @PR45314( ; BE-LABEL: @PR45314(
; BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i64> [[X:%.*]] to <8 x i32> ; BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i64> [[X:%.*]] to <8 x i32>
; BE-NEXT: [[S:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> ; BE-NEXT: [[S:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; BE-NEXT: [[B:%.*]] = bitcast <8 x i32> [[S]] to <4 x i64> ; BE-NEXT: [[B:%.*]] = bitcast <8 x i32> [[S]] to <4 x i64>
; BE-NEXT: ret <4 x i64> [[B]] ; BE-NEXT: ret <4 x i64> [[B]]
; ;
%e = extractelement <4 x i64> %x, i32 0 %e = extractelement <4 x i64> %x, i32 0
%t = trunc i64 %e to i32 %t = trunc i64 %e to i32
%i = insertelement <8 x i32> poison, i32 %t, i32 0 %i = insertelement <8 x i32> poison, i32 %t, i32 0
%s = shufflevector <8 x i32> %i, <8 x i32> poison, <8 x i32> zeroinitializer %s = shufflevector <8 x i32> %i, <8 x i32> poison, <8 x i32> zeroinitializer
%b = bitcast <8 x i32> %s to <4 x i64> %b = bitcast <8 x i32> %s to <4 x i64>
ret <4 x i64> %b ret <4 x i64> %b
} }

llvm/test/Transforms/InstCombine/trunc-extractelement.ll

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; LE-LABEL: @PR45314( ; LE-LABEL: @PR45314(
; LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i64> [[X:%.*]] to <8 x i32> ; LE-NEXT: [[TMP1:%.*]] = bitcast <4 x i64> [[X:%.*]] to <8 x i32>
; LE-NEXT: [[S:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> zeroinitializer ; LE-NEXT: [[S:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> zeroinitializer
; LE-NEXT: [[B:%.*]] = bitcast <8 x i32> [[S]] to <4 x i64> ; LE-NEXT: [[B:%.*]] = bitcast <8 x i32> [[S]] to <4 x i64>
; LE-NEXT: ret <4 x i64> [[B]] ; LE-NEXT: ret <4 x i64> [[B]]
; ;
; BE-LABEL: @PR45314( ; BE-LABEL: @PR45314(
; BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i64> [[X:%.*]] to <8 x i32> ; BE-NEXT: [[TMP1:%.*]] = bitcast <4 x i64> [[X:%.*]] to <8 x i32>
; BE-NEXT: [[S:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> ; BE-NEXT: [[S:%.*]] = shufflevector <8 x i32> [[TMP1]], <8 x i32> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
; BE-NEXT: [[B:%.*]] = bitcast <8 x i32> [[S]] to <4 x i64> ; BE-NEXT: [[B:%.*]] = bitcast <8 x i32> [[S]] to <4 x i64>
; BE-NEXT: ret <4 x i64> [[B]] ; BE-NEXT: ret <4 x i64> [[B]]
; ;
%e = extractelement <4 x i64> %x, i32 0 %e = extractelement <4 x i64> %x, i32 0
%t = trunc i64 %e to i32 %t = trunc i64 %e to i32
%i = insertelement <8 x i32> undef, i32 %t, i32 0 %i = insertelement <8 x i32> undef, i32 %t, i32 0
%s = shufflevector <8 x i32> %i, <8 x i32> undef, <8 x i32> zeroinitializer %s = shufflevector <8 x i32> %i, <8 x i32> undef, <8 x i32> zeroinitializer
%b = bitcast <8 x i32> %s to <4 x i64> %b = bitcast <8 x i32> %s to <4 x i64>
ret <4 x i64> %b ret <4 x i64> %b
} }

llvm/test/Transforms/InstCombine/trunc.ll

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} }
; FIXME: ; FIXME:
; trunc (shuffle X, undef, SplatMask) --> shuffle (trunc X), undef, SplatMask ; trunc (shuffle X, undef, SplatMask) --> shuffle (trunc X), undef, SplatMask
; A mask with undef elements should still be considered a splat mask. ; A mask with undef elements should still be considered a splat mask.
define <3 x i31> @wide_splat3(<3 x i33> %x) { define <3 x i31> @wide_splat3(<3 x i33> %x) {
; CHECK-LABEL: @wide_splat3( ; CHECK-LABEL: @wide_splat3(
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x i33> [[X:%.*]], <3 x i33> undef, <3 x i32> <i32 poison, i32 1, i32 1> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <3 x i33> [[X:%.*]], <3 x i33> poison, <3 x i32> <i32 poison, i32 1, i32 1>
; CHECK-NEXT: [[TRUNC:%.*]] = trunc <3 x i33> [[SHUF]] to <3 x i31> ; CHECK-NEXT: [[TRUNC:%.*]] = trunc <3 x i33> [[SHUF]] to <3 x i31>
; CHECK-NEXT: ret <3 x i31> [[TRUNC]] ; CHECK-NEXT: ret <3 x i31> [[TRUNC]]
; ;
%shuf = shufflevector <3 x i33> %x, <3 x i33> undef, <3 x i32> <i32 undef, i32 1, i32 1> %shuf = shufflevector <3 x i33> %x, <3 x i33> undef, <3 x i32> <i32 undef, i32 1, i32 1>
%trunc = trunc <3 x i33> %shuf to <3 x i31> %trunc = trunc <3 x i33> %shuf to <3 x i31>
ret <3 x i31> %trunc ret <3 x i31> %trunc
} }
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llvm/test/Transforms/InstCombine/type_pun.ll

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%i = phi i32 [ %lhs, %left ], [ %rhs, %right ] %i = phi i32 [ %lhs, %left ], [ %rhs, %right ]
ret i32 %i ret i32 %i
} }
; Extracting a type that won't fit in a vector isn't handled. The function ; Extracting a type that won't fit in a vector isn't handled. The function
; should stay the same. ; should stay the same.
define i40 @type_pun_unhandled(<16 x i8> %in) { define i40 @type_pun_unhandled(<16 x i8> %in) {
; CHECK-LABEL: @type_pun_unhandled( ; CHECK-LABEL: @type_pun_unhandled(
; CHECK-NEXT: [[SROA:%.*]] = shufflevector <16 x i8> [[IN:%.*]], <16 x i8> undef, <5 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8> ; CHECK-NEXT: [[SROA:%.*]] = shufflevector <16 x i8> [[IN:%.*]], <16 x i8> poison, <5 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8>
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <5 x i8> [[SROA]] to i40 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <5 x i8> [[SROA]] to i40
; CHECK-NEXT: ret i40 [[TMP1]] ; CHECK-NEXT: ret i40 [[TMP1]]
; ;
%sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <5 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8> %sroa = shufflevector <16 x i8> %in, <16 x i8> undef, <5 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8>
%1 = bitcast <5 x i8> %sroa to i40 %1 = bitcast <5 x i8> %sroa to i40
ret i40 %1 ret i40 %1
} }

llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll

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%result = select <2 x i1> <i1 icmp eq (i64 extractelement (<2 x i64> bitcast (<4 x i32> <i32 15, i32 15, i32 15, i32 15> to <2 x i64>), i64 0), i64 0), i1 true>, <2 x i64> %v, <2 x i64> zeroinitializer %result = select <2 x i1> <i1 icmp eq (i64 extractelement (<2 x i64> bitcast (<4 x i32> <i32 15, i32 15, i32 15, i32 15> to <2 x i64>), i64 0), i64 0), i1 true>, <2 x i64> %v, <2 x i64> zeroinitializer
ret <2 x i64> %result ret <2 x i64> %result
} }
; The shuffle only demands the 0th (undef) element of 'out123', so everything should fold away. ; The shuffle only demands the 0th (undef) element of 'out123', so everything should fold away.
define <4 x float> @inselt_shuf_no_demand(float %a1, float %a2, float %a3) { define <4 x float> @inselt_shuf_no_demand(float %a1, float %a2, float %a3) {
; CHECK-LABEL: @inselt_shuf_no_demand( ; CHECK-LABEL: @inselt_shuf_no_demand(
; CHECK-NEXT: ret <4 x float> undef ; CHECK-NEXT: ret <4 x float> poison
; ;
%out1 = insertelement <4 x float> poison, float %a1, i32 1 %out1 = insertelement <4 x float> poison, float %a1, i32 1
%out12 = insertelement <4 x float> %out1, float %a2, i32 2 %out12 = insertelement <4 x float> %out1, float %a2, i32 2
%out123 = insertelement <4 x float> %out12, float %a3, i32 3 %out123 = insertelement <4 x float> %out12, float %a3, i32 3
%shuffle = shufflevector <4 x float> %out123, <4 x float> poison, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %shuffle = shufflevector <4 x float> %out123, <4 x float> poison, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
; The shuffle only demands the 0th (undef) element of 'out123', so everything should fold away. ; The shuffle only demands the 0th (undef) element of 'out123', so everything should fold away.
define <4 x float> @inselt_shuf_no_demand_commute(float %a1, float %a2, float %a3) { define <4 x float> @inselt_shuf_no_demand_commute(float %a1, float %a2, float %a3) {
; CHECK-LABEL: @inselt_shuf_no_demand_commute( ; CHECK-LABEL: @inselt_shuf_no_demand_commute(
; CHECK-NEXT: ret <4 x float> undef ; CHECK-NEXT: ret <4 x float> poison
; ;
%out1 = insertelement <4 x float> poison, float %a1, i32 1 %out1 = insertelement <4 x float> poison, float %a1, i32 1
%out12 = insertelement <4 x float> %out1, float %a2, i32 2 %out12 = insertelement <4 x float> %out1, float %a2, i32 2
%out123 = insertelement <4 x float> %out12, float %a3, i32 3 %out123 = insertelement <4 x float> %out12, float %a3, i32 3
%shuffle = shufflevector <4 x float> undef, <4 x float> %out123, <4 x i32> <i32 4, i32 undef, i32 undef, i32 undef> %shuffle = shufflevector <4 x float> undef, <4 x float> %out123, <4 x i32> <i32 4, i32 undef, i32 undef, i32 undef>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
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%idxvec2 = shufflevector <2 x i64> %idxvec1, <2 x i64> poison, <2 x i32> zeroinitializer %idxvec2 = shufflevector <2 x i64> %idxvec1, <2 x i64> poison, <2 x i32> zeroinitializer
%gep = getelementptr i32, <2 x ptr> %basevec2, <2 x i64> %idxvec2 %gep = getelementptr i32, <2 x ptr> %basevec2, <2 x i64> %idxvec2
%ee = extractelement <2 x ptr> %gep, i32 1 %ee = extractelement <2 x ptr> %gep, i32 1
ret ptr %ee ret ptr %ee
} }
define <2 x ptr> @gep_all_lanes_undef(ptr %base, i64 %idx) {; define <2 x ptr> @gep_all_lanes_undef(ptr %base, i64 %idx) {;
; CHECK-LABEL: @gep_all_lanes_undef( ; CHECK-LABEL: @gep_all_lanes_undef(
; CHECK-NEXT: [[BASEVEC:%.*]] = insertelement <2 x ptr> poison, ptr [[BASE:%.*]], i64 0 ; CHECK-NEXT: ret <2 x ptr> poison
; CHECK-NEXT: [[IDXVEC:%.*]] = insertelement <2 x i64> poison, i64 [[IDX:%.*]], i64 1
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, <2 x ptr> [[BASEVEC]], <2 x i64> [[IDXVEC]]
; CHECK-NEXT: ret <2 x ptr> [[GEP]]
; ;
%basevec = insertelement <2 x ptr> poison, ptr %base, i32 0 %basevec = insertelement <2 x ptr> poison, ptr %base, i32 0
%idxvec = insertelement <2 x i64> poison, i64 %idx, i32 1 %idxvec = insertelement <2 x i64> poison, i64 %idx, i32 1
%gep = getelementptr i32, <2 x ptr> %basevec, <2 x i64> %idxvec %gep = getelementptr i32, <2 x ptr> %basevec, <2 x i64> %idxvec
ret <2 x ptr> %gep ret <2 x ptr> %gep
} }
define ptr @gep_demanded_lane_undef(ptr %base, i64 %idx) { define ptr @gep_demanded_lane_undef(ptr %base, i64 %idx) {
; CHECK-LABEL: @gep_demanded_lane_undef( ; CHECK-LABEL: @gep_demanded_lane_undef(
; CHECK-NEXT: ret ptr undef ; CHECK-NEXT: ret ptr poison
; ;
%basevec = insertelement <2 x ptr> poison, ptr %base, i32 0 %basevec = insertelement <2 x ptr> poison, ptr %base, i32 0
%idxvec = insertelement <2 x i64> poison, i64 %idx, i32 1 %idxvec = insertelement <2 x i64> poison, i64 %idx, i32 1
%gep = getelementptr i32, <2 x ptr> %basevec, <2 x i64> %idxvec %gep = getelementptr i32, <2 x ptr> %basevec, <2 x i64> %idxvec
%ee = extractelement <2 x ptr> %gep, i32 1 %ee = extractelement <2 x ptr> %gep, i32 1
ret ptr %ee ret ptr %ee
} }
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llvm/test/Transforms/InstCombine/vec_demanded_elts.ll

Show First 20 Lines • Show All 142 Lines • ▼ Show 20 Lines;
%result = select <2 x i1> <i1 icmp eq (i64 extractelement (<2 x i64> bitcast (<4 x i32> <i32 15, i32 15, i32 15, i32 15> to <2 x i64>), i64 0), i64 0), i1 true>, <2 x i64> %v, <2 x i64> zeroinitializer %result = select <2 x i1> <i1 icmp eq (i64 extractelement (<2 x i64> bitcast (<4 x i32> <i32 15, i32 15, i32 15, i32 15> to <2 x i64>), i64 0), i64 0), i1 true>, <2 x i64> %v, <2 x i64> zeroinitializer
ret <2 x i64> %result ret <2 x i64> %result
} }
; The shuffle only demands the 0th (undef) element of 'out123', so everything should fold away. ; The shuffle only demands the 0th (undef) element of 'out123', so everything should fold away.
define <4 x float> @inselt_shuf_no_demand(float %a1, float %a2, float %a3) { define <4 x float> @inselt_shuf_no_demand(float %a1, float %a2, float %a3) {
; CHECK-LABEL: @inselt_shuf_no_demand( ; CHECK-LABEL: @inselt_shuf_no_demand(
; CHECK-NEXT: ret <4 x float> undef ; CHECK-NEXT: ret <4 x float> <float undef, float poison, float poison, float poison>
; ;
%out1 = insertelement <4 x float> undef, float %a1, i32 1 %out1 = insertelement <4 x float> undef, float %a1, i32 1
%out12 = insertelement <4 x float> %out1, float %a2, i32 2 %out12 = insertelement <4 x float> %out1, float %a2, i32 2
%out123 = insertelement <4 x float> %out12, float %a3, i32 3 %out123 = insertelement <4 x float> %out12, float %a3, i32 3
%shuffle = shufflevector <4 x float> %out123, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %shuffle = shufflevector <4 x float> %out123, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
; The shuffle only demands the 0th (undef) element of 'out123', so everything should fold away. ; The shuffle only demands the 0th (undef) element of 'out123', so everything should fold away.
define <4 x float> @inselt_shuf_no_demand_commute(float %a1, float %a2, float %a3) { define <4 x float> @inselt_shuf_no_demand_commute(float %a1, float %a2, float %a3) {
; CHECK-LABEL: @inselt_shuf_no_demand_commute( ; CHECK-LABEL: @inselt_shuf_no_demand_commute(
; CHECK-NEXT: ret <4 x float> undef ; CHECK-NEXT: ret <4 x float> <float undef, float poison, float poison, float poison>
; ;
%out1 = insertelement <4 x float> undef, float %a1, i32 1 %out1 = insertelement <4 x float> undef, float %a1, i32 1
%out12 = insertelement <4 x float> %out1, float %a2, i32 2 %out12 = insertelement <4 x float> %out1, float %a2, i32 2
%out123 = insertelement <4 x float> %out12, float %a3, i32 3 %out123 = insertelement <4 x float> %out12, float %a3, i32 3
%shuffle = shufflevector <4 x float> undef, <4 x float> %out123, <4 x i32> <i32 4, i32 undef, i32 undef, i32 undef> %shuffle = shufflevector <4 x float> undef, <4 x float> %out123, <4 x i32> <i32 4, i32 undef, i32 undef, i32 undef>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
; The add uses 'out012' giving it multiple uses after the shuffle is transformed to also ; The add uses 'out012' giving it multiple uses after the shuffle is transformed to also
; use 'out012'. The analysis should be able to see past that. ; use 'out012'. The analysis should be able to see past that.
define <4 x i32> @inselt_shuf_no_demand_multiuse(i32 %a0, i32 %a1, <4 x i32> %b) { define <4 x i32> @inselt_shuf_no_demand_multiuse(i32 %a0, i32 %a1, <4 x i32> %b) {
; CHECK-LABEL: @inselt_shuf_no_demand_multiuse( ; CHECK-LABEL: @inselt_shuf_no_demand_multiuse(
; CHECK-NEXT: [[OUT0:%.*]] = insertelement <4 x i32> undef, i32 [[A0:%.*]], i64 0 ; CHECK-NEXT: [[OUT0:%.*]] = insertelement <4 x i32> poison, i32 [[A0:%.*]], i64 0
; CHECK-NEXT: [[OUT01:%.*]] = insertelement <4 x i32> [[OUT0]], i32 [[A1:%.*]], i64 1 ; CHECK-NEXT: [[OUT01:%.*]] = insertelement <4 x i32> [[OUT0]], i32 [[A1:%.*]], i64 1
; CHECK-NEXT: [[FOO:%.*]] = add <4 x i32> [[OUT01]], [[B:%.*]] ; CHECK-NEXT: [[FOO:%.*]] = add <4 x i32> [[OUT01]], [[B:%.*]]
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[FOO]], <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[FOO]], <4 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x i32> [[SHUFFLE]] ; CHECK-NEXT: ret <4 x i32> [[SHUFFLE]]
; ;
%out0 = insertelement <4 x i32> undef, i32 %a0, i32 0 %out0 = insertelement <4 x i32> undef, i32 %a0, i32 0
%out01 = insertelement <4 x i32> %out0, i32 %a1, i32 1 %out01 = insertelement <4 x i32> %out0, i32 %a1, i32 1
%out012 = insertelement <4 x i32> %out01, i32 %a0, i32 2 %out012 = insertelement <4 x i32> %out01, i32 %a0, i32 2
%foo = add <4 x i32> %out012, %b %foo = add <4 x i32> %out012, %b
%out0123 = insertelement <4 x i32> %foo, i32 %a1, i32 3 %out0123 = insertelement <4 x i32> %foo, i32 %a1, i32 3
%shuffle = shufflevector <4 x i32> %out0123, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %shuffle = shufflevector <4 x i32> %out0123, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x i32> %shuffle ret <4 x i32> %shuffle
} }
define <4 x float> @inselt_shuf_no_demand_bogus_insert_index_in_chain(float %a1, float %a2, float %a3, i32 %variable_index) { define <4 x float> @inselt_shuf_no_demand_bogus_insert_index_in_chain(float %a1, float %a2, float %a3, i32 %variable_index) {
; CHECK-LABEL: @inselt_shuf_no_demand_bogus_insert_index_in_chain( ; CHECK-LABEL: @inselt_shuf_no_demand_bogus_insert_index_in_chain(
; CHECK-NEXT: [[OUT12:%.*]] = insertelement <4 x float> undef, float [[A2:%.*]], i32 [[VARIABLE_INDEX:%.*]] ; CHECK-NEXT: [[OUT12:%.*]] = insertelement <4 x float> <float undef, float poison, float poison, float poison>, float [[A2:%.*]], i32 [[VARIABLE_INDEX:%.*]]
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x float> [[OUT12]], <4 x float> undef, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x float> [[OUT12]], <4 x float> poison, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x float> [[SHUFFLE]] ; CHECK-NEXT: ret <4 x float> [[SHUFFLE]]
; ;
%out1 = insertelement <4 x float> undef, float %a1, i32 1 %out1 = insertelement <4 x float> undef, float %a1, i32 1
%out12 = insertelement <4 x float> %out1, float %a2, i32 %variable_index ; something unexpected %out12 = insertelement <4 x float> %out1, float %a2, i32 %variable_index ; something unexpected
%out123 = insertelement <4 x float> %out12, float %a3, i32 3 %out123 = insertelement <4 x float> %out12, float %a3, i32 3
%shuffle = shufflevector <4 x float> %out123, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %shuffle = shufflevector <4 x float> %out123, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
ret <4 x float> %shuffle ret <4 x float> %shuffle
} }
; Test undef replacement in constant vector elements with binops. ; Test undef replacement in constant vector elements with binops.
define <3 x i8> @shuf_add(<3 x i8> %x) { define <3 x i8> @shuf_add(<3 x i8> %x) {
; CHECK-LABEL: @shuf_add( ; CHECK-LABEL: @shuf_add(
; CHECK-NEXT: [[BO:%.*]] = add nsw <3 x i8> [[X:%.*]], <i8 poison, i8 2, i8 3> ; CHECK-NEXT: [[BO:%.*]] = add nsw <3 x i8> [[X:%.*]], <i8 poison, i8 2, i8 3>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 poison, i32 2> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 1, i32 poison, i32 2>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = add nsw <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = add nsw <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 2> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 2>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_sub(<3 x i8> %x) { define <3 x i8> @shuf_sub(<3 x i8> %x) {
; CHECK-LABEL: @shuf_sub( ; CHECK-LABEL: @shuf_sub(
; CHECK-NEXT: [[BO:%.*]] = sub nuw <3 x i8> <i8 1, i8 poison, i8 3>, [[X:%.*]] ; CHECK-NEXT: [[BO:%.*]] = sub nuw <3 x i8> <i8 1, i8 poison, i8 3>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 poison, i32 2> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 0, i32 poison, i32 2>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = sub nuw <3 x i8> <i8 1, i8 2, i8 3>, %x %bo = sub nuw <3 x i8> <i8 1, i8 2, i8 3>, %x
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 poison, i32 2> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 poison, i32 2>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_mul(<3 x i8> %x) { define <3 x i8> @shuf_mul(<3 x i8> %x) {
; CHECK-LABEL: @shuf_mul( ; CHECK-LABEL: @shuf_mul(
; CHECK-NEXT: [[BO:%.*]] = mul nsw <3 x i8> [[X:%.*]], <i8 1, i8 poison, i8 3> ; CHECK-NEXT: [[BO:%.*]] = mul nsw <3 x i8> [[X:%.*]], <i8 1, i8 poison, i8 3>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 2, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 0, i32 2, i32 0>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = mul nsw <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = mul nsw <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 2, i32 0> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 2, i32 0>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_and(<3 x i8> %x) { define <3 x i8> @shuf_and(<3 x i8> %x) {
; CHECK-LABEL: @shuf_and( ; CHECK-LABEL: @shuf_and(
; CHECK-NEXT: [[BO:%.*]] = and <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 poison> ; CHECK-NEXT: [[BO:%.*]] = and <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 poison>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 1, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 1, i32 1, i32 0>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = and <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = and <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 1, i32 0> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 1, i32 0>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_or(<3 x i8> %x) { define <3 x i8> @shuf_or(<3 x i8> %x) {
; CHECK-LABEL: @shuf_or( ; CHECK-LABEL: @shuf_or(
; CHECK-NEXT: [[BO:%.*]] = or <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 poison> ; CHECK-NEXT: [[BO:%.*]] = or <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 poison>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 poison, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 1, i32 poison, i32 0>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = or <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = or <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 0> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 0>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_xor(<3 x i8> %x) { define <3 x i8> @shuf_xor(<3 x i8> %x) {
; CHECK-LABEL: @shuf_xor( ; CHECK-LABEL: @shuf_xor(
; CHECK-NEXT: [[BO:%.*]] = xor <3 x i8> [[X:%.*]], <i8 1, i8 poison, i8 3> ; CHECK-NEXT: [[BO:%.*]] = xor <3 x i8> [[X:%.*]], <i8 1, i8 poison, i8 3>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 poison, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 2, i32 poison, i32 0>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = xor <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = xor <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_lshr_const_op0(<3 x i8> %x) { define <3 x i8> @shuf_lshr_const_op0(<3 x i8> %x) {
; CHECK-LABEL: @shuf_lshr_const_op0( ; CHECK-LABEL: @shuf_lshr_const_op0(
; CHECK-NEXT: [[BO:%.*]] = lshr <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]] ; CHECK-NEXT: [[BO:%.*]] = lshr <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 poison> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 2, i32 1, i32 poison>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = lshr <3 x i8> <i8 1, i8 2, i8 3>, %x %bo = lshr <3 x i8> <i8 1, i8 2, i8 3>, %x
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_lshr_const_op1(<3 x i8> %x) { define <3 x i8> @shuf_lshr_const_op1(<3 x i8> %x) {
; CHECK-LABEL: @shuf_lshr_const_op1( ; CHECK-LABEL: @shuf_lshr_const_op1(
; CHECK-NEXT: [[BO:%.*]] = lshr exact <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3> ; CHECK-NEXT: [[BO:%.*]] = lshr exact <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 poison> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 2, i32 1, i32 poison>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = lshr exact <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = lshr exact <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_ashr_const_op0(<3 x i8> %x) { define <3 x i8> @shuf_ashr_const_op0(<3 x i8> %x) {
; CHECK-LABEL: @shuf_ashr_const_op0( ; CHECK-LABEL: @shuf_ashr_const_op0(
; CHECK-NEXT: [[BO:%.*]] = lshr <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]] ; CHECK-NEXT: [[BO:%.*]] = lshr <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 poison, i32 1> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 0, i32 poison, i32 1>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = ashr <3 x i8> <i8 1, i8 2, i8 3>, %x %bo = ashr <3 x i8> <i8 1, i8 2, i8 3>, %x
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_ashr_const_op1(<3 x i8> %x) { define <3 x i8> @shuf_ashr_const_op1(<3 x i8> %x) {
; CHECK-LABEL: @shuf_ashr_const_op1( ; CHECK-LABEL: @shuf_ashr_const_op1(
; CHECK-NEXT: [[BO:%.*]] = ashr exact <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3> ; CHECK-NEXT: [[BO:%.*]] = ashr exact <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 poison, i32 1> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 0, i32 poison, i32 1>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = ashr exact <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = ashr exact <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_shl_const_op0(<3 x i8> %x) { define <3 x i8> @shuf_shl_const_op0(<3 x i8> %x) {
; CHECK-LABEL: @shuf_shl_const_op0( ; CHECK-LABEL: @shuf_shl_const_op0(
; CHECK-NEXT: [[BO:%.*]] = shl nsw <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]] ; CHECK-NEXT: [[BO:%.*]] = shl nsw <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 poison, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 2, i32 poison, i32 0>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = shl nsw <3 x i8> <i8 1, i8 2, i8 3>, %x %bo = shl nsw <3 x i8> <i8 1, i8 2, i8 3>, %x
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_shl_const_op1(<3 x i8> %x) { define <3 x i8> @shuf_shl_const_op1(<3 x i8> %x) {
; CHECK-LABEL: @shuf_shl_const_op1( ; CHECK-LABEL: @shuf_shl_const_op1(
; CHECK-NEXT: [[BO:%.*]] = shl nuw <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3> ; CHECK-NEXT: [[BO:%.*]] = shl nuw <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 poison, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 2, i32 poison, i32 0>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = shl nuw <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = shl nuw <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_sdiv_const_op0(<3 x i8> %x) { define <3 x i8> @shuf_sdiv_const_op0(<3 x i8> %x) {
; CHECK-LABEL: @shuf_sdiv_const_op0( ; CHECK-LABEL: @shuf_sdiv_const_op0(
; CHECK-NEXT: [[BO:%.*]] = sdiv exact <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]] ; CHECK-NEXT: [[BO:%.*]] = sdiv exact <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 0, i32 poison, i32 1> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 0, i32 poison, i32 1>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = sdiv exact <3 x i8> <i8 1, i8 2, i8 3>, %x %bo = sdiv exact <3 x i8> <i8 1, i8 2, i8 3>, %x
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 0, i32 undef, i32 1>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_sdiv_const_op1(<3 x i8> %x) { define <3 x i8> @shuf_sdiv_const_op1(<3 x i8> %x) {
; CHECK-LABEL: @shuf_sdiv_const_op1( ; CHECK-LABEL: @shuf_sdiv_const_op1(
; CHECK-NEXT: [[BO:%.*]] = sdiv <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3> ; CHECK-NEXT: [[BO:%.*]] = sdiv <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 poison, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 1, i32 poison, i32 0>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = sdiv <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = sdiv <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 0> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 0>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_srem_const_op0(<3 x i8> %x) { define <3 x i8> @shuf_srem_const_op0(<3 x i8> %x) {
; CHECK-LABEL: @shuf_srem_const_op0( ; CHECK-LABEL: @shuf_srem_const_op0(
; CHECK-NEXT: [[BO:%.*]] = srem <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]] ; CHECK-NEXT: [[BO:%.*]] = srem <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 1, i32 poison, i32 2> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 1, i32 poison, i32 2>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = srem <3 x i8> <i8 1, i8 2, i8 3>, %x %bo = srem <3 x i8> <i8 1, i8 2, i8 3>, %x
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 2> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 1, i32 undef, i32 2>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_srem_const_op1(<3 x i8> %x) { define <3 x i8> @shuf_srem_const_op1(<3 x i8> %x) {
; CHECK-LABEL: @shuf_srem_const_op1( ; CHECK-LABEL: @shuf_srem_const_op1(
; CHECK-NEXT: [[BO:%.*]] = srem <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3> ; CHECK-NEXT: [[BO:%.*]] = srem <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 poison, i32 1> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 2, i32 poison, i32 1>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = srem <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = srem <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 1> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 1>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_udiv_const_op0(<3 x i8> %x) { define <3 x i8> @shuf_udiv_const_op0(<3 x i8> %x) {
; CHECK-LABEL: @shuf_udiv_const_op0( ; CHECK-LABEL: @shuf_udiv_const_op0(
; CHECK-NEXT: [[BO:%.*]] = udiv exact <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]] ; CHECK-NEXT: [[BO:%.*]] = udiv exact <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 poison, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 2, i32 poison, i32 0>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = udiv exact <3 x i8> <i8 1, i8 2, i8 3>, %x %bo = udiv exact <3 x i8> <i8 1, i8 2, i8 3>, %x
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_udiv_const_op1(<3 x i8> %x) { define <3 x i8> @shuf_udiv_const_op1(<3 x i8> %x) {
; CHECK-LABEL: @shuf_udiv_const_op1( ; CHECK-LABEL: @shuf_udiv_const_op1(
; CHECK-NEXT: [[BO:%.*]] = udiv <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3> ; CHECK-NEXT: [[BO:%.*]] = udiv <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 poison, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 2, i32 poison, i32 0>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = udiv <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = udiv <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 undef, i32 0>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_urem_const_op0(<3 x i8> %x) { define <3 x i8> @shuf_urem_const_op0(<3 x i8> %x) {
; CHECK-LABEL: @shuf_urem_const_op0( ; CHECK-LABEL: @shuf_urem_const_op0(
; CHECK-NEXT: [[BO:%.*]] = urem <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]] ; CHECK-NEXT: [[BO:%.*]] = urem <3 x i8> <i8 1, i8 2, i8 3>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 poison> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 2, i32 1, i32 poison>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = urem <3 x i8> <i8 1, i8 2, i8 3>, %x %bo = urem <3 x i8> <i8 1, i8 2, i8 3>, %x
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 2, i32 1, i32 undef>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @shuf_urem_const_op1(<3 x i8> %x) { define <3 x i8> @shuf_urem_const_op1(<3 x i8> %x) {
; CHECK-LABEL: @shuf_urem_const_op1( ; CHECK-LABEL: @shuf_urem_const_op1(
; CHECK-NEXT: [[BO:%.*]] = urem <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3> ; CHECK-NEXT: [[BO:%.*]] = urem <3 x i8> [[X:%.*]], <i8 1, i8 2, i8 3>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> undef, <3 x i32> <i32 poison, i32 1, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x i8> [[BO]], <3 x i8> poison, <3 x i32> <i32 poison, i32 1, i32 0>
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%bo = urem <3 x i8> %x, <i8 1, i8 2, i8 3> %bo = urem <3 x i8> %x, <i8 1, i8 2, i8 3>
%r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 undef, i32 1, i32 0> %r = shufflevector <3 x i8> %bo, <3 x i8> undef, <3 x i32> <i32 undef, i32 1, i32 0>
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x float> @shuf_fadd(<3 x float> %x) { define <3 x float> @shuf_fadd(<3 x float> %x) {
; CHECK-LABEL: @shuf_fadd( ; CHECK-LABEL: @shuf_fadd(
; CHECK-NEXT: [[BO:%.*]] = fadd <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison> ; CHECK-NEXT: [[BO:%.*]] = fadd <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 poison, i32 1, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> <i32 poison, i32 1, i32 0>
; CHECK-NEXT: ret <3 x float> [[R]] ; CHECK-NEXT: ret <3 x float> [[R]]
; ;
%bo = fadd <3 x float> %x, <float 1.0, float 2.0, float 3.0> %bo = fadd <3 x float> %x, <float 1.0, float 2.0, float 3.0>
%r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0> %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @shuf_fsub(<3 x float> %x) { define <3 x float> @shuf_fsub(<3 x float> %x) {
; CHECK-LABEL: @shuf_fsub( ; CHECK-LABEL: @shuf_fsub(
; CHECK-NEXT: [[BO:%.*]] = fsub fast <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]] ; CHECK-NEXT: [[BO:%.*]] = fsub fast <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 poison, i32 0, i32 2> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> <i32 poison, i32 0, i32 2>
; CHECK-NEXT: ret <3 x float> [[R]] ; CHECK-NEXT: ret <3 x float> [[R]]
; ;
%bo = fsub fast <3 x float> <float 1.0, float 2.0, float 3.0>, %x %bo = fsub fast <3 x float> <float 1.0, float 2.0, float 3.0>, %x
%r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 0, i32 2> %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 0, i32 2>
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @shuf_fmul(<3 x float> %x) { define <3 x float> @shuf_fmul(<3 x float> %x) {
; CHECK-LABEL: @shuf_fmul( ; CHECK-LABEL: @shuf_fmul(
; CHECK-NEXT: [[BO:%.*]] = fmul reassoc <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison> ; CHECK-NEXT: [[BO:%.*]] = fmul reassoc <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 poison, i32 1, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> <i32 poison, i32 1, i32 0>
; CHECK-NEXT: ret <3 x float> [[R]] ; CHECK-NEXT: ret <3 x float> [[R]]
; ;
%bo = fmul reassoc <3 x float> %x, <float 1.0, float 2.0, float 3.0> %bo = fmul reassoc <3 x float> %x, <float 1.0, float 2.0, float 3.0>
%r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0> %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @shuf_fdiv_const_op0(<3 x float> %x) { define <3 x float> @shuf_fdiv_const_op0(<3 x float> %x) {
; CHECK-LABEL: @shuf_fdiv_const_op0( ; CHECK-LABEL: @shuf_fdiv_const_op0(
; CHECK-NEXT: [[BO:%.*]] = fdiv reassoc ninf <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]] ; CHECK-NEXT: [[BO:%.*]] = fdiv reassoc ninf <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 poison, i32 0, i32 2> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> <i32 poison, i32 0, i32 2>
; CHECK-NEXT: ret <3 x float> [[R]] ; CHECK-NEXT: ret <3 x float> [[R]]
; ;
%bo = fdiv ninf reassoc <3 x float> <float 1.0, float 2.0, float 3.0>, %x %bo = fdiv ninf reassoc <3 x float> <float 1.0, float 2.0, float 3.0>, %x
%r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 0, i32 2> %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 0, i32 2>
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @shuf_fdiv_const_op1(<3 x float> %x) { define <3 x float> @shuf_fdiv_const_op1(<3 x float> %x) {
; CHECK-LABEL: @shuf_fdiv_const_op1( ; CHECK-LABEL: @shuf_fdiv_const_op1(
; CHECK-NEXT: [[BO:%.*]] = fdiv nnan ninf <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison> ; CHECK-NEXT: [[BO:%.*]] = fdiv nnan ninf <3 x float> [[X:%.*]], <float 1.000000e+00, float 2.000000e+00, float poison>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 poison, i32 1, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> <i32 poison, i32 1, i32 0>
; CHECK-NEXT: ret <3 x float> [[R]] ; CHECK-NEXT: ret <3 x float> [[R]]
; ;
%bo = fdiv ninf nnan <3 x float> %x, <float 1.0, float 2.0, float 3.0> %bo = fdiv ninf nnan <3 x float> %x, <float 1.0, float 2.0, float 3.0>
%r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0> %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 1, i32 0>
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @shuf_frem_const_op0(<3 x float> %x) { define <3 x float> @shuf_frem_const_op0(<3 x float> %x) {
; CHECK-LABEL: @shuf_frem_const_op0( ; CHECK-LABEL: @shuf_frem_const_op0(
; CHECK-NEXT: [[BO:%.*]] = frem nnan <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]] ; CHECK-NEXT: [[BO:%.*]] = frem nnan <3 x float> <float 1.000000e+00, float poison, float 3.000000e+00>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 poison, i32 2, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> <i32 poison, i32 2, i32 0>
; CHECK-NEXT: ret <3 x float> [[R]] ; CHECK-NEXT: ret <3 x float> [[R]]
; ;
%bo = frem nnan <3 x float> <float 1.0, float 2.0, float 3.0>, %x %bo = frem nnan <3 x float> <float 1.0, float 2.0, float 3.0>, %x
%r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 2, i32 0> %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 undef, i32 2, i32 0>
ret <3 x float> %r ret <3 x float> %r
} }
define <3 x float> @shuf_frem_const_op1(<3 x float> %x) { define <3 x float> @shuf_frem_const_op1(<3 x float> %x) {
; CHECK-LABEL: @shuf_frem_const_op1( ; CHECK-LABEL: @shuf_frem_const_op1(
; CHECK-NEXT: [[BO:%.*]] = frem reassoc ninf <3 x float> [[X:%.*]], <float poison, float 2.000000e+00, float 3.000000e+00> ; CHECK-NEXT: [[BO:%.*]] = frem reassoc ninf <3 x float> [[X:%.*]], <float poison, float 2.000000e+00, float 3.000000e+00>
; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> undef, <3 x i32> <i32 1, i32 poison, i32 2> ; CHECK-NEXT: [[R:%.*]] = shufflevector <3 x float> [[BO]], <3 x float> poison, <3 x i32> <i32 1, i32 poison, i32 2>
; CHECK-NEXT: ret <3 x float> [[R]] ; CHECK-NEXT: ret <3 x float> [[R]]
; ;
%bo = frem ninf reassoc <3 x float> %x, <float 1.0, float 2.0, float 3.0> %bo = frem ninf reassoc <3 x float> %x, <float 1.0, float 2.0, float 3.0>
%r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 1, i32 undef, i32 2> %r = shufflevector <3 x float> %bo, <3 x float> undef, <3 x i32> <i32 1, i32 undef, i32 2>
ret <3 x float> %r ret <3 x float> %r
} }
define ptr @gep_vbase_w_s_idx(<2 x ptr> %base, i64 %index) { define ptr @gep_vbase_w_s_idx(<2 x ptr> %base, i64 %index) {
Show All 17 Lines;
%gep = getelementptr i32, <2 x ptr> %basevec2, i64 1 %gep = getelementptr i32, <2 x ptr> %basevec2, i64 1
%ee = extractelement <2 x ptr> %gep, i32 1 %ee = extractelement <2 x ptr> %gep, i32 1
ret ptr %ee ret ptr %ee
} }
define ptr @gep_splat_base_w_cv_idx(ptr %base) { define ptr @gep_splat_base_w_cv_idx(ptr %base) {
; CHECK-LABEL: @gep_splat_base_w_cv_idx( ; CHECK-LABEL: @gep_splat_base_w_cv_idx(
; CHECK-NEXT: [[BASEVEC2:%.*]] = insertelement <2 x ptr> undef, ptr [[BASE:%.*]], i64 1 ; CHECK-NEXT: [[BASEVEC2:%.*]] = insertelement <2 x ptr> poison, ptr [[BASE:%.*]], i64 1
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, <2 x ptr> [[BASEVEC2]], <2 x i64> <i64 poison, i64 1> ; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, <2 x ptr> [[BASEVEC2]], <2 x i64> <i64 poison, i64 1>
; CHECK-NEXT: [[EE:%.*]] = extractelement <2 x ptr> [[GEP]], i64 1 ; CHECK-NEXT: [[EE:%.*]] = extractelement <2 x ptr> [[GEP]], i64 1
; CHECK-NEXT: ret ptr [[EE]] ; CHECK-NEXT: ret ptr [[EE]]
; ;
%basevec1 = insertelement <2 x ptr> undef, ptr %base, i32 0 %basevec1 = insertelement <2 x ptr> undef, ptr %base, i32 0
%basevec2 = shufflevector <2 x ptr> %basevec1, <2 x ptr> undef, <2 x i32> zeroinitializer %basevec2 = shufflevector <2 x ptr> %basevec1, <2 x ptr> undef, <2 x i32> zeroinitializer
%gep = getelementptr i32, <2 x ptr> %basevec2, <2 x i64> <i64 0, i64 1> %gep = getelementptr i32, <2 x ptr> %basevec2, <2 x i64> <i64 0, i64 1>
%ee = extractelement <2 x ptr> %gep, i32 1 %ee = extractelement <2 x ptr> %gep, i32 1
ret ptr %ee ret ptr %ee
} }
define ptr @gep_splat_base_w_vidx(ptr %base, <2 x i64> %idxvec) { define ptr @gep_splat_base_w_vidx(ptr %base, <2 x i64> %idxvec) {
; CHECK-LABEL: @gep_splat_base_w_vidx( ; CHECK-LABEL: @gep_splat_base_w_vidx(
; CHECK-NEXT: [[BASEVEC2:%.*]] = insertelement <2 x ptr> undef, ptr [[BASE:%.*]], i64 1 ; CHECK-NEXT: [[BASEVEC2:%.*]] = insertelement <2 x ptr> poison, ptr [[BASE:%.*]], i64 1
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, <2 x ptr> [[BASEVEC2]], <2 x i64> [[IDXVEC:%.*]] ; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, <2 x ptr> [[BASEVEC2]], <2 x i64> [[IDXVEC:%.*]]
; CHECK-NEXT: [[EE:%.*]] = extractelement <2 x ptr> [[GEP]], i64 1 ; CHECK-NEXT: [[EE:%.*]] = extractelement <2 x ptr> [[GEP]], i64 1
; CHECK-NEXT: ret ptr [[EE]] ; CHECK-NEXT: ret ptr [[EE]]
; ;
%basevec1 = insertelement <2 x ptr> undef, ptr %base, i32 0 %basevec1 = insertelement <2 x ptr> undef, ptr %base, i32 0
%basevec2 = shufflevector <2 x ptr> %basevec1, <2 x ptr> undef, <2 x i32> zeroinitializer %basevec2 = shufflevector <2 x ptr> %basevec1, <2 x ptr> undef, <2 x i32> zeroinitializer
%gep = getelementptr i32, <2 x ptr> %basevec2, <2 x i64> %idxvec %gep = getelementptr i32, <2 x ptr> %basevec2, <2 x i64> %idxvec
%ee = extractelement <2 x ptr> %gep, i32 1 %ee = extractelement <2 x ptr> %gep, i32 1
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%idxvec1 = insertelement <2 x i64> undef, i64 %idx, i32 0 %idxvec1 = insertelement <2 x i64> undef, i64 %idx, i32 0
%idxvec2 = shufflevector <2 x i64> %idxvec1, <2 x i64> undef, <2 x i32> zeroinitializer %idxvec2 = shufflevector <2 x i64> %idxvec1, <2 x i64> undef, <2 x i32> zeroinitializer
%gep = getelementptr i32, ptr %base, <2 x i64> %idxvec2 %gep = getelementptr i32, ptr %base, <2 x i64> %idxvec2
%ee = extractelement <2 x ptr> %gep, i32 1 %ee = extractelement <2 x ptr> %gep, i32 1
ret ptr %ee ret ptr %ee
} }
define ptr @gep_splat_both(ptr %base, i64 %idx) { define ptr @gep_splat_both(ptr %base, i64 %idx) {
; CHECK-LABEL: @gep_splat_both( ; CHECK-LABEL: @gep_splat_both(
; CHECK-NEXT: [[BASEVEC2:%.*]] = insertelement <2 x ptr> undef, ptr [[BASE:%.*]], i64 1 ; CHECK-NEXT: [[BASEVEC2:%.*]] = insertelement <2 x ptr> poison, ptr [[BASE:%.*]], i64 1
; CHECK-NEXT: [[IDXVEC2:%.*]] = insertelement <2 x i64> undef, i64 [[IDX:%.*]], i64 1 ; CHECK-NEXT: [[IDXVEC2:%.*]] = insertelement <2 x i64> poison, i64 [[IDX:%.*]], i64 1
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, <2 x ptr> [[BASEVEC2]], <2 x i64> [[IDXVEC2]] ; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, <2 x ptr> [[BASEVEC2]], <2 x i64> [[IDXVEC2]]
; CHECK-NEXT: [[EE:%.*]] = extractelement <2 x ptr> [[GEP]], i64 1 ; CHECK-NEXT: [[EE:%.*]] = extractelement <2 x ptr> [[GEP]], i64 1
; CHECK-NEXT: ret ptr [[EE]] ; CHECK-NEXT: ret ptr [[EE]]
; ;
%basevec1 = insertelement <2 x ptr> undef, ptr %base, i32 0 %basevec1 = insertelement <2 x ptr> undef, ptr %base, i32 0
%basevec2 = shufflevector <2 x ptr> %basevec1, <2 x ptr> undef, <2 x i32> zeroinitializer %basevec2 = shufflevector <2 x ptr> %basevec1, <2 x ptr> undef, <2 x i32> zeroinitializer
%idxvec1 = insertelement <2 x i64> undef, i64 %idx, i32 0 %idxvec1 = insertelement <2 x i64> undef, i64 %idx, i32 0
%idxvec2 = shufflevector <2 x i64> %idxvec1, <2 x i64> undef, <2 x i32> zeroinitializer %idxvec2 = shufflevector <2 x i64> %idxvec1, <2 x i64> undef, <2 x i32> zeroinitializer
%gep = getelementptr i32, <2 x ptr> %basevec2, <2 x i64> %idxvec2 %gep = getelementptr i32, <2 x ptr> %basevec2, <2 x i64> %idxvec2
%ee = extractelement <2 x ptr> %gep, i32 1 %ee = extractelement <2 x ptr> %gep, i32 1
ret ptr %ee ret ptr %ee
} }
define <2 x ptr> @gep_all_lanes_undef(ptr %base, i64 %idx) {; define <2 x ptr> @gep_all_lanes_undef(ptr %base, i64 %idx) {;
; CHECK-LABEL: @gep_all_lanes_undef( ; CHECK-LABEL: @gep_all_lanes_undef(
; CHECK-NEXT: [[BASEVEC:%.*]] = insertelement <2 x ptr> undef, ptr [[BASE:%.*]], i64 0 ; CHECK-NEXT: [[BASEVEC:%.*]] = insertelement <2 x ptr> <ptr poison, ptr undef>, ptr [[BASE:%.*]], i64 0
; CHECK-NEXT: [[IDXVEC:%.*]] = insertelement <2 x i64> undef, i64 [[IDX:%.*]], i64 1 ; CHECK-NEXT: [[IDXVEC:%.*]] = insertelement <2 x i64> <i64 undef, i64 poison>, i64 [[IDX:%.*]], i64 1
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, <2 x ptr> [[BASEVEC]], <2 x i64> [[IDXVEC]] ; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, <2 x ptr> [[BASEVEC]], <2 x i64> [[IDXVEC]]
; CHECK-NEXT: ret <2 x ptr> [[GEP]] ; CHECK-NEXT: ret <2 x ptr> [[GEP]]
; ;
%basevec = insertelement <2 x ptr> undef, ptr %base, i32 0 %basevec = insertelement <2 x ptr> undef, ptr %base, i32 0
%idxvec = insertelement <2 x i64> undef, i64 %idx, i32 1 %idxvec = insertelement <2 x i64> undef, i64 %idx, i32 1
%gep = getelementptr i32, <2 x ptr> %basevec, <2 x i64> %idxvec %gep = getelementptr i32, <2 x ptr> %basevec, <2 x i64> %idxvec
ret <2 x ptr> %gep ret <2 x ptr> %gep
} }
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%r = select <4 x i1> %splat, <4 x i8> %tval, <4 x i8> %y %r = select <4 x i1> %splat, <4 x i8> %tval, <4 x i8> %y
ret <4 x i8> %r ret <4 x i8> %r
} }
; First element of the result is always x[0], so first element of select condition is unnecessary. ; First element of the result is always x[0], so first element of select condition is unnecessary.
define <4 x i8> @select_cond_with_eq_true_false_elts2(<4 x i8> %x, <4 x i8> %y, <4 x i1> %cmp) { define <4 x i8> @select_cond_with_eq_true_false_elts2(<4 x i8> %x, <4 x i8> %y, <4 x i1> %cmp) {
; CHECK-LABEL: @select_cond_with_eq_true_false_elts2( ; CHECK-LABEL: @select_cond_with_eq_true_false_elts2(
; CHECK-NEXT: [[COND:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> undef, <4 x i32> <i32 poison, i32 1, i32 0, i32 1> ; CHECK-NEXT: [[COND:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> poison, <4 x i32> <i32 poison, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[COND]], <4 x i8> [[Y:%.*]], <4 x i8> [[X:%.*]] ; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[COND]], <4 x i8> [[Y:%.*]], <4 x i8> [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> [[SEL]], <4 x i32> <i32 0, i32 5, i32 6, i32 7> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[X]], <4 x i8> [[SEL]], <4 x i32> <i32 0, i32 5, i32 6, i32 7>
; CHECK-NEXT: ret <4 x i8> [[R]] ; CHECK-NEXT: ret <4 x i8> [[R]]
; ;
%tval = shufflevector <4 x i8> %x, <4 x i8> %y, <4 x i32> <i32 0, i32 5, i32 6, i32 7> %tval = shufflevector <4 x i8> %x, <4 x i8> %y, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
%cond = shufflevector <4 x i1> %cmp, <4 x i1> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> %cond = shufflevector <4 x i1> %cmp, <4 x i1> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%r = select <4 x i1> %cond, <4 x i8> %tval, <4 x i8> %x %r = select <4 x i1> %cond, <4 x i8> %tval, <4 x i8> %x
ret <4 x i8> %r ret <4 x i8> %r
} }
; Second element of the result is always x[3], so second element of select condition is unnecessary. ; Second element of the result is always x[3], so second element of select condition is unnecessary.
; Fourth element of the result is always undef, so fourth element of select condition is unnecessary. ; Fourth element of the result is always undef, so fourth element of select condition is unnecessary.
define <4 x float> @select_cond_with_eq_true_false_elts3(<4 x float> %x, <4 x float> %y, <4 x i1> %cmp) { define <4 x float> @select_cond_with_eq_true_false_elts3(<4 x float> %x, <4 x float> %y, <4 x i1> %cmp) {
; CHECK-LABEL: @select_cond_with_eq_true_false_elts3( ; CHECK-LABEL: @select_cond_with_eq_true_false_elts3(
; CHECK-NEXT: [[TVAL:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x i32> <i32 1, i32 3, i32 5, i32 poison> ; CHECK-NEXT: [[TVAL:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x i32> <i32 1, i32 3, i32 5, i32 poison>
; CHECK-NEXT: [[FVAL:%.*]] = shufflevector <4 x float> [[Y]], <4 x float> [[X]], <4 x i32> <i32 0, i32 7, i32 6, i32 poison> ; CHECK-NEXT: [[FVAL:%.*]] = shufflevector <4 x float> [[Y]], <4 x float> [[X]], <4 x i32> <i32 0, i32 7, i32 6, i32 poison>
; CHECK-NEXT: [[COND:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> undef, <4 x i32> <i32 poison, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[COND:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> poison, <4 x i32> <i32 poison, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[COND]], <4 x float> [[TVAL]], <4 x float> [[FVAL]] ; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[COND]], <4 x float> [[TVAL]], <4 x float> [[FVAL]]
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%tval = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 undef> %tval = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 undef>
%fval = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 7, i32 6, i32 undef> %fval = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 0, i32 7, i32 6, i32 undef>
%cond = shufflevector <4 x i1> %cmp, <4 x i1> undef, <4 x i32> <i32 undef, i32 1, i32 2, i32 3> %cond = shufflevector <4 x i1> %cmp, <4 x i1> undef, <4 x i32> <i32 undef, i32 1, i32 2, i32 3>
%r = select <4 x i1> %cond, <4 x float> %tval, <4 x float> %fval %r = select <4 x i1> %cond, <4 x float> %tval, <4 x float> %fval
ret <4 x float> %r ret <4 x float> %r
} }
define <4 x i8> @select_cond_with_undef_true_false_elts(<4 x i8> %x, <4 x i8> %y, <4 x i1> %cmp) { define <4 x i8> @select_cond_with_undef_true_false_elts(<4 x i8> %x, <4 x i8> %y, <4 x i1> %cmp) {
; CHECK-LABEL: @select_cond_with_undef_true_false_elts( ; CHECK-LABEL: @select_cond_with_undef_true_false_elts(
; CHECK-NEXT: [[TVAL:%.*]] = shufflevector <4 x i8> [[Y:%.*]], <4 x i8> poison, <4 x i32> <i32 poison, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[TVAL:%.*]] = shufflevector <4 x i8> [[Y:%.*]], <4 x i8> poison, <4 x i32> <i32 poison, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[COND:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> ; CHECK-NEXT: [[COND:%.*]] = shufflevector <4 x i1> [[CMP:%.*]], <4 x i1> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[COND]], <4 x i8> [[TVAL]], <4 x i8> [[X:%.*]] ; CHECK-NEXT: [[R:%.*]] = select <4 x i1> [[COND]], <4 x i8> [[TVAL]], <4 x i8> [[X:%.*]]
; CHECK-NEXT: ret <4 x i8> [[R]] ; CHECK-NEXT: ret <4 x i8> [[R]]
; ;
%tval = shufflevector <4 x i8> %x, <4 x i8> %y, <4 x i32> <i32 undef, i32 5, i32 6, i32 7> %tval = shufflevector <4 x i8> %x, <4 x i8> %y, <4 x i32> <i32 undef, i32 5, i32 6, i32 7>
%cond = shufflevector <4 x i1> %cmp, <4 x i1> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> %cond = shufflevector <4 x i1> %cmp, <4 x i1> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
%r = select <4 x i1> %cond, <4 x i8> %tval, <4 x i8> %x %r = select <4 x i1> %cond, <4 x i8> %tval, <4 x i8> %x
ret <4 x i8> %r ret <4 x i8> %r
} }
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} }
; Negative test - element 3 of the result must be undef to be poison safe. ; Negative test - element 3 of the result must be undef to be poison safe.
; TODO: Could convert insert/extract to identity shuffle with undef mask elements. ; TODO: Could convert insert/extract to identity shuffle with undef mask elements.
define <4 x float> @ins_of_ext_wrong_demand(<4 x float> %x, float %y) { define <4 x float> @ins_of_ext_wrong_demand(<4 x float> %x, float %y) {
; CHECK-LABEL: @ins_of_ext_wrong_demand( ; CHECK-LABEL: @ins_of_ext_wrong_demand(
; CHECK-NEXT: [[E0:%.*]] = extractelement <4 x float> [[X:%.*]], i64 0 ; CHECK-NEXT: [[E0:%.*]] = extractelement <4 x float> [[X:%.*]], i64 0
; CHECK-NEXT: [[I0:%.*]] = insertelement <4 x float> undef, float [[E0]], i64 0 ; CHECK-NEXT: [[I0:%.*]] = insertelement <4 x float> <float poison, float poison, float poison, float undef>, float [[E0]], i64 0
; CHECK-NEXT: [[I1:%.*]] = insertelement <4 x float> [[I0]], float [[Y:%.*]], i64 1 ; CHECK-NEXT: [[I1:%.*]] = insertelement <4 x float> [[I0]], float [[Y:%.*]], i64 1
; CHECK-NEXT: [[I2:%.*]] = insertelement <4 x float> [[I1]], float [[Y]], i64 2 ; CHECK-NEXT: [[I2:%.*]] = insertelement <4 x float> [[I1]], float [[Y]], i64 2
; CHECK-NEXT: ret <4 x float> [[I2]] ; CHECK-NEXT: ret <4 x float> [[I2]]
; ;
%e0 = extractelement <4 x float> %x, i32 0 %e0 = extractelement <4 x float> %x, i32 0
%i0 = insertelement <4 x float> undef, float %e0, i32 0 %i0 = insertelement <4 x float> undef, float %e0, i32 0
%i1 = insertelement <4 x float> %i0, float %y, i32 1 %i1 = insertelement <4 x float> %i0, float %y, i32 1
%i2 = insertelement <4 x float> %i1, float %y, i32 2 %i2 = insertelement <4 x float> %i1, float %y, i32 2
ret <4 x float> %i2 ret <4 x float> %i2
} }
; Negative test - can't replace i0 with x. ; Negative test - can't replace i0 with x.
; TODO: Could convert insert/extract to identity shuffle with undef mask elements. ; TODO: Could convert insert/extract to identity shuffle with undef mask elements.
define <4 x float> @ins_of_ext_wrong_type(<5 x float> %x, float %y) { define <4 x float> @ins_of_ext_wrong_type(<5 x float> %x, float %y) {
; CHECK-LABEL: @ins_of_ext_wrong_type( ; CHECK-LABEL: @ins_of_ext_wrong_type(
; CHECK-NEXT: [[E0:%.*]] = extractelement <5 x float> [[X:%.*]], i64 0 ; CHECK-NEXT: [[E0:%.*]] = extractelement <5 x float> [[X:%.*]], i64 0
; CHECK-NEXT: [[I0:%.*]] = insertelement <4 x float> undef, float [[E0]], i64 0 ; CHECK-NEXT: [[I0:%.*]] = insertelement <4 x float> poison, float [[E0]], i64 0
; CHECK-NEXT: [[I1:%.*]] = insertelement <4 x float> [[I0]], float [[Y:%.*]], i64 1 ; CHECK-NEXT: [[I1:%.*]] = insertelement <4 x float> [[I0]], float [[Y:%.*]], i64 1
; CHECK-NEXT: [[I2:%.*]] = insertelement <4 x float> [[I1]], float [[Y]], i64 2 ; CHECK-NEXT: [[I2:%.*]] = insertelement <4 x float> [[I1]], float [[Y]], i64 2
; CHECK-NEXT: [[I3:%.*]] = insertelement <4 x float> [[I2]], float [[Y]], i64 3 ; CHECK-NEXT: [[I3:%.*]] = insertelement <4 x float> [[I2]], float [[Y]], i64 3
; CHECK-NEXT: ret <4 x float> [[I3]] ; CHECK-NEXT: ret <4 x float> [[I3]]
; ;
%e0 = extractelement <5 x float> %x, i32 0 %e0 = extractelement <5 x float> %x, i32 0
%i0 = insertelement <4 x float> undef, float %e0, i32 0 %i0 = insertelement <4 x float> undef, float %e0, i32 0
%i1 = insertelement <4 x float> %i0, float %y, i32 1 %i1 = insertelement <4 x float> %i0, float %y, i32 1
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llvm/test/Transforms/InstCombine/vec_gep_scalar_arg.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=instcombine -S < %s | FileCheck %s ; RUN: opt -passes=instcombine -S < %s | FileCheck %s
define <4 x ptr> @PR41270(ptr %x) { define <4 x ptr> @PR41270(ptr %x) {
; CHECK-LABEL: @PR41270( ; CHECK-LABEL: @PR41270(
; CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds [4 x i16], ptr [[X:%.*]], i64 0, i64 3 ; CHECK-NEXT: [[T3:%.*]] = getelementptr inbounds [4 x i16], ptr [[X:%.*]], i64 0, i64 3
; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x ptr> undef, ptr [[T3]], i64 0 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <4 x ptr> <ptr poison, ptr undef, ptr undef, ptr undef>, ptr [[T3]], i64 0
; CHECK-NEXT: ret <4 x ptr> [[INS2]] ; CHECK-NEXT: ret <4 x ptr> [[INS2]]
; ;
%ins = insertelement <4 x ptr> undef, ptr %x, i32 0 %ins = insertelement <4 x ptr> undef, ptr %x, i32 0
%splat = shufflevector <4 x ptr> %ins, <4 x ptr> undef, <4 x i32> zeroinitializer %splat = shufflevector <4 x ptr> %ins, <4 x ptr> undef, <4 x i32> zeroinitializer
%t2 = getelementptr inbounds [4 x i16], <4 x ptr> %splat, i32 0, i32 3 %t2 = getelementptr inbounds [4 x i16], <4 x ptr> %splat, i32 0, i32 3
%t3 = extractelement <4 x ptr> %t2, i32 3 %t3 = extractelement <4 x ptr> %t2, i32 3
%ins2 = insertelement <4 x ptr> undef, ptr %t3, i32 0 %ins2 = insertelement <4 x ptr> undef, ptr %t3, i32 0
ret <4 x ptr> %ins2 ret <4 x ptr> %ins2
} }

llvm/test/Transforms/InstCombine/vec_phi_extract-inseltpoison.ll

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ret: ret:
ret void ret void
} }
define void @nocopy(i64 %val, i32 %limit, ptr %ptr) { define void @nocopy(i64 %val, i32 %limit, ptr %ptr) {
; CHECK-LABEL: @nocopy( ; CHECK-LABEL: @nocopy(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[VAL:%.*]] to i32 ; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[VAL:%.*]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i32> undef, i32 [[TMP0]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[TMP1]], <16 x i32> poison, <16 x i32> zeroinitializer ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[TMP1]], <16 x i32> poison, <16 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add <16 x i32> [[TMP2]], <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP3:%.*]] = add <16 x i32> [[TMP2]], <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop: ; CHECK: loop:
; CHECK-NEXT: [[TMP4:%.*]] = phi <16 x i32> [ [[TMP3]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[TMP4:%.*]] = phi <16 x i32> [ [[TMP3]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[ELT:%.*]] = extractelement <16 x i32> [[TMP4]], i64 0 ; CHECK-NEXT: [[ELT:%.*]] = extractelement <16 x i32> [[TMP4]], i64 0
; CHECK-NEXT: [[ELTCOPY:%.*]] = extractelement <16 x i32> [[TMP4]], i64 1 ; CHECK-NEXT: [[ELTCOPY:%.*]] = extractelement <16 x i32> [[TMP4]], i64 1
; CHECK-NEXT: [[END:%.*]] = icmp ult i32 [[ELT]], [[LIMIT:%.*]] ; CHECK-NEXT: [[END:%.*]] = icmp ult i32 [[ELT]], [[LIMIT:%.*]]
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llvm/test/Transforms/InstCombine/vec_phi_extract.ll

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ret: ret:
ret void ret void
} }
define void @nocopy(i64 %val, i32 %limit, ptr %ptr) { define void @nocopy(i64 %val, i32 %limit, ptr %ptr) {
; CHECK-LABEL: @nocopy( ; CHECK-LABEL: @nocopy(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[VAL:%.*]] to i32 ; CHECK-NEXT: [[TMP0:%.*]] = trunc i64 [[VAL:%.*]] to i32
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i32> undef, i32 [[TMP0]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i32> poison, i32 [[TMP0]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[TMP1]], <16 x i32> poison, <16 x i32> zeroinitializer ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i32> [[TMP1]], <16 x i32> poison, <16 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add <16 x i32> [[TMP2]], <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[TMP3:%.*]] = add <16 x i32> [[TMP2]], <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop: ; CHECK: loop:
; CHECK-NEXT: [[TMP4:%.*]] = phi <16 x i32> [ [[TMP3]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[LOOP]] ] ; CHECK-NEXT: [[TMP4:%.*]] = phi <16 x i32> [ [[TMP3]], [[ENTRY:%.*]] ], [ [[INC:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[ELT:%.*]] = extractelement <16 x i32> [[TMP4]], i64 0 ; CHECK-NEXT: [[ELT:%.*]] = extractelement <16 x i32> [[TMP4]], i64 0
; CHECK-NEXT: [[ELTCOPY:%.*]] = extractelement <16 x i32> [[TMP4]], i64 1 ; CHECK-NEXT: [[ELTCOPY:%.*]] = extractelement <16 x i32> [[TMP4]], i64 1
; CHECK-NEXT: [[END:%.*]] = icmp ult i32 [[ELT]], [[LIMIT:%.*]] ; CHECK-NEXT: [[END:%.*]] = icmp ult i32 [[ELT]], [[LIMIT:%.*]]
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llvm/test/Transforms/InstCombine/vec_shuffle-inseltpoison.ll

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%shuf = shufflevector <2 x i8> %x, <2 x i8> %y, <5 x i32> <i32 undef, i32 2, i32 0, i32 1, i32 0> %shuf = shufflevector <2 x i8> %x, <2 x i8> %y, <5 x i32> <i32 undef, i32 2, i32 0, i32 1, i32 0>
call void @use_v5i8(<5 x i8> %shuf) call void @use_v5i8(<5 x i8> %shuf)
%extract_subv = shufflevector <5 x i8> %shuf, <5 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> %extract_subv = shufflevector <5 x i8> %shuf, <5 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
ret <4 x i8> %extract_subv ret <4 x i8> %extract_subv
} }
define <2 x i8> @test13a(i8 %x1, i8 %x2) { define <2 x i8> @test13a(i8 %x1, i8 %x2) {
; CHECK-LABEL: @test13a( ; CHECK-LABEL: @test13a(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X2:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> poison, i8 [[X2:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X1:%.*]], i64 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X1:%.*]], i64 1
; CHECK-NEXT: [[D:%.*]] = add <2 x i8> [[TMP2]], <i8 7, i8 5> ; CHECK-NEXT: [[D:%.*]] = add <2 x i8> [[TMP2]], <i8 7, i8 5>
; CHECK-NEXT: ret <2 x i8> [[D]] ; CHECK-NEXT: ret <2 x i8> [[D]]
; ;
%A = insertelement <2 x i8> poison, i8 %x1, i32 0 %A = insertelement <2 x i8> poison, i8 %x1, i32 0
%B = insertelement <2 x i8> %A, i8 %x2, i32 1 %B = insertelement <2 x i8> %A, i8 %x2, i32 1
%C = add <2 x i8> %B, <i8 5, i8 7> %C = add <2 x i8> %B, <i8 5, i8 7>
%D = shufflevector <2 x i8> %C, <2 x i8> poison, <2 x i32> <i32 1, i32 0> %D = shufflevector <2 x i8> %C, <2 x i8> poison, <2 x i32> <i32 1, i32 0>
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%ext = shufflevector <2 x i32> %a, <2 x i32> poison, <3 x i32> <i32 0, i32 1, i32 undef> %ext = shufflevector <2 x i32> %a, <2 x i32> poison, <3 x i32> <i32 0, i32 1, i32 undef>
ret <3 x i32> %ext ret <3 x i32> %ext
} }
; Increasing length of insertelements (no math ops) is a good canonicalization. ; Increasing length of insertelements (no math ops) is a good canonicalization.
define <3 x i8> @fold_inselts_with_widening_shuffle(i8 %x, i8 %y) { define <3 x i8> @fold_inselts_with_widening_shuffle(i8 %x, i8 %y) {
; CHECK-LABEL: @fold_inselts_with_widening_shuffle( ; CHECK-LABEL: @fold_inselts_with_widening_shuffle(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i8> <i8 poison, i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[WIDEN:%.*]] = insertelement <3 x i8> [[TMP1]], i8 [[Y:%.*]], i64 1 ; CHECK-NEXT: [[WIDEN:%.*]] = insertelement <3 x i8> [[TMP1]], i8 [[Y:%.*]], i64 1
; CHECK-NEXT: ret <3 x i8> [[WIDEN]] ; CHECK-NEXT: ret <3 x i8> [[WIDEN]]
; ;
%ins0 = insertelement <2 x i8> poison, i8 %x, i32 0 %ins0 = insertelement <2 x i8> poison, i8 %x, i32 0
%ins1 = insertelement <2 x i8> %ins0, i8 %y, i32 1 %ins1 = insertelement <2 x i8> %ins0, i8 %y, i32 1
%widen = shufflevector <2 x i8> %ins1, <2 x i8> poison, <3 x i32> <i32 0, i32 1, i32 undef> %widen = shufflevector <2 x i8> %ins1, <2 x i8> poison, <3 x i32> <i32 0, i32 1, i32 undef>
ret <3 x i8> %widen ret <3 x i8> %widen
} }
define <2 x i8> @test13b(i8 %x) { define <2 x i8> @test13b(i8 %x) {
; CHECK-LABEL: @test13b( ; CHECK-LABEL: @test13b(
; CHECK-NEXT: [[B:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[B:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i64 1
; CHECK-NEXT: ret <2 x i8> [[B]] ; CHECK-NEXT: ret <2 x i8> [[B]]
; ;
%A = insertelement <2 x i8> poison, i8 %x, i32 0 %A = insertelement <2 x i8> poison, i8 %x, i32 0
%B = shufflevector <2 x i8> %A, <2 x i8> poison, <2 x i32> <i32 undef, i32 0> %B = shufflevector <2 x i8> %A, <2 x i8> poison, <2 x i32> <i32 undef, i32 0>
ret <2 x i8> %B ret <2 x i8> %B
} }
define <2 x i8> @test13c(i8 %x1, i8 %x2) { define <2 x i8> @test13c(i8 %x1, i8 %x2) {
; CHECK-LABEL: @test13c( ; CHECK-LABEL: @test13c(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X1:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> poison, i8 [[X1:%.*]], i64 0
; CHECK-NEXT: [[C:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X2:%.*]], i64 1 ; CHECK-NEXT: [[C:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X2:%.*]], i64 1
; CHECK-NEXT: ret <2 x i8> [[C]] ; CHECK-NEXT: ret <2 x i8> [[C]]
; ;
%A = insertelement <4 x i8> poison, i8 %x1, i32 0 %A = insertelement <4 x i8> poison, i8 %x1, i32 0
%B = insertelement <4 x i8> %A, i8 %x2, i32 2 %B = insertelement <4 x i8> %A, i8 %x2, i32 2
%C = shufflevector <4 x i8> %B, <4 x i8> poison, <2 x i32> <i32 0, i32 2> %C = shufflevector <4 x i8> %B, <4 x i8> poison, <2 x i32> <i32 0, i32 2>
ret <2 x i8> %C ret <2 x i8> %C
} }
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llvm/test/Transforms/InstCombine/vec_shuffle.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines;
%t2 = bitcast <vscale x 4 x i32> %t to <vscale x 4 x float> %t2 = bitcast <vscale x 4 x i32> %t to <vscale x 4 x float>
%r = extractelement <vscale x 4 x float> %t2, i32 0 %r = extractelement <vscale x 4 x float> %t2, i32 0
ret float %r ret float %r
} }
define <4 x float> @test7(<4 x float> %x) { define <4 x float> @test7(<4 x float> %x) {
; CHECK-LABEL: @test7( ; CHECK-LABEL: @test7(
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[X:%.*]], <4 x float> <float poison, float poison, float undef, float undef>, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
; CHECK-NEXT: ret <4 x float> [[R]] ; CHECK-NEXT: ret <4 x float> [[R]]
; ;
%r = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> < i32 0, i32 1, i32 6, i32 7 > %r = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> < i32 0, i32 1, i32 6, i32 7 >
ret <4 x float> %r ret <4 x float> %r
} }
; This should turn into a single shuffle. ; This should turn into a single shuffle.
define <4 x float> @test8(<4 x float> %x, <4 x float> %y) { define <4 x float> @test8(<4 x float> %x, <4 x float> %y) {
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%t134 = insertelement <4 x float> %t132, float %t1, i32 3 %t134 = insertelement <4 x float> %t132, float %t1, i32 3
ret <4 x float> %t134 ret <4 x float> %t134
} }
; Test fold of two shuffles where the first shuffle vectors inputs are a ; Test fold of two shuffles where the first shuffle vectors inputs are a
; different length then the second. ; different length then the second.
define <4 x i8> @test9(<16 x i8> %t6) { define <4 x i8> @test9(<16 x i8> %t6) {
; CHECK-LABEL: @test9( ; CHECK-LABEL: @test9(
; CHECK-NEXT: [[T9:%.*]] = shufflevector <16 x i8> [[T6:%.*]], <16 x i8> undef, <4 x i32> <i32 13, i32 9, i32 4, i32 13> ; CHECK-NEXT: [[T9:%.*]] = shufflevector <16 x i8> [[T6:%.*]], <16 x i8> poison, <4 x i32> <i32 13, i32 9, i32 4, i32 13>
; CHECK-NEXT: ret <4 x i8> [[T9]] ; CHECK-NEXT: ret <4 x i8> [[T9]]
; ;
%t7 = shufflevector <16 x i8> %t6, <16 x i8> undef, <4 x i32> < i32 13, i32 9, i32 4, i32 13 > %t7 = shufflevector <16 x i8> %t6, <16 x i8> undef, <4 x i32> < i32 13, i32 9, i32 4, i32 13 >
%t9 = shufflevector <4 x i8> %t7, <4 x i8> undef, <4 x i32> < i32 3, i32 1, i32 2, i32 0 > %t9 = shufflevector <4 x i8> %t7, <4 x i8> undef, <4 x i32> < i32 3, i32 1, i32 2, i32 0 >
ret <4 x i8> %t9 ret <4 x i8> %t9
} }
; Same as test9, but make sure that "undef" mask values are not confused with ; Same as test9, but make sure that "undef" mask values are not confused with
; mask values of 2*N, where N is the mask length. These shuffles should not ; mask values of 2*N, where N is the mask length. These shuffles should not
; be folded (because [8,9,4,8] may not be a mask supported by the target). ; be folded (because [8,9,4,8] may not be a mask supported by the target).
define <4 x i8> @test9a(<16 x i8> %t6) { define <4 x i8> @test9a(<16 x i8> %t6) {
; CHECK-LABEL: @test9a( ; CHECK-LABEL: @test9a(
; CHECK-NEXT: [[T7:%.*]] = shufflevector <16 x i8> [[T6:%.*]], <16 x i8> undef, <4 x i32> <i32 poison, i32 9, i32 4, i32 8> ; CHECK-NEXT: [[T7:%.*]] = shufflevector <16 x i8> [[T6:%.*]], <16 x i8> poison, <4 x i32> <i32 poison, i32 9, i32 4, i32 8>
; CHECK-NEXT: [[T9:%.*]] = shufflevector <4 x i8> [[T7]], <4 x i8> undef, <4 x i32> <i32 3, i32 1, i32 2, i32 poison> ; CHECK-NEXT: [[T9:%.*]] = shufflevector <4 x i8> [[T7]], <4 x i8> poison, <4 x i32> <i32 3, i32 1, i32 2, i32 poison>
; CHECK-NEXT: ret <4 x i8> [[T9]] ; CHECK-NEXT: ret <4 x i8> [[T9]]
; ;
%t7 = shufflevector <16 x i8> %t6, <16 x i8> undef, <4 x i32> < i32 undef, i32 9, i32 4, i32 8 > %t7 = shufflevector <16 x i8> %t6, <16 x i8> undef, <4 x i32> < i32 undef, i32 9, i32 4, i32 8 >
%t9 = shufflevector <4 x i8> %t7, <4 x i8> undef, <4 x i32> < i32 3, i32 1, i32 2, i32 0 > %t9 = shufflevector <4 x i8> %t7, <4 x i8> undef, <4 x i32> < i32 3, i32 1, i32 2, i32 0 >
ret <4 x i8> %t9 ret <4 x i8> %t9
} }
; Test fold of two shuffles where the first shuffle vectors inputs are a ; Test fold of two shuffles where the first shuffle vectors inputs are a
; different length then the second. ; different length then the second.
define <4 x i8> @test9b(<4 x i8> %t6, <4 x i8> %t7) { define <4 x i8> @test9b(<4 x i8> %t6, <4 x i8> %t7) {
; CHECK-LABEL: @test9b( ; CHECK-LABEL: @test9b(
; CHECK-NEXT: [[T9:%.*]] = shufflevector <4 x i8> [[T6:%.*]], <4 x i8> [[T7:%.*]], <4 x i32> <i32 0, i32 1, i32 4, i32 5> ; CHECK-NEXT: [[T9:%.*]] = shufflevector <4 x i8> [[T6:%.*]], <4 x i8> [[T7:%.*]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT: ret <4 x i8> [[T9]] ; CHECK-NEXT: ret <4 x i8> [[T9]]
; ;
%t1 = shufflevector <4 x i8> %t6, <4 x i8> %t7, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 4, i32 5, i32 2, i32 3> %t1 = shufflevector <4 x i8> %t6, <4 x i8> %t7, <8 x i32> <i32 0, i32 1, i32 4, i32 5, i32 4, i32 5, i32 2, i32 3>
%t9 = shufflevector <8 x i8> %t1, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 5> %t9 = shufflevector <8 x i8> %t1, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
ret <4 x i8> %t9 ret <4 x i8> %t9
} }
; Redundant vector splats should be removed. Radar 8597790. ; Redundant vector splats should be removed. Radar 8597790.
define <4 x i32> @test10(<4 x i32> %t5) { define <4 x i32> @test10(<4 x i32> %t5) {
; CHECK-LABEL: @test10( ; CHECK-LABEL: @test10(
; CHECK-NEXT: [[T7:%.*]] = shufflevector <4 x i32> [[T5:%.*]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; CHECK-NEXT: [[T7:%.*]] = shufflevector <4 x i32> [[T5:%.*]], <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: ret <4 x i32> [[T7]] ; CHECK-NEXT: ret <4 x i32> [[T7]]
; ;
%t6 = shufflevector <4 x i32> %t5, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %t6 = shufflevector <4 x i32> %t5, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%t7 = shufflevector <4 x i32> %t6, <4 x i32> undef, <4 x i32> zeroinitializer %t7 = shufflevector <4 x i32> %t6, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %t7 ret <4 x i32> %t7
} }
; Test fold of two shuffles where the two shufflevector inputs's op1 are the same. ; Test fold of two shuffles where the two shufflevector inputs's op1 are the same.
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; Extra uses are not ok - we only do the transform when we can eliminate an instruction. ; Extra uses are not ok - we only do the transform when we can eliminate an instruction.
declare void @use_v5i8(<5 x i8>) declare void @use_v5i8(<5 x i8>)
define <4 x i8> @extract_subvector_of_shuffle_extra_use(<2 x i8> %x, <2 x i8> %y) { define <4 x i8> @extract_subvector_of_shuffle_extra_use(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @extract_subvector_of_shuffle_extra_use( ; CHECK-LABEL: @extract_subvector_of_shuffle_extra_use(
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]], <5 x i32> <i32 poison, i32 2, i32 0, i32 1, i32 0> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> [[Y:%.*]], <5 x i32> <i32 poison, i32 2, i32 0, i32 1, i32 0>
; CHECK-NEXT: call void @use_v5i8(<5 x i8> [[SHUF]]) ; CHECK-NEXT: call void @use_v5i8(<5 x i8> [[SHUF]])
; CHECK-NEXT: [[EXTRACT_SUBV:%.*]] = shufflevector <5 x i8> [[SHUF]], <5 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 poison> ; CHECK-NEXT: [[EXTRACT_SUBV:%.*]] = shufflevector <5 x i8> [[SHUF]], <5 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 poison>
; CHECK-NEXT: ret <4 x i8> [[EXTRACT_SUBV]] ; CHECK-NEXT: ret <4 x i8> [[EXTRACT_SUBV]]
; ;
%shuf = shufflevector <2 x i8> %x, <2 x i8> %y, <5 x i32> <i32 undef, i32 2, i32 0, i32 1, i32 0> %shuf = shufflevector <2 x i8> %x, <2 x i8> %y, <5 x i32> <i32 undef, i32 2, i32 0, i32 1, i32 0>
call void @use_v5i8(<5 x i8> %shuf) call void @use_v5i8(<5 x i8> %shuf)
%extract_subv = shufflevector <5 x i8> %shuf, <5 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> %extract_subv = shufflevector <5 x i8> %shuf, <5 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
ret <4 x i8> %extract_subv ret <4 x i8> %extract_subv
} }
define <2 x i8> @test13a(i8 %x1, i8 %x2) { define <2 x i8> @test13a(i8 %x1, i8 %x2) {
; CHECK-LABEL: @test13a( ; CHECK-LABEL: @test13a(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X2:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> poison, i8 [[X2:%.*]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X1:%.*]], i64 1 ; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X1:%.*]], i64 1
; CHECK-NEXT: [[D:%.*]] = add <2 x i8> [[TMP2]], <i8 7, i8 5> ; CHECK-NEXT: [[D:%.*]] = add <2 x i8> [[TMP2]], <i8 7, i8 5>
; CHECK-NEXT: ret <2 x i8> [[D]] ; CHECK-NEXT: ret <2 x i8> [[D]]
; ;
%A = insertelement <2 x i8> undef, i8 %x1, i32 0 %A = insertelement <2 x i8> undef, i8 %x1, i32 0
%B = insertelement <2 x i8> %A, i8 %x2, i32 1 %B = insertelement <2 x i8> %A, i8 %x2, i32 1
%C = add <2 x i8> %B, <i8 5, i8 7> %C = add <2 x i8> %B, <i8 5, i8 7>
%D = shufflevector <2 x i8> %C, <2 x i8> undef, <2 x i32> <i32 1, i32 0> %D = shufflevector <2 x i8> %C, <2 x i8> undef, <2 x i32> <i32 1, i32 0>
ret <2 x i8> %D ret <2 x i8> %D
} }
; Increasing length of vector ops is not a good canonicalization. ; Increasing length of vector ops is not a good canonicalization.
define <3 x i32> @add_wider(i32 %y, i32 %z) { define <3 x i32> @add_wider(i32 %y, i32 %z) {
; CHECK-LABEL: @add_wider( ; CHECK-LABEL: @add_wider(
; CHECK-NEXT: [[I0:%.*]] = insertelement <2 x i32> undef, i32 [[Y:%.*]], i64 0 ; CHECK-NEXT: [[I0:%.*]] = insertelement <2 x i32> poison, i32 [[Y:%.*]], i64 0
; CHECK-NEXT: [[I1:%.*]] = insertelement <2 x i32> [[I0]], i32 [[Z:%.*]], i64 1 ; CHECK-NEXT: [[I1:%.*]] = insertelement <2 x i32> [[I0]], i32 [[Z:%.*]], i64 1
; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[I1]], <i32 255, i32 255> ; CHECK-NEXT: [[A:%.*]] = add <2 x i32> [[I1]], <i32 255, i32 255>
; CHECK-NEXT: [[EXT:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> undef, <3 x i32> <i32 0, i32 1, i32 poison> ; CHECK-NEXT: [[EXT:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> poison, <3 x i32> <i32 0, i32 1, i32 poison>
; CHECK-NEXT: ret <3 x i32> [[EXT]] ; CHECK-NEXT: ret <3 x i32> [[EXT]]
; ;
%i0 = insertelement <2 x i32> undef, i32 %y, i32 0 %i0 = insertelement <2 x i32> undef, i32 %y, i32 0
%i1 = insertelement <2 x i32> %i0, i32 %z, i32 1 %i1 = insertelement <2 x i32> %i0, i32 %z, i32 1
%a = add <2 x i32> %i1, <i32 255, i32 255> %a = add <2 x i32> %i1, <i32 255, i32 255>
%ext = shufflevector <2 x i32> %a, <2 x i32> undef, <3 x i32> <i32 0, i32 1, i32 undef> %ext = shufflevector <2 x i32> %a, <2 x i32> undef, <3 x i32> <i32 0, i32 1, i32 undef>
ret <3 x i32> %ext ret <3 x i32> %ext
} }
; Increasing length of vector ops must be safe from illegal undef propagation. ; Increasing length of vector ops must be safe from illegal undef propagation.
define <3 x i32> @div_wider(i32 %y, i32 %z) { define <3 x i32> @div_wider(i32 %y, i32 %z) {
; CHECK-LABEL: @div_wider( ; CHECK-LABEL: @div_wider(
; CHECK-NEXT: [[I0:%.*]] = insertelement <2 x i32> undef, i32 [[Y:%.*]], i64 0 ; CHECK-NEXT: [[I0:%.*]] = insertelement <2 x i32> poison, i32 [[Y:%.*]], i64 0
; CHECK-NEXT: [[I1:%.*]] = insertelement <2 x i32> [[I0]], i32 [[Z:%.*]], i64 1 ; CHECK-NEXT: [[I1:%.*]] = insertelement <2 x i32> [[I0]], i32 [[Z:%.*]], i64 1
; CHECK-NEXT: [[A:%.*]] = sdiv <2 x i32> [[I1]], <i32 255, i32 255> ; CHECK-NEXT: [[A:%.*]] = sdiv <2 x i32> [[I1]], <i32 255, i32 255>
; CHECK-NEXT: [[EXT:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> undef, <3 x i32> <i32 0, i32 1, i32 poison> ; CHECK-NEXT: [[EXT:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> poison, <3 x i32> <i32 0, i32 1, i32 poison>
; CHECK-NEXT: ret <3 x i32> [[EXT]] ; CHECK-NEXT: ret <3 x i32> [[EXT]]
; ;
%i0 = insertelement <2 x i32> undef, i32 %y, i32 0 %i0 = insertelement <2 x i32> undef, i32 %y, i32 0
%i1 = insertelement <2 x i32> %i0, i32 %z, i32 1 %i1 = insertelement <2 x i32> %i0, i32 %z, i32 1
%a = sdiv <2 x i32> %i1, <i32 255, i32 255> %a = sdiv <2 x i32> %i1, <i32 255, i32 255>
%ext = shufflevector <2 x i32> %a, <2 x i32> undef, <3 x i32> <i32 0, i32 1, i32 undef> %ext = shufflevector <2 x i32> %a, <2 x i32> undef, <3 x i32> <i32 0, i32 1, i32 undef>
ret <3 x i32> %ext ret <3 x i32> %ext
} }
; Increasing length of insertelements (no math ops) is a good canonicalization. ; Increasing length of insertelements (no math ops) is a good canonicalization.
define <3 x i8> @fold_inselts_with_widening_shuffle(i8 %x, i8 %y) { define <3 x i8> @fold_inselts_with_widening_shuffle(i8 %x, i8 %y) {
; CHECK-LABEL: @fold_inselts_with_widening_shuffle( ; CHECK-LABEL: @fold_inselts_with_widening_shuffle(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i8> undef, i8 [[X:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <3 x i8> <i8 poison, i8 poison, i8 undef>, i8 [[X:%.*]], i64 0
; CHECK-NEXT: [[WIDEN:%.*]] = insertelement <3 x i8> [[TMP1]], i8 [[Y:%.*]], i64 1 ; CHECK-NEXT: [[WIDEN:%.*]] = insertelement <3 x i8> [[TMP1]], i8 [[Y:%.*]], i64 1
; CHECK-NEXT: ret <3 x i8> [[WIDEN]] ; CHECK-NEXT: ret <3 x i8> [[WIDEN]]
; ;
%ins0 = insertelement <2 x i8> undef, i8 %x, i32 0 %ins0 = insertelement <2 x i8> undef, i8 %x, i32 0
%ins1 = insertelement <2 x i8> %ins0, i8 %y, i32 1 %ins1 = insertelement <2 x i8> %ins0, i8 %y, i32 1
%widen = shufflevector <2 x i8> %ins1, <2 x i8> undef, <3 x i32> <i32 0, i32 1, i32 undef> %widen = shufflevector <2 x i8> %ins1, <2 x i8> undef, <3 x i32> <i32 0, i32 1, i32 undef>
ret <3 x i8> %widen ret <3 x i8> %widen
} }
define <2 x i8> @test13b(i8 %x) { define <2 x i8> @test13b(i8 %x) {
; CHECK-LABEL: @test13b( ; CHECK-LABEL: @test13b(
; CHECK-NEXT: [[B:%.*]] = insertelement <2 x i8> undef, i8 [[X:%.*]], i64 1 ; CHECK-NEXT: [[B:%.*]] = insertelement <2 x i8> poison, i8 [[X:%.*]], i64 1
; CHECK-NEXT: ret <2 x i8> [[B]] ; CHECK-NEXT: ret <2 x i8> [[B]]
; ;
%A = insertelement <2 x i8> undef, i8 %x, i32 0 %A = insertelement <2 x i8> undef, i8 %x, i32 0
%B = shufflevector <2 x i8> %A, <2 x i8> undef, <2 x i32> <i32 undef, i32 0> %B = shufflevector <2 x i8> %A, <2 x i8> undef, <2 x i32> <i32 undef, i32 0>
ret <2 x i8> %B ret <2 x i8> %B
} }
define <2 x i8> @test13c(i8 %x1, i8 %x2) { define <2 x i8> @test13c(i8 %x1, i8 %x2) {
; CHECK-LABEL: @test13c( ; CHECK-LABEL: @test13c(
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> undef, i8 [[X1:%.*]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> poison, i8 [[X1:%.*]], i64 0
; CHECK-NEXT: [[C:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X2:%.*]], i64 1 ; CHECK-NEXT: [[C:%.*]] = insertelement <2 x i8> [[TMP1]], i8 [[X2:%.*]], i64 1
; CHECK-NEXT: ret <2 x i8> [[C]] ; CHECK-NEXT: ret <2 x i8> [[C]]
; ;
%A = insertelement <4 x i8> undef, i8 %x1, i32 0 %A = insertelement <4 x i8> undef, i8 %x1, i32 0
%B = insertelement <4 x i8> %A, i8 %x2, i32 2 %B = insertelement <4 x i8> %A, i8 %x2, i32 2
%C = shufflevector <4 x i8> %B, <4 x i8> undef, <2 x i32> <i32 0, i32 2> %C = shufflevector <4 x i8> %B, <4 x i8> undef, <2 x i32> <i32 0, i32 2>
ret <2 x i8> %C ret <2 x i8> %C
} }
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%t3 = insertelement <4 x float> %RHS, float %t2, i32 1 %t3 = insertelement <4 x float> %RHS, float %t2, i32 1
%t4 = extractelement <4 x float> %RHS, i32 2 %t4 = extractelement <4 x float> %RHS, i32 2
%t5 = insertelement <4 x float> %t3, float %t4, i32 3 %t5 = insertelement <4 x float> %t3, float %t4, i32 3
ret <4 x float> %t5 ret <4 x float> %t5
} }
define <1 x i32> @test16a(i32 %ele) { define <1 x i32> @test16a(i32 %ele) {
; CHECK-LABEL: @test16a( ; CHECK-LABEL: @test16a(
; CHECK-NEXT: ret <1 x i32> <i32 2> ; CHECK-NEXT: [[T0:%.*]] = insertelement <2 x i32> <i32 1, i32 poison>, i32 [[ELE:%.*]], i64 1
; CHECK-NEXT: [[T1:%.*]] = shl <2 x i32> [[T0]], <i32 1, i32 1>
; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x i32> [[T1]], <2 x i32> undef, <1 x i32> zeroinitializer
; CHECK-NEXT: ret <1 x i32> [[T2]]
aqjuneUnsubmitted
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Do you have any idea about the reason of this regression?

aqjune: Do you have any idea about the reason of this regression?
; ;
%t0 = insertelement <2 x i32> <i32 1, i32 undef>, i32 %ele, i32 1 %t0 = insertelement <2 x i32> <i32 1, i32 undef>, i32 %ele, i32 1
%t1 = shl <2 x i32> %t0, <i32 1, i32 1> %t1 = shl <2 x i32> %t0, <i32 1, i32 1>
%t2 = shufflevector <2 x i32> %t1, <2 x i32> undef, <1 x i32> <i32 0> %t2 = shufflevector <2 x i32> %t1, <2 x i32> undef, <1 x i32> <i32 0>
ret <1 x i32> %t2 ret <1 x i32> %t2
} }
define <4 x i8> @test16b(i8 %ele) { define <4 x i8> @test16b(i8 %ele) {
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declare void @use(<2 x float>) declare void @use(<2 x float>)
declare void @use4(<4 x float>) declare void @use4(<4 x float>)
; One extra use is ok to transform. ; One extra use is ok to transform.
define <2 x float> @shuffle_fadd_multiuse(<2 x float> %v1, <2 x float> %v2) { define <2 x float> @shuffle_fadd_multiuse(<2 x float> %v1, <2 x float> %v2) {
; CHECK-LABEL: @shuffle_fadd_multiuse( ; CHECK-LABEL: @shuffle_fadd_multiuse(
; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x float> [[V1:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x float> [[V1:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x float> [[V1]], [[V2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = fadd <2 x float> [[V1]], [[V2:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: call void @use(<2 x float> [[T1]]) ; CHECK-NEXT: call void @use(<2 x float> [[T1]])
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%t1 = shufflevector <2 x float> %v1, <2 x float> undef, <2 x i32> <i32 1, i32 0> %t1 = shufflevector <2 x float> %v1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
%t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0> %t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0>
%r = fadd <2 x float> %t1, %t2 %r = fadd <2 x float> %t1, %t2
call void @use(<2 x float> %t1) call void @use(<2 x float> %t1)
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @shuffle_fdiv_multiuse(<2 x float> %v1, <2 x float> %v2) { define <2 x float> @shuffle_fdiv_multiuse(<2 x float> %v1, <2 x float> %v2) {
; CHECK-LABEL: @shuffle_fdiv_multiuse( ; CHECK-LABEL: @shuffle_fdiv_multiuse(
; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x float> [[V2:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x float> [[V2:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[TMP1:%.*]] = fdiv <2 x float> [[V1:%.*]], [[V2]] ; CHECK-NEXT: [[TMP1:%.*]] = fdiv <2 x float> [[V1:%.*]], [[V2]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: call void @use(<2 x float> [[T2]]) ; CHECK-NEXT: call void @use(<2 x float> [[T2]])
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%t1 = shufflevector <2 x float> %v1, <2 x float> undef, <2 x i32> <i32 1, i32 0> %t1 = shufflevector <2 x float> %v1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
%t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0> %t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0>
%r = fdiv <2 x float> %t1, %t2 %r = fdiv <2 x float> %t1, %t2
call void @use(<2 x float> %t2) call void @use(<2 x float> %t2)
ret <2 x float> %r ret <2 x float> %r
} }
; But 2 extra uses would require an extra instruction. ; But 2 extra uses would require an extra instruction.
define <2 x float> @shuffle_fsub_multiuse(<2 x float> %v1, <2 x float> %v2) { define <2 x float> @shuffle_fsub_multiuse(<2 x float> %v1, <2 x float> %v2) {
; CHECK-LABEL: @shuffle_fsub_multiuse( ; CHECK-LABEL: @shuffle_fsub_multiuse(
; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x float> [[V1:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x float> [[V1:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x float> [[V2:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[T2:%.*]] = shufflevector <2 x float> [[V2:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[R:%.*]] = fsub <2 x float> [[T1]], [[T2]] ; CHECK-NEXT: [[R:%.*]] = fsub <2 x float> [[T1]], [[T2]]
; CHECK-NEXT: call void @use(<2 x float> [[T1]]) ; CHECK-NEXT: call void @use(<2 x float> [[T1]])
; CHECK-NEXT: call void @use(<2 x float> [[T2]]) ; CHECK-NEXT: call void @use(<2 x float> [[T2]])
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%t1 = shufflevector <2 x float> %v1, <2 x float> undef, <2 x i32> <i32 1, i32 0> %t1 = shufflevector <2 x float> %v1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
%t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0> %t2 = shufflevector <2 x float> %v2, <2 x float> undef, <2 x i32> <i32 1, i32 0>
%r = fsub <2 x float> %t1, %t2 %r = fsub <2 x float> %t1, %t2
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%r = sub <4 x i32> <i32 41, i32 42, i32 43, i32 44>, %t1 %r = sub <4 x i32> <i32 41, i32 42, i32 43, i32 44>, %t1
ret <4 x i32> %r ret <4 x i32> %r
} }
; Math before shuffle requires an extra shuffle. ; Math before shuffle requires an extra shuffle.
define <2 x float> @fadd_const_multiuse(<2 x float> %v) { define <2 x float> @fadd_const_multiuse(<2 x float> %v) {
; CHECK-LABEL: @fadd_const_multiuse( ; CHECK-LABEL: @fadd_const_multiuse(
; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x float> [[V:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 0> ; CHECK-NEXT: [[T1:%.*]] = shufflevector <2 x float> [[V:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 0>
; CHECK-NEXT: [[R:%.*]] = fadd <2 x float> [[T1]], <float 4.100000e+01, float 4.200000e+01> ; CHECK-NEXT: [[R:%.*]] = fadd <2 x float> [[T1]], <float 4.100000e+01, float 4.200000e+01>
; CHECK-NEXT: call void @use(<2 x float> [[T1]]) ; CHECK-NEXT: call void @use(<2 x float> [[T1]])
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%t1 = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> <i32 1, i32 0> %t1 = shufflevector <2 x float> %v, <2 x float> undef, <2 x i32> <i32 1, i32 0>
%r = fadd <2 x float> %t1, <float 41.0, float 42.0> %r = fadd <2 x float> %t1, <float 41.0, float 42.0>
call void @use(<2 x float> %t1) call void @use(<2 x float> %t1)
ret <2 x float> %r ret <2 x float> %r
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%r = add <4 x i8> %widex, <i8 42, i8 43, i8 44, i8 45> %r = add <4 x i8> %widex, <i8 42, i8 43, i8 44, i8 45>
ret <4 x i8> %r ret <4 x i8> %r
} }
; Negative test - widening shuffles have the same mask/constant constraint as non-size-changing shuffles. ; Negative test - widening shuffles have the same mask/constant constraint as non-size-changing shuffles.
define <4 x i8> @widening_shuffle_add_invalid_constant(<2 x i8> %x) { define <4 x i8> @widening_shuffle_add_invalid_constant(<2 x i8> %x) {
; CHECK-LABEL: @widening_shuffle_add_invalid_constant( ; CHECK-LABEL: @widening_shuffle_add_invalid_constant(
; CHECK-NEXT: [[WIDEX:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 1, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[WIDEX:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> poison, <4 x i32> <i32 1, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[R:%.*]] = add <4 x i8> [[WIDEX]], <i8 42, i8 43, i8 44, i8 45> ; CHECK-NEXT: [[R:%.*]] = add <4 x i8> [[WIDEX]], <i8 42, i8 43, i8 44, i8 45>
; CHECK-NEXT: ret <4 x i8> [[R]] ; CHECK-NEXT: ret <4 x i8> [[R]]
; ;
%widex = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 1, i32 1, i32 undef, i32 undef> %widex = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 1, i32 1, i32 undef, i32 undef>
%r = add <4 x i8> %widex, <i8 42, i8 43, i8 44, i8 45> %r = add <4 x i8> %widex, <i8 42, i8 43, i8 44, i8 45>
ret <4 x i8> %r ret <4 x i8> %r
} }
; Negative test - widening shuffles have an additional constraint: they must not extend with anything but undefs. ; Negative test - widening shuffles have an additional constraint: they must not extend with anything but undefs.
define <4 x i8> @widening_shuffle_add_invalid_mask(<2 x i8> %x) { define <4 x i8> @widening_shuffle_add_invalid_mask(<2 x i8> %x) {
; CHECK-LABEL: @widening_shuffle_add_invalid_mask( ; CHECK-LABEL: @widening_shuffle_add_invalid_mask(
; CHECK-NEXT: [[WIDEX:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 0> ; CHECK-NEXT: [[WIDEX:%.*]] = shufflevector <2 x i8> [[X:%.*]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 0>
; CHECK-NEXT: [[R:%.*]] = add <4 x i8> [[WIDEX]], <i8 42, i8 43, i8 44, i8 45> ; CHECK-NEXT: [[R:%.*]] = add <4 x i8> [[WIDEX]], <i8 42, i8 43, i8 44, i8 45>
; CHECK-NEXT: ret <4 x i8> [[R]] ; CHECK-NEXT: ret <4 x i8> [[R]]
; ;
%widex = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 0> %widex = shufflevector <2 x i8> %x, <2 x i8> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 0>
%r = add <4 x i8> %widex, <i8 42, i8 43, i8 44, i8 45> %r = add <4 x i8> %widex, <i8 42, i8 43, i8 44, i8 45>
ret <4 x i8> %r ret <4 x i8> %r
} }
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ret <4 x i16> %bo ret <4 x i16> %bo
} }
; A binop that does not produce undef in the high lanes can not be moved before the shuffle. ; A binop that does not produce undef in the high lanes can not be moved before the shuffle.
; This is not ok because 'shl undef, 1 (or 2)' --> 0' but moving the shuffle results in undef instead. ; This is not ok because 'shl undef, 1 (or 2)' --> 0' but moving the shuffle results in undef instead.
define <4 x i16> @widening_shuffle_shl_constant_op1_non0(<2 x i16> %v) { define <4 x i16> @widening_shuffle_shl_constant_op1_non0(<2 x i16> %v) {
; CHECK-LABEL: @widening_shuffle_shl_constant_op1_non0( ; CHECK-LABEL: @widening_shuffle_shl_constant_op1_non0(
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i16> [[V:%.*]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i16> [[V:%.*]], <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[BO:%.*]] = shl <4 x i16> [[SHUF]], <i16 2, i16 4, i16 1, i16 2> ; CHECK-NEXT: [[BO:%.*]] = shl <4 x i16> [[SHUF]], <i16 2, i16 4, i16 1, i16 2>
; CHECK-NEXT: ret <4 x i16> [[BO]] ; CHECK-NEXT: ret <4 x i16> [[BO]]
; ;
%shuf = shufflevector <2 x i16> %v, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %shuf = shufflevector <2 x i16> %v, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%bo = shl <4 x i16> %shuf, <i16 2, i16 4, i16 1, i16 2> %bo = shl <4 x i16> %shuf, <i16 2, i16 4, i16 1, i16 2>
ret <4 x i16> %bo ret <4 x i16> %bo
} }
; A binop that does not produce undef in the high lanes can not be moved before the shuffle. ; A binop that does not produce undef in the high lanes can not be moved before the shuffle.
; This is not ok because 'or -1, undef --> -1' but moving the shuffle results in undef instead. ; This is not ok because 'or -1, undef --> -1' but moving the shuffle results in undef instead.
define <4 x i16> @widening_shuffle_or(<2 x i16> %v) { define <4 x i16> @widening_shuffle_or(<2 x i16> %v) {
; CHECK-LABEL: @widening_shuffle_or( ; CHECK-LABEL: @widening_shuffle_or(
; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i16> [[V:%.*]], <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[SHUF:%.*]] = shufflevector <2 x i16> [[V:%.*]], <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[BO:%.*]] = or <4 x i16> [[SHUF]], <i16 42, i16 -42, i16 -1, i16 -1> ; CHECK-NEXT: [[BO:%.*]] = or <4 x i16> [[SHUF]], <i16 42, i16 -42, i16 -1, i16 -1>
; CHECK-NEXT: ret <4 x i16> [[BO]] ; CHECK-NEXT: ret <4 x i16> [[BO]]
; ;
%shuf = shufflevector <2 x i16> %v, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %shuf = shufflevector <2 x i16> %v, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%bo = or <4 x i16> %shuf, <i16 42, i16 -42, i16 -1, i16 -1> %bo = or <4 x i16> %shuf, <i16 42, i16 -42, i16 -1, i16 -1>
ret <4 x i16> %bo ret <4 x i16> %bo
} }
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%shuffle = shufflevector <8 x i16> %in0, <8 x i16> %in0, <4 x i32> <i32 5, i32 5, i32 5, i32 5> %shuffle = shufflevector <8 x i16> %in0, <8 x i16> %in0, <4 x i32> <i32 5, i32 5, i32 5, i32 5>
%shuffle1 = shufflevector <8 x i16> %in1, <8 x i16> %in1, <4 x i32> <i32 5, i32 5, i32 5, i32 5> %shuffle1 = shufflevector <8 x i16> %in1, <8 x i16> %in1, <4 x i32> <i32 5, i32 5, i32 5, i32 5>
%mul = mul <4 x i16> %shuffle, %shuffle1 %mul = mul <4 x i16> %shuffle, %shuffle1
ret <4 x i16> %mul ret <4 x i16> %mul
} }
define <8 x i8> @pr19730(<16 x i8> %in0) { define <8 x i8> @pr19730(<16 x i8> %in0) {
; CHECK-LABEL: @pr19730( ; CHECK-LABEL: @pr19730(
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <16 x i8> [[IN0:%.*]], <16 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <16 x i8> [[IN0:%.*]], <16 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <8 x i8> [[SHUFFLE]], <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> ; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <8 x i8> [[SHUFFLE]], <8 x i8> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
; CHECK-NEXT: ret <8 x i8> [[SHUFFLE1]] ; CHECK-NEXT: ret <8 x i8> [[SHUFFLE1]]
; ;
%shuffle = shufflevector <16 x i8> %in0, <16 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %shuffle = shufflevector <16 x i8> %in0, <16 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
%shuffle1 = shufflevector <8 x i8> %shuffle, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %shuffle1 = shufflevector <8 x i8> %shuffle, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <8 x i8> %shuffle1 ret <8 x i8> %shuffle1
} }
define i32 @pr19737(<4 x i32> %in0) { define i32 @pr19737(<4 x i32> %in0) {
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%splat1 = shufflevector <4 x i32> %p1, <4 x i32> undef, <4 x i32> zeroinitializer %splat1 = shufflevector <4 x i32> %p1, <4 x i32> undef, <4 x i32> zeroinitializer
%splat2 = shufflevector <4 x i32> %p2, <4 x i32> undef, <4 x i32> zeroinitializer %splat2 = shufflevector <4 x i32> %p2, <4 x i32> undef, <4 x i32> zeroinitializer
%retval = srem <4 x i32> %splat1, %splat2 %retval = srem <4 x i32> %splat1, %splat2
ret <4 x i32> %retval ret <4 x i32> %retval
} }
define <4 x i32> @pr20114(<4 x i32> %__mask) { define <4 x i32> @pr20114(<4 x i32> %__mask) {
; CHECK-LABEL: @pr20114( ; CHECK-LABEL: @pr20114(
; CHECK-NEXT: [[MASK01_I:%.*]] = shufflevector <4 x i32> [[__MASK:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1> ; CHECK-NEXT: [[MASK01_I:%.*]] = shufflevector <4 x i32> [[__MASK:%.*]], <4 x i32> poison, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
; CHECK-NEXT: [[MASKED_NEW_I_I_I:%.*]] = and <4 x i32> [[MASK01_I]], bitcast (<2 x i64> <i64 ptrtoint (ptr @pr20114 to i64), i64 ptrtoint (ptr @pr20114 to i64)> to <4 x i32>) ; CHECK-NEXT: [[MASKED_NEW_I_I_I:%.*]] = and <4 x i32> [[MASK01_I]], bitcast (<2 x i64> <i64 ptrtoint (ptr @pr20114 to i64), i64 ptrtoint (ptr @pr20114 to i64)> to <4 x i32>)
; CHECK-NEXT: ret <4 x i32> [[MASKED_NEW_I_I_I]] ; CHECK-NEXT: ret <4 x i32> [[MASKED_NEW_I_I_I]]
; ;
%mask01.i = shufflevector <4 x i32> %__mask, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1> %mask01.i = shufflevector <4 x i32> %__mask, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
%masked_new.i.i.i = and <4 x i32> bitcast (<2 x i64> <i64 ptrtoint (ptr @pr20114 to i64), i64 ptrtoint (ptr @pr20114 to i64)> to <4 x i32>), %mask01.i %masked_new.i.i.i = and <4 x i32> bitcast (<2 x i64> <i64 ptrtoint (ptr @pr20114 to i64), i64 ptrtoint (ptr @pr20114 to i64)> to <4 x i32>), %mask01.i
ret <4 x i32> %masked_new.i.i.i ret <4 x i32> %masked_new.i.i.i
} }
define <2 x ptr> @pr23113(<4 x ptr> %A) { define <2 x ptr> @pr23113(<4 x ptr> %A) {
; CHECK-LABEL: @pr23113( ; CHECK-LABEL: @pr23113(
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x ptr> [[A:%.*]], <4 x ptr> undef, <2 x i32> <i32 0, i32 1> ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x ptr> [[A:%.*]], <4 x ptr> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: ret <2 x ptr> [[TMP1]] ; CHECK-NEXT: ret <2 x ptr> [[TMP1]]
; ;
%1 = shufflevector <4 x ptr> %A, <4 x ptr> undef, <2 x i32> <i32 0, i32 1> %1 = shufflevector <4 x ptr> %A, <4 x ptr> undef, <2 x i32> <i32 0, i32 1>
ret <2 x ptr> %1 ret <2 x ptr> %1
} }
; Unused lanes in the new binop should not kill the entire op (although it may simplify anyway as shown here). ; Unused lanes in the new binop should not kill the entire op (although it may simplify anyway as shown here).
define <2 x i32> @PR37648(<2 x i32> %x) { define <2 x i32> @PR37648(<2 x i32> %x) {
; CHECK-LABEL: @PR37648( ; CHECK-LABEL: @PR37648(
; CHECK-NEXT: ret <2 x i32> zeroinitializer ; CHECK-NEXT: ret <2 x i32> zeroinitializer
; ;
%splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
%r = urem <2 x i32> %splat, <i32 1, i32 1> %r = urem <2 x i32> %splat, <i32 1, i32 1>
ret <2 x i32> %r ret <2 x i32> %r
} }
; Test shuffle followed by binop with splat constant for all 18 binop opcodes. ; Test shuffle followed by binop with splat constant for all 18 binop opcodes.
; Test with constant as operand 0 and operand 1 for non-commutative opcodes. ; Test with constant as operand 0 and operand 1 for non-commutative opcodes.
define <2 x i32> @add_splat_constant(<2 x i32> %x) { define <2 x i32> @add_splat_constant(<2 x i32> %x) {
; CHECK-LABEL: @add_splat_constant( ; CHECK-LABEL: @add_splat_constant(
; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 42, i32 poison> ; CHECK-NEXT: [[TMP1:%.*]] = add <2 x i32> [[X:%.*]], <i32 42, i32 poison>
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[R]] ; CHECK-NEXT: ret <2 x i32> [[R]]
; ;
%splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
%r = add <2 x i32> %splat, <i32 42, i32 42> %r = add <2 x i32> %splat, <i32 42, i32 42>
ret <2 x i32> %r ret <2 x i32> %r
} }
define <2 x i32> @sub_splat_constant0(<2 x i32> %x) { define <2 x i32> @sub_splat_constant0(<2 x i32> %x) {
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%splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
%r = mul <2 x i32> %splat, <i32 42, i32 42> %r = mul <2 x i32> %splat, <i32 42, i32 42>
ret <2 x i32> %r ret <2 x i32> %r
} }
define <2 x i32> @shl_splat_constant0(<2 x i32> %x) { define <2 x i32> @shl_splat_constant0(<2 x i32> %x) {
; CHECK-LABEL: @shl_splat_constant0( ; CHECK-LABEL: @shl_splat_constant0(
; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> <i32 5, i32 undef>, [[X:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> <i32 5, i32 undef>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[R]] ; CHECK-NEXT: ret <2 x i32> [[R]]
; ;
%splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
%r = shl <2 x i32> <i32 5, i32 5>, %splat %r = shl <2 x i32> <i32 5, i32 5>, %splat
ret <2 x i32> %r ret <2 x i32> %r
} }
define <2 x i32> @shl_splat_constant1(<2 x i32> %x) { define <2 x i32> @shl_splat_constant1(<2 x i32> %x) {
; CHECK-LABEL: @shl_splat_constant1( ; CHECK-LABEL: @shl_splat_constant1(
; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 5, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = shl <2 x i32> [[X:%.*]], <i32 5, i32 0>
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[R]] ; CHECK-NEXT: ret <2 x i32> [[R]]
; ;
%splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
%r = shl <2 x i32> %splat, <i32 5, i32 5> %r = shl <2 x i32> %splat, <i32 5, i32 5>
ret <2 x i32> %r ret <2 x i32> %r
} }
define <2 x i32> @ashr_splat_constant0(<2 x i32> %x) { define <2 x i32> @ashr_splat_constant0(<2 x i32> %x) {
; CHECK-LABEL: @ashr_splat_constant0( ; CHECK-LABEL: @ashr_splat_constant0(
; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> <i32 5, i32 undef>, [[X:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> <i32 5, i32 undef>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[R]] ; CHECK-NEXT: ret <2 x i32> [[R]]
; ;
%splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
%r = ashr <2 x i32> <i32 5, i32 5>, %splat %r = ashr <2 x i32> <i32 5, i32 5>, %splat
ret <2 x i32> %r ret <2 x i32> %r
} }
define <2 x i32> @ashr_splat_constant1(<2 x i32> %x) { define <2 x i32> @ashr_splat_constant1(<2 x i32> %x) {
; CHECK-LABEL: @ashr_splat_constant1( ; CHECK-LABEL: @ashr_splat_constant1(
; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 5, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i32> [[X:%.*]], <i32 5, i32 0>
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[R]] ; CHECK-NEXT: ret <2 x i32> [[R]]
; ;
%splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
%r = ashr <2 x i32> %splat, <i32 5, i32 5> %r = ashr <2 x i32> %splat, <i32 5, i32 5>
ret <2 x i32> %r ret <2 x i32> %r
} }
define <2 x i32> @lshr_splat_constant0(<2 x i32> %x) { define <2 x i32> @lshr_splat_constant0(<2 x i32> %x) {
; CHECK-LABEL: @lshr_splat_constant0( ; CHECK-LABEL: @lshr_splat_constant0(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> <i32 5, i32 undef>, [[X:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> <i32 5, i32 undef>, [[X:%.*]]
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[R]] ; CHECK-NEXT: ret <2 x i32> [[R]]
; ;
%splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
%r = lshr <2 x i32> <i32 5, i32 5>, %splat %r = lshr <2 x i32> <i32 5, i32 5>, %splat
ret <2 x i32> %r ret <2 x i32> %r
} }
define <2 x i32> @lshr_splat_constant1(<2 x i32> %x) { define <2 x i32> @lshr_splat_constant1(<2 x i32> %x) {
; CHECK-LABEL: @lshr_splat_constant1( ; CHECK-LABEL: @lshr_splat_constant1(
; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 5, i32 0> ; CHECK-NEXT: [[TMP1:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 5, i32 0>
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[R]] ; CHECK-NEXT: ret <2 x i32> [[R]]
; ;
%splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x i32> %x, <2 x i32> undef, <2 x i32> zeroinitializer
%r = lshr <2 x i32> %splat, <i32 5, i32 5> %r = lshr <2 x i32> %splat, <i32 5, i32 5>
ret <2 x i32> %r ret <2 x i32> %r
} }
define <2 x i32> @urem_splat_constant0(<2 x i32> %x) { define <2 x i32> @urem_splat_constant0(<2 x i32> %x) {
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ret <2 x i32> %r ret <2 x i32> %r
} }
; AND does not fold to undef for undef operands, we cannot move it ; AND does not fold to undef for undef operands, we cannot move it
; across a shuffle with undef masks. ; across a shuffle with undef masks.
define <4 x i16> @and_constant_mask_undef(<4 x i16> %add) { define <4 x i16> @and_constant_mask_undef(<4 x i16> %add) {
; CHECK-LABEL: @and_constant_mask_undef( ; CHECK-LABEL: @and_constant_mask_undef(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[ADD:%.*]], <4 x i16> undef, <4 x i32> <i32 poison, i32 poison, i32 1, i32 1> ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[ADD:%.*]], <4 x i16> poison, <4 x i32> <i32 poison, i32 poison, i32 1, i32 1>
; CHECK-NEXT: [[AND:%.*]] = and <4 x i16> [[SHUFFLE]], <i16 0, i16 0, i16 -1, i16 -1> ; CHECK-NEXT: [[AND:%.*]] = and <4 x i16> [[SHUFFLE]], <i16 0, i16 0, i16 -1, i16 -1>
; CHECK-NEXT: ret <4 x i16> [[AND]] ; CHECK-NEXT: ret <4 x i16> [[AND]]
; ;
entry: entry:
%shuffle = shufflevector <4 x i16> %add, <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1> %shuffle = shufflevector <4 x i16> %add, <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1>
%and = and <4 x i16> %shuffle, <i16 0, i16 0, i16 -1, i16 -1> %and = and <4 x i16> %shuffle, <i16 0, i16 0, i16 -1, i16 -1>
ret <4 x i16> %and ret <4 x i16> %and
} }
; AND does not fold to undef for undef operands, we cannot move it ; AND does not fold to undef for undef operands, we cannot move it
; across a shuffle with undef masks. ; across a shuffle with undef masks.
define <4 x i16> @and_constant_mask_undef_2(<4 x i16> %add) { define <4 x i16> @and_constant_mask_undef_2(<4 x i16> %add) {
; CHECK-LABEL: @and_constant_mask_undef_2( ; CHECK-LABEL: @and_constant_mask_undef_2(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[ADD:%.*]], <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 poison> ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[ADD:%.*]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 poison>
; CHECK-NEXT: [[AND:%.*]] = and <4 x i16> [[SHUFFLE]], <i16 -1, i16 -1, i16 -1, i16 0> ; CHECK-NEXT: [[AND:%.*]] = and <4 x i16> [[SHUFFLE]], <i16 -1, i16 -1, i16 -1, i16 0>
; CHECK-NEXT: ret <4 x i16> [[AND]] ; CHECK-NEXT: ret <4 x i16> [[AND]]
; ;
entry: entry:
%shuffle = shufflevector <4 x i16> %add, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 undef> %shuffle = shufflevector <4 x i16> %add, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 undef>
%and = and <4 x i16> %shuffle, <i16 -1, i16 -1, i16 -1, i16 -0> %and = and <4 x i16> %shuffle, <i16 -1, i16 -1, i16 -1, i16 -0>
ret <4 x i16> %and ret <4 x i16> %and
} }
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ret <4 x i16> %and ret <4 x i16> %and
} }
; OR does not fold to undef for undef operands, we cannot move it ; OR does not fold to undef for undef operands, we cannot move it
; across a shuffle with undef masks. ; across a shuffle with undef masks.
define <4 x i16> @or_constant_mask_undef(<4 x i16> %in) { define <4 x i16> @or_constant_mask_undef(<4 x i16> %in) {
; CHECK-LABEL: @or_constant_mask_undef( ; CHECK-LABEL: @or_constant_mask_undef(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[IN:%.*]], <4 x i16> undef, <4 x i32> <i32 poison, i32 poison, i32 1, i32 1> ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[IN:%.*]], <4 x i16> poison, <4 x i32> <i32 poison, i32 poison, i32 1, i32 1>
; CHECK-NEXT: [[OR:%.*]] = or <4 x i16> [[SHUFFLE]], <i16 -1, i16 -1, i16 0, i16 0> ; CHECK-NEXT: [[OR:%.*]] = or <4 x i16> [[SHUFFLE]], <i16 -1, i16 -1, i16 0, i16 0>
; CHECK-NEXT: ret <4 x i16> [[OR]] ; CHECK-NEXT: ret <4 x i16> [[OR]]
; ;
entry: entry:
%shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1> %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 1>
%or = or <4 x i16> %shuffle, <i16 -1, i16 -1, i16 0, i16 0> %or = or <4 x i16> %shuffle, <i16 -1, i16 -1, i16 0, i16 0>
ret <4 x i16> %or ret <4 x i16> %or
} }
; OR does not fold to undef for undef operands, we cannot move it ; OR does not fold to undef for undef operands, we cannot move it
; across a shuffle with undef masks. ; across a shuffle with undef masks.
define <4 x i16> @or_constant_mask_undef_2(<4 x i16> %in) { define <4 x i16> @or_constant_mask_undef_2(<4 x i16> %in) {
; CHECK-LABEL: @or_constant_mask_undef_2( ; CHECK-LABEL: @or_constant_mask_undef_2(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[IN:%.*]], <4 x i16> undef, <4 x i32> <i32 poison, i32 1, i32 1, i32 poison> ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[IN:%.*]], <4 x i16> poison, <4 x i32> <i32 poison, i32 1, i32 1, i32 poison>
; CHECK-NEXT: [[OR:%.*]] = or <4 x i16> [[SHUFFLE]], <i16 -1, i16 0, i16 0, i16 -1> ; CHECK-NEXT: [[OR:%.*]] = or <4 x i16> [[SHUFFLE]], <i16 -1, i16 0, i16 0, i16 -1>
; CHECK-NEXT: ret <4 x i16> [[OR]] ; CHECK-NEXT: ret <4 x i16> [[OR]]
; ;
entry: entry:
%shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef> %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 undef, i32 1, i32 1, i32 undef>
%or = or <4 x i16> %shuffle, <i16 -1, i16 0, i16 0, i16 -1> %or = or <4 x i16> %shuffle, <i16 -1, i16 0, i16 0, i16 -1>
ret <4 x i16> %or ret <4 x i16> %or
} }
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%shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 1> %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 1>
%and = or <4 x i16> %shuffle, <i16 0, i16 0, i16 -1, i16 -1> %and = or <4 x i16> %shuffle, <i16 0, i16 0, i16 -1, i16 -1>
ret <4 x i16> %and ret <4 x i16> %and
} }
define <4 x i16> @shl_constant_mask_undef(<4 x i16> %in) { define <4 x i16> @shl_constant_mask_undef(<4 x i16> %in) {
; CHECK-LABEL: @shl_constant_mask_undef( ; CHECK-LABEL: @shl_constant_mask_undef(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[IN:%.*]], <4 x i16> undef, <4 x i32> <i32 0, i32 poison, i32 1, i32 1> ; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[IN:%.*]], <4 x i16> poison, <4 x i32> <i32 0, i32 poison, i32 1, i32 1>
; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i16> [[SHUFFLE]], <i16 10, i16 3, i16 0, i16 0> ; CHECK-NEXT: [[SHL:%.*]] = shl <4 x i16> [[SHUFFLE]], <i16 10, i16 3, i16 0, i16 0>
; CHECK-NEXT: ret <4 x i16> [[SHL]] ; CHECK-NEXT: ret <4 x i16> [[SHL]]
; ;
entry: entry:
%shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 0, i32 undef, i32 1, i32 1> %shuffle = shufflevector <4 x i16> %in, <4 x i16> undef, <4 x i32> <i32 0, i32 undef, i32 1, i32 1>
%shl = shl <4 x i16> %shuffle, <i16 10, i16 3, i16 0, i16 0> %shl = shl <4 x i16> %shuffle, <i16 10, i16 3, i16 0, i16 0>
ret <4 x i16> %shl ret <4 x i16> %shl
} }
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%splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
%r = fsub <2 x float> <float -0.0, float -0.0>, %splat %r = fsub <2 x float> <float -0.0, float -0.0>, %splat
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @fmul_splat_constant(<2 x float> %x) { define <2 x float> @fmul_splat_constant(<2 x float> %x) {
; CHECK-LABEL: @fmul_splat_constant( ; CHECK-LABEL: @fmul_splat_constant(
; CHECK-NEXT: [[TMP1:%.*]] = fmul <2 x float> [[X:%.*]], <float 4.200000e+01, float poison> ; CHECK-NEXT: [[TMP1:%.*]] = fmul <2 x float> [[X:%.*]], <float 4.200000e+01, float poison>
; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> poison, <2 x i32> zeroinitializer
nlopesUnsubmitted
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Why does it regress here (goes from poison to undef)?

nlopes: Why does it regress here (goes from poison to undef)?
ManuelJBritoAuthorUnsubmitted
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This regression is due to the change in foldVectorBinop in InstructionCombining.cpp
It seems that without this canonicalization, demanded elements doesn't trigger causing the regression.

I changed it to match poison instead of undef, because of the following:

shufflevector < 4 x i32 > %1, < 4 x i32 > undef , <1, 2, 6, 7> --> shufflevector < 4 x i32 > %1, < 4 x i32 > undef , <1, 2, undef, undef>

Now we don't do this because it would insert poison.

Not simplifying the mask causes the following assert to fail:

assert(ShMask[I] < (int)NumElts && "Not expecting narrowing shuffle")
ManuelJBrito: This regression is due to the change in foldVectorBinop in InstructionCombining.cpp It seems…
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer %splat = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> zeroinitializer
%r = fmul <2 x float> %splat, <float 42.0, float 42.0> %r = fmul <2 x float> %splat, <float 42.0, float 42.0>
ret <2 x float> %r ret <2 x float> %r
} }
define <2 x float> @fdiv_splat_constant0(<2 x float> %x) { define <2 x float> @fdiv_splat_constant0(<2 x float> %x) {
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ret <2 x float> %r ret <2 x float> %r
} }
; Equivalent shuffle masks, but only one is a narrowing op. ; Equivalent shuffle masks, but only one is a narrowing op.
define <2 x i1> @PR40734(<1 x i1> %x, <4 x i1> %y) { define <2 x i1> @PR40734(<1 x i1> %x, <4 x i1> %y) {
; CHECK-LABEL: @PR40734( ; CHECK-LABEL: @PR40734(
; CHECK-NEXT: [[WIDEN:%.*]] = shufflevector <1 x i1> zeroinitializer, <1 x i1> [[X:%.*]], <2 x i32> <i32 0, i32 1> ; CHECK-NEXT: [[WIDEN:%.*]] = shufflevector <1 x i1> zeroinitializer, <1 x i1> [[X:%.*]], <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[NARROW:%.*]] = shufflevector <4 x i1> [[Y:%.*]], <4 x i1> undef, <2 x i32> <i32 0, i32 1> ; CHECK-NEXT: [[NARROW:%.*]] = shufflevector <4 x i1> [[Y:%.*]], <4 x i1> poison, <2 x i32> <i32 0, i32 1>
; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[WIDEN]], [[NARROW]] ; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[WIDEN]], [[NARROW]]
; CHECK-NEXT: ret <2 x i1> [[R]] ; CHECK-NEXT: ret <2 x i1> [[R]]
; ;
%widen = shufflevector <1 x i1> zeroinitializer, <1 x i1> %x, <2 x i32> <i32 0, i32 1> %widen = shufflevector <1 x i1> zeroinitializer, <1 x i1> %x, <2 x i32> <i32 0, i32 1>
%narrow = shufflevector <4 x i1> %y, <4 x i1> undef, <2 x i32> <i32 0, i32 1> %narrow = shufflevector <4 x i1> %y, <4 x i1> undef, <2 x i32> <i32 0, i32 1>
%r = and <2 x i1> %widen, %narrow %r = and <2 x i1> %widen, %narrow
ret <2 x i1> %r ret <2 x i1> %r
} }
; Negative test - do not transform non-power-of-2 unless we know the backend handles these sequences identically. ; Negative test - do not transform non-power-of-2 unless we know the backend handles these sequences identically.
define <7 x i8> @insert_subvector_shuffles(<3 x i8> %x, <3 x i8> %y) { define <7 x i8> @insert_subvector_shuffles(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @insert_subvector_shuffles( ; CHECK-LABEL: @insert_subvector_shuffles(
; CHECK-NEXT: [[S1:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> undef, <7 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> poison, <7 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[S2:%.*]] = shufflevector <3 x i8> [[Y:%.*]], <3 x i8> undef, <7 x i32> <i32 poison, i32 1, i32 2, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[S2:%.*]] = shufflevector <3 x i8> [[Y:%.*]], <3 x i8> poison, <7 x i32> <i32 poison, i32 1, i32 2, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[S3:%.*]] = shufflevector <7 x i8> [[S1]], <7 x i8> [[S2]], <7 x i32> <i32 0, i32 8, i32 1, i32 poison, i32 8, i32 1, i32 9> ; CHECK-NEXT: [[S3:%.*]] = shufflevector <7 x i8> [[S1]], <7 x i8> [[S2]], <7 x i32> <i32 0, i32 8, i32 1, i32 poison, i32 8, i32 1, i32 9>
; CHECK-NEXT: ret <7 x i8> [[S3]] ; CHECK-NEXT: ret <7 x i8> [[S3]]
; ;
%s1 = shufflevector <3 x i8> %x, <3 x i8> undef, <7 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %s1 = shufflevector <3 x i8> %x, <3 x i8> undef, <7 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s2 = shufflevector <3 x i8> %y, <3 x i8> undef, <7 x i32> <i32 undef, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef> %s2 = shufflevector <3 x i8> %y, <3 x i8> undef, <7 x i32> <i32 undef, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef>
%s3 = shufflevector <7 x i8> %s1, <7 x i8> %s2, <7 x i32> <i32 0, i32 8, i32 1, i32 undef, i32 8, i32 1, i32 9> %s3 = shufflevector <7 x i8> %s1, <7 x i8> %s2, <7 x i32> <i32 0, i32 8, i32 1, i32 undef, i32 8, i32 1, i32 9>
ret <7 x i8> %s3 ret <7 x i8> %s3
} }
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ret <8 x i8> %s3 ret <8 x i8> %s3
} }
; The last shuffle may change the vector type. ; The last shuffle may change the vector type.
; Negative test - do not transform non-power-of-2 unless we know the backend handles these sequences identically. ; Negative test - do not transform non-power-of-2 unless we know the backend handles these sequences identically.
define <2 x i8> @insert_subvector_shuffles_narrowing(<3 x i8> %x, <3 x i8> %y) { define <2 x i8> @insert_subvector_shuffles_narrowing(<3 x i8> %x, <3 x i8> %y) {
; CHECK-LABEL: @insert_subvector_shuffles_narrowing( ; CHECK-LABEL: @insert_subvector_shuffles_narrowing(
; CHECK-NEXT: [[S1:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> undef, <7 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> poison, <7 x i32> <i32 0, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[S2:%.*]] = shufflevector <3 x i8> [[Y:%.*]], <3 x i8> undef, <7 x i32> <i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[S2:%.*]] = shufflevector <3 x i8> [[Y:%.*]], <3 x i8> poison, <7 x i32> <i32 poison, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[S3:%.*]] = shufflevector <7 x i8> [[S1]], <7 x i8> [[S2]], <2 x i32> <i32 0, i32 8> ; CHECK-NEXT: [[S3:%.*]] = shufflevector <7 x i8> [[S1]], <7 x i8> [[S2]], <2 x i32> <i32 0, i32 8>
; CHECK-NEXT: ret <2 x i8> [[S3]] ; CHECK-NEXT: ret <2 x i8> [[S3]]
; ;
%s1 = shufflevector <3 x i8> %x, <3 x i8> undef, <7 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> %s1 = shufflevector <3 x i8> %x, <3 x i8> undef, <7 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%s2 = shufflevector <3 x i8> %y, <3 x i8> undef, <7 x i32> <i32 undef, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef> %s2 = shufflevector <3 x i8> %y, <3 x i8> undef, <7 x i32> <i32 undef, i32 1, i32 2, i32 undef, i32 undef, i32 undef, i32 undef>
%s3 = shufflevector <7 x i8> %s1, <7 x i8> %s2, <2 x i32> <i32 0, i32 8> %s3 = shufflevector <7 x i8> %s1, <7 x i8> %s2, <2 x i32> <i32 0, i32 8>
ret <2 x i8> %s3 ret <2 x i8> %s3
} }
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%s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef> %s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
ret <4 x double> %s3 ret <4 x double> %s3
} }
; Negative test - not identity with padding (although this could be folded with better analysis). ; Negative test - not identity with padding (although this could be folded with better analysis).
define <4 x double> @not_insert_subvector_shuffle(<2 x double> %x) { define <4 x double> @not_insert_subvector_shuffle(<2 x double> %x) {
; CHECK-LABEL: @not_insert_subvector_shuffle( ; CHECK-LABEL: @not_insert_subvector_shuffle(
; CHECK-NEXT: [[S1:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> undef, <4 x i32> <i32 poison, i32 1, i32 poison, i32 1> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> poison, <4 x i32> <i32 poison, i32 1, i32 poison, i32 1>
; CHECK-NEXT: [[S2:%.*]] = shufflevector <2 x double> [[X]], <2 x double> undef, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[S2:%.*]] = shufflevector <2 x double> [[X]], <2 x double> poison, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[S3:%.*]] = shufflevector <4 x double> [[S2]], <4 x double> [[S1]], <4 x i32> <i32 0, i32 5, i32 7, i32 poison> ; CHECK-NEXT: [[S3:%.*]] = shufflevector <4 x double> [[S2]], <4 x double> [[S1]], <4 x i32> <i32 0, i32 5, i32 7, i32 poison>
; CHECK-NEXT: ret <4 x double> [[S3]] ; CHECK-NEXT: ret <4 x double> [[S3]]
; ;
%s1 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 1> %s1 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 1>
%s2 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %s2 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
%s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 7, i32 undef> %s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 7, i32 undef>
ret <4 x double> %s3 ret <4 x double> %s3
} }
; Negative test - operands are not the same size (although this could be partly folded with better analysis). ; Negative test - operands are not the same size (although this could be partly folded with better analysis).
define <4 x double> @not_insert_subvector_shuffles_with_same_size(<2 x double> %x, <3 x double> %y) { define <4 x double> @not_insert_subvector_shuffles_with_same_size(<2 x double> %x, <3 x double> %y) {
; CHECK-LABEL: @not_insert_subvector_shuffles_with_same_size( ; CHECK-LABEL: @not_insert_subvector_shuffles_with_same_size(
; CHECK-NEXT: [[S1:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> undef, <4 x i32> <i32 poison, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[S1:%.*]] = shufflevector <2 x double> [[X:%.*]], <2 x double> poison, <4 x i32> <i32 poison, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[S2:%.*]] = shufflevector <3 x double> [[Y:%.*]], <3 x double> undef, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison> ; CHECK-NEXT: [[S2:%.*]] = shufflevector <3 x double> [[Y:%.*]], <3 x double> poison, <4 x i32> <i32 0, i32 poison, i32 poison, i32 poison>
; CHECK-NEXT: [[S3:%.*]] = shufflevector <4 x double> [[S2]], <4 x double> [[S1]], <4 x i32> <i32 0, i32 5, i32 poison, i32 poison> ; CHECK-NEXT: [[S3:%.*]] = shufflevector <4 x double> [[S2]], <4 x double> [[S1]], <4 x i32> <i32 0, i32 5, i32 poison, i32 poison>
; CHECK-NEXT: ret <4 x double> [[S3]] ; CHECK-NEXT: ret <4 x double> [[S3]]
; ;
%s1 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef> %s1 = shufflevector <2 x double> %x, <2 x double> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef>
%s2 = shufflevector <3 x double> %y, <3 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %s2 = shufflevector <3 x double> %y, <3 x double> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
%s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef> %s3 = shufflevector <4 x double> %s2, <4 x double> %s1, <4 x i32> <i32 0, i32 5, i32 undef, i32 undef>
ret <4 x double> %s3 ret <4 x double> %s3
} }
; Demanded vector elements may not be able to simplify a shuffle mask ; Demanded vector elements may not be able to simplify a shuffle mask
; before we try to narrow it. This used to crash. ; before we try to narrow it. This used to crash.
define <4 x float> @insert_subvector_crash_invalid_mask_elt(<2 x float> %x, ptr %p) { define <4 x float> @insert_subvector_crash_invalid_mask_elt(<2 x float> %x, ptr %p) {
; CHECK-LABEL: @insert_subvector_crash_invalid_mask_elt( ; CHECK-LABEL: @insert_subvector_crash_invalid_mask_elt(
; CHECK-NEXT: [[WIDEN:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[WIDEN:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[I:%.*]] = shufflevector <2 x float> [[X]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[I:%.*]] = shufflevector <2 x float> [[X]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: store <4 x float> [[I]], ptr [[P:%.*]], align 16 ; CHECK-NEXT: store <4 x float> [[I]], ptr [[P:%.*]], align 16
; CHECK-NEXT: ret <4 x float> [[WIDEN]] ; CHECK-NEXT: ret <4 x float> [[WIDEN]]
; ;
%widen = shufflevector <2 x float> %x, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> %widen = shufflevector <2 x float> %x, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
%ext2 = extractelement <2 x float> %x, i32 0 %ext2 = extractelement <2 x float> %x, i32 0
%I = insertelement <4 x float> %widen, float %ext2, i16 0 %I = insertelement <4 x float> %widen, float %ext2, i16 0
store <4 x float> %I, ptr %p store <4 x float> %I, ptr %p
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%splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> zeroinitializer %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> zeroinitializer
%a = add <4 x i32> %y, <i32 undef, i32 42, i32 undef, i32 42> %a = add <4 x i32> %y, <i32 undef, i32 42, i32 undef, i32 42>
%r = add <4 x i32> %splatx, %a %r = add <4 x i32> %splatx, %a
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @splat_assoc_add_undef_mask_elts_undef_constant_elts(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @splat_assoc_add_undef_mask_elts_undef_constant_elts(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @splat_assoc_add_undef_mask_elts_undef_constant_elts( ; CHECK-LABEL: @splat_assoc_add_undef_mask_elts_undef_constant_elts(
; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 0, i32 poison, i32 0, i32 poison> ; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <4 x i32> <i32 0, i32 poison, i32 0, i32 poison>
; CHECK-NEXT: [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 42, i32 undef, i32 undef, i32 42> ; CHECK-NEXT: [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 42, i32 undef, i32 undef, i32 42>
; CHECK-NEXT: [[R:%.*]] = add <4 x i32> [[SPLATX]], [[A]] ; CHECK-NEXT: [[R:%.*]] = add <4 x i32> [[SPLATX]], [[A]]
; CHECK-NEXT: ret <4 x i32> [[R]] ; CHECK-NEXT: ret <4 x i32> [[R]]
; ;
%splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 undef> %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 0, i32 undef>
%a = add <4 x i32> %y, <i32 42, i32 undef, i32 undef, i32 42> %a = add <4 x i32> %y, <i32 42, i32 undef, i32 undef, i32 42>
%r = add <4 x i32> %splatx, %a %r = add <4 x i32> %splatx, %a
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elts(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elts(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elts( ; CHECK-LABEL: @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elts(
; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 poison, i32 0, i32 0, i32 0> ; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 0>
; CHECK-NEXT: [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 42, i32 undef, i32 undef, i32 42> ; CHECK-NEXT: [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 42, i32 undef, i32 undef, i32 42>
; CHECK-NEXT: [[R:%.*]] = add <4 x i32> [[SPLATX]], [[A]] ; CHECK-NEXT: [[R:%.*]] = add <4 x i32> [[SPLATX]], [[A]]
; CHECK-NEXT: ret <4 x i32> [[R]] ; CHECK-NEXT: ret <4 x i32> [[R]]
; ;
%splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0> %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
%a = add <4 x i32> %y, <i32 42, i32 undef, i32 undef, i32 42> %a = add <4 x i32> %y, <i32 42, i32 undef, i32 undef, i32 42>
%r = add <4 x i32> %splatx, %a %r = add <4 x i32> %splatx, %a
ret <4 x i32> %r ret <4 x i32> %r
} }
define <4 x i32> @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elt_at_splat_index(<4 x i32> %x, <4 x i32> %y) { define <4 x i32> @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elt_at_splat_index(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elt_at_splat_index( ; CHECK-LABEL: @splat_assoc_add_undef_mask_elt_at_splat_index_undef_constant_elt_at_splat_index(
; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 poison, i32 0, i32 0, i32 0> ; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 0, i32 0>
; CHECK-NEXT: [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 undef, i32 42, i32 undef, i32 42> ; CHECK-NEXT: [[A:%.*]] = add <4 x i32> [[Y:%.*]], <i32 undef, i32 42, i32 undef, i32 42>
; CHECK-NEXT: [[R:%.*]] = add <4 x i32> [[SPLATX]], [[A]] ; CHECK-NEXT: [[R:%.*]] = add <4 x i32> [[SPLATX]], [[A]]
; CHECK-NEXT: ret <4 x i32> [[R]] ; CHECK-NEXT: ret <4 x i32> [[R]]
; ;
%splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0> %splatx = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 0, i32 0>
%a = add <4 x i32> %y, <i32 undef, i32 42, i32 undef, i32 42> %a = add <4 x i32> %y, <i32 undef, i32 42, i32 undef, i32 42>
%r = add <4 x i32> %splatx, %a %r = add <4 x i32> %splatx, %a
ret <4 x i32> %r ret <4 x i32> %r
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%splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2> %splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
%a = mul nsw <3 x i8> %y, %splatz %a = mul nsw <3 x i8> %y, %splatz
%r = mul nsw nuw <3 x i8> %a, %splatx %r = mul nsw nuw <3 x i8> %a, %splatx
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @splat_assoc_mul_undef_elt2(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) { define <3 x i8> @splat_assoc_mul_undef_elt2(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) {
; CHECK-LABEL: @splat_assoc_mul_undef_elt2( ; CHECK-LABEL: @splat_assoc_mul_undef_elt2(
; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2> ; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> poison, <3 x i32> <i32 2, i32 2, i32 2>
; CHECK-NEXT: [[SPLATZ:%.*]] = shufflevector <3 x i8> [[Z:%.*]], <3 x i8> undef, <3 x i32> <i32 poison, i32 2, i32 2> ; CHECK-NEXT: [[SPLATZ:%.*]] = shufflevector <3 x i8> [[Z:%.*]], <3 x i8> poison, <3 x i32> <i32 poison, i32 2, i32 2>
; CHECK-NEXT: [[A:%.*]] = mul nsw <3 x i8> [[SPLATZ]], [[Y:%.*]] ; CHECK-NEXT: [[A:%.*]] = mul nsw <3 x i8> [[SPLATZ]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = mul nuw nsw <3 x i8> [[A]], [[SPLATX]] ; CHECK-NEXT: [[R:%.*]] = mul nuw nsw <3 x i8> [[A]], [[SPLATX]]
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2> %splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
%splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 undef, i32 2, i32 2> %splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 undef, i32 2, i32 2>
%a = mul nsw <3 x i8> %y, %splatz %a = mul nsw <3 x i8> %y, %splatz
%r = mul nsw nuw <3 x i8> %a, %splatx %r = mul nsw nuw <3 x i8> %a, %splatx
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%splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2> %splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
%a = mul nsw <3 x i8> %y, %splatz %a = mul nsw <3 x i8> %y, %splatz
%r = mul nsw nuw <3 x i8> %a, %splatx %r = mul nsw nuw <3 x i8> %a, %splatx
ret <3 x i8> %r ret <3 x i8> %r
} }
define <3 x i8> @splat_assoc_mul_undef_elt_at_splat_index2(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) { define <3 x i8> @splat_assoc_mul_undef_elt_at_splat_index2(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) {
; CHECK-LABEL: @splat_assoc_mul_undef_elt_at_splat_index2( ; CHECK-LABEL: @splat_assoc_mul_undef_elt_at_splat_index2(
; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2> ; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> poison, <3 x i32> <i32 2, i32 2, i32 2>
; CHECK-NEXT: [[SPLATZ:%.*]] = shufflevector <3 x i8> [[Z:%.*]], <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 poison> ; CHECK-NEXT: [[SPLATZ:%.*]] = shufflevector <3 x i8> [[Z:%.*]], <3 x i8> poison, <3 x i32> <i32 2, i32 2, i32 poison>
; CHECK-NEXT: [[A:%.*]] = mul nsw <3 x i8> [[SPLATZ]], [[Y:%.*]] ; CHECK-NEXT: [[A:%.*]] = mul nsw <3 x i8> [[SPLATZ]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = mul nuw nsw <3 x i8> [[A]], [[SPLATX]] ; CHECK-NEXT: [[R:%.*]] = mul nuw nsw <3 x i8> [[A]], [[SPLATX]]
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2> %splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
%splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 undef> %splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 undef>
%a = mul nsw <3 x i8> %y, %splatz %a = mul nsw <3 x i8> %y, %splatz
%r = mul nsw nuw <3 x i8> %a, %splatx %r = mul nsw nuw <3 x i8> %a, %splatx
ret <3 x i8> %r ret <3 x i8> %r
} }
; Negative test - mismatched splat elements ; Negative test - mismatched splat elements
define <3 x i8> @splat_assoc_or(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) { define <3 x i8> @splat_assoc_or(<3 x i8> %x, <3 x i8> %y, <3 x i8> %z) {
; CHECK-LABEL: @splat_assoc_or( ; CHECK-LABEL: @splat_assoc_or(
; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> undef, <3 x i32> <i32 1, i32 1, i32 1> ; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <3 x i8> [[X:%.*]], <3 x i8> poison, <3 x i32> <i32 1, i32 1, i32 1>
; CHECK-NEXT: [[SPLATZ:%.*]] = shufflevector <3 x i8> [[Z:%.*]], <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2> ; CHECK-NEXT: [[SPLATZ:%.*]] = shufflevector <3 x i8> [[Z:%.*]], <3 x i8> poison, <3 x i32> <i32 2, i32 2, i32 2>
; CHECK-NEXT: [[A:%.*]] = or <3 x i8> [[SPLATZ]], [[Y:%.*]] ; CHECK-NEXT: [[A:%.*]] = or <3 x i8> [[SPLATZ]], [[Y:%.*]]
; CHECK-NEXT: [[R:%.*]] = or <3 x i8> [[A]], [[SPLATX]] ; CHECK-NEXT: [[R:%.*]] = or <3 x i8> [[A]], [[SPLATX]]
; CHECK-NEXT: ret <3 x i8> [[R]] ; CHECK-NEXT: ret <3 x i8> [[R]]
; ;
%splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 1, i32 1, i32 1> %splatx = shufflevector <3 x i8> %x, <3 x i8> undef, <3 x i32> <i32 1, i32 1, i32 1>
%splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2> %splatz = shufflevector <3 x i8> %z, <3 x i8> undef, <3 x i32> <i32 2, i32 2, i32 2>
%a = or <3 x i8> %y, %splatz %a = or <3 x i8> %y, %splatz
%r = or <3 x i8> %a, %splatx %r = or <3 x i8> %a, %splatx
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%r = fdiv reassoc nsz <2 x float> %a, %splatx %r = fdiv reassoc nsz <2 x float> %a, %splatx
ret <2 x float> %r ret <2 x float> %r
} }
; Negative test - extra use ; Negative test - extra use
define <2 x float> @splat_assoc_fadd(<2 x float> %x, <2 x float> %y) { define <2 x float> @splat_assoc_fadd(<2 x float> %x, <2 x float> %y) {
; CHECK-LABEL: @splat_assoc_fadd( ; CHECK-LABEL: @splat_assoc_fadd(
; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLATX:%.*]] = shufflevector <2 x float> [[X:%.*]], <2 x float> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[A:%.*]] = fadd fast <2 x float> [[Y:%.*]], <float 3.000000e+00, float 3.000000e+00> ; CHECK-NEXT: [[A:%.*]] = fadd fast <2 x float> [[Y:%.*]], <float 3.000000e+00, float 3.000000e+00>
; CHECK-NEXT: call void @use(<2 x float> [[A]]) ; CHECK-NEXT: call void @use(<2 x float> [[A]])
; CHECK-NEXT: [[R:%.*]] = fadd fast <2 x float> [[A]], [[SPLATX]] ; CHECK-NEXT: [[R:%.*]] = fadd fast <2 x float> [[A]], [[SPLATX]]
; CHECK-NEXT: ret <2 x float> [[R]] ; CHECK-NEXT: ret <2 x float> [[R]]
; ;
%splatx = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> <i32 1, i32 1> %splatx = shufflevector <2 x float> %x, <2 x float> undef, <2 x i32> <i32 1, i32 1>
%a = fadd fast <2 x float> %y, <float 3.0, float 3.0> %a = fadd fast <2 x float> %y, <float 3.0, float 3.0>
call void @use(<2 x float> %a) call void @use(<2 x float> %a)
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ret <4 x i32> %r ret <4 x i32> %r
} }
; Do not crash on constant expressions. ; Do not crash on constant expressions.
define <4 x i32> @PR46872(<4 x i32> %x) { define <4 x i32> @PR46872(<4 x i32> %x) {
; CHECK-LABEL: @PR46872( ; CHECK-LABEL: @PR46872(
; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> undef, <4 x i32> <i32 poison, i32 0, i32 1, i32 1> ; CHECK-NEXT: [[S:%.*]] = shufflevector <4 x i32> [[X:%.*]], <4 x i32> poison, <4 x i32> <i32 poison, i32 0, i32 1, i32 1>
; CHECK-NEXT: [[A:%.*]] = and <4 x i32> [[S]], bitcast (<2 x i64> <i64 ptrtoint (ptr @PR46872 to i64), i64 ptrtoint (ptr @PR46872 to i64)> to <4 x i32>) ; CHECK-NEXT: [[A:%.*]] = and <4 x i32> [[S]], bitcast (<2 x i64> <i64 ptrtoint (ptr @PR46872 to i64), i64 ptrtoint (ptr @PR46872 to i64)> to <4 x i32>)
; CHECK-NEXT: ret <4 x i32> [[A]] ; CHECK-NEXT: ret <4 x i32> [[A]]
; ;
%s = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 1> %s = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 0, i32 1, i32 1>
%a = and <4 x i32> %s, bitcast (<2 x i64> <i64 ptrtoint (ptr @PR46872 to i64), i64 ptrtoint (ptr @PR46872 to i64)> to <4 x i32>) %a = and <4 x i32> %s, bitcast (<2 x i64> <i64 ptrtoint (ptr @PR46872 to i64), i64 ptrtoint (ptr @PR46872 to i64)> to <4 x i32>)
ret <4 x i32> %a ret <4 x i32> %a
} }
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llvm/test/Transforms/InstCombine/vector-casts-inseltpoison.ll

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} }
; Hoist a trunc to a scalar if we're inserting into an undef vector. ; Hoist a trunc to a scalar if we're inserting into an undef vector.
; trunc (inselt undef, X, Index) --> inselt undef, (trunc X), Index ; trunc (inselt undef, X, Index) --> inselt undef, (trunc X), Index
define <3 x i16> @trunc_inselt_undef(i32 %x) { define <3 x i16> @trunc_inselt_undef(i32 %x) {
; CHECK-LABEL: @trunc_inselt_undef( ; CHECK-LABEL: @trunc_inselt_undef(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16 ; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16
; CHECK-NEXT: [[TRUNC:%.*]] = insertelement <3 x i16> undef, i16 [[TMP1]], i64 1 ; CHECK-NEXT: [[TRUNC:%.*]] = insertelement <3 x i16> <i16 undef, i16 poison, i16 undef>, i16 [[TMP1]], i64 1
aqjuneUnsubmitted
Not Done
ReplyInline Actions

This looks interesting - do you have idea how the undef elements are introduced?

aqjune: This looks interesting - do you have idea how the undef elements are introduced?
; CHECK-NEXT: ret <3 x i16> [[TRUNC]] ; CHECK-NEXT: ret <3 x i16> [[TRUNC]]
; ;
%vec = insertelement <3 x i32> poison, i32 %x, i32 1 %vec = insertelement <3 x i32> poison, i32 %x, i32 1
%trunc = trunc <3 x i32> %vec to <3 x i16> %trunc = trunc <3 x i32> %vec to <3 x i16>
ret <3 x i16> %trunc ret <3 x i16> %trunc
} }
; Hoist a trunc to a scalar if we're inserting into an undef vector. ; Hoist a trunc to a scalar if we're inserting into an undef vector.
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llvm/test/Transforms/InstCombine/vector-casts.ll

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} }
; Hoist a trunc to a scalar if we're inserting into an undef vector. ; Hoist a trunc to a scalar if we're inserting into an undef vector.
; trunc (inselt undef, X, Index) --> inselt undef, (trunc X), Index ; trunc (inselt undef, X, Index) --> inselt undef, (trunc X), Index
define <3 x i16> @trunc_inselt_undef(i32 %x) { define <3 x i16> @trunc_inselt_undef(i32 %x) {
; CHECK-LABEL: @trunc_inselt_undef( ; CHECK-LABEL: @trunc_inselt_undef(
; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16 ; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[X:%.*]] to i16
; CHECK-NEXT: [[TRUNC:%.*]] = insertelement <3 x i16> undef, i16 [[TMP1]], i64 1 ; CHECK-NEXT: [[TRUNC:%.*]] = insertelement <3 x i16> <i16 undef, i16 poison, i16 undef>, i16 [[TMP1]], i64 1
; CHECK-NEXT: ret <3 x i16> [[TRUNC]] ; CHECK-NEXT: ret <3 x i16> [[TRUNC]]
; ;
%vec = insertelement <3 x i32> undef, i32 %x, i32 1 %vec = insertelement <3 x i32> undef, i32 %x, i32 1
%trunc = trunc <3 x i32> %vec to <3 x i16> %trunc = trunc <3 x i32> %vec to <3 x i16>
ret <3 x i16> %trunc ret <3 x i16> %trunc
} }
; Hoist a trunc to a scalar if we're inserting into an undef vector. ; Hoist a trunc to a scalar if we're inserting into an undef vector.
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llvm/test/Transforms/LoopVectorize/invariant-store-vectorization-2.ll

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; CHECK-NEXT: [[BOUND0:%.*]] = icmp ugt ptr [[UGLYGEP1]], [[B]] ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ugt ptr [[UGLYGEP1]], [[B]]
; CHECK-NEXT: [[BOUND1:%.*]] = icmp ugt ptr [[UGLYGEP]], [[A]] ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ugt ptr [[UGLYGEP]], [[A]]
; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]]
; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph: ; CHECK: vector.ph:
; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[SMAX2]], 9223372036854775804 ; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[SMAX2]], 9223372036854775804
; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[NTRUNC]], i64 0 ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[NTRUNC]], i64 0
; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i1> undef, i1 [[CMP]], i64 3 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i1> poison, i1 [[CMP]], i64 3
; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = insertelement <4 x i32> poison, i32 [[K]], i64 3 ; CHECK-NEXT: [[BROADCAST_SPLAT6:%.*]] = insertelement <4 x i32> poison, i32 [[K]], i64 3
; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[BROADCAST_SPLAT]], <4 x i32> [[BROADCAST_SPLAT6]] ; CHECK-NEXT: [[PREDPHI:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[BROADCAST_SPLAT]], <4 x i32> [[BROADCAST_SPLAT6]]
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[PREDPHI]], i64 3 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[PREDPHI]], i64 3
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body: ; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]] ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[INDEX]]
; CHECK-NEXT: store <4 x i32> [[BROADCAST_SPLAT]], ptr [[TMP3]], align 4, !alias.scope !9, !noalias !12 ; CHECK-NEXT: store <4 x i32> [[BROADCAST_SPLAT]], ptr [[TMP3]], align 4, !alias.scope !9, !noalias !12
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llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-dominance.ll

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; CHECK-LABEL: @multiply_dont_hoist_phi( ; CHECK-LABEL: @multiply_dont_hoist_phi(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[NEXT:%.*]] ; CHECK-NEXT: br label [[NEXT:%.*]]
; CHECK: next: ; CHECK: next:
; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[A:%.*]], i64 2 ; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[A:%.*]], i64 2
; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8 ; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8
; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr double, ptr [[B:%.*]], i64 2 ; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr double, ptr [[B:%.*]], i64 2
; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8 ; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT13:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT13:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[A]], align 8 ; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[A]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT10:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT10:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT10]] ; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT10]]
; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT13]], <2 x double> [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT13]], <2 x double> [[TMP0]])
; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[B]], align 8 ; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[B]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]] ; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]]
; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT7]], <2 x double> [[TMP2]]) ; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT7]], <2 x double> [[TMP2]])
; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr <4 x double>, ptr [[C:%.*]], i64 26 ; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr <4 x double>, ptr [[C:%.*]], i64 26
; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[GEP_1]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[GEP_1]], align 8
; CHECK-NEXT: [[VEC_GEP14:%.*]] = getelementptr i8, ptr [[C]], i64 848 ; CHECK-NEXT: [[VEC_GEP14:%.*]] = getelementptr i8, ptr [[C]], i64 848
; CHECK-NEXT: store <2 x double> [[TMP1]], ptr [[VEC_GEP14]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP1]], ptr [[VEC_GEP14]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
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; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8 ; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8
; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[A]], i64 2 ; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[A]], i64 2
; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8 ; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8
; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[B:%.*]], align 8 ; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[B:%.*]], align 8
; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr double, ptr [[B]], i64 2 ; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr double, ptr [[B]], i64 2
; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8 ; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]] ; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]]
; CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT7]], <2 x double> [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT7]], <2 x double> [[TMP0]])
; CHECK-NEXT: [[SPLAT_SPLAT10:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT10:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT10]] ; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT10]]
; CHECK-NEXT: [[SPLAT_SPLAT13:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT13:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT13]], <2 x double> [[TMP2]]) ; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT13]], <2 x double> [[TMP2]])
; CHECK-NEXT: [[C:%.*]] = load ptr, ptr [[C_PTR:%.*]], align 8 ; CHECK-NEXT: [[C:%.*]] = load ptr, ptr [[C_PTR:%.*]], align 8
; CHECK-NEXT: store <2 x double> [[TMP1]], ptr [[C]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP1]], ptr [[C]], align 8
; CHECK-NEXT: [[VEC_GEP14:%.*]] = getelementptr double, ptr [[C]], i64 2 ; CHECK-NEXT: [[VEC_GEP14:%.*]] = getelementptr double, ptr [[C]], i64 2
; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[VEC_GEP14]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[VEC_GEP14]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
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; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8 ; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8
; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[A]], i64 2 ; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[A]], i64 2
; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8 ; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8
; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[B:%.*]], align 8 ; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[B:%.*]], align 8
; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr double, ptr [[B]], i64 2 ; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr double, ptr [[B]], i64 2
; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8 ; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]] ; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]]
; CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT7]], <2 x double> [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT7]], <2 x double> [[TMP0]])
; CHECK-NEXT: [[SPLAT_SPLAT10:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT10:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT10]] ; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT10]]
; CHECK-NEXT: [[SPLAT_SPLAT13:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT13:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT13]], <2 x double> [[TMP2]]) ; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT13]], <2 x double> [[TMP2]])
; CHECK-NEXT: [[C:%.*]] = load ptr, ptr [[C_PTR:%.*]], align 8 ; CHECK-NEXT: [[C:%.*]] = load ptr, ptr [[C_PTR:%.*]], align 8
; CHECK-NEXT: store <2 x double> [[TMP1]], ptr [[C]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP1]], ptr [[C]], align 8
; CHECK-NEXT: [[VEC_GEP14:%.*]] = getelementptr double, ptr [[C]], i64 2 ; CHECK-NEXT: [[VEC_GEP14:%.*]] = getelementptr double, ptr [[C]], i64 2
; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[VEC_GEP14]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[VEC_GEP14]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
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; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8 ; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8
; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[A]], i64 2 ; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[A]], i64 2
; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8 ; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8
; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[B:%.*]], align 8 ; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[B:%.*]], align 8
; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr double, ptr [[B]], i64 2 ; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr double, ptr [[B]], i64 2
; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8 ; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]] ; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]]
; CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT7]], <2 x double> [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT7]], <2 x double> [[TMP0]])
; CHECK-NEXT: [[SPLAT_SPLAT10:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT10:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT10]] ; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT10]]
; CHECK-NEXT: [[SPLAT_SPLAT13:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT13:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT13]], <2 x double> [[TMP2]]) ; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT13]], <2 x double> [[TMP2]])
; CHECK-NEXT: [[C:%.*]] = call ptr @get_address() ; CHECK-NEXT: [[C:%.*]] = call ptr @get_address()
; CHECK-NEXT: store <2 x double> [[TMP1]], ptr [[C]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP1]], ptr [[C]], align 8
; CHECK-NEXT: [[VEC_GEP14:%.*]] = getelementptr double, ptr [[C]], i64 2 ; CHECK-NEXT: [[VEC_GEP14:%.*]] = getelementptr double, ptr [[C]], i64 2
; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[VEC_GEP14]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[VEC_GEP14]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
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llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-loops.ll

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; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[COLS_IV]], 2 ; CHECK-NEXT: [[TMP3:%.*]] = shl i64 [[COLS_IV]], 2
; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], [[INNER_IV]] ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], [[INNER_IV]]
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[B:%.*]], i64 [[TMP4]] ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[B:%.*]], i64 [[TMP4]]
; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[TMP5]], align 8 ; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x double>, ptr [[TMP5]], align 8
; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr double, ptr [[TMP5]], i64 4 ; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr double, ptr [[TMP5]], i64 4
; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8 ; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x double>, ptr [[VEC_GEP3]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD]], <2 x double> [[SPLAT_SPLAT]], <2 x double> [[RESULT_VEC_0]]) ; CHECK-NEXT: [[TMP6:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD]], <2 x double> [[SPLAT_SPLAT]], <2 x double> [[RESULT_VEC_0]])
; CHECK-NEXT: [[SPLAT_SPLAT8:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT8:%.*]] = shufflevector <2 x double> [[COL_LOAD2]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP7]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT8]], <2 x double> [[TMP6]]) ; CHECK-NEXT: [[TMP7]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT8]], <2 x double> [[TMP6]])
; CHECK-NEXT: [[SPLAT_SPLAT12:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT12:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD]], <2 x double> [[SPLAT_SPLAT12]], <2 x double> [[RESULT_VEC_1]]) ; CHECK-NEXT: [[TMP8:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD]], <2 x double> [[SPLAT_SPLAT12]], <2 x double> [[RESULT_VEC_1]])
; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x double> [[COL_LOAD4]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP9]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT15]], <2 x double> [[TMP8]]) ; CHECK-NEXT: [[TMP9]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT15]], <2 x double> [[TMP8]])
; CHECK-NEXT: br label [[INNER_LATCH]] ; CHECK-NEXT: br label [[INNER_LATCH]]
; CHECK: inner.latch: ; CHECK: inner.latch:
; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2 ; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2
; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_STEP]], 4 ; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_STEP]], 4
; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: rows.latch: ; CHECK: rows.latch:
; CHECK-NEXT: [[ROWS_STEP]] = add i64 [[ROWS_IV]], 2 ; CHECK-NEXT: [[ROWS_STEP]] = add i64 [[ROWS_IV]], 2
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; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], [[INNER_IV]] ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], [[INNER_IV]]
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[B:%.*]], i64 [[TMP4]] ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[B:%.*]], i64 [[TMP4]]
; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8 ; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8
; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr i64, ptr [[TMP5]], i64 4 ; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr i64, ptr [[TMP5]], i64 4
; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x i64>, ptr [[VEC_GEP3]], align 8 ; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x i64>, ptr [[VEC_GEP3]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT]] ; CHECK-NEXT: [[TMP6:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT]]
; CHECK-NEXT: [[TMP7:%.*]] = add <2 x i64> [[RESULT_VEC_0]], [[TMP6]] ; CHECK-NEXT: [[TMP7:%.*]] = add <2 x i64> [[RESULT_VEC_0]], [[TMP6]]
; CHECK-NEXT: [[SPLAT_SPLAT8:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT8:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP8:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT8]] ; CHECK-NEXT: [[TMP8:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT8]]
; CHECK-NEXT: [[TMP9]] = add <2 x i64> [[TMP7]], [[TMP8]] ; CHECK-NEXT: [[TMP9]] = add <2 x i64> [[TMP7]], [[TMP8]]
; CHECK-NEXT: [[SPLAT_SPLAT12:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT12:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP10:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT12]] ; CHECK-NEXT: [[TMP10:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT12]]
; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[RESULT_VEC_1]], [[TMP10]] ; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[RESULT_VEC_1]], [[TMP10]]
; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP12:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT15]] ; CHECK-NEXT: [[TMP12:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT15]]
; CHECK-NEXT: [[TMP13]] = add <2 x i64> [[TMP11]], [[TMP12]] ; CHECK-NEXT: [[TMP13]] = add <2 x i64> [[TMP11]], [[TMP12]]
; CHECK-NEXT: br label [[INNER_LATCH]] ; CHECK-NEXT: br label [[INNER_LATCH]]
; CHECK: inner.latch: ; CHECK: inner.latch:
; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2 ; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2
; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_STEP]], 4 ; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_STEP]], 4
; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP2:![0-9]+]] ; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: rows.latch: ; CHECK: rows.latch:
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; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], [[INNER_IV]] ; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], [[INNER_IV]]
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[B:%.*]], i64 [[TMP4]] ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[B:%.*]], i64 [[TMP4]]
; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8 ; CHECK-NEXT: [[COL_LOAD2:%.*]] = load <2 x i64>, ptr [[TMP5]], align 8
; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr i64, ptr [[TMP5]], i64 2 ; CHECK-NEXT: [[VEC_GEP3:%.*]] = getelementptr i64, ptr [[TMP5]], i64 2
; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x i64>, ptr [[VEC_GEP3]], align 8 ; CHECK-NEXT: [[COL_LOAD4:%.*]] = load <2 x i64>, ptr [[VEC_GEP3]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT]] ; CHECK-NEXT: [[TMP6:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT]]
; CHECK-NEXT: [[TMP7:%.*]] = add <2 x i64> [[RESULT_VEC_0]], [[TMP6]] ; CHECK-NEXT: [[TMP7:%.*]] = add <2 x i64> [[RESULT_VEC_0]], [[TMP6]]
; CHECK-NEXT: [[SPLAT_SPLAT8:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT8:%.*]] = shufflevector <2 x i64> [[COL_LOAD2]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP8:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT8]] ; CHECK-NEXT: [[TMP8:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT8]]
; CHECK-NEXT: [[TMP9]] = add <2 x i64> [[TMP7]], [[TMP8]] ; CHECK-NEXT: [[TMP9]] = add <2 x i64> [[TMP7]], [[TMP8]]
; CHECK-NEXT: [[SPLAT_SPLAT12:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT12:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP10:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT12]] ; CHECK-NEXT: [[TMP10:%.*]] = mul <2 x i64> [[COL_LOAD]], [[SPLAT_SPLAT12]]
; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[RESULT_VEC_1]], [[TMP10]] ; CHECK-NEXT: [[TMP11:%.*]] = add <2 x i64> [[RESULT_VEC_1]], [[TMP10]]
; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x i64> [[COL_LOAD4]], <2 x i64> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP12:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT15]] ; CHECK-NEXT: [[TMP12:%.*]] = mul <2 x i64> [[COL_LOAD1]], [[SPLAT_SPLAT15]]
; CHECK-NEXT: [[TMP13]] = add <2 x i64> [[TMP11]], [[TMP12]] ; CHECK-NEXT: [[TMP13]] = add <2 x i64> [[TMP11]], [[TMP12]]
; CHECK-NEXT: br label [[INNER_LATCH]] ; CHECK-NEXT: br label [[INNER_LATCH]]
; CHECK: inner.latch: ; CHECK: inner.latch:
; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2 ; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2
; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_IV]], 0 ; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_IV]], 0
; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] ; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: rows.latch: ; CHECK: rows.latch:
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; CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[COLS_IV]], 1 ; CHECK-NEXT: [[TMP11:%.*]] = shl i64 [[COLS_IV]], 1
; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], [[INNER_IV]] ; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], [[INNER_IV]]
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr float, ptr [[TMP7]], i64 [[TMP12]] ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr float, ptr [[TMP7]], i64 [[TMP12]]
; CHECK-NEXT: [[COL_LOAD9:%.*]] = load <2 x float>, ptr [[TMP13]], align 4 ; CHECK-NEXT: [[COL_LOAD9:%.*]] = load <2 x float>, ptr [[TMP13]], align 4
; CHECK-NEXT: [[VEC_GEP10:%.*]] = getelementptr float, ptr [[TMP13]], i64 2 ; CHECK-NEXT: [[VEC_GEP10:%.*]] = getelementptr float, ptr [[TMP13]], i64 2
; CHECK-NEXT: [[COL_LOAD11:%.*]] = load <2 x float>, ptr [[VEC_GEP10]], align 4 ; CHECK-NEXT: [[COL_LOAD11:%.*]] = load <2 x float>, ptr [[VEC_GEP10]], align 4
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x float> [[COL_LOAD9]], <2 x float> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x float> [[COL_LOAD9]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP14:%.*]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD]], <2 x float> [[SPLAT_SPLAT]], <2 x float> [[RESULT_VEC_0]]) ; CHECK-NEXT: [[TMP14:%.*]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD]], <2 x float> [[SPLAT_SPLAT]], <2 x float> [[RESULT_VEC_0]])
; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x float> [[COL_LOAD9]], <2 x float> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT15:%.*]] = shufflevector <2 x float> [[COL_LOAD9]], <2 x float> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP15]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD8]], <2 x float> [[SPLAT_SPLAT15]], <2 x float> [[TMP14]]) ; CHECK-NEXT: [[TMP15]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD8]], <2 x float> [[SPLAT_SPLAT15]], <2 x float> [[TMP14]])
; CHECK-NEXT: [[SPLAT_SPLAT19:%.*]] = shufflevector <2 x float> [[COL_LOAD11]], <2 x float> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT19:%.*]] = shufflevector <2 x float> [[COL_LOAD11]], <2 x float> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP16:%.*]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD]], <2 x float> [[SPLAT_SPLAT19]], <2 x float> [[RESULT_VEC_1]]) ; CHECK-NEXT: [[TMP16:%.*]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD]], <2 x float> [[SPLAT_SPLAT19]], <2 x float> [[RESULT_VEC_1]])
; CHECK-NEXT: [[SPLAT_SPLAT22:%.*]] = shufflevector <2 x float> [[COL_LOAD11]], <2 x float> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT22:%.*]] = shufflevector <2 x float> [[COL_LOAD11]], <2 x float> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP17]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD8]], <2 x float> [[SPLAT_SPLAT22]], <2 x float> [[TMP16]]) ; CHECK-NEXT: [[TMP17]] = call contract <2 x float> @llvm.fmuladd.v2f32(<2 x float> [[COL_LOAD8]], <2 x float> [[SPLAT_SPLAT22]], <2 x float> [[TMP16]])
; CHECK-NEXT: br label [[INNER_LATCH]] ; CHECK-NEXT: br label [[INNER_LATCH]]
; CHECK: inner.latch: ; CHECK: inner.latch:
; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2 ; CHECK-NEXT: [[INNER_STEP]] = add i64 [[INNER_IV]], 2
; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_IV]], 0 ; CHECK-NEXT: [[INNER_COND_NOT:%.*]] = icmp eq i64 [[INNER_IV]], 0
; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP5:![0-9]+]] ; CHECK-NEXT: br i1 [[INNER_COND_NOT]], label [[ROWS_LATCH]], label [[INNER_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: rows.latch: ; CHECK: rows.latch:
; CHECK-NEXT: [[ROWS_STEP]] = add i64 [[ROWS_IV]], 2 ; CHECK-NEXT: [[ROWS_STEP]] = add i64 [[ROWS_IV]], 2
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llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-multiple-blocks.ll

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; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[TMP3]], align 8 ; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[TMP3]], align 8
; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[TMP3]], i64 3 ; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[TMP3]], i64 3
; CHECK-NEXT: [[COL_LOAD8:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8 ; CHECK-NEXT: [[COL_LOAD8:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8
; CHECK-NEXT: [[COL_LOAD9:%.*]] = load <2 x double>, ptr [[TMP7]], align 8 ; CHECK-NEXT: [[COL_LOAD9:%.*]] = load <2 x double>, ptr [[TMP7]], align 8
; CHECK-NEXT: [[VEC_GEP10:%.*]] = getelementptr double, ptr [[TMP7]], i64 2 ; CHECK-NEXT: [[VEC_GEP10:%.*]] = getelementptr double, ptr [[TMP7]], i64 2
; CHECK-NEXT: [[COL_LOAD11:%.*]] = load <2 x double>, ptr [[VEC_GEP10]], align 8 ; CHECK-NEXT: [[COL_LOAD11:%.*]] = load <2 x double>, ptr [[VEC_GEP10]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD9]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD9]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]]
; CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <2 x double> [[COL_LOAD9]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <2 x double> [[COL_LOAD9]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP9:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD8]], <2 x double> [[SPLAT_SPLAT14]], <2 x double> [[TMP8]]) ; CHECK-NEXT: [[TMP9:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD8]], <2 x double> [[SPLAT_SPLAT14]], <2 x double> [[TMP8]])
; CHECK-NEXT: [[SPLAT_SPLAT17:%.*]] = shufflevector <2 x double> [[COL_LOAD11]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT17:%.*]] = shufflevector <2 x double> [[COL_LOAD11]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP10:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT17]] ; CHECK-NEXT: [[TMP10:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT17]]
; CHECK-NEXT: [[SPLAT_SPLAT20:%.*]] = shufflevector <2 x double> [[COL_LOAD11]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT20:%.*]] = shufflevector <2 x double> [[COL_LOAD11]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP11:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD8]], <2 x double> [[SPLAT_SPLAT20]], <2 x double> [[TMP10]]) ; CHECK-NEXT: [[TMP11:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD8]], <2 x double> [[SPLAT_SPLAT20]], <2 x double> [[TMP10]])
; CHECK-NEXT: store <2 x double> [[TMP9]], ptr [[C]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP9]], ptr [[C]], align 8
; CHECK-NEXT: [[VEC_GEP21:%.*]] = getelementptr double, ptr [[C]], i64 3 ; CHECK-NEXT: [[VEC_GEP21:%.*]] = getelementptr double, ptr [[C]], i64 3
; CHECK-NEXT: store <2 x double> [[TMP11]], ptr [[VEC_GEP21]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP11]], ptr [[VEC_GEP21]], align 8
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr double, ptr [[TMP3]], i64 2 ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr double, ptr [[TMP3]], i64 2
; CHECK-NEXT: [[COL_LOAD22:%.*]] = load <1 x double>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[COL_LOAD22:%.*]] = load <1 x double>, ptr [[TMP12]], align 8
; CHECK-NEXT: [[VEC_GEP23:%.*]] = getelementptr double, ptr [[TMP3]], i64 5 ; CHECK-NEXT: [[VEC_GEP23:%.*]] = getelementptr double, ptr [[TMP3]], i64 5
; CHECK-NEXT: [[COL_LOAD24:%.*]] = load <1 x double>, ptr [[VEC_GEP23]], align 8 ; CHECK-NEXT: [[COL_LOAD24:%.*]] = load <1 x double>, ptr [[VEC_GEP23]], align 8
; CHECK-NEXT: [[COL_LOAD25:%.*]] = load <2 x double>, ptr [[TMP7]], align 8 ; CHECK-NEXT: [[COL_LOAD25:%.*]] = load <2 x double>, ptr [[TMP7]], align 8
; CHECK-NEXT: [[VEC_GEP26:%.*]] = getelementptr double, ptr [[TMP7]], i64 2 ; CHECK-NEXT: [[VEC_GEP26:%.*]] = getelementptr double, ptr [[TMP7]], i64 2
; CHECK-NEXT: [[COL_LOAD27:%.*]] = load <2 x double>, ptr [[VEC_GEP26]], align 8 ; CHECK-NEXT: [[COL_LOAD27:%.*]] = load <2 x double>, ptr [[VEC_GEP26]], align 8
; CHECK-NEXT: [[SPLAT_SPLATINSERT29:%.*]] = shufflevector <2 x double> [[COL_LOAD25]], <2 x double> undef, <1 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLATINSERT29:%.*]] = shufflevector <2 x double> [[COL_LOAD25]], <2 x double> undef, <1 x i32> zeroinitializer
; CHECK-NEXT: [[TMP13:%.*]] = fmul contract <1 x double> [[COL_LOAD22]], [[SPLAT_SPLATINSERT29]] ; CHECK-NEXT: [[TMP13:%.*]] = fmul contract <1 x double> [[COL_LOAD22]], [[SPLAT_SPLATINSERT29]]
; CHECK-NEXT: [[SPLAT_SPLATINSERT32:%.*]] = shufflevector <2 x double> [[COL_LOAD25]], <2 x double> undef, <1 x i32> <i32 1> ; CHECK-NEXT: [[SPLAT_SPLATINSERT32:%.*]] = shufflevector <2 x double> [[COL_LOAD25]], <2 x double> poison, <1 x i32> <i32 1>
; CHECK-NEXT: [[TMP14:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD24]], <1 x double> [[SPLAT_SPLATINSERT32]], <1 x double> [[TMP13]]) ; CHECK-NEXT: [[TMP14:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD24]], <1 x double> [[SPLAT_SPLATINSERT32]], <1 x double> [[TMP13]])
; CHECK-NEXT: [[SPLAT_SPLATINSERT35:%.*]] = shufflevector <2 x double> [[COL_LOAD27]], <2 x double> undef, <1 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLATINSERT35:%.*]] = shufflevector <2 x double> [[COL_LOAD27]], <2 x double> undef, <1 x i32> zeroinitializer
; CHECK-NEXT: [[TMP15:%.*]] = fmul contract <1 x double> [[COL_LOAD22]], [[SPLAT_SPLATINSERT35]] ; CHECK-NEXT: [[TMP15:%.*]] = fmul contract <1 x double> [[COL_LOAD22]], [[SPLAT_SPLATINSERT35]]
; CHECK-NEXT: [[SPLAT_SPLATINSERT38:%.*]] = shufflevector <2 x double> [[COL_LOAD27]], <2 x double> undef, <1 x i32> <i32 1> ; CHECK-NEXT: [[SPLAT_SPLATINSERT38:%.*]] = shufflevector <2 x double> [[COL_LOAD27]], <2 x double> poison, <1 x i32> <i32 1>
; CHECK-NEXT: [[TMP16:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD24]], <1 x double> [[SPLAT_SPLATINSERT38]], <1 x double> [[TMP15]]) ; CHECK-NEXT: [[TMP16:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD24]], <1 x double> [[SPLAT_SPLATINSERT38]], <1 x double> [[TMP15]])
; CHECK-NEXT: [[TMP17:%.*]] = getelementptr double, ptr [[C]], i64 2 ; CHECK-NEXT: [[TMP17:%.*]] = getelementptr double, ptr [[C]], i64 2
; CHECK-NEXT: store <1 x double> [[TMP14]], ptr [[TMP17]], align 8 ; CHECK-NEXT: store <1 x double> [[TMP14]], ptr [[TMP17]], align 8
; CHECK-NEXT: [[VEC_GEP40:%.*]] = getelementptr double, ptr [[C]], i64 5 ; CHECK-NEXT: [[VEC_GEP40:%.*]] = getelementptr double, ptr [[C]], i64 5
; CHECK-NEXT: store <1 x double> [[TMP16]], ptr [[VEC_GEP40]], align 8 ; CHECK-NEXT: store <1 x double> [[TMP16]], ptr [[VEC_GEP40]], align 8
; CHECK-NEXT: [[COL_LOAD41:%.*]] = load <2 x double>, ptr [[TMP3]], align 8 ; CHECK-NEXT: [[COL_LOAD41:%.*]] = load <2 x double>, ptr [[TMP3]], align 8
; CHECK-NEXT: [[VEC_GEP42:%.*]] = getelementptr double, ptr [[TMP3]], i64 3 ; CHECK-NEXT: [[VEC_GEP42:%.*]] = getelementptr double, ptr [[TMP3]], i64 3
; CHECK-NEXT: [[COL_LOAD43:%.*]] = load <2 x double>, ptr [[VEC_GEP42]], align 8 ; CHECK-NEXT: [[COL_LOAD43:%.*]] = load <2 x double>, ptr [[VEC_GEP42]], align 8
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr double, ptr [[TMP7]], i64 4 ; CHECK-NEXT: [[TMP18:%.*]] = getelementptr double, ptr [[TMP7]], i64 4
; CHECK-NEXT: [[COL_LOAD44:%.*]] = load <2 x double>, ptr [[TMP18]], align 8 ; CHECK-NEXT: [[COL_LOAD44:%.*]] = load <2 x double>, ptr [[TMP18]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT47:%.*]] = shufflevector <2 x double> [[COL_LOAD44]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT47:%.*]] = shufflevector <2 x double> [[COL_LOAD44]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP19:%.*]] = fmul contract <2 x double> [[COL_LOAD41]], [[SPLAT_SPLAT47]] ; CHECK-NEXT: [[TMP19:%.*]] = fmul contract <2 x double> [[COL_LOAD41]], [[SPLAT_SPLAT47]]
; CHECK-NEXT: [[SPLAT_SPLAT50:%.*]] = shufflevector <2 x double> [[COL_LOAD44]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT50:%.*]] = shufflevector <2 x double> [[COL_LOAD44]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP20:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD43]], <2 x double> [[SPLAT_SPLAT50]], <2 x double> [[TMP19]]) ; CHECK-NEXT: [[TMP20:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD43]], <2 x double> [[SPLAT_SPLAT50]], <2 x double> [[TMP19]])
; CHECK-NEXT: [[TMP21:%.*]] = getelementptr double, ptr [[C]], i64 6 ; CHECK-NEXT: [[TMP21:%.*]] = getelementptr double, ptr [[C]], i64 6
; CHECK-NEXT: store <2 x double> [[TMP20]], ptr [[TMP21]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP20]], ptr [[TMP21]], align 8
; CHECK-NEXT: [[TMP22:%.*]] = getelementptr double, ptr [[TMP3]], i64 2 ; CHECK-NEXT: [[TMP22:%.*]] = getelementptr double, ptr [[TMP3]], i64 2
; CHECK-NEXT: [[COL_LOAD51:%.*]] = load <1 x double>, ptr [[TMP22]], align 8 ; CHECK-NEXT: [[COL_LOAD51:%.*]] = load <1 x double>, ptr [[TMP22]], align 8
; CHECK-NEXT: [[VEC_GEP52:%.*]] = getelementptr double, ptr [[TMP3]], i64 5 ; CHECK-NEXT: [[VEC_GEP52:%.*]] = getelementptr double, ptr [[TMP3]], i64 5
; CHECK-NEXT: [[COL_LOAD53:%.*]] = load <1 x double>, ptr [[VEC_GEP52]], align 8 ; CHECK-NEXT: [[COL_LOAD53:%.*]] = load <1 x double>, ptr [[VEC_GEP52]], align 8
; CHECK-NEXT: [[TMP23:%.*]] = getelementptr double, ptr [[TMP7]], i64 4 ; CHECK-NEXT: [[TMP23:%.*]] = getelementptr double, ptr [[TMP7]], i64 4
; CHECK-NEXT: [[COL_LOAD54:%.*]] = load <2 x double>, ptr [[TMP23]], align 8 ; CHECK-NEXT: [[COL_LOAD54:%.*]] = load <2 x double>, ptr [[TMP23]], align 8
; CHECK-NEXT: [[SPLAT_SPLATINSERT56:%.*]] = shufflevector <2 x double> [[COL_LOAD54]], <2 x double> undef, <1 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLATINSERT56:%.*]] = shufflevector <2 x double> [[COL_LOAD54]], <2 x double> undef, <1 x i32> zeroinitializer
; CHECK-NEXT: [[TMP24:%.*]] = fmul contract <1 x double> [[COL_LOAD51]], [[SPLAT_SPLATINSERT56]] ; CHECK-NEXT: [[TMP24:%.*]] = fmul contract <1 x double> [[COL_LOAD51]], [[SPLAT_SPLATINSERT56]]
; CHECK-NEXT: [[SPLAT_SPLATINSERT59:%.*]] = shufflevector <2 x double> [[COL_LOAD54]], <2 x double> undef, <1 x i32> <i32 1> ; CHECK-NEXT: [[SPLAT_SPLATINSERT59:%.*]] = shufflevector <2 x double> [[COL_LOAD54]], <2 x double> poison, <1 x i32> <i32 1>
; CHECK-NEXT: [[TMP25:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD53]], <1 x double> [[SPLAT_SPLATINSERT59]], <1 x double> [[TMP24]]) ; CHECK-NEXT: [[TMP25:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD53]], <1 x double> [[SPLAT_SPLATINSERT59]], <1 x double> [[TMP24]])
; CHECK-NEXT: [[TMP26:%.*]] = getelementptr double, ptr [[C]], i64 8 ; CHECK-NEXT: [[TMP26:%.*]] = getelementptr double, ptr [[C]], i64 8
; CHECK-NEXT: store <1 x double> [[TMP25]], ptr [[TMP26]], align 8 ; CHECK-NEXT: store <1 x double> [[TMP25]], ptr [[TMP26]], align 8
; CHECK-NEXT: br i1 [[COND:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]] ; CHECK-NEXT: br i1 [[COND:%.*]], label [[TRUE:%.*]], label [[FALSE:%.*]]
; CHECK: true: ; CHECK: true:
; CHECK-NEXT: [[TMP27:%.*]] = fadd contract <3 x double> [[COL_LOAD133]], [[COL_LOAD133]] ; CHECK-NEXT: [[TMP27:%.*]] = fadd contract <3 x double> [[COL_LOAD133]], [[COL_LOAD133]]
; CHECK-NEXT: [[TMP28:%.*]] = fadd contract <3 x double> [[COL_LOAD135]], [[COL_LOAD135]] ; CHECK-NEXT: [[TMP28:%.*]] = fadd contract <3 x double> [[COL_LOAD135]], [[COL_LOAD135]]
; CHECK-NEXT: store <3 x double> [[TMP27]], ptr [[A]], align 8 ; CHECK-NEXT: store <3 x double> [[TMP27]], ptr [[A]], align 8
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; CHECK-NEXT: [[COL_LOAD75:%.*]] = load <2 x double>, ptr [[TMP35]], align 8 ; CHECK-NEXT: [[COL_LOAD75:%.*]] = load <2 x double>, ptr [[TMP35]], align 8
; CHECK-NEXT: [[VEC_GEP76:%.*]] = getelementptr double, ptr [[TMP35]], i64 3 ; CHECK-NEXT: [[VEC_GEP76:%.*]] = getelementptr double, ptr [[TMP35]], i64 3
; CHECK-NEXT: [[COL_LOAD77:%.*]] = load <2 x double>, ptr [[VEC_GEP76]], align 8 ; CHECK-NEXT: [[COL_LOAD77:%.*]] = load <2 x double>, ptr [[VEC_GEP76]], align 8
; CHECK-NEXT: [[COL_LOAD78:%.*]] = load <2 x double>, ptr [[TMP39]], align 8 ; CHECK-NEXT: [[COL_LOAD78:%.*]] = load <2 x double>, ptr [[TMP39]], align 8
; CHECK-NEXT: [[VEC_GEP79:%.*]] = getelementptr double, ptr [[TMP39]], i64 2 ; CHECK-NEXT: [[VEC_GEP79:%.*]] = getelementptr double, ptr [[TMP39]], i64 2
; CHECK-NEXT: [[COL_LOAD80:%.*]] = load <2 x double>, ptr [[VEC_GEP79]], align 8 ; CHECK-NEXT: [[COL_LOAD80:%.*]] = load <2 x double>, ptr [[VEC_GEP79]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT83:%.*]] = shufflevector <2 x double> [[COL_LOAD78]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT83:%.*]] = shufflevector <2 x double> [[COL_LOAD78]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP40:%.*]] = fmul contract <2 x double> [[COL_LOAD75]], [[SPLAT_SPLAT83]] ; CHECK-NEXT: [[TMP40:%.*]] = fmul contract <2 x double> [[COL_LOAD75]], [[SPLAT_SPLAT83]]
; CHECK-NEXT: [[SPLAT_SPLAT86:%.*]] = shufflevector <2 x double> [[COL_LOAD78]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT86:%.*]] = shufflevector <2 x double> [[COL_LOAD78]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP41:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD77]], <2 x double> [[SPLAT_SPLAT86]], <2 x double> [[TMP40]]) ; CHECK-NEXT: [[TMP41:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD77]], <2 x double> [[SPLAT_SPLAT86]], <2 x double> [[TMP40]])
; CHECK-NEXT: [[SPLAT_SPLAT89:%.*]] = shufflevector <2 x double> [[COL_LOAD80]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT89:%.*]] = shufflevector <2 x double> [[COL_LOAD80]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP42:%.*]] = fmul contract <2 x double> [[COL_LOAD75]], [[SPLAT_SPLAT89]] ; CHECK-NEXT: [[TMP42:%.*]] = fmul contract <2 x double> [[COL_LOAD75]], [[SPLAT_SPLAT89]]
; CHECK-NEXT: [[SPLAT_SPLAT92:%.*]] = shufflevector <2 x double> [[COL_LOAD80]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT92:%.*]] = shufflevector <2 x double> [[COL_LOAD80]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP43:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD77]], <2 x double> [[SPLAT_SPLAT92]], <2 x double> [[TMP42]]) ; CHECK-NEXT: [[TMP43:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD77]], <2 x double> [[SPLAT_SPLAT92]], <2 x double> [[TMP42]])
; CHECK-NEXT: store <2 x double> [[TMP41]], ptr [[C]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP41]], ptr [[C]], align 8
; CHECK-NEXT: [[VEC_GEP93:%.*]] = getelementptr double, ptr [[C]], i64 3 ; CHECK-NEXT: [[VEC_GEP93:%.*]] = getelementptr double, ptr [[C]], i64 3
; CHECK-NEXT: store <2 x double> [[TMP43]], ptr [[VEC_GEP93]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP43]], ptr [[VEC_GEP93]], align 8
; CHECK-NEXT: [[TMP44:%.*]] = getelementptr double, ptr [[TMP35]], i64 2 ; CHECK-NEXT: [[TMP44:%.*]] = getelementptr double, ptr [[TMP35]], i64 2
; CHECK-NEXT: [[COL_LOAD94:%.*]] = load <1 x double>, ptr [[TMP44]], align 8 ; CHECK-NEXT: [[COL_LOAD94:%.*]] = load <1 x double>, ptr [[TMP44]], align 8
; CHECK-NEXT: [[VEC_GEP95:%.*]] = getelementptr double, ptr [[TMP35]], i64 5 ; CHECK-NEXT: [[VEC_GEP95:%.*]] = getelementptr double, ptr [[TMP35]], i64 5
; CHECK-NEXT: [[COL_LOAD96:%.*]] = load <1 x double>, ptr [[VEC_GEP95]], align 8 ; CHECK-NEXT: [[COL_LOAD96:%.*]] = load <1 x double>, ptr [[VEC_GEP95]], align 8
; CHECK-NEXT: [[COL_LOAD97:%.*]] = load <2 x double>, ptr [[TMP39]], align 8 ; CHECK-NEXT: [[COL_LOAD97:%.*]] = load <2 x double>, ptr [[TMP39]], align 8
; CHECK-NEXT: [[VEC_GEP98:%.*]] = getelementptr double, ptr [[TMP39]], i64 2 ; CHECK-NEXT: [[VEC_GEP98:%.*]] = getelementptr double, ptr [[TMP39]], i64 2
; CHECK-NEXT: [[COL_LOAD99:%.*]] = load <2 x double>, ptr [[VEC_GEP98]], align 8 ; CHECK-NEXT: [[COL_LOAD99:%.*]] = load <2 x double>, ptr [[VEC_GEP98]], align 8
; CHECK-NEXT: [[SPLAT_SPLATINSERT101:%.*]] = shufflevector <2 x double> [[COL_LOAD97]], <2 x double> undef, <1 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLATINSERT101:%.*]] = shufflevector <2 x double> [[COL_LOAD97]], <2 x double> undef, <1 x i32> zeroinitializer
; CHECK-NEXT: [[TMP45:%.*]] = fmul contract <1 x double> [[COL_LOAD94]], [[SPLAT_SPLATINSERT101]] ; CHECK-NEXT: [[TMP45:%.*]] = fmul contract <1 x double> [[COL_LOAD94]], [[SPLAT_SPLATINSERT101]]
; CHECK-NEXT: [[SPLAT_SPLATINSERT104:%.*]] = shufflevector <2 x double> [[COL_LOAD97]], <2 x double> undef, <1 x i32> <i32 1> ; CHECK-NEXT: [[SPLAT_SPLATINSERT104:%.*]] = shufflevector <2 x double> [[COL_LOAD97]], <2 x double> poison, <1 x i32> <i32 1>
; CHECK-NEXT: [[TMP46:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD96]], <1 x double> [[SPLAT_SPLATINSERT104]], <1 x double> [[TMP45]]) ; CHECK-NEXT: [[TMP46:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD96]], <1 x double> [[SPLAT_SPLATINSERT104]], <1 x double> [[TMP45]])
; CHECK-NEXT: [[SPLAT_SPLATINSERT107:%.*]] = shufflevector <2 x double> [[COL_LOAD99]], <2 x double> undef, <1 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLATINSERT107:%.*]] = shufflevector <2 x double> [[COL_LOAD99]], <2 x double> undef, <1 x i32> zeroinitializer
; CHECK-NEXT: [[TMP47:%.*]] = fmul contract <1 x double> [[COL_LOAD94]], [[SPLAT_SPLATINSERT107]] ; CHECK-NEXT: [[TMP47:%.*]] = fmul contract <1 x double> [[COL_LOAD94]], [[SPLAT_SPLATINSERT107]]
; CHECK-NEXT: [[SPLAT_SPLATINSERT110:%.*]] = shufflevector <2 x double> [[COL_LOAD99]], <2 x double> undef, <1 x i32> <i32 1> ; CHECK-NEXT: [[SPLAT_SPLATINSERT110:%.*]] = shufflevector <2 x double> [[COL_LOAD99]], <2 x double> poison, <1 x i32> <i32 1>
; CHECK-NEXT: [[TMP48:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD96]], <1 x double> [[SPLAT_SPLATINSERT110]], <1 x double> [[TMP47]]) ; CHECK-NEXT: [[TMP48:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD96]], <1 x double> [[SPLAT_SPLATINSERT110]], <1 x double> [[TMP47]])
; CHECK-NEXT: [[TMP49:%.*]] = getelementptr double, ptr [[C]], i64 2 ; CHECK-NEXT: [[TMP49:%.*]] = getelementptr double, ptr [[C]], i64 2
; CHECK-NEXT: store <1 x double> [[TMP46]], ptr [[TMP49]], align 8 ; CHECK-NEXT: store <1 x double> [[TMP46]], ptr [[TMP49]], align 8
; CHECK-NEXT: [[VEC_GEP112:%.*]] = getelementptr double, ptr [[C]], i64 5 ; CHECK-NEXT: [[VEC_GEP112:%.*]] = getelementptr double, ptr [[C]], i64 5
; CHECK-NEXT: store <1 x double> [[TMP48]], ptr [[VEC_GEP112]], align 8 ; CHECK-NEXT: store <1 x double> [[TMP48]], ptr [[VEC_GEP112]], align 8
; CHECK-NEXT: [[COL_LOAD113:%.*]] = load <2 x double>, ptr [[TMP35]], align 8 ; CHECK-NEXT: [[COL_LOAD113:%.*]] = load <2 x double>, ptr [[TMP35]], align 8
; CHECK-NEXT: [[VEC_GEP114:%.*]] = getelementptr double, ptr [[TMP35]], i64 3 ; CHECK-NEXT: [[VEC_GEP114:%.*]] = getelementptr double, ptr [[TMP35]], i64 3
; CHECK-NEXT: [[COL_LOAD115:%.*]] = load <2 x double>, ptr [[VEC_GEP114]], align 8 ; CHECK-NEXT: [[COL_LOAD115:%.*]] = load <2 x double>, ptr [[VEC_GEP114]], align 8
; CHECK-NEXT: [[TMP50:%.*]] = getelementptr double, ptr [[TMP39]], i64 4 ; CHECK-NEXT: [[TMP50:%.*]] = getelementptr double, ptr [[TMP39]], i64 4
; CHECK-NEXT: [[COL_LOAD116:%.*]] = load <2 x double>, ptr [[TMP50]], align 8 ; CHECK-NEXT: [[COL_LOAD116:%.*]] = load <2 x double>, ptr [[TMP50]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT119:%.*]] = shufflevector <2 x double> [[COL_LOAD116]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT119:%.*]] = shufflevector <2 x double> [[COL_LOAD116]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP51:%.*]] = fmul contract <2 x double> [[COL_LOAD113]], [[SPLAT_SPLAT119]] ; CHECK-NEXT: [[TMP51:%.*]] = fmul contract <2 x double> [[COL_LOAD113]], [[SPLAT_SPLAT119]]
; CHECK-NEXT: [[SPLAT_SPLAT122:%.*]] = shufflevector <2 x double> [[COL_LOAD116]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT122:%.*]] = shufflevector <2 x double> [[COL_LOAD116]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP52:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD115]], <2 x double> [[SPLAT_SPLAT122]], <2 x double> [[TMP51]]) ; CHECK-NEXT: [[TMP52:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD115]], <2 x double> [[SPLAT_SPLAT122]], <2 x double> [[TMP51]])
; CHECK-NEXT: [[TMP53:%.*]] = getelementptr double, ptr [[C]], i64 6 ; CHECK-NEXT: [[TMP53:%.*]] = getelementptr double, ptr [[C]], i64 6
; CHECK-NEXT: store <2 x double> [[TMP52]], ptr [[TMP53]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP52]], ptr [[TMP53]], align 8
; CHECK-NEXT: [[TMP54:%.*]] = getelementptr double, ptr [[TMP35]], i64 2 ; CHECK-NEXT: [[TMP54:%.*]] = getelementptr double, ptr [[TMP35]], i64 2
; CHECK-NEXT: [[COL_LOAD123:%.*]] = load <1 x double>, ptr [[TMP54]], align 8 ; CHECK-NEXT: [[COL_LOAD123:%.*]] = load <1 x double>, ptr [[TMP54]], align 8
; CHECK-NEXT: [[VEC_GEP124:%.*]] = getelementptr double, ptr [[TMP35]], i64 5 ; CHECK-NEXT: [[VEC_GEP124:%.*]] = getelementptr double, ptr [[TMP35]], i64 5
; CHECK-NEXT: [[COL_LOAD125:%.*]] = load <1 x double>, ptr [[VEC_GEP124]], align 8 ; CHECK-NEXT: [[COL_LOAD125:%.*]] = load <1 x double>, ptr [[VEC_GEP124]], align 8
; CHECK-NEXT: [[TMP55:%.*]] = getelementptr double, ptr [[TMP39]], i64 4 ; CHECK-NEXT: [[TMP55:%.*]] = getelementptr double, ptr [[TMP39]], i64 4
; CHECK-NEXT: [[COL_LOAD126:%.*]] = load <2 x double>, ptr [[TMP55]], align 8 ; CHECK-NEXT: [[COL_LOAD126:%.*]] = load <2 x double>, ptr [[TMP55]], align 8
; CHECK-NEXT: [[SPLAT_SPLATINSERT128:%.*]] = shufflevector <2 x double> [[COL_LOAD126]], <2 x double> undef, <1 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLATINSERT128:%.*]] = shufflevector <2 x double> [[COL_LOAD126]], <2 x double> undef, <1 x i32> zeroinitializer
; CHECK-NEXT: [[TMP56:%.*]] = fmul contract <1 x double> [[COL_LOAD123]], [[SPLAT_SPLATINSERT128]] ; CHECK-NEXT: [[TMP56:%.*]] = fmul contract <1 x double> [[COL_LOAD123]], [[SPLAT_SPLATINSERT128]]
; CHECK-NEXT: [[SPLAT_SPLATINSERT131:%.*]] = shufflevector <2 x double> [[COL_LOAD126]], <2 x double> undef, <1 x i32> <i32 1> ; CHECK-NEXT: [[SPLAT_SPLATINSERT131:%.*]] = shufflevector <2 x double> [[COL_LOAD126]], <2 x double> poison, <1 x i32> <i32 1>
; CHECK-NEXT: [[TMP57:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD125]], <1 x double> [[SPLAT_SPLATINSERT131]], <1 x double> [[TMP56]]) ; CHECK-NEXT: [[TMP57:%.*]] = call contract <1 x double> @llvm.fmuladd.v1f64(<1 x double> [[COL_LOAD125]], <1 x double> [[SPLAT_SPLATINSERT131]], <1 x double> [[TMP56]])
; CHECK-NEXT: [[TMP58:%.*]] = getelementptr double, ptr [[C]], i64 8 ; CHECK-NEXT: [[TMP58:%.*]] = getelementptr double, ptr [[C]], i64 8
; CHECK-NEXT: store <1 x double> [[TMP57]], ptr [[TMP58]], align 8 ; CHECK-NEXT: store <1 x double> [[TMP57]], ptr [[TMP58]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%a = load <6 x double>, ptr %A, align 8 %a = load <6 x double>, ptr %A, align 8
%b = load <6 x double>, ptr %B, align 8 %b = load <6 x double>, ptr %B, align 8
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llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[TMP3]], align 8 ; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[TMP3]], align 8
; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[TMP3]], i64 4 ; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[TMP3]], i64 4
; CHECK-NEXT: [[COL_LOAD8:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8 ; CHECK-NEXT: [[COL_LOAD8:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8
; CHECK-NEXT: [[COL_LOAD9:%.*]] = load <2 x double>, ptr [[TMP7]], align 8 ; CHECK-NEXT: [[COL_LOAD9:%.*]] = load <2 x double>, ptr [[TMP7]], align 8
; CHECK-NEXT: [[VEC_GEP10:%.*]] = getelementptr double, ptr [[TMP7]], i64 4 ; CHECK-NEXT: [[VEC_GEP10:%.*]] = getelementptr double, ptr [[TMP7]], i64 4
; CHECK-NEXT: [[COL_LOAD11:%.*]] = load <2 x double>, ptr [[VEC_GEP10]], align 8 ; CHECK-NEXT: [[COL_LOAD11:%.*]] = load <2 x double>, ptr [[VEC_GEP10]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD9]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD9]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]] ; CHECK-NEXT: [[TMP8:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]]
; CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <2 x double> [[COL_LOAD9]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <2 x double> [[COL_LOAD9]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP9:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD8]], <2 x double> [[SPLAT_SPLAT14]], <2 x double> [[TMP8]]) ; CHECK-NEXT: [[TMP9:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD8]], <2 x double> [[SPLAT_SPLAT14]], <2 x double> [[TMP8]])
; CHECK-NEXT: [[SPLAT_SPLAT17:%.*]] = shufflevector <2 x double> [[COL_LOAD11]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT17:%.*]] = shufflevector <2 x double> [[COL_LOAD11]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP10:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT17]] ; CHECK-NEXT: [[TMP10:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT17]]
; CHECK-NEXT: [[SPLAT_SPLAT20:%.*]] = shufflevector <2 x double> [[COL_LOAD11]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT20:%.*]] = shufflevector <2 x double> [[COL_LOAD11]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP11:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD8]], <2 x double> [[SPLAT_SPLAT20]], <2 x double> [[TMP10]]) ; CHECK-NEXT: [[TMP11:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD8]], <2 x double> [[SPLAT_SPLAT20]], <2 x double> [[TMP10]])
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr double, ptr [[TMP3]], i64 8 ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr double, ptr [[TMP3]], i64 8
; CHECK-NEXT: [[COL_LOAD21:%.*]] = load <2 x double>, ptr [[TMP12]], align 8 ; CHECK-NEXT: [[COL_LOAD21:%.*]] = load <2 x double>, ptr [[TMP12]], align 8
; CHECK-NEXT: [[VEC_GEP22:%.*]] = getelementptr double, ptr [[TMP3]], i64 12 ; CHECK-NEXT: [[VEC_GEP22:%.*]] = getelementptr double, ptr [[TMP3]], i64 12
; CHECK-NEXT: [[COL_LOAD23:%.*]] = load <2 x double>, ptr [[VEC_GEP22]], align 8 ; CHECK-NEXT: [[COL_LOAD23:%.*]] = load <2 x double>, ptr [[VEC_GEP22]], align 8
; CHECK-NEXT: [[TMP13:%.*]] = getelementptr double, ptr [[TMP7]], i64 2 ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr double, ptr [[TMP7]], i64 2
; CHECK-NEXT: [[COL_LOAD24:%.*]] = load <2 x double>, ptr [[TMP13]], align 8 ; CHECK-NEXT: [[COL_LOAD24:%.*]] = load <2 x double>, ptr [[TMP13]], align 8
; CHECK-NEXT: [[VEC_GEP25:%.*]] = getelementptr double, ptr [[TMP7]], i64 6 ; CHECK-NEXT: [[VEC_GEP25:%.*]] = getelementptr double, ptr [[TMP7]], i64 6
; CHECK-NEXT: [[COL_LOAD26:%.*]] = load <2 x double>, ptr [[VEC_GEP25]], align 8 ; CHECK-NEXT: [[COL_LOAD26:%.*]] = load <2 x double>, ptr [[VEC_GEP25]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT30:%.*]] = shufflevector <2 x double> [[COL_LOAD24]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT30:%.*]] = shufflevector <2 x double> [[COL_LOAD24]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP14:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD21]], <2 x double> [[SPLAT_SPLAT30]], <2 x double> [[TMP9]]) ; CHECK-NEXT: [[TMP14:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD21]], <2 x double> [[SPLAT_SPLAT30]], <2 x double> [[TMP9]])
; CHECK-NEXT: [[SPLAT_SPLAT33:%.*]] = shufflevector <2 x double> [[COL_LOAD24]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT33:%.*]] = shufflevector <2 x double> [[COL_LOAD24]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP15:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD23]], <2 x double> [[SPLAT_SPLAT33]], <2 x double> [[TMP14]]) ; CHECK-NEXT: [[TMP15:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD23]], <2 x double> [[SPLAT_SPLAT33]], <2 x double> [[TMP14]])
; CHECK-NEXT: [[SPLAT_SPLAT37:%.*]] = shufflevector <2 x double> [[COL_LOAD26]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT37:%.*]] = shufflevector <2 x double> [[COL_LOAD26]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP16:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD21]], <2 x double> [[SPLAT_SPLAT37]], <2 x double> [[TMP11]]) ; CHECK-NEXT: [[TMP16:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD21]], <2 x double> [[SPLAT_SPLAT37]], <2 x double> [[TMP11]])
; CHECK-NEXT: [[SPLAT_SPLAT40:%.*]] = shufflevector <2 x double> [[COL_LOAD26]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT40:%.*]] = shufflevector <2 x double> [[COL_LOAD26]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP17:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD23]], <2 x double> [[SPLAT_SPLAT40]], <2 x double> [[TMP16]]) ; CHECK-NEXT: [[TMP17:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD23]], <2 x double> [[SPLAT_SPLAT40]], <2 x double> [[TMP16]])
; CHECK-NEXT: store <2 x double> [[TMP15]], ptr [[C]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP15]], ptr [[C]], align 8
; CHECK-NEXT: [[VEC_GEP41:%.*]] = getelementptr double, ptr [[C]], i64 4 ; CHECK-NEXT: [[VEC_GEP41:%.*]] = getelementptr double, ptr [[C]], i64 4
; CHECK-NEXT: store <2 x double> [[TMP17]], ptr [[VEC_GEP41]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP17]], ptr [[VEC_GEP41]], align 8
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr double, ptr [[TMP3]], i64 2 ; CHECK-NEXT: [[TMP18:%.*]] = getelementptr double, ptr [[TMP3]], i64 2
; CHECK-NEXT: [[COL_LOAD42:%.*]] = load <2 x double>, ptr [[TMP18]], align 8 ; CHECK-NEXT: [[COL_LOAD42:%.*]] = load <2 x double>, ptr [[TMP18]], align 8
; CHECK-NEXT: [[VEC_GEP43:%.*]] = getelementptr double, ptr [[TMP3]], i64 6 ; CHECK-NEXT: [[VEC_GEP43:%.*]] = getelementptr double, ptr [[TMP3]], i64 6
; CHECK-NEXT: [[COL_LOAD44:%.*]] = load <2 x double>, ptr [[VEC_GEP43]], align 8 ; CHECK-NEXT: [[COL_LOAD44:%.*]] = load <2 x double>, ptr [[VEC_GEP43]], align 8
; CHECK-NEXT: [[COL_LOAD45:%.*]] = load <2 x double>, ptr [[TMP7]], align 8 ; CHECK-NEXT: [[COL_LOAD45:%.*]] = load <2 x double>, ptr [[TMP7]], align 8
; CHECK-NEXT: [[VEC_GEP46:%.*]] = getelementptr double, ptr [[TMP7]], i64 4 ; CHECK-NEXT: [[VEC_GEP46:%.*]] = getelementptr double, ptr [[TMP7]], i64 4
; CHECK-NEXT: [[COL_LOAD47:%.*]] = load <2 x double>, ptr [[VEC_GEP46]], align 8 ; CHECK-NEXT: [[COL_LOAD47:%.*]] = load <2 x double>, ptr [[VEC_GEP46]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT50:%.*]] = shufflevector <2 x double> [[COL_LOAD45]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT50:%.*]] = shufflevector <2 x double> [[COL_LOAD45]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP19:%.*]] = fmul contract <2 x double> [[COL_LOAD42]], [[SPLAT_SPLAT50]] ; CHECK-NEXT: [[TMP19:%.*]] = fmul contract <2 x double> [[COL_LOAD42]], [[SPLAT_SPLAT50]]
; CHECK-NEXT: [[SPLAT_SPLAT53:%.*]] = shufflevector <2 x double> [[COL_LOAD45]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT53:%.*]] = shufflevector <2 x double> [[COL_LOAD45]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP20:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD44]], <2 x double> [[SPLAT_SPLAT53]], <2 x double> [[TMP19]]) ; CHECK-NEXT: [[TMP20:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD44]], <2 x double> [[SPLAT_SPLAT53]], <2 x double> [[TMP19]])
; CHECK-NEXT: [[SPLAT_SPLAT56:%.*]] = shufflevector <2 x double> [[COL_LOAD47]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT56:%.*]] = shufflevector <2 x double> [[COL_LOAD47]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP21:%.*]] = fmul contract <2 x double> [[COL_LOAD42]], [[SPLAT_SPLAT56]] ; CHECK-NEXT: [[TMP21:%.*]] = fmul contract <2 x double> [[COL_LOAD42]], [[SPLAT_SPLAT56]]
; CHECK-NEXT: [[SPLAT_SPLAT59:%.*]] = shufflevector <2 x double> [[COL_LOAD47]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT59:%.*]] = shufflevector <2 x double> [[COL_LOAD47]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP22:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD44]], <2 x double> [[SPLAT_SPLAT59]], <2 x double> [[TMP21]]) ; CHECK-NEXT: [[TMP22:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD44]], <2 x double> [[SPLAT_SPLAT59]], <2 x double> [[TMP21]])
; CHECK-NEXT: [[TMP23:%.*]] = getelementptr double, ptr [[TMP3]], i64 10 ; CHECK-NEXT: [[TMP23:%.*]] = getelementptr double, ptr [[TMP3]], i64 10
; CHECK-NEXT: [[COL_LOAD60:%.*]] = load <2 x double>, ptr [[TMP23]], align 8 ; CHECK-NEXT: [[COL_LOAD60:%.*]] = load <2 x double>, ptr [[TMP23]], align 8
; CHECK-NEXT: [[VEC_GEP61:%.*]] = getelementptr double, ptr [[TMP3]], i64 14 ; CHECK-NEXT: [[VEC_GEP61:%.*]] = getelementptr double, ptr [[TMP3]], i64 14
; CHECK-NEXT: [[COL_LOAD62:%.*]] = load <2 x double>, ptr [[VEC_GEP61]], align 8 ; CHECK-NEXT: [[COL_LOAD62:%.*]] = load <2 x double>, ptr [[VEC_GEP61]], align 8
; CHECK-NEXT: [[TMP24:%.*]] = getelementptr double, ptr [[TMP7]], i64 2 ; CHECK-NEXT: [[TMP24:%.*]] = getelementptr double, ptr [[TMP7]], i64 2
; CHECK-NEXT: [[COL_LOAD63:%.*]] = load <2 x double>, ptr [[TMP24]], align 8 ; CHECK-NEXT: [[COL_LOAD63:%.*]] = load <2 x double>, ptr [[TMP24]], align 8
; CHECK-NEXT: [[VEC_GEP64:%.*]] = getelementptr double, ptr [[TMP7]], i64 6 ; CHECK-NEXT: [[VEC_GEP64:%.*]] = getelementptr double, ptr [[TMP7]], i64 6
; CHECK-NEXT: [[COL_LOAD65:%.*]] = load <2 x double>, ptr [[VEC_GEP64]], align 8 ; CHECK-NEXT: [[COL_LOAD65:%.*]] = load <2 x double>, ptr [[VEC_GEP64]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT69:%.*]] = shufflevector <2 x double> [[COL_LOAD63]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT69:%.*]] = shufflevector <2 x double> [[COL_LOAD63]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP25:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD60]], <2 x double> [[SPLAT_SPLAT69]], <2 x double> [[TMP20]]) ; CHECK-NEXT: [[TMP25:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD60]], <2 x double> [[SPLAT_SPLAT69]], <2 x double> [[TMP20]])
; CHECK-NEXT: [[SPLAT_SPLAT72:%.*]] = shufflevector <2 x double> [[COL_LOAD63]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT72:%.*]] = shufflevector <2 x double> [[COL_LOAD63]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP26:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD62]], <2 x double> [[SPLAT_SPLAT72]], <2 x double> [[TMP25]]) ; CHECK-NEXT: [[TMP26:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD62]], <2 x double> [[SPLAT_SPLAT72]], <2 x double> [[TMP25]])
; CHECK-NEXT: [[SPLAT_SPLAT76:%.*]] = shufflevector <2 x double> [[COL_LOAD65]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT76:%.*]] = shufflevector <2 x double> [[COL_LOAD65]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP27:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD60]], <2 x double> [[SPLAT_SPLAT76]], <2 x double> [[TMP22]]) ; CHECK-NEXT: [[TMP27:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD60]], <2 x double> [[SPLAT_SPLAT76]], <2 x double> [[TMP22]])
; CHECK-NEXT: [[SPLAT_SPLAT79:%.*]] = shufflevector <2 x double> [[COL_LOAD65]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT79:%.*]] = shufflevector <2 x double> [[COL_LOAD65]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP28:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD62]], <2 x double> [[SPLAT_SPLAT79]], <2 x double> [[TMP27]]) ; CHECK-NEXT: [[TMP28:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD62]], <2 x double> [[SPLAT_SPLAT79]], <2 x double> [[TMP27]])
; CHECK-NEXT: [[TMP29:%.*]] = getelementptr double, ptr [[C]], i64 2 ; CHECK-NEXT: [[TMP29:%.*]] = getelementptr double, ptr [[C]], i64 2
; CHECK-NEXT: store <2 x double> [[TMP26]], ptr [[TMP29]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP26]], ptr [[TMP29]], align 8
; CHECK-NEXT: [[VEC_GEP80:%.*]] = getelementptr double, ptr [[C]], i64 6 ; CHECK-NEXT: [[VEC_GEP80:%.*]] = getelementptr double, ptr [[C]], i64 6
; CHECK-NEXT: store <2 x double> [[TMP28]], ptr [[VEC_GEP80]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP28]], ptr [[VEC_GEP80]], align 8
; CHECK-NEXT: [[COL_LOAD81:%.*]] = load <2 x double>, ptr [[TMP3]], align 8 ; CHECK-NEXT: [[COL_LOAD81:%.*]] = load <2 x double>, ptr [[TMP3]], align 8
; CHECK-NEXT: [[VEC_GEP82:%.*]] = getelementptr double, ptr [[TMP3]], i64 4 ; CHECK-NEXT: [[VEC_GEP82:%.*]] = getelementptr double, ptr [[TMP3]], i64 4
; CHECK-NEXT: [[COL_LOAD83:%.*]] = load <2 x double>, ptr [[VEC_GEP82]], align 8 ; CHECK-NEXT: [[COL_LOAD83:%.*]] = load <2 x double>, ptr [[VEC_GEP82]], align 8
; CHECK-NEXT: [[TMP30:%.*]] = getelementptr double, ptr [[TMP7]], i64 8 ; CHECK-NEXT: [[TMP30:%.*]] = getelementptr double, ptr [[TMP7]], i64 8
; CHECK-NEXT: [[COL_LOAD84:%.*]] = load <2 x double>, ptr [[TMP30]], align 8 ; CHECK-NEXT: [[COL_LOAD84:%.*]] = load <2 x double>, ptr [[TMP30]], align 8
; CHECK-NEXT: [[VEC_GEP85:%.*]] = getelementptr double, ptr [[TMP7]], i64 12 ; CHECK-NEXT: [[VEC_GEP85:%.*]] = getelementptr double, ptr [[TMP7]], i64 12
; CHECK-NEXT: [[COL_LOAD86:%.*]] = load <2 x double>, ptr [[VEC_GEP85]], align 8 ; CHECK-NEXT: [[COL_LOAD86:%.*]] = load <2 x double>, ptr [[VEC_GEP85]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT89:%.*]] = shufflevector <2 x double> [[COL_LOAD84]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT89:%.*]] = shufflevector <2 x double> [[COL_LOAD84]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP31:%.*]] = fmul contract <2 x double> [[COL_LOAD81]], [[SPLAT_SPLAT89]] ; CHECK-NEXT: [[TMP31:%.*]] = fmul contract <2 x double> [[COL_LOAD81]], [[SPLAT_SPLAT89]]
; CHECK-NEXT: [[SPLAT_SPLAT92:%.*]] = shufflevector <2 x double> [[COL_LOAD84]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT92:%.*]] = shufflevector <2 x double> [[COL_LOAD84]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP32:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD83]], <2 x double> [[SPLAT_SPLAT92]], <2 x double> [[TMP31]]) ; CHECK-NEXT: [[TMP32:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD83]], <2 x double> [[SPLAT_SPLAT92]], <2 x double> [[TMP31]])
; CHECK-NEXT: [[SPLAT_SPLAT95:%.*]] = shufflevector <2 x double> [[COL_LOAD86]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT95:%.*]] = shufflevector <2 x double> [[COL_LOAD86]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP33:%.*]] = fmul contract <2 x double> [[COL_LOAD81]], [[SPLAT_SPLAT95]] ; CHECK-NEXT: [[TMP33:%.*]] = fmul contract <2 x double> [[COL_LOAD81]], [[SPLAT_SPLAT95]]
; CHECK-NEXT: [[SPLAT_SPLAT98:%.*]] = shufflevector <2 x double> [[COL_LOAD86]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT98:%.*]] = shufflevector <2 x double> [[COL_LOAD86]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP34:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD83]], <2 x double> [[SPLAT_SPLAT98]], <2 x double> [[TMP33]]) ; CHECK-NEXT: [[TMP34:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD83]], <2 x double> [[SPLAT_SPLAT98]], <2 x double> [[TMP33]])
; CHECK-NEXT: [[TMP35:%.*]] = getelementptr double, ptr [[TMP3]], i64 8 ; CHECK-NEXT: [[TMP35:%.*]] = getelementptr double, ptr [[TMP3]], i64 8
; CHECK-NEXT: [[COL_LOAD99:%.*]] = load <2 x double>, ptr [[TMP35]], align 8 ; CHECK-NEXT: [[COL_LOAD99:%.*]] = load <2 x double>, ptr [[TMP35]], align 8
; CHECK-NEXT: [[VEC_GEP100:%.*]] = getelementptr double, ptr [[TMP3]], i64 12 ; CHECK-NEXT: [[VEC_GEP100:%.*]] = getelementptr double, ptr [[TMP3]], i64 12
; CHECK-NEXT: [[COL_LOAD101:%.*]] = load <2 x double>, ptr [[VEC_GEP100]], align 8 ; CHECK-NEXT: [[COL_LOAD101:%.*]] = load <2 x double>, ptr [[VEC_GEP100]], align 8
; CHECK-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[TMP7]], i64 10 ; CHECK-NEXT: [[TMP36:%.*]] = getelementptr double, ptr [[TMP7]], i64 10
; CHECK-NEXT: [[COL_LOAD102:%.*]] = load <2 x double>, ptr [[TMP36]], align 8 ; CHECK-NEXT: [[COL_LOAD102:%.*]] = load <2 x double>, ptr [[TMP36]], align 8
; CHECK-NEXT: [[VEC_GEP103:%.*]] = getelementptr double, ptr [[TMP7]], i64 14 ; CHECK-NEXT: [[VEC_GEP103:%.*]] = getelementptr double, ptr [[TMP7]], i64 14
; CHECK-NEXT: [[COL_LOAD104:%.*]] = load <2 x double>, ptr [[VEC_GEP103]], align 8 ; CHECK-NEXT: [[COL_LOAD104:%.*]] = load <2 x double>, ptr [[VEC_GEP103]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT108:%.*]] = shufflevector <2 x double> [[COL_LOAD102]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT108:%.*]] = shufflevector <2 x double> [[COL_LOAD102]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP37:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD99]], <2 x double> [[SPLAT_SPLAT108]], <2 x double> [[TMP32]]) ; CHECK-NEXT: [[TMP37:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD99]], <2 x double> [[SPLAT_SPLAT108]], <2 x double> [[TMP32]])
; CHECK-NEXT: [[SPLAT_SPLAT111:%.*]] = shufflevector <2 x double> [[COL_LOAD102]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT111:%.*]] = shufflevector <2 x double> [[COL_LOAD102]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP38:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD101]], <2 x double> [[SPLAT_SPLAT111]], <2 x double> [[TMP37]]) ; CHECK-NEXT: [[TMP38:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD101]], <2 x double> [[SPLAT_SPLAT111]], <2 x double> [[TMP37]])
; CHECK-NEXT: [[SPLAT_SPLAT115:%.*]] = shufflevector <2 x double> [[COL_LOAD104]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT115:%.*]] = shufflevector <2 x double> [[COL_LOAD104]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP39:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD99]], <2 x double> [[SPLAT_SPLAT115]], <2 x double> [[TMP34]]) ; CHECK-NEXT: [[TMP39:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD99]], <2 x double> [[SPLAT_SPLAT115]], <2 x double> [[TMP34]])
; CHECK-NEXT: [[SPLAT_SPLAT118:%.*]] = shufflevector <2 x double> [[COL_LOAD104]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT118:%.*]] = shufflevector <2 x double> [[COL_LOAD104]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP40:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD101]], <2 x double> [[SPLAT_SPLAT118]], <2 x double> [[TMP39]]) ; CHECK-NEXT: [[TMP40:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD101]], <2 x double> [[SPLAT_SPLAT118]], <2 x double> [[TMP39]])
; CHECK-NEXT: [[TMP41:%.*]] = getelementptr double, ptr [[C]], i64 8 ; CHECK-NEXT: [[TMP41:%.*]] = getelementptr double, ptr [[C]], i64 8
; CHECK-NEXT: store <2 x double> [[TMP38]], ptr [[TMP41]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP38]], ptr [[TMP41]], align 8
; CHECK-NEXT: [[VEC_GEP119:%.*]] = getelementptr double, ptr [[C]], i64 12 ; CHECK-NEXT: [[VEC_GEP119:%.*]] = getelementptr double, ptr [[C]], i64 12
; CHECK-NEXT: store <2 x double> [[TMP40]], ptr [[VEC_GEP119]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP40]], ptr [[VEC_GEP119]], align 8
; CHECK-NEXT: [[TMP42:%.*]] = getelementptr double, ptr [[TMP3]], i64 2 ; CHECK-NEXT: [[TMP42:%.*]] = getelementptr double, ptr [[TMP3]], i64 2
; CHECK-NEXT: [[COL_LOAD120:%.*]] = load <2 x double>, ptr [[TMP42]], align 8 ; CHECK-NEXT: [[COL_LOAD120:%.*]] = load <2 x double>, ptr [[TMP42]], align 8
; CHECK-NEXT: [[VEC_GEP121:%.*]] = getelementptr double, ptr [[TMP3]], i64 6 ; CHECK-NEXT: [[VEC_GEP121:%.*]] = getelementptr double, ptr [[TMP3]], i64 6
; CHECK-NEXT: [[COL_LOAD122:%.*]] = load <2 x double>, ptr [[VEC_GEP121]], align 8 ; CHECK-NEXT: [[COL_LOAD122:%.*]] = load <2 x double>, ptr [[VEC_GEP121]], align 8
; CHECK-NEXT: [[TMP43:%.*]] = getelementptr double, ptr [[TMP7]], i64 8 ; CHECK-NEXT: [[TMP43:%.*]] = getelementptr double, ptr [[TMP7]], i64 8
; CHECK-NEXT: [[COL_LOAD123:%.*]] = load <2 x double>, ptr [[TMP43]], align 8 ; CHECK-NEXT: [[COL_LOAD123:%.*]] = load <2 x double>, ptr [[TMP43]], align 8
; CHECK-NEXT: [[VEC_GEP124:%.*]] = getelementptr double, ptr [[TMP7]], i64 12 ; CHECK-NEXT: [[VEC_GEP124:%.*]] = getelementptr double, ptr [[TMP7]], i64 12
; CHECK-NEXT: [[COL_LOAD125:%.*]] = load <2 x double>, ptr [[VEC_GEP124]], align 8 ; CHECK-NEXT: [[COL_LOAD125:%.*]] = load <2 x double>, ptr [[VEC_GEP124]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT128:%.*]] = shufflevector <2 x double> [[COL_LOAD123]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT128:%.*]] = shufflevector <2 x double> [[COL_LOAD123]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP44:%.*]] = fmul contract <2 x double> [[COL_LOAD120]], [[SPLAT_SPLAT128]] ; CHECK-NEXT: [[TMP44:%.*]] = fmul contract <2 x double> [[COL_LOAD120]], [[SPLAT_SPLAT128]]
; CHECK-NEXT: [[SPLAT_SPLAT131:%.*]] = shufflevector <2 x double> [[COL_LOAD123]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT131:%.*]] = shufflevector <2 x double> [[COL_LOAD123]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP45:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD122]], <2 x double> [[SPLAT_SPLAT131]], <2 x double> [[TMP44]]) ; CHECK-NEXT: [[TMP45:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD122]], <2 x double> [[SPLAT_SPLAT131]], <2 x double> [[TMP44]])
; CHECK-NEXT: [[SPLAT_SPLAT134:%.*]] = shufflevector <2 x double> [[COL_LOAD125]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT134:%.*]] = shufflevector <2 x double> [[COL_LOAD125]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP46:%.*]] = fmul contract <2 x double> [[COL_LOAD120]], [[SPLAT_SPLAT134]] ; CHECK-NEXT: [[TMP46:%.*]] = fmul contract <2 x double> [[COL_LOAD120]], [[SPLAT_SPLAT134]]
; CHECK-NEXT: [[SPLAT_SPLAT137:%.*]] = shufflevector <2 x double> [[COL_LOAD125]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT137:%.*]] = shufflevector <2 x double> [[COL_LOAD125]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP47:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD122]], <2 x double> [[SPLAT_SPLAT137]], <2 x double> [[TMP46]]) ; CHECK-NEXT: [[TMP47:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD122]], <2 x double> [[SPLAT_SPLAT137]], <2 x double> [[TMP46]])
; CHECK-NEXT: [[TMP48:%.*]] = getelementptr double, ptr [[TMP3]], i64 10 ; CHECK-NEXT: [[TMP48:%.*]] = getelementptr double, ptr [[TMP3]], i64 10
; CHECK-NEXT: [[COL_LOAD138:%.*]] = load <2 x double>, ptr [[TMP48]], align 8 ; CHECK-NEXT: [[COL_LOAD138:%.*]] = load <2 x double>, ptr [[TMP48]], align 8
; CHECK-NEXT: [[VEC_GEP139:%.*]] = getelementptr double, ptr [[TMP3]], i64 14 ; CHECK-NEXT: [[VEC_GEP139:%.*]] = getelementptr double, ptr [[TMP3]], i64 14
; CHECK-NEXT: [[COL_LOAD140:%.*]] = load <2 x double>, ptr [[VEC_GEP139]], align 8 ; CHECK-NEXT: [[COL_LOAD140:%.*]] = load <2 x double>, ptr [[VEC_GEP139]], align 8
; CHECK-NEXT: [[TMP49:%.*]] = getelementptr double, ptr [[TMP7]], i64 10 ; CHECK-NEXT: [[TMP49:%.*]] = getelementptr double, ptr [[TMP7]], i64 10
; CHECK-NEXT: [[COL_LOAD141:%.*]] = load <2 x double>, ptr [[TMP49]], align 8 ; CHECK-NEXT: [[COL_LOAD141:%.*]] = load <2 x double>, ptr [[TMP49]], align 8
; CHECK-NEXT: [[VEC_GEP142:%.*]] = getelementptr double, ptr [[TMP7]], i64 14 ; CHECK-NEXT: [[VEC_GEP142:%.*]] = getelementptr double, ptr [[TMP7]], i64 14
; CHECK-NEXT: [[COL_LOAD143:%.*]] = load <2 x double>, ptr [[VEC_GEP142]], align 8 ; CHECK-NEXT: [[COL_LOAD143:%.*]] = load <2 x double>, ptr [[VEC_GEP142]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT147:%.*]] = shufflevector <2 x double> [[COL_LOAD141]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT147:%.*]] = shufflevector <2 x double> [[COL_LOAD141]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP50:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD138]], <2 x double> [[SPLAT_SPLAT147]], <2 x double> [[TMP45]]) ; CHECK-NEXT: [[TMP50:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD138]], <2 x double> [[SPLAT_SPLAT147]], <2 x double> [[TMP45]])
; CHECK-NEXT: [[SPLAT_SPLAT150:%.*]] = shufflevector <2 x double> [[COL_LOAD141]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT150:%.*]] = shufflevector <2 x double> [[COL_LOAD141]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP51:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD140]], <2 x double> [[SPLAT_SPLAT150]], <2 x double> [[TMP50]]) ; CHECK-NEXT: [[TMP51:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD140]], <2 x double> [[SPLAT_SPLAT150]], <2 x double> [[TMP50]])
; CHECK-NEXT: [[SPLAT_SPLAT154:%.*]] = shufflevector <2 x double> [[COL_LOAD143]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT154:%.*]] = shufflevector <2 x double> [[COL_LOAD143]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP52:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD138]], <2 x double> [[SPLAT_SPLAT154]], <2 x double> [[TMP47]]) ; CHECK-NEXT: [[TMP52:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD138]], <2 x double> [[SPLAT_SPLAT154]], <2 x double> [[TMP47]])
; CHECK-NEXT: [[SPLAT_SPLAT157:%.*]] = shufflevector <2 x double> [[COL_LOAD143]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT157:%.*]] = shufflevector <2 x double> [[COL_LOAD143]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP53:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD140]], <2 x double> [[SPLAT_SPLAT157]], <2 x double> [[TMP52]]) ; CHECK-NEXT: [[TMP53:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD140]], <2 x double> [[SPLAT_SPLAT157]], <2 x double> [[TMP52]])
; CHECK-NEXT: [[TMP54:%.*]] = getelementptr double, ptr [[C]], i64 10 ; CHECK-NEXT: [[TMP54:%.*]] = getelementptr double, ptr [[C]], i64 10
; CHECK-NEXT: store <2 x double> [[TMP51]], ptr [[TMP54]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP51]], ptr [[TMP54]], align 8
; CHECK-NEXT: [[VEC_GEP158:%.*]] = getelementptr double, ptr [[C]], i64 14 ; CHECK-NEXT: [[VEC_GEP158:%.*]] = getelementptr double, ptr [[C]], i64 14
; CHECK-NEXT: store <2 x double> [[TMP53]], ptr [[VEC_GEP158]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP53]], ptr [[VEC_GEP158]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
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define void @multiply_reuse_load(ptr noalias %A, ptr noalias %B, ptr noalias %C) { define void @multiply_reuse_load(ptr noalias %A, ptr noalias %B, ptr noalias %C) {
; CHECK-LABEL: @multiply_reuse_load( ; CHECK-LABEL: @multiply_reuse_load(
; CHECK-NEXT: entry: ; CHECK-NEXT: entry:
; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8 ; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr [[A:%.*]], align 8
; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[A]], i64 4 ; CHECK-NEXT: [[VEC_GEP:%.*]] = getelementptr double, ptr [[A]], i64 4
; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8 ; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <2 x double> [[COL_LOAD]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]] ; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]]
; CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <2 x double> [[COL_LOAD]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT7:%.*]] = shufflevector <2 x double> [[COL_LOAD]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT7]], <2 x double> [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT7]], <2 x double> [[TMP0]])
; CHECK-NEXT: [[SPLAT_SPLAT10:%.*]] = shufflevector <2 x double> [[COL_LOAD1]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT10:%.*]] = shufflevector <2 x double> [[COL_LOAD1]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT10]] ; CHECK-NEXT: [[TMP2:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT10]]
; CHECK-NEXT: [[SPLAT_SPLAT13:%.*]] = shufflevector <2 x double> [[COL_LOAD1]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT13:%.*]] = shufflevector <2 x double> [[COL_LOAD1]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT13]], <2 x double> [[TMP2]]) ; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT13]], <2 x double> [[TMP2]])
; CHECK-NEXT: [[TMP4:%.*]] = getelementptr double, ptr [[A]], i64 8 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr double, ptr [[A]], i64 8
; CHECK-NEXT: [[COL_LOAD14:%.*]] = load <2 x double>, ptr [[TMP4]], align 8 ; CHECK-NEXT: [[COL_LOAD14:%.*]] = load <2 x double>, ptr [[TMP4]], align 8
; CHECK-NEXT: [[VEC_GEP15:%.*]] = getelementptr double, ptr [[A]], i64 12 ; CHECK-NEXT: [[VEC_GEP15:%.*]] = getelementptr double, ptr [[A]], i64 12
; CHECK-NEXT: [[COL_LOAD16:%.*]] = load <2 x double>, ptr [[VEC_GEP15]], align 8 ; CHECK-NEXT: [[COL_LOAD16:%.*]] = load <2 x double>, ptr [[VEC_GEP15]], align 8
; CHECK-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[A]], i64 2 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[A]], i64 2
; CHECK-NEXT: [[COL_LOAD17:%.*]] = load <2 x double>, ptr [[TMP5]], align 8 ; CHECK-NEXT: [[COL_LOAD17:%.*]] = load <2 x double>, ptr [[TMP5]], align 8
; CHECK-NEXT: [[VEC_GEP18:%.*]] = getelementptr double, ptr [[A]], i64 6 ; CHECK-NEXT: [[VEC_GEP18:%.*]] = getelementptr double, ptr [[A]], i64 6
; CHECK-NEXT: [[COL_LOAD19:%.*]] = load <2 x double>, ptr [[VEC_GEP18]], align 8 ; CHECK-NEXT: [[COL_LOAD19:%.*]] = load <2 x double>, ptr [[VEC_GEP18]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT23:%.*]] = shufflevector <2 x double> [[COL_LOAD17]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT23:%.*]] = shufflevector <2 x double> [[COL_LOAD17]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD14]], <2 x double> [[SPLAT_SPLAT23]], <2 x double> [[TMP1]]) ; CHECK-NEXT: [[TMP6:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD14]], <2 x double> [[SPLAT_SPLAT23]], <2 x double> [[TMP1]])
; CHECK-NEXT: [[SPLAT_SPLAT26:%.*]] = shufflevector <2 x double> [[COL_LOAD17]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT26:%.*]] = shufflevector <2 x double> [[COL_LOAD17]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP7:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD16]], <2 x double> [[SPLAT_SPLAT26]], <2 x double> [[TMP6]]) ; CHECK-NEXT: [[TMP7:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD16]], <2 x double> [[SPLAT_SPLAT26]], <2 x double> [[TMP6]])
; CHECK-NEXT: [[SPLAT_SPLAT30:%.*]] = shufflevector <2 x double> [[COL_LOAD19]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT30:%.*]] = shufflevector <2 x double> [[COL_LOAD19]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD14]], <2 x double> [[SPLAT_SPLAT30]], <2 x double> [[TMP3]]) ; CHECK-NEXT: [[TMP8:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD14]], <2 x double> [[SPLAT_SPLAT30]], <2 x double> [[TMP3]])
; CHECK-NEXT: [[SPLAT_SPLAT33:%.*]] = shufflevector <2 x double> [[COL_LOAD19]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT33:%.*]] = shufflevector <2 x double> [[COL_LOAD19]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP9:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD16]], <2 x double> [[SPLAT_SPLAT33]], <2 x double> [[TMP8]]) ; CHECK-NEXT: [[TMP9:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD16]], <2 x double> [[SPLAT_SPLAT33]], <2 x double> [[TMP8]])
; CHECK-NEXT: store <2 x double> [[TMP7]], ptr [[C:%.*]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP7]], ptr [[C:%.*]], align 8
; CHECK-NEXT: [[VEC_GEP34:%.*]] = getelementptr double, ptr [[C]], i64 4 ; CHECK-NEXT: [[VEC_GEP34:%.*]] = getelementptr double, ptr [[C]], i64 4
; CHECK-NEXT: store <2 x double> [[TMP9]], ptr [[VEC_GEP34]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP9]], ptr [[VEC_GEP34]], align 8
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr double, ptr [[A]], i64 2 ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr double, ptr [[A]], i64 2
; CHECK-NEXT: [[COL_LOAD35:%.*]] = load <2 x double>, ptr [[TMP10]], align 8 ; CHECK-NEXT: [[COL_LOAD35:%.*]] = load <2 x double>, ptr [[TMP10]], align 8
; CHECK-NEXT: [[VEC_GEP36:%.*]] = getelementptr double, ptr [[A]], i64 6 ; CHECK-NEXT: [[VEC_GEP36:%.*]] = getelementptr double, ptr [[A]], i64 6
; CHECK-NEXT: [[COL_LOAD37:%.*]] = load <2 x double>, ptr [[VEC_GEP36]], align 8 ; CHECK-NEXT: [[COL_LOAD37:%.*]] = load <2 x double>, ptr [[VEC_GEP36]], align 8
; CHECK-NEXT: [[COL_LOAD38:%.*]] = load <2 x double>, ptr [[A]], align 8 ; CHECK-NEXT: [[COL_LOAD38:%.*]] = load <2 x double>, ptr [[A]], align 8
; CHECK-NEXT: [[VEC_GEP39:%.*]] = getelementptr double, ptr [[A]], i64 4 ; CHECK-NEXT: [[VEC_GEP39:%.*]] = getelementptr double, ptr [[A]], i64 4
; CHECK-NEXT: [[COL_LOAD40:%.*]] = load <2 x double>, ptr [[VEC_GEP39]], align 8 ; CHECK-NEXT: [[COL_LOAD40:%.*]] = load <2 x double>, ptr [[VEC_GEP39]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT43:%.*]] = shufflevector <2 x double> [[COL_LOAD38]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT43:%.*]] = shufflevector <2 x double> [[COL_LOAD38]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP11:%.*]] = fmul contract <2 x double> [[COL_LOAD35]], [[SPLAT_SPLAT43]] ; CHECK-NEXT: [[TMP11:%.*]] = fmul contract <2 x double> [[COL_LOAD35]], [[SPLAT_SPLAT43]]
; CHECK-NEXT: [[SPLAT_SPLAT46:%.*]] = shufflevector <2 x double> [[COL_LOAD38]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT46:%.*]] = shufflevector <2 x double> [[COL_LOAD38]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP12:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD37]], <2 x double> [[SPLAT_SPLAT46]], <2 x double> [[TMP11]]) ; CHECK-NEXT: [[TMP12:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD37]], <2 x double> [[SPLAT_SPLAT46]], <2 x double> [[TMP11]])
; CHECK-NEXT: [[SPLAT_SPLAT49:%.*]] = shufflevector <2 x double> [[COL_LOAD40]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT49:%.*]] = shufflevector <2 x double> [[COL_LOAD40]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP13:%.*]] = fmul contract <2 x double> [[COL_LOAD35]], [[SPLAT_SPLAT49]] ; CHECK-NEXT: [[TMP13:%.*]] = fmul contract <2 x double> [[COL_LOAD35]], [[SPLAT_SPLAT49]]
; CHECK-NEXT: [[SPLAT_SPLAT52:%.*]] = shufflevector <2 x double> [[COL_LOAD40]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT52:%.*]] = shufflevector <2 x double> [[COL_LOAD40]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP14:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD37]], <2 x double> [[SPLAT_SPLAT52]], <2 x double> [[TMP13]]) ; CHECK-NEXT: [[TMP14:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD37]], <2 x double> [[SPLAT_SPLAT52]], <2 x double> [[TMP13]])
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr double, ptr [[A]], i64 10 ; CHECK-NEXT: [[TMP15:%.*]] = getelementptr double, ptr [[A]], i64 10
; CHECK-NEXT: [[COL_LOAD53:%.*]] = load <2 x double>, ptr [[TMP15]], align 8 ; CHECK-NEXT: [[COL_LOAD53:%.*]] = load <2 x double>, ptr [[TMP15]], align 8
; CHECK-NEXT: [[VEC_GEP54:%.*]] = getelementptr double, ptr [[A]], i64 14 ; CHECK-NEXT: [[VEC_GEP54:%.*]] = getelementptr double, ptr [[A]], i64 14
; CHECK-NEXT: [[COL_LOAD55:%.*]] = load <2 x double>, ptr [[VEC_GEP54]], align 8 ; CHECK-NEXT: [[COL_LOAD55:%.*]] = load <2 x double>, ptr [[VEC_GEP54]], align 8
; CHECK-NEXT: [[TMP16:%.*]] = getelementptr double, ptr [[A]], i64 2 ; CHECK-NEXT: [[TMP16:%.*]] = getelementptr double, ptr [[A]], i64 2
; CHECK-NEXT: [[COL_LOAD56:%.*]] = load <2 x double>, ptr [[TMP16]], align 8 ; CHECK-NEXT: [[COL_LOAD56:%.*]] = load <2 x double>, ptr [[TMP16]], align 8
; CHECK-NEXT: [[VEC_GEP57:%.*]] = getelementptr double, ptr [[A]], i64 6 ; CHECK-NEXT: [[VEC_GEP57:%.*]] = getelementptr double, ptr [[A]], i64 6
; CHECK-NEXT: [[COL_LOAD58:%.*]] = load <2 x double>, ptr [[VEC_GEP57]], align 8 ; CHECK-NEXT: [[COL_LOAD58:%.*]] = load <2 x double>, ptr [[VEC_GEP57]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT62:%.*]] = shufflevector <2 x double> [[COL_LOAD56]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT62:%.*]] = shufflevector <2 x double> [[COL_LOAD56]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP17:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD53]], <2 x double> [[SPLAT_SPLAT62]], <2 x double> [[TMP12]]) ; CHECK-NEXT: [[TMP17:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD53]], <2 x double> [[SPLAT_SPLAT62]], <2 x double> [[TMP12]])
; CHECK-NEXT: [[SPLAT_SPLAT65:%.*]] = shufflevector <2 x double> [[COL_LOAD56]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT65:%.*]] = shufflevector <2 x double> [[COL_LOAD56]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP18:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD55]], <2 x double> [[SPLAT_SPLAT65]], <2 x double> [[TMP17]]) ; CHECK-NEXT: [[TMP18:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD55]], <2 x double> [[SPLAT_SPLAT65]], <2 x double> [[TMP17]])
; CHECK-NEXT: [[SPLAT_SPLAT69:%.*]] = shufflevector <2 x double> [[COL_LOAD58]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT69:%.*]] = shufflevector <2 x double> [[COL_LOAD58]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP19:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD53]], <2 x double> [[SPLAT_SPLAT69]], <2 x double> [[TMP14]]) ; CHECK-NEXT: [[TMP19:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD53]], <2 x double> [[SPLAT_SPLAT69]], <2 x double> [[TMP14]])
; CHECK-NEXT: [[SPLAT_SPLAT72:%.*]] = shufflevector <2 x double> [[COL_LOAD58]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT72:%.*]] = shufflevector <2 x double> [[COL_LOAD58]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP20:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD55]], <2 x double> [[SPLAT_SPLAT72]], <2 x double> [[TMP19]]) ; CHECK-NEXT: [[TMP20:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD55]], <2 x double> [[SPLAT_SPLAT72]], <2 x double> [[TMP19]])
; CHECK-NEXT: [[TMP21:%.*]] = getelementptr double, ptr [[C]], i64 2 ; CHECK-NEXT: [[TMP21:%.*]] = getelementptr double, ptr [[C]], i64 2
; CHECK-NEXT: store <2 x double> [[TMP18]], ptr [[TMP21]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP18]], ptr [[TMP21]], align 8
; CHECK-NEXT: [[VEC_GEP73:%.*]] = getelementptr double, ptr [[C]], i64 6 ; CHECK-NEXT: [[VEC_GEP73:%.*]] = getelementptr double, ptr [[C]], i64 6
; CHECK-NEXT: store <2 x double> [[TMP20]], ptr [[VEC_GEP73]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP20]], ptr [[VEC_GEP73]], align 8
; CHECK-NEXT: [[COL_LOAD74:%.*]] = load <2 x double>, ptr [[A]], align 8 ; CHECK-NEXT: [[COL_LOAD74:%.*]] = load <2 x double>, ptr [[A]], align 8
; CHECK-NEXT: [[VEC_GEP75:%.*]] = getelementptr double, ptr [[A]], i64 4 ; CHECK-NEXT: [[VEC_GEP75:%.*]] = getelementptr double, ptr [[A]], i64 4
; CHECK-NEXT: [[COL_LOAD76:%.*]] = load <2 x double>, ptr [[VEC_GEP75]], align 8 ; CHECK-NEXT: [[COL_LOAD76:%.*]] = load <2 x double>, ptr [[VEC_GEP75]], align 8
; CHECK-NEXT: [[TMP22:%.*]] = getelementptr double, ptr [[A]], i64 8 ; CHECK-NEXT: [[TMP22:%.*]] = getelementptr double, ptr [[A]], i64 8
; CHECK-NEXT: [[COL_LOAD77:%.*]] = load <2 x double>, ptr [[TMP22]], align 8 ; CHECK-NEXT: [[COL_LOAD77:%.*]] = load <2 x double>, ptr [[TMP22]], align 8
; CHECK-NEXT: [[VEC_GEP78:%.*]] = getelementptr double, ptr [[A]], i64 12 ; CHECK-NEXT: [[VEC_GEP78:%.*]] = getelementptr double, ptr [[A]], i64 12
; CHECK-NEXT: [[COL_LOAD79:%.*]] = load <2 x double>, ptr [[VEC_GEP78]], align 8 ; CHECK-NEXT: [[COL_LOAD79:%.*]] = load <2 x double>, ptr [[VEC_GEP78]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT82:%.*]] = shufflevector <2 x double> [[COL_LOAD77]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT82:%.*]] = shufflevector <2 x double> [[COL_LOAD77]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP23:%.*]] = fmul contract <2 x double> [[COL_LOAD74]], [[SPLAT_SPLAT82]] ; CHECK-NEXT: [[TMP23:%.*]] = fmul contract <2 x double> [[COL_LOAD74]], [[SPLAT_SPLAT82]]
; CHECK-NEXT: [[SPLAT_SPLAT85:%.*]] = shufflevector <2 x double> [[COL_LOAD77]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT85:%.*]] = shufflevector <2 x double> [[COL_LOAD77]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP24:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD76]], <2 x double> [[SPLAT_SPLAT85]], <2 x double> [[TMP23]]) ; CHECK-NEXT: [[TMP24:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD76]], <2 x double> [[SPLAT_SPLAT85]], <2 x double> [[TMP23]])
; CHECK-NEXT: [[SPLAT_SPLAT88:%.*]] = shufflevector <2 x double> [[COL_LOAD79]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT88:%.*]] = shufflevector <2 x double> [[COL_LOAD79]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP25:%.*]] = fmul contract <2 x double> [[COL_LOAD74]], [[SPLAT_SPLAT88]] ; CHECK-NEXT: [[TMP25:%.*]] = fmul contract <2 x double> [[COL_LOAD74]], [[SPLAT_SPLAT88]]
; CHECK-NEXT: [[SPLAT_SPLAT91:%.*]] = shufflevector <2 x double> [[COL_LOAD79]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT91:%.*]] = shufflevector <2 x double> [[COL_LOAD79]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP26:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD76]], <2 x double> [[SPLAT_SPLAT91]], <2 x double> [[TMP25]]) ; CHECK-NEXT: [[TMP26:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD76]], <2 x double> [[SPLAT_SPLAT91]], <2 x double> [[TMP25]])
; CHECK-NEXT: [[TMP27:%.*]] = getelementptr double, ptr [[A]], i64 8 ; CHECK-NEXT: [[TMP27:%.*]] = getelementptr double, ptr [[A]], i64 8
; CHECK-NEXT: [[COL_LOAD92:%.*]] = load <2 x double>, ptr [[TMP27]], align 8 ; CHECK-NEXT: [[COL_LOAD92:%.*]] = load <2 x double>, ptr [[TMP27]], align 8
; CHECK-NEXT: [[VEC_GEP93:%.*]] = getelementptr double, ptr [[A]], i64 12 ; CHECK-NEXT: [[VEC_GEP93:%.*]] = getelementptr double, ptr [[A]], i64 12
; CHECK-NEXT: [[COL_LOAD94:%.*]] = load <2 x double>, ptr [[VEC_GEP93]], align 8 ; CHECK-NEXT: [[COL_LOAD94:%.*]] = load <2 x double>, ptr [[VEC_GEP93]], align 8
; CHECK-NEXT: [[TMP28:%.*]] = getelementptr double, ptr [[A]], i64 10 ; CHECK-NEXT: [[TMP28:%.*]] = getelementptr double, ptr [[A]], i64 10
; CHECK-NEXT: [[COL_LOAD95:%.*]] = load <2 x double>, ptr [[TMP28]], align 8 ; CHECK-NEXT: [[COL_LOAD95:%.*]] = load <2 x double>, ptr [[TMP28]], align 8
; CHECK-NEXT: [[VEC_GEP96:%.*]] = getelementptr double, ptr [[A]], i64 14 ; CHECK-NEXT: [[VEC_GEP96:%.*]] = getelementptr double, ptr [[A]], i64 14
; CHECK-NEXT: [[COL_LOAD97:%.*]] = load <2 x double>, ptr [[VEC_GEP96]], align 8 ; CHECK-NEXT: [[COL_LOAD97:%.*]] = load <2 x double>, ptr [[VEC_GEP96]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT101:%.*]] = shufflevector <2 x double> [[COL_LOAD95]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT101:%.*]] = shufflevector <2 x double> [[COL_LOAD95]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP29:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD92]], <2 x double> [[SPLAT_SPLAT101]], <2 x double> [[TMP24]]) ; CHECK-NEXT: [[TMP29:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD92]], <2 x double> [[SPLAT_SPLAT101]], <2 x double> [[TMP24]])
; CHECK-NEXT: [[SPLAT_SPLAT104:%.*]] = shufflevector <2 x double> [[COL_LOAD95]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT104:%.*]] = shufflevector <2 x double> [[COL_LOAD95]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP30:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD94]], <2 x double> [[SPLAT_SPLAT104]], <2 x double> [[TMP29]]) ; CHECK-NEXT: [[TMP30:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD94]], <2 x double> [[SPLAT_SPLAT104]], <2 x double> [[TMP29]])
; CHECK-NEXT: [[SPLAT_SPLAT108:%.*]] = shufflevector <2 x double> [[COL_LOAD97]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT108:%.*]] = shufflevector <2 x double> [[COL_LOAD97]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP31:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD92]], <2 x double> [[SPLAT_SPLAT108]], <2 x double> [[TMP26]]) ; CHECK-NEXT: [[TMP31:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD92]], <2 x double> [[SPLAT_SPLAT108]], <2 x double> [[TMP26]])
; CHECK-NEXT: [[SPLAT_SPLAT111:%.*]] = shufflevector <2 x double> [[COL_LOAD97]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT111:%.*]] = shufflevector <2 x double> [[COL_LOAD97]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP32:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD94]], <2 x double> [[SPLAT_SPLAT111]], <2 x double> [[TMP31]]) ; CHECK-NEXT: [[TMP32:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD94]], <2 x double> [[SPLAT_SPLAT111]], <2 x double> [[TMP31]])
; CHECK-NEXT: [[TMP33:%.*]] = getelementptr double, ptr [[C]], i64 8 ; CHECK-NEXT: [[TMP33:%.*]] = getelementptr double, ptr [[C]], i64 8
; CHECK-NEXT: store <2 x double> [[TMP30]], ptr [[TMP33]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP30]], ptr [[TMP33]], align 8
; CHECK-NEXT: [[VEC_GEP112:%.*]] = getelementptr double, ptr [[C]], i64 12 ; CHECK-NEXT: [[VEC_GEP112:%.*]] = getelementptr double, ptr [[C]], i64 12
; CHECK-NEXT: store <2 x double> [[TMP32]], ptr [[VEC_GEP112]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP32]], ptr [[VEC_GEP112]], align 8
; CHECK-NEXT: [[TMP34:%.*]] = getelementptr double, ptr [[A]], i64 2 ; CHECK-NEXT: [[TMP34:%.*]] = getelementptr double, ptr [[A]], i64 2
; CHECK-NEXT: [[COL_LOAD113:%.*]] = load <2 x double>, ptr [[TMP34]], align 8 ; CHECK-NEXT: [[COL_LOAD113:%.*]] = load <2 x double>, ptr [[TMP34]], align 8
; CHECK-NEXT: [[VEC_GEP114:%.*]] = getelementptr double, ptr [[A]], i64 6 ; CHECK-NEXT: [[VEC_GEP114:%.*]] = getelementptr double, ptr [[A]], i64 6
; CHECK-NEXT: [[COL_LOAD115:%.*]] = load <2 x double>, ptr [[VEC_GEP114]], align 8 ; CHECK-NEXT: [[COL_LOAD115:%.*]] = load <2 x double>, ptr [[VEC_GEP114]], align 8
; CHECK-NEXT: [[TMP35:%.*]] = getelementptr double, ptr [[A]], i64 8 ; CHECK-NEXT: [[TMP35:%.*]] = getelementptr double, ptr [[A]], i64 8
; CHECK-NEXT: [[COL_LOAD116:%.*]] = load <2 x double>, ptr [[TMP35]], align 8 ; CHECK-NEXT: [[COL_LOAD116:%.*]] = load <2 x double>, ptr [[TMP35]], align 8
; CHECK-NEXT: [[VEC_GEP117:%.*]] = getelementptr double, ptr [[A]], i64 12 ; CHECK-NEXT: [[VEC_GEP117:%.*]] = getelementptr double, ptr [[A]], i64 12
; CHECK-NEXT: [[COL_LOAD118:%.*]] = load <2 x double>, ptr [[VEC_GEP117]], align 8 ; CHECK-NEXT: [[COL_LOAD118:%.*]] = load <2 x double>, ptr [[VEC_GEP117]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT121:%.*]] = shufflevector <2 x double> [[COL_LOAD116]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT121:%.*]] = shufflevector <2 x double> [[COL_LOAD116]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP36:%.*]] = fmul contract <2 x double> [[COL_LOAD113]], [[SPLAT_SPLAT121]] ; CHECK-NEXT: [[TMP36:%.*]] = fmul contract <2 x double> [[COL_LOAD113]], [[SPLAT_SPLAT121]]
; CHECK-NEXT: [[SPLAT_SPLAT124:%.*]] = shufflevector <2 x double> [[COL_LOAD116]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT124:%.*]] = shufflevector <2 x double> [[COL_LOAD116]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP37:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD115]], <2 x double> [[SPLAT_SPLAT124]], <2 x double> [[TMP36]]) ; CHECK-NEXT: [[TMP37:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD115]], <2 x double> [[SPLAT_SPLAT124]], <2 x double> [[TMP36]])
; CHECK-NEXT: [[SPLAT_SPLAT127:%.*]] = shufflevector <2 x double> [[COL_LOAD118]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT127:%.*]] = shufflevector <2 x double> [[COL_LOAD118]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP38:%.*]] = fmul contract <2 x double> [[COL_LOAD113]], [[SPLAT_SPLAT127]] ; CHECK-NEXT: [[TMP38:%.*]] = fmul contract <2 x double> [[COL_LOAD113]], [[SPLAT_SPLAT127]]
; CHECK-NEXT: [[SPLAT_SPLAT130:%.*]] = shufflevector <2 x double> [[COL_LOAD118]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT130:%.*]] = shufflevector <2 x double> [[COL_LOAD118]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP39:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD115]], <2 x double> [[SPLAT_SPLAT130]], <2 x double> [[TMP38]]) ; CHECK-NEXT: [[TMP39:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD115]], <2 x double> [[SPLAT_SPLAT130]], <2 x double> [[TMP38]])
; CHECK-NEXT: [[TMP40:%.*]] = getelementptr double, ptr [[A]], i64 10 ; CHECK-NEXT: [[TMP40:%.*]] = getelementptr double, ptr [[A]], i64 10
; CHECK-NEXT: [[COL_LOAD131:%.*]] = load <2 x double>, ptr [[TMP40]], align 8 ; CHECK-NEXT: [[COL_LOAD131:%.*]] = load <2 x double>, ptr [[TMP40]], align 8
; CHECK-NEXT: [[VEC_GEP132:%.*]] = getelementptr double, ptr [[A]], i64 14 ; CHECK-NEXT: [[VEC_GEP132:%.*]] = getelementptr double, ptr [[A]], i64 14
; CHECK-NEXT: [[COL_LOAD133:%.*]] = load <2 x double>, ptr [[VEC_GEP132]], align 8 ; CHECK-NEXT: [[COL_LOAD133:%.*]] = load <2 x double>, ptr [[VEC_GEP132]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT140:%.*]] = shufflevector <2 x double> [[COL_LOAD131]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT140:%.*]] = shufflevector <2 x double> [[COL_LOAD131]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP41:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD131]], <2 x double> [[SPLAT_SPLAT140]], <2 x double> [[TMP37]]) ; CHECK-NEXT: [[TMP41:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD131]], <2 x double> [[SPLAT_SPLAT140]], <2 x double> [[TMP37]])
; CHECK-NEXT: [[SPLAT_SPLAT143:%.*]] = shufflevector <2 x double> [[COL_LOAD131]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT143:%.*]] = shufflevector <2 x double> [[COL_LOAD131]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP42:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD133]], <2 x double> [[SPLAT_SPLAT143]], <2 x double> [[TMP41]]) ; CHECK-NEXT: [[TMP42:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD133]], <2 x double> [[SPLAT_SPLAT143]], <2 x double> [[TMP41]])
; CHECK-NEXT: [[SPLAT_SPLAT147:%.*]] = shufflevector <2 x double> [[COL_LOAD133]], <2 x double> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT147:%.*]] = shufflevector <2 x double> [[COL_LOAD133]], <2 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP43:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD131]], <2 x double> [[SPLAT_SPLAT147]], <2 x double> [[TMP39]]) ; CHECK-NEXT: [[TMP43:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD131]], <2 x double> [[SPLAT_SPLAT147]], <2 x double> [[TMP39]])
; CHECK-NEXT: [[SPLAT_SPLAT150:%.*]] = shufflevector <2 x double> [[COL_LOAD133]], <2 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT150:%.*]] = shufflevector <2 x double> [[COL_LOAD133]], <2 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP44:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD133]], <2 x double> [[SPLAT_SPLAT150]], <2 x double> [[TMP43]]) ; CHECK-NEXT: [[TMP44:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD133]], <2 x double> [[SPLAT_SPLAT150]], <2 x double> [[TMP43]])
; CHECK-NEXT: [[TMP45:%.*]] = getelementptr double, ptr [[C]], i64 10 ; CHECK-NEXT: [[TMP45:%.*]] = getelementptr double, ptr [[C]], i64 10
; CHECK-NEXT: store <2 x double> [[TMP42]], ptr [[TMP45]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP42]], ptr [[TMP45]], align 8
; CHECK-NEXT: [[VEC_GEP151:%.*]] = getelementptr double, ptr [[C]], i64 14 ; CHECK-NEXT: [[VEC_GEP151:%.*]] = getelementptr double, ptr [[C]], i64 14
; CHECK-NEXT: store <2 x double> [[TMP44]], ptr [[VEC_GEP151]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP44]], ptr [[VEC_GEP151]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%a = load <16 x double>, ptr %A, align 8 %a = load <16 x double>, ptr %A, align 8
%c = call <16 x double> @llvm.matrix.multiply(<16 x double> %a, <16 x double> %a, i32 4, i32 4, i32 4) %c = call <16 x double> @llvm.matrix.multiply(<16 x double> %a, <16 x double> %a, i32 4, i32 4, i32 4)
store <16 x double> %c, ptr %C, align 8 store <16 x double> %c, ptr %C, align 8
ret void ret void
} }
declare <16 x double> @llvm.matrix.multiply(<16 x double>, <16 x double>, i32, i32, i32) declare <16 x double> @llvm.matrix.multiply(<16 x double>, <16 x double>, i32, i32, i32)

llvm/test/Transforms/LowerMatrixIntrinsics/multiply-minimal.ll

Show All 17 Lines
; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8 ; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr [[VEC_GEP]], align 8
; CHECK-NEXT: [[VEC_GEP2:%.*]] = getelementptr double, ptr [[A]], i64 4 ; CHECK-NEXT: [[VEC_GEP2:%.*]] = getelementptr double, ptr [[A]], i64 4
; CHECK-NEXT: [[COL_LOAD3:%.*]] = load <2 x double>, ptr [[VEC_GEP2]], align 8 ; CHECK-NEXT: [[COL_LOAD3:%.*]] = load <2 x double>, ptr [[VEC_GEP2]], align 8
; CHECK-NEXT: [[VEC_GEP4:%.*]] = getelementptr double, ptr [[A]], i64 6 ; CHECK-NEXT: [[VEC_GEP4:%.*]] = getelementptr double, ptr [[A]], i64 6
; CHECK-NEXT: [[COL_LOAD5:%.*]] = load <2 x double>, ptr [[VEC_GEP4]], align 8 ; CHECK-NEXT: [[COL_LOAD5:%.*]] = load <2 x double>, ptr [[VEC_GEP4]], align 8
; CHECK-NEXT: [[COL_LOAD6:%.*]] = load <4 x double>, ptr [[B:%.*]], align 8 ; CHECK-NEXT: [[COL_LOAD6:%.*]] = load <4 x double>, ptr [[B:%.*]], align 8
; CHECK-NEXT: [[VEC_GEP7:%.*]] = getelementptr double, ptr [[B]], i64 4 ; CHECK-NEXT: [[VEC_GEP7:%.*]] = getelementptr double, ptr [[B]], i64 4
; CHECK-NEXT: [[COL_LOAD8:%.*]] = load <4 x double>, ptr [[VEC_GEP7]], align 8 ; CHECK-NEXT: [[COL_LOAD8:%.*]] = load <4 x double>, ptr [[VEC_GEP7]], align 8
; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <4 x double> [[COL_LOAD6]], <4 x double> undef, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT:%.*]] = shufflevector <4 x double> [[COL_LOAD6]], <4 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]] ; CHECK-NEXT: [[TMP0:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT]]
; CHECK-NEXT: [[SPLAT_SPLAT11:%.*]] = shufflevector <4 x double> [[COL_LOAD6]], <4 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT11:%.*]] = shufflevector <4 x double> [[COL_LOAD6]], <4 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT11]], <2 x double> [[TMP0]]) ; CHECK-NEXT: [[TMP1:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT11]], <2 x double> [[TMP0]])
; CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <4 x double> [[COL_LOAD6]], <4 x double> undef, <2 x i32> <i32 2, i32 2> ; CHECK-NEXT: [[SPLAT_SPLAT14:%.*]] = shufflevector <4 x double> [[COL_LOAD6]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
; CHECK-NEXT: [[TMP2:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD3]], <2 x double> [[SPLAT_SPLAT14]], <2 x double> [[TMP1]]) ; CHECK-NEXT: [[TMP2:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD3]], <2 x double> [[SPLAT_SPLAT14]], <2 x double> [[TMP1]])
; CHECK-NEXT: [[SPLAT_SPLAT17:%.*]] = shufflevector <4 x double> [[COL_LOAD6]], <4 x double> undef, <2 x i32> <i32 3, i32 3> ; CHECK-NEXT: [[SPLAT_SPLAT17:%.*]] = shufflevector <4 x double> [[COL_LOAD6]], <4 x double> poison, <2 x i32> <i32 3, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD5]], <2 x double> [[SPLAT_SPLAT17]], <2 x double> [[TMP2]]) ; CHECK-NEXT: [[TMP3:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD5]], <2 x double> [[SPLAT_SPLAT17]], <2 x double> [[TMP2]])
; CHECK-NEXT: [[SPLAT_SPLAT20:%.*]] = shufflevector <4 x double> [[COL_LOAD8]], <4 x double> undef, <2 x i32> zeroinitializer ; CHECK-NEXT: [[SPLAT_SPLAT20:%.*]] = shufflevector <4 x double> [[COL_LOAD8]], <4 x double> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT20]] ; CHECK-NEXT: [[TMP4:%.*]] = fmul contract <2 x double> [[COL_LOAD]], [[SPLAT_SPLAT20]]
; CHECK-NEXT: [[SPLAT_SPLAT23:%.*]] = shufflevector <4 x double> [[COL_LOAD8]], <4 x double> undef, <2 x i32> <i32 1, i32 1> ; CHECK-NEXT: [[SPLAT_SPLAT23:%.*]] = shufflevector <4 x double> [[COL_LOAD8]], <4 x double> poison, <2 x i32> <i32 1, i32 1>
; CHECK-NEXT: [[TMP5:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT23]], <2 x double> [[TMP4]]) ; CHECK-NEXT: [[TMP5:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD1]], <2 x double> [[SPLAT_SPLAT23]], <2 x double> [[TMP4]])
; CHECK-NEXT: [[SPLAT_SPLAT26:%.*]] = shufflevector <4 x double> [[COL_LOAD8]], <4 x double> undef, <2 x i32> <i32 2, i32 2> ; CHECK-NEXT: [[SPLAT_SPLAT26:%.*]] = shufflevector <4 x double> [[COL_LOAD8]], <4 x double> poison, <2 x i32> <i32 2, i32 2>
; CHECK-NEXT: [[TMP6:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD3]], <2 x double> [[SPLAT_SPLAT26]], <2 x double> [[TMP5]]) ; CHECK-NEXT: [[TMP6:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD3]], <2 x double> [[SPLAT_SPLAT26]], <2 x double> [[TMP5]])
; CHECK-NEXT: [[SPLAT_SPLAT29:%.*]] = shufflevector <4 x double> [[COL_LOAD8]], <4 x double> undef, <2 x i32> <i32 3, i32 3> ; CHECK-NEXT: [[SPLAT_SPLAT29:%.*]] = shufflevector <4 x double> [[COL_LOAD8]], <4 x double> poison, <2 x i32> <i32 3, i32 3>
; CHECK-NEXT: [[TMP7:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD5]], <2 x double> [[SPLAT_SPLAT29]], <2 x double> [[TMP6]]) ; CHECK-NEXT: [[TMP7:%.*]] = call contract <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[COL_LOAD5]], <2 x double> [[SPLAT_SPLAT29]], <2 x double> [[TMP6]])
; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[C:%.*]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP3]], ptr [[C:%.*]], align 8
; CHECK-NEXT: [[VEC_GEP30:%.*]] = getelementptr double, ptr [[C]], i64 2 ; CHECK-NEXT: [[VEC_GEP30:%.*]] = getelementptr double, ptr [[C]], i64 2
; CHECK-NEXT: store <2 x double> [[TMP7]], ptr [[VEC_GEP30]], align 8 ; CHECK-NEXT: store <2 x double> [[TMP7]], ptr [[VEC_GEP30]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
; ;
entry: entry:
%a = load <8 x double>, ptr %A, align 8 %a = load <8 x double>, ptr %A, align 8
Show All 9 Lines

llvm/test/Transforms/PhaseOrdering/X86/pr61061.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s ; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s
; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s ; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s
; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s ; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s ; RUN: opt < %s -O3 -S -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s
define <2 x i64> @PR61061(<2 x i64> noundef %vect) { define <2 x i64> @PR61061(<2 x i64> noundef %vect) {
; CHECK-LABEL: define <2 x i64> @PR61061 ; CHECK-LABEL: define <2 x i64> @PR61061
; CHECK-SAME: (<2 x i64> noundef [[VECT:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { ; CHECK-SAME: (<2 x i64> noundef [[VECT:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[BC0:%.*]] = bitcast <2 x i64> [[VECT]] to <16 x i8> ; CHECK-NEXT: [[BC0:%.*]] = bitcast <2 x i64> [[VECT]] to <16 x i8>
; CHECK-NEXT: [[PTR_SROA_0_15_VEC_INSERT:%.*]] = shufflevector <16 x i8> [[BC0]], <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[PTR_SROA_0_15_VEC_INSERT:%.*]] = shufflevector <16 x i8> [[BC0]], <16 x i8> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[PTR_SROA_0_15_VEC_INSERT]] to <2 x i64> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[PTR_SROA_0_15_VEC_INSERT]] to <2 x i64>
; CHECK-NEXT: ret <2 x i64> [[TMP1]] ; CHECK-NEXT: ret <2 x i64> [[TMP1]]
; ;
%ptr = alloca <2 x i64>, align 16 %ptr = alloca <2 x i64>, align 16
call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %ptr) call void @llvm.lifetime.start.p0(i64 16, ptr nonnull %ptr)
%bc0 = bitcast <2 x i64> %vect to <16 x i8> %bc0 = bitcast <2 x i64> %vect to <16 x i8>
%bc1 = bitcast <2 x i64> %vect to <16 x i8> %bc1 = bitcast <2 x i64> %vect to <16 x i8>
%bc2 = bitcast <2 x i64> %vect to <16 x i8> %bc2 = bitcast <2 x i64> %vect to <16 x i8>
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llvm/test/Transforms/PhaseOrdering/X86/scalarization.ll

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; CHECK-NEXT: [[OP_RDX:%.*]] = add nsw i32 [[DIV17]], 317426 ; CHECK-NEXT: [[OP_RDX:%.*]] = add nsw i32 [[DIV17]], 317426
; CHECK-NEXT: [[OP_RDX9:%.*]] = add nsw i32 [[DIV]], [[DIV9]] ; CHECK-NEXT: [[OP_RDX9:%.*]] = add nsw i32 [[DIV]], [[DIV9]]
; CHECK-NEXT: [[OP_RDX10:%.*]] = add i32 [[MUL5]], [[MUL13]] ; CHECK-NEXT: [[OP_RDX10:%.*]] = add i32 [[MUL5]], [[MUL13]]
; CHECK-NEXT: [[OP_RDX11:%.*]] = add i32 [[MUL]], [[MUL21]] ; CHECK-NEXT: [[OP_RDX11:%.*]] = add i32 [[MUL]], [[MUL21]]
; CHECK-NEXT: [[OP_RDX12:%.*]] = add i32 [[OP_RDX]], [[OP_RDX9]] ; CHECK-NEXT: [[OP_RDX12:%.*]] = add i32 [[OP_RDX]], [[OP_RDX9]]
; CHECK-NEXT: [[OP_RDX13:%.*]] = add i32 [[OP_RDX10]], [[OP_RDX11]] ; CHECK-NEXT: [[OP_RDX13:%.*]] = add i32 [[OP_RDX10]], [[OP_RDX11]]
; CHECK-NEXT: [[OP_RDX14:%.*]] = add i32 [[OP_RDX12]], [[OP_RDX13]] ; CHECK-NEXT: [[OP_RDX14:%.*]] = add i32 [[OP_RDX12]], [[OP_RDX13]]
; CHECK-NEXT: [[OP_RDX15:%.*]] = add i32 [[OP_RDX14]], [[Y:%.*]] ; CHECK-NEXT: [[OP_RDX15:%.*]] = add i32 [[OP_RDX14]], [[Y:%.*]]
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> <i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[OP_RDX15]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[OP_RDX15]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT: [[ADD29:%.*]] = add <4 x i32> [[TMP2]], [[NUM:%.*]] ; CHECK-NEXT: [[ADD29:%.*]] = add <4 x i32> [[TMP2]], [[NUM:%.*]]
; CHECK-NEXT: ret <4 x i32> [[ADD29]] ; CHECK-NEXT: ret <4 x i32> [[ADD29]]
; ;
%add = add <4 x i32> %num, <i32 1, i32 1, i32 1, i32 1> %add = add <4 x i32> %num, <i32 1, i32 1, i32 1, i32 1>
%div = sdiv i32 %k, 2 %div = sdiv i32 %k, 2
%splatinsert = insertelement <4 x i32> undef, i32 %div, i32 0 %splatinsert = insertelement <4 x i32> undef, i32 %div, i32 0
%splat = shufflevector <4 x i32> %splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer %splat = shufflevector <4 x i32> %splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
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llvm/test/Transforms/PhaseOrdering/X86/shuffle.ll

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; shuffle<8 x i16>( bitcast<8 x i16>( shuffle<4 x i32>(v))) ; shuffle<8 x i16>( bitcast<8 x i16>( shuffle<4 x i32>(v)))
; TODO: Squash shuffles and widen type? ; TODO: Squash shuffles and widen type?
define <8 x i16> @shuffle_32_bitcast_16_shuffle_16_can_be_converted_up(<4 x i32> %v1) { define <8 x i16> @shuffle_32_bitcast_16_shuffle_16_can_be_converted_up(<4 x i32> %v1) {
; CHECK-LABEL: @shuffle_32_bitcast_16_shuffle_16_can_be_converted_up( ; CHECK-LABEL: @shuffle_32_bitcast_16_shuffle_16_can_be_converted_up(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[V1:%.*]] to <8 x i16> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[V1:%.*]] to <8 x i16>
; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: ret <8 x i16> [[SHUFFLE2]] ; CHECK-NEXT: ret <8 x i16> [[SHUFFLE2]]
; ;
%shuffle1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> %shuffle1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
%bc1 = bitcast <4 x i32> %shuffle1 to <8 x i16> %bc1 = bitcast <4 x i32> %shuffle1 to <8 x i16>
%shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> %shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
ret <8 x i16> %shuffle2 ret <8 x i16> %shuffle2
} }
; shuffle<8 x i16>( bitcast<8 x i16>( shuffle<4 x i32>(v))) ; shuffle<8 x i16>( bitcast<8 x i16>( shuffle<4 x i32>(v)))
; TODO: Squash shuffles? ; TODO: Squash shuffles?
define <8 x i16> @shuffle_32_bitcast_16_shuffle_16_can_not_be_converted_up(<4 x i32> %v1) { define <8 x i16> @shuffle_32_bitcast_16_shuffle_16_can_not_be_converted_up(<4 x i32> %v1) {
; CHECK-LABEL: @shuffle_32_bitcast_16_shuffle_16_can_not_be_converted_up( ; CHECK-LABEL: @shuffle_32_bitcast_16_shuffle_16_can_not_be_converted_up(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[V1:%.*]] to <8 x i16> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[V1:%.*]] to <8 x i16>
; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> undef, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> poison, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: ret <8 x i16> [[SHUFFLE2]] ; CHECK-NEXT: ret <8 x i16> [[SHUFFLE2]]
; ;
%shuffle1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> %shuffle1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
%bc1 = bitcast <4 x i32> %shuffle1 to <8 x i16> %bc1 = bitcast <4 x i32> %shuffle1 to <8 x i16>
%shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> undef, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> %shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> undef, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
ret <8 x i16> %shuffle2 ret <8 x i16> %shuffle2
} }
; shuffle<16 x i8>( bitcast<16 x i8>( shuffle<4 x i32>(v))) ; shuffle<16 x i8>( bitcast<16 x i8>( shuffle<4 x i32>(v)))
; TODO: Squash shuffles and widen type? ; TODO: Squash shuffles and widen type?
define <16 x i8> @shuffle_32_bitcast_8_shuffle_8_can_be_converted_up(<4 x i32> %v1) { define <16 x i8> @shuffle_32_bitcast_8_shuffle_8_can_be_converted_up(<4 x i32> %v1) {
; CHECK-LABEL: @shuffle_32_bitcast_8_shuffle_8_can_be_converted_up( ; CHECK-LABEL: @shuffle_32_bitcast_8_shuffle_8_can_be_converted_up(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[V1:%.*]] to <16 x i8> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[V1:%.*]] to <16 x i8>
; CHECK-NEXT: [[BC1:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <16 x i8> [[BC1]], <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <16 x i8> [[BC1]], <16 x i8> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: ret <16 x i8> [[SHUFFLE2]] ; CHECK-NEXT: ret <16 x i8> [[SHUFFLE2]]
; ;
%shuffle1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> %shuffle1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
%bc1 = bitcast <4 x i32> %shuffle1 to <16 x i8> %bc1 = bitcast <4 x i32> %shuffle1 to <16 x i8>
%shuffle2 = shufflevector <16 x i8> %bc1, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> %shuffle2 = shufflevector <16 x i8> %bc1, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
ret <16 x i8> %shuffle2 ret <16 x i8> %shuffle2
} }
; shuffle<16 x i8>( bitcast<16 x i8>( shuffle<4 x i32>(v))) ; shuffle<16 x i8>( bitcast<16 x i8>( shuffle<4 x i32>(v)))
; TODO: Squash shuffles? ; TODO: Squash shuffles?
define <16 x i8> @shuffle_32_bitcast_8_shuffle_8_can_not_be_converted_up(<4 x i32> %v1) { define <16 x i8> @shuffle_32_bitcast_8_shuffle_8_can_not_be_converted_up(<4 x i32> %v1) {
; CHECK-LABEL: @shuffle_32_bitcast_8_shuffle_8_can_not_be_converted_up( ; CHECK-LABEL: @shuffle_32_bitcast_8_shuffle_8_can_not_be_converted_up(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[V1:%.*]] to <16 x i8> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[V1:%.*]] to <16 x i8>
; CHECK-NEXT: [[BC1:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <16 x i8> [[TMP1]], <16 x i8> poison, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <16 x i8> [[BC1]], <16 x i8> undef, <16 x i32> <i32 5, i32 4, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <16 x i8> [[BC1]], <16 x i8> poison, <16 x i32> <i32 5, i32 4, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
; CHECK-NEXT: ret <16 x i8> [[SHUFFLE2]] ; CHECK-NEXT: ret <16 x i8> [[SHUFFLE2]]
; ;
%shuffle1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> %shuffle1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
%bc1 = bitcast <4 x i32> %shuffle1 to <16 x i8> %bc1 = bitcast <4 x i32> %shuffle1 to <16 x i8>
%shuffle2 = shufflevector <16 x i8> %bc1, <16 x i8> undef, <16 x i32> <i32 5, i32 4, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> %shuffle2 = shufflevector <16 x i8> %bc1, <16 x i8> undef, <16 x i32> <i32 5, i32 4, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %shuffle2 ret <16 x i8> %shuffle2
} }
; shuffle<4 x i32>( bitcast<4 x i32>( shuffle<16 x i8>(v))) ; shuffle<4 x i32>( bitcast<4 x i32>( shuffle<16 x i8>(v)))
; TODO: squash shuffles? ; TODO: squash shuffles?
define <4 x i32> @shuffle_8_bitcast_32_shuffle_32_can_be_converted_up(<16 x i8> %v1) { define <4 x i32> @shuffle_8_bitcast_32_shuffle_32_can_be_converted_up(<16 x i8> %v1) {
; CHECK-LABEL: @shuffle_8_bitcast_32_shuffle_32_can_be_converted_up( ; CHECK-LABEL: @shuffle_8_bitcast_32_shuffle_32_can_be_converted_up(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[V1:%.*]] to <4 x i32> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[V1:%.*]] to <4 x i32>
; CHECK-NEXT: [[BC1:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 1, i32 0> ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
; CHECK-NEXT: ret <4 x i32> [[SHUFFLE2]] ; CHECK-NEXT: ret <4 x i32> [[SHUFFLE2]]
; ;
%shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> %shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
%bc1 = bitcast <16 x i8> %shuffle1 to <4 x i32> %bc1 = bitcast <16 x i8> %shuffle1 to <4 x i32>
%shuffle2 = shufflevector <4 x i32> %bc1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> %shuffle2 = shufflevector <4 x i32> %bc1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
ret <4 x i32> %shuffle2 ret <4 x i32> %shuffle2
} }
; shuffle<4 x i32>( bitcast<4 x i32>( shuffle<8 x i16>(v))) ; shuffle<4 x i32>( bitcast<4 x i32>( shuffle<8 x i16>(v)))
; TODO: squash shuffles? ; TODO: squash shuffles?
define <4 x i32> @shuffle_16_bitcast_32_shuffle_32_can_be_converted_up(<8 x i16> %v1) { define <4 x i32> @shuffle_16_bitcast_32_shuffle_32_can_be_converted_up(<8 x i16> %v1) {
; CHECK-LABEL: @shuffle_16_bitcast_32_shuffle_32_can_be_converted_up( ; CHECK-LABEL: @shuffle_16_bitcast_32_shuffle_32_can_be_converted_up(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[V1:%.*]] to <4 x i32> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[V1:%.*]] to <4 x i32>
; CHECK-NEXT: [[BC1:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 1, i32 0> ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
; CHECK-NEXT: ret <4 x i32> [[SHUFFLE2]] ; CHECK-NEXT: ret <4 x i32> [[SHUFFLE2]]
; ;
%shuffle1 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> %shuffle1 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
%bc1 = bitcast <8 x i16> %shuffle1 to <4 x i32> %bc1 = bitcast <8 x i16> %shuffle1 to <4 x i32>
%shuffle2 = shufflevector <4 x i32> %bc1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> %shuffle2 = shufflevector <4 x i32> %bc1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
ret <4 x i32> %shuffle2 ret <4 x i32> %shuffle2
} }
; shuffle<4 x i32>( bitcast<4 x i32>( shuffle<16 x i8>(v))) ; shuffle<4 x i32>( bitcast<4 x i32>( shuffle<16 x i8>(v)))
; TODO: Narrow and squash shuffles? ; TODO: Narrow and squash shuffles?
define <4 x i32> @shuffle_8_bitcast_32_shuffle_32_can_not_be_converted_up(<16 x i8> %v1) { define <4 x i32> @shuffle_8_bitcast_32_shuffle_32_can_not_be_converted_up(<16 x i8> %v1) {
; CHECK-LABEL: @shuffle_8_bitcast_32_shuffle_32_can_not_be_converted_up( ; CHECK-LABEL: @shuffle_8_bitcast_32_shuffle_32_can_not_be_converted_up(
; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <16 x i8> [[V1:%.*]], <16 x i8> undef, <16 x i32> <i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <16 x i8> [[V1:%.*]], <16 x i8> poison, <16 x i32> <i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[BC1:%.*]] = bitcast <16 x i8> [[SHUFFLE1]] to <4 x i32> ; CHECK-NEXT: [[BC1:%.*]] = bitcast <16 x i8> [[SHUFFLE1]] to <4 x i32>
; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
; CHECK-NEXT: ret <4 x i32> [[SHUFFLE2]] ; CHECK-NEXT: ret <4 x i32> [[SHUFFLE2]]
; ;
%shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> %shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
%bc1 = bitcast <16 x i8> %shuffle1 to <4 x i32> %bc1 = bitcast <16 x i8> %shuffle1 to <4 x i32>
%shuffle2 = shufflevector <4 x i32> %bc1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> %shuffle2 = shufflevector <4 x i32> %bc1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
ret <4 x i32> %shuffle2 ret <4 x i32> %shuffle2
} }
; shuffle<4 x i32>( bitcast<4 x i32>( shuffle<8 x i16>(v))) ; shuffle<4 x i32>( bitcast<4 x i32>( shuffle<8 x i16>(v)))
; TODO: Narrow and squash shuffles? ; TODO: Narrow and squash shuffles?
define <4 x i32> @shuffle_16_bitcast_32_shuffle_32_can_not_be_converted_up(<8 x i16> %v1) { define <4 x i32> @shuffle_16_bitcast_32_shuffle_32_can_not_be_converted_up(<8 x i16> %v1) {
; CHECK-LABEL: @shuffle_16_bitcast_32_shuffle_32_can_not_be_converted_up( ; CHECK-LABEL: @shuffle_16_bitcast_32_shuffle_32_can_not_be_converted_up(
; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <8 x i16> [[V1:%.*]], <8 x i16> undef, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> ; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <8 x i16> [[V1:%.*]], <8 x i16> poison, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: [[BC1:%.*]] = bitcast <8 x i16> [[SHUFFLE1]] to <4 x i32> ; CHECK-NEXT: [[BC1:%.*]] = bitcast <8 x i16> [[SHUFFLE1]] to <4 x i32>
; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i32> [[BC1]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
; CHECK-NEXT: ret <4 x i32> [[SHUFFLE2]] ; CHECK-NEXT: ret <4 x i32> [[SHUFFLE2]]
; ;
%shuffle1 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> %shuffle1 = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
%bc1 = bitcast <8 x i16> %shuffle1 to <4 x i32> %bc1 = bitcast <8 x i16> %shuffle1 to <4 x i32>
%shuffle2 = shufflevector <4 x i32> %bc1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0> %shuffle2 = shufflevector <4 x i32> %bc1, <4 x i32> undef, <4 x i32> <i32 2, i32 3, i32 1, i32 0>
ret <4 x i32> %shuffle2 ret <4 x i32> %shuffle2
} }
; shuffle<8 x i16>( bitcast<8 x i16>( shuffle<16 x i8>(v))) ; shuffle<8 x i16>( bitcast<8 x i16>( shuffle<16 x i8>(v)))
; TODO: squash shuffles and widen type? ; TODO: squash shuffles and widen type?
define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_can__be_converted_up(<16 x i8> %v1) { define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_can__be_converted_up(<16 x i8> %v1) {
; CHECK-LABEL: @shuffle_8_bitcast_16_shuffle_16_can__be_converted_up( ; CHECK-LABEL: @shuffle_8_bitcast_16_shuffle_16_can__be_converted_up(
; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[V1:%.*]] to <8 x i16> ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i8> [[V1:%.*]] to <8 x i16>
; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> ; CHECK-NEXT: [[BC1:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> poison, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: ret <8 x i16> [[SHUFFLE2]] ; CHECK-NEXT: ret <8 x i16> [[SHUFFLE2]]
; ;
%shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> %shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
%bc1 = bitcast <16 x i8> %shuffle1 to <8 x i16> %bc1 = bitcast <16 x i8> %shuffle1 to <8 x i16>
%shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> %shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
ret <8 x i16> %shuffle2 ret <8 x i16> %shuffle2
} }
; shuffle<8 x i16>( bitcast<8 x i16>( shuffle<16 x i8>(v))) ; shuffle<8 x i16>( bitcast<8 x i16>( shuffle<16 x i8>(v)))
; TODO: Narrow and squash shuffles? ; TODO: Narrow and squash shuffles?
define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_can_not_be_converted_up(<16 x i8> %v1) { define <8 x i16> @shuffle_8_bitcast_16_shuffle_16_can_not_be_converted_up(<16 x i8> %v1) {
; CHECK-LABEL: @shuffle_8_bitcast_16_shuffle_16_can_not_be_converted_up( ; CHECK-LABEL: @shuffle_8_bitcast_16_shuffle_16_can_not_be_converted_up(
; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <16 x i8> [[V1:%.*]], <16 x i8> undef, <16 x i32> <i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> ; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <16 x i8> [[V1:%.*]], <16 x i8> poison, <16 x i32> <i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[BC1:%.*]] = bitcast <16 x i8> [[SHUFFLE1]] to <8 x i16> ; CHECK-NEXT: [[BC1:%.*]] = bitcast <16 x i8> [[SHUFFLE1]] to <8 x i16>
; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> undef, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> ; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <8 x i16> [[BC1]], <8 x i16> poison, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
; CHECK-NEXT: ret <8 x i16> [[SHUFFLE2]] ; CHECK-NEXT: ret <8 x i16> [[SHUFFLE2]]
; ;
%shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3> %shuffle1 = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 9, i32 8, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3>
%bc1 = bitcast <16 x i8> %shuffle1 to <8 x i16> %bc1 = bitcast <16 x i8> %shuffle1 to <8 x i16>
%shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> undef, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1> %shuffle2 = shufflevector <8 x i16> %bc1, <8 x i16> undef, <8 x i32> <i32 5, i32 4, i32 6, i32 7, i32 2, i32 3, i32 0, i32 1>
ret <8 x i16> %shuffle2 ret <8 x i16> %shuffle2
} }

llvm/test/Transforms/SLPVectorizer/AMDGPU/add_sub_sat.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer,instcombine %s | FileCheck -check-prefixes=GCN,GFX7 %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -passes=slp-vectorizer,instcombine %s | FileCheck -check-prefixes=GCN,GFX7 %s
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer,instcombine %s | FileCheck -check-prefixes=GCN,GFX8 %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -passes=slp-vectorizer,instcombine %s | FileCheck -check-prefixes=GCN,GFX8 %s
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer,instcombine %s | FileCheck -check-prefixes=GCN,GFX8 %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -passes=slp-vectorizer,instcombine %s | FileCheck -check-prefixes=GCN,GFX8 %s
define <2 x i16> @uadd_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) { define <2 x i16> @uadd_sat_v2i16(<2 x i16> %arg0, <2 x i16> %arg1) {
; GFX7-LABEL: @uadd_sat_v2i16( ; GFX7-LABEL: @uadd_sat_v2i16(
; GFX7-NEXT: bb: ; GFX7-NEXT: bb:
; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0 ; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1 ; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0 ; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1 ; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) ; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) ; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> undef, i16 [[ADD_0]], i64 0 ; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 ; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
; GFX7-NEXT: ret <2 x i16> [[INS_1]] ; GFX7-NEXT: ret <2 x i16> [[INS_1]]
; ;
; GFX8-LABEL: @uadd_sat_v2i16( ; GFX8-LABEL: @uadd_sat_v2i16(
; GFX8-NEXT: bb: ; GFX8-NEXT: bb:
; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]]) ; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
; GFX8-NEXT: ret <2 x i16> [[TMP0]] ; GFX8-NEXT: ret <2 x i16> [[TMP0]]
; ;
Show All 13 Lines
; GFX7-LABEL: @usub_sat_v2i16( ; GFX7-LABEL: @usub_sat_v2i16(
; GFX7-NEXT: bb: ; GFX7-NEXT: bb:
; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0 ; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1 ; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0 ; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1 ; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.usub.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) ; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.usub.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.usub.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) ; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.usub.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> undef, i16 [[ADD_0]], i64 0 ; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 ; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
; GFX7-NEXT: ret <2 x i16> [[INS_1]] ; GFX7-NEXT: ret <2 x i16> [[INS_1]]
; ;
; GFX8-LABEL: @usub_sat_v2i16( ; GFX8-LABEL: @usub_sat_v2i16(
; GFX8-NEXT: bb: ; GFX8-NEXT: bb:
; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]]) ; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
; GFX8-NEXT: ret <2 x i16> [[TMP0]] ; GFX8-NEXT: ret <2 x i16> [[TMP0]]
; ;
Show All 13 Lines
; GFX7-LABEL: @sadd_sat_v2i16( ; GFX7-LABEL: @sadd_sat_v2i16(
; GFX7-NEXT: bb: ; GFX7-NEXT: bb:
; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0 ; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1 ; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0 ; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1 ; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) ; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) ; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.sadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> undef, i16 [[ADD_0]], i64 0 ; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 ; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
; GFX7-NEXT: ret <2 x i16> [[INS_1]] ; GFX7-NEXT: ret <2 x i16> [[INS_1]]
; ;
; GFX8-LABEL: @sadd_sat_v2i16( ; GFX8-LABEL: @sadd_sat_v2i16(
; GFX8-NEXT: bb: ; GFX8-NEXT: bb:
; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]]) ; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
; GFX8-NEXT: ret <2 x i16> [[TMP0]] ; GFX8-NEXT: ret <2 x i16> [[TMP0]]
; ;
Show All 13 Lines
; GFX7-LABEL: @ssub_sat_v2i16( ; GFX7-LABEL: @ssub_sat_v2i16(
; GFX7-NEXT: bb: ; GFX7-NEXT: bb:
; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0 ; GFX7-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i16> [[ARG0:%.*]], i64 0
; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1 ; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i16> [[ARG0]], i64 1
; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0 ; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i16> [[ARG1:%.*]], i64 0
; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1 ; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i16> [[ARG1]], i64 1
; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) ; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) ; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.ssub.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> undef, i16 [[ADD_0]], i64 0 ; GFX7-NEXT: [[INS_0:%.*]] = insertelement <2 x i16> poison, i16 [[ADD_0]], i64 0
; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 ; GFX7-NEXT: [[INS_1:%.*]] = insertelement <2 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
; GFX7-NEXT: ret <2 x i16> [[INS_1]] ; GFX7-NEXT: ret <2 x i16> [[INS_1]]
; ;
; GFX8-LABEL: @ssub_sat_v2i16( ; GFX8-LABEL: @ssub_sat_v2i16(
; GFX8-NEXT: bb: ; GFX8-NEXT: bb:
; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]]) ; GFX8-NEXT: [[TMP0:%.*]] = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> [[ARG0:%.*]], <2 x i16> [[ARG1:%.*]])
; GFX8-NEXT: ret <2 x i16> [[TMP0]] ; GFX8-NEXT: ret <2 x i16> [[TMP0]]
; ;
Show All 13 Lines
; GCN-LABEL: @uadd_sat_v2i32( ; GCN-LABEL: @uadd_sat_v2i32(
; GCN-NEXT: bb: ; GCN-NEXT: bb:
; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0 ; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1 ; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0 ; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1 ; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]]) ; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]]) ; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> undef, i32 [[ADD_0]], i64 0 ; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1 ; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
; GCN-NEXT: ret <2 x i32> [[INS_1]] ; GCN-NEXT: ret <2 x i32> [[INS_1]]
; ;
bb: bb:
%arg0.0 = extractelement <2 x i32> %arg0, i64 0 %arg0.0 = extractelement <2 x i32> %arg0, i64 0
%arg0.1 = extractelement <2 x i32> %arg0, i64 1 %arg0.1 = extractelement <2 x i32> %arg0, i64 1
%arg1.0 = extractelement <2 x i32> %arg1, i64 0 %arg1.0 = extractelement <2 x i32> %arg1, i64 0
%arg1.1 = extractelement <2 x i32> %arg1, i64 1 %arg1.1 = extractelement <2 x i32> %arg1, i64 1
%add.0 = call i32 @llvm.uadd.sat.i32(i32 %arg0.0, i32 %arg1.0) %add.0 = call i32 @llvm.uadd.sat.i32(i32 %arg0.0, i32 %arg1.0)
%add.1 = call i32 @llvm.uadd.sat.i32(i32 %arg0.1, i32 %arg1.1) %add.1 = call i32 @llvm.uadd.sat.i32(i32 %arg0.1, i32 %arg1.1)
%ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0 %ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1 %ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1
ret <2 x i32> %ins.1 ret <2 x i32> %ins.1
} }
define <2 x i32> @usub_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) { define <2 x i32> @usub_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) {
; GCN-LABEL: @usub_sat_v2i32( ; GCN-LABEL: @usub_sat_v2i32(
; GCN-NEXT: bb: ; GCN-NEXT: bb:
; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0 ; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1 ; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0 ; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1 ; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]]) ; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]]) ; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.usub.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> undef, i32 [[ADD_0]], i64 0 ; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1 ; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
; GCN-NEXT: ret <2 x i32> [[INS_1]] ; GCN-NEXT: ret <2 x i32> [[INS_1]]
; ;
bb: bb:
%arg0.0 = extractelement <2 x i32> %arg0, i64 0 %arg0.0 = extractelement <2 x i32> %arg0, i64 0
%arg0.1 = extractelement <2 x i32> %arg0, i64 1 %arg0.1 = extractelement <2 x i32> %arg0, i64 1
%arg1.0 = extractelement <2 x i32> %arg1, i64 0 %arg1.0 = extractelement <2 x i32> %arg1, i64 0
%arg1.1 = extractelement <2 x i32> %arg1, i64 1 %arg1.1 = extractelement <2 x i32> %arg1, i64 1
%add.0 = call i32 @llvm.usub.sat.i32(i32 %arg0.0, i32 %arg1.0) %add.0 = call i32 @llvm.usub.sat.i32(i32 %arg0.0, i32 %arg1.0)
%add.1 = call i32 @llvm.usub.sat.i32(i32 %arg0.1, i32 %arg1.1) %add.1 = call i32 @llvm.usub.sat.i32(i32 %arg0.1, i32 %arg1.1)
%ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0 %ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1 %ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1
ret <2 x i32> %ins.1 ret <2 x i32> %ins.1
} }
define <2 x i32> @sadd_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) { define <2 x i32> @sadd_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) {
; GCN-LABEL: @sadd_sat_v2i32( ; GCN-LABEL: @sadd_sat_v2i32(
; GCN-NEXT: bb: ; GCN-NEXT: bb:
; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0 ; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1 ; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0 ; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1 ; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]]) ; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]]) ; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.sadd.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> undef, i32 [[ADD_0]], i64 0 ; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1 ; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
; GCN-NEXT: ret <2 x i32> [[INS_1]] ; GCN-NEXT: ret <2 x i32> [[INS_1]]
; ;
bb: bb:
%arg0.0 = extractelement <2 x i32> %arg0, i64 0 %arg0.0 = extractelement <2 x i32> %arg0, i64 0
%arg0.1 = extractelement <2 x i32> %arg0, i64 1 %arg0.1 = extractelement <2 x i32> %arg0, i64 1
%arg1.0 = extractelement <2 x i32> %arg1, i64 0 %arg1.0 = extractelement <2 x i32> %arg1, i64 0
%arg1.1 = extractelement <2 x i32> %arg1, i64 1 %arg1.1 = extractelement <2 x i32> %arg1, i64 1
%add.0 = call i32 @llvm.sadd.sat.i32(i32 %arg0.0, i32 %arg1.0) %add.0 = call i32 @llvm.sadd.sat.i32(i32 %arg0.0, i32 %arg1.0)
%add.1 = call i32 @llvm.sadd.sat.i32(i32 %arg0.1, i32 %arg1.1) %add.1 = call i32 @llvm.sadd.sat.i32(i32 %arg0.1, i32 %arg1.1)
%ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0 %ins.0 = insertelement <2 x i32> undef, i32 %add.0, i64 0
%ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1 %ins.1 = insertelement <2 x i32> %ins.0, i32 %add.1, i64 1
ret <2 x i32> %ins.1 ret <2 x i32> %ins.1
} }
define <2 x i32> @ssub_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) { define <2 x i32> @ssub_sat_v2i32(<2 x i32> %arg0, <2 x i32> %arg1) {
; GCN-LABEL: @ssub_sat_v2i32( ; GCN-LABEL: @ssub_sat_v2i32(
; GCN-NEXT: bb: ; GCN-NEXT: bb:
; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0 ; GCN-NEXT: [[ARG0_0:%.*]] = extractelement <2 x i32> [[ARG0:%.*]], i64 0
; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1 ; GCN-NEXT: [[ARG0_1:%.*]] = extractelement <2 x i32> [[ARG0]], i64 1
; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0 ; GCN-NEXT: [[ARG1_0:%.*]] = extractelement <2 x i32> [[ARG1:%.*]], i64 0
; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1 ; GCN-NEXT: [[ARG1_1:%.*]] = extractelement <2 x i32> [[ARG1]], i64 1
; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.ssub.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]]) ; GCN-NEXT: [[ADD_0:%.*]] = call i32 @llvm.ssub.sat.i32(i32 [[ARG0_0]], i32 [[ARG1_0]])
; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.ssub.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]]) ; GCN-NEXT: [[ADD_1:%.*]] = call i32 @llvm.ssub.sat.i32(i32 [[ARG0_1]], i32 [[ARG1_1]])
; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> undef, i32 [[ADD_0]], i64 0 ; GCN-NEXT: [[INS_0:%.*]] = insertelement <2 x i32> poison, i32 [[ADD_0]], i64 0
; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1 ; GCN-NEXT: [[INS_1:%.*]] = insertelement <2 x i32> [[INS_0]], i32 [[ADD_1]], i64 1
; GCN-NEXT: ret <2 x i32> [[INS_1]] ; GCN-NEXT: ret <2 x i32> [[INS_1]]
; ;
bb: bb:
%arg0.0 = extractelement <2 x i32> %arg0, i64 0 %arg0.0 = extractelement <2 x i32> %arg0, i64 0
%arg0.1 = extractelement <2 x i32> %arg0, i64 1 %arg0.1 = extractelement <2 x i32> %arg0, i64 1
%arg1.0 = extractelement <2 x i32> %arg1, i64 0 %arg1.0 = extractelement <2 x i32> %arg1, i64 0
%arg1.1 = extractelement <2 x i32> %arg1, i64 1 %arg1.1 = extractelement <2 x i32> %arg1, i64 1
Show All 11 Lines
; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <3 x i16> [[ARG0]], i64 1 ; GFX7-NEXT: [[ARG0_1:%.*]] = extractelement <3 x i16> [[ARG0]], i64 1
; GFX7-NEXT: [[ARG0_2:%.*]] = extractelement <3 x i16> [[ARG0]], i64 2 ; GFX7-NEXT: [[ARG0_2:%.*]] = extractelement <3 x i16> [[ARG0]], i64 2
; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <3 x i16> [[ARG1:%.*]], i64 0 ; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <3 x i16> [[ARG1:%.*]], i64 0
; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <3 x i16> [[ARG1]], i64 1 ; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <3 x i16> [[ARG1]], i64 1
; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <3 x i16> [[ARG1]], i64 2 ; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <3 x i16> [[ARG1]], i64 2
; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) ; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) ; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
; GFX7-NEXT: [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]]) ; GFX7-NEXT: [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
; GFX7-NEXT: [[INS_0:%.*]] = insertelement <3 x i16> undef, i16 [[ADD_0]], i64 0 ; GFX7-NEXT: [[INS_0:%.*]] = insertelement <3 x i16> poison, i16 [[ADD_0]], i64 0
; GFX7-NEXT: [[INS_1:%.*]] = insertelement <3 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 ; GFX7-NEXT: [[INS_1:%.*]] = insertelement <3 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
; GFX7-NEXT: [[INS_2:%.*]] = insertelement <3 x i16> [[INS_1]], i16 [[ADD_2]], i64 2 ; GFX7-NEXT: [[INS_2:%.*]] = insertelement <3 x i16> [[INS_1]], i16 [[ADD_2]], i64 2
; GFX7-NEXT: ret <3 x i16> [[INS_2]] ; GFX7-NEXT: ret <3 x i16> [[INS_2]]
; ;
; GFX8-LABEL: @uadd_sat_v3i16( ; GFX8-LABEL: @uadd_sat_v3i16(
; GFX8-NEXT: bb: ; GFX8-NEXT: bb:
; GFX8-NEXT: [[ARG0_2:%.*]] = extractelement <3 x i16> [[ARG0:%.*]], i64 2 ; GFX8-NEXT: [[ARG0_2:%.*]] = extractelement <3 x i16> [[ARG0:%.*]], i64 2
; GFX8-NEXT: [[ARG1_2:%.*]] = extractelement <3 x i16> [[ARG1:%.*]], i64 2 ; GFX8-NEXT: [[ARG1_2:%.*]] = extractelement <3 x i16> [[ARG1:%.*]], i64 2
Show All 31 Lines
; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <4 x i16> [[ARG1:%.*]], i64 0 ; GFX7-NEXT: [[ARG1_0:%.*]] = extractelement <4 x i16> [[ARG1:%.*]], i64 0
; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <4 x i16> [[ARG1]], i64 1 ; GFX7-NEXT: [[ARG1_1:%.*]] = extractelement <4 x i16> [[ARG1]], i64 1
; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <4 x i16> [[ARG1]], i64 2 ; GFX7-NEXT: [[ARG1_2:%.*]] = extractelement <4 x i16> [[ARG1]], i64 2
; GFX7-NEXT: [[ARG1_3:%.*]] = extractelement <4 x i16> [[ARG1]], i64 3 ; GFX7-NEXT: [[ARG1_3:%.*]] = extractelement <4 x i16> [[ARG1]], i64 3
; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]]) ; GFX7-NEXT: [[ADD_0:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_0]], i16 [[ARG1_0]])
; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]]) ; GFX7-NEXT: [[ADD_1:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_1]], i16 [[ARG1_1]])
; GFX7-NEXT: [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]]) ; GFX7-NEXT: [[ADD_2:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_2]], i16 [[ARG1_2]])
; GFX7-NEXT: [[ADD_3:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_3]], i16 [[ARG1_3]]) ; GFX7-NEXT: [[ADD_3:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG0_3]], i16 [[ARG1_3]])
; GFX7-NEXT: [[INS_0:%.*]] = insertelement <4 x i16> undef, i16 [[ADD_0]], i64 0 ; GFX7-NEXT: [[INS_0:%.*]] = insertelement <4 x i16> poison, i16 [[ADD_0]], i64 0
; GFX7-NEXT: [[INS_1:%.*]] = insertelement <4 x i16> [[INS_0]], i16 [[ADD_1]], i64 1 ; GFX7-NEXT: [[INS_1:%.*]] = insertelement <4 x i16> [[INS_0]], i16 [[ADD_1]], i64 1
; GFX7-NEXT: [[INS_2:%.*]] = insertelement <4 x i16> [[INS_1]], i16 [[ADD_2]], i64 2 ; GFX7-NEXT: [[INS_2:%.*]] = insertelement <4 x i16> [[INS_1]], i16 [[ADD_2]], i64 2
; GFX7-NEXT: [[INS_3:%.*]] = insertelement <4 x i16> [[INS_2]], i16 [[ADD_3]], i64 3 ; GFX7-NEXT: [[INS_3:%.*]] = insertelement <4 x i16> [[INS_2]], i16 [[ADD_3]], i64 3
; GFX7-NEXT: ret <4 x i16> [[INS_3]] ; GFX7-NEXT: ret <4 x i16> [[INS_3]]
; ;
; GFX8-LABEL: @uadd_sat_v4i16( ; GFX8-LABEL: @uadd_sat_v4i16(
; GFX8-NEXT: bb: ; GFX8-NEXT: bb:
; GFX8-NEXT: [[TMP0:%.*]] = shufflevector <4 x i16> [[ARG0:%.*]], <4 x i16> poison, <2 x i32> <i32 0, i32 1> ; GFX8-NEXT: [[TMP0:%.*]] = shufflevector <4 x i16> [[ARG0:%.*]], <4 x i16> poison, <2 x i32> <i32 0, i32 1>
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llvm/test/Transforms/SLPVectorizer/X86/alternate-calls.ll

Show All 12 Lines
; SSE-NEXT: [[AB0:%.*]] = call float @llvm.ceil.f32(float [[A0]]) ; SSE-NEXT: [[AB0:%.*]] = call float @llvm.ceil.f32(float [[A0]])
; SSE-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 1, i32 2> ; SSE-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 1, i32 2>
; SSE-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP1]]) ; SSE-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP1]])
; SSE-NEXT: [[AB3:%.*]] = call float @llvm.ceil.f32(float [[A3]]) ; SSE-NEXT: [[AB3:%.*]] = call float @llvm.ceil.f32(float [[A3]])
; SSE-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 4, i32 5> ; SSE-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 4, i32 5>
; SSE-NEXT: [[TMP4:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> [[TMP3]]) ; SSE-NEXT: [[TMP4:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> [[TMP3]])
; SSE-NEXT: [[TMP5:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 6, i32 7> ; SSE-NEXT: [[TMP5:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 6, i32 7>
; SSE-NEXT: [[TMP6:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP5]]) ; SSE-NEXT: [[TMP6:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP5]])
; SSE-NEXT: [[R0:%.*]] = insertelement <8 x float> undef, float [[AB0]], i64 0 ; SSE-NEXT: [[R0:%.*]] = insertelement <8 x float> poison, float [[AB0]], i64 0
; SSE-NEXT: [[TMP7:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; SSE-NEXT: [[TMP7:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; SSE-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32 0, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; SSE-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32 0, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; SSE-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3 ; SSE-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3
; SSE-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; SSE-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; SSE-NEXT: [[R52:%.*]] = shufflevector <8 x float> [[R3]], <8 x float> [[TMP8]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 poison, i32 poison> ; SSE-NEXT: [[R52:%.*]] = shufflevector <8 x float> [[R3]], <8 x float> [[TMP8]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 poison, i32 poison>
; SSE-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; SSE-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; SSE-NEXT: [[R71:%.*]] = shufflevector <8 x float> [[R52]], <8 x float> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9> ; SSE-NEXT: [[R71:%.*]] = shufflevector <8 x float> [[R52]], <8 x float> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; SSE-NEXT: ret <8 x float> [[R71]] ; SSE-NEXT: ret <8 x float> [[R71]]
; ;
; SLM-LABEL: @ceil_floor( ; SLM-LABEL: @ceil_floor(
; SLM-NEXT: [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i64 0 ; SLM-NEXT: [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i64 0
; SLM-NEXT: [[A3:%.*]] = extractelement <8 x float> [[A]], i64 3 ; SLM-NEXT: [[A3:%.*]] = extractelement <8 x float> [[A]], i64 3
; SLM-NEXT: [[AB0:%.*]] = call float @llvm.ceil.f32(float [[A0]]) ; SLM-NEXT: [[AB0:%.*]] = call float @llvm.ceil.f32(float [[A0]])
; SLM-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 1, i32 2> ; SLM-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 1, i32 2>
; SLM-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP1]]) ; SLM-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP1]])
; SLM-NEXT: [[AB3:%.*]] = call float @llvm.ceil.f32(float [[A3]]) ; SLM-NEXT: [[AB3:%.*]] = call float @llvm.ceil.f32(float [[A3]])
; SLM-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 4, i32 5> ; SLM-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 4, i32 5>
; SLM-NEXT: [[TMP4:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> [[TMP3]]) ; SLM-NEXT: [[TMP4:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> [[TMP3]])
; SLM-NEXT: [[TMP5:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 6, i32 7> ; SLM-NEXT: [[TMP5:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 6, i32 7>
; SLM-NEXT: [[TMP6:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP5]]) ; SLM-NEXT: [[TMP6:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP5]])
; SLM-NEXT: [[R0:%.*]] = insertelement <8 x float> undef, float [[AB0]], i64 0 ; SLM-NEXT: [[R0:%.*]] = insertelement <8 x float> poison, float [[AB0]], i64 0
; SLM-NEXT: [[TMP7:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; SLM-NEXT: [[TMP7:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; SLM-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32 0, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; SLM-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32 0, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; SLM-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3 ; SLM-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3
; SLM-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; SLM-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; SLM-NEXT: [[R52:%.*]] = shufflevector <8 x float> [[R3]], <8 x float> [[TMP8]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 poison, i32 poison> ; SLM-NEXT: [[R52:%.*]] = shufflevector <8 x float> [[R3]], <8 x float> [[TMP8]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 poison, i32 poison>
; SLM-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; SLM-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; SLM-NEXT: [[R71:%.*]] = shufflevector <8 x float> [[R52]], <8 x float> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9> ; SLM-NEXT: [[R71:%.*]] = shufflevector <8 x float> [[R52]], <8 x float> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; SLM-NEXT: ret <8 x float> [[R71]] ; SLM-NEXT: ret <8 x float> [[R71]]
; ;
; AVX-LABEL: @ceil_floor( ; AVX-LABEL: @ceil_floor(
; AVX-NEXT: [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i64 0 ; AVX-NEXT: [[A0:%.*]] = extractelement <8 x float> [[A:%.*]], i64 0
; AVX-NEXT: [[A3:%.*]] = extractelement <8 x float> [[A]], i64 3 ; AVX-NEXT: [[A3:%.*]] = extractelement <8 x float> [[A]], i64 3
; AVX-NEXT: [[AB0:%.*]] = call float @llvm.ceil.f32(float [[A0]]) ; AVX-NEXT: [[AB0:%.*]] = call float @llvm.ceil.f32(float [[A0]])
; AVX-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 1, i32 2> ; AVX-NEXT: [[TMP1:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 1, i32 2>
; AVX-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP1]]) ; AVX-NEXT: [[TMP2:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP1]])
; AVX-NEXT: [[AB3:%.*]] = call float @llvm.ceil.f32(float [[A3]]) ; AVX-NEXT: [[AB3:%.*]] = call float @llvm.ceil.f32(float [[A3]])
; AVX-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 4, i32 5> ; AVX-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 4, i32 5>
; AVX-NEXT: [[TMP4:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> [[TMP3]]) ; AVX-NEXT: [[TMP4:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> [[TMP3]])
; AVX-NEXT: [[TMP5:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 6, i32 7> ; AVX-NEXT: [[TMP5:%.*]] = shufflevector <8 x float> [[A]], <8 x float> poison, <2 x i32> <i32 6, i32 7>
; AVX-NEXT: [[TMP6:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP5]]) ; AVX-NEXT: [[TMP6:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[TMP5]])
; AVX-NEXT: [[R0:%.*]] = insertelement <8 x float> undef, float [[AB0]], i64 0 ; AVX-NEXT: [[R0:%.*]] = insertelement <8 x float> poison, float [[AB0]], i64 0
; AVX-NEXT: [[TMP7:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; AVX-NEXT: [[TMP7:%.*]] = shufflevector <2 x float> [[TMP2]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32 0, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; AVX-NEXT: [[R23:%.*]] = shufflevector <8 x float> [[R0]], <8 x float> [[TMP7]], <8 x i32> <i32 0, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3 ; AVX-NEXT: [[R3:%.*]] = insertelement <8 x float> [[R23]], float [[AB3]], i64 3
; AVX-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; AVX-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[R52:%.*]] = shufflevector <8 x float> [[R3]], <8 x float> [[TMP8]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 poison, i32 poison> ; AVX-NEXT: [[R52:%.*]] = shufflevector <8 x float> [[R3]], <8 x float> [[TMP8]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 poison, i32 poison>
; AVX-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; AVX-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX-NEXT: [[R71:%.*]] = shufflevector <8 x float> [[R52]], <8 x float> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9> ; AVX-NEXT: [[R71:%.*]] = shufflevector <8 x float> [[R52]], <8 x float> [[TMP9]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; AVX-NEXT: ret <8 x float> [[R71]] ; AVX-NEXT: ret <8 x float> [[R71]]
Show All 30 Lines

llvm/test/Transforms/SLPVectorizer/X86/alternate-int.ll

Show First 20 Lines • Show All 383 Lines • ▼ Show 20 Lines
; SSE-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i64 6 ; SSE-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i64 6
; SSE-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i64 7 ; SSE-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i64 7
; SSE-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4 ; SSE-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4
; SSE-NEXT: [[AB2:%.*]] = sdiv i32 [[A2]], 8 ; SSE-NEXT: [[AB2:%.*]] = sdiv i32 [[A2]], 8
; SSE-NEXT: [[AB3:%.*]] = sdiv i32 [[A3]], 16 ; SSE-NEXT: [[AB3:%.*]] = sdiv i32 [[A3]], 16
; SSE-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4 ; SSE-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; SSE-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8 ; SSE-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8
; SSE-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16 ; SSE-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16
; SSE-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, i32 [[AB1]], i64 1 ; SSE-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i64 1
; SSE-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i64 2 ; SSE-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i64 2
; SSE-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i64 3 ; SSE-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i64 3
; SSE-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB5]], i64 5 ; SSE-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB5]], i64 5
; SSE-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i64 6 ; SSE-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i64 6
; SSE-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i64 7 ; SSE-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i64 7
; SSE-NEXT: ret <8 x i32> [[R7]] ; SSE-NEXT: ret <8 x i32> [[R7]]
; ;
; SLM-LABEL: @sdiv_v8i32_undefs( ; SLM-LABEL: @sdiv_v8i32_undefs(
; SLM-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A:%.*]], i64 1 ; SLM-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A:%.*]], i64 1
; SLM-NEXT: [[A2:%.*]] = extractelement <8 x i32> [[A]], i64 2 ; SLM-NEXT: [[A2:%.*]] = extractelement <8 x i32> [[A]], i64 2
; SLM-NEXT: [[A3:%.*]] = extractelement <8 x i32> [[A]], i64 3 ; SLM-NEXT: [[A3:%.*]] = extractelement <8 x i32> [[A]], i64 3
; SLM-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i64 5 ; SLM-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i64 5
; SLM-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i64 6 ; SLM-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i64 6
; SLM-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i64 7 ; SLM-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i64 7
; SLM-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4 ; SLM-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4
; SLM-NEXT: [[AB2:%.*]] = sdiv i32 [[A2]], 8 ; SLM-NEXT: [[AB2:%.*]] = sdiv i32 [[A2]], 8
; SLM-NEXT: [[AB3:%.*]] = sdiv i32 [[A3]], 16 ; SLM-NEXT: [[AB3:%.*]] = sdiv i32 [[A3]], 16
; SLM-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4 ; SLM-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; SLM-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8 ; SLM-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8
; SLM-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16 ; SLM-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16
; SLM-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, i32 [[AB1]], i64 1 ; SLM-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i64 1
; SLM-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i64 2 ; SLM-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i64 2
; SLM-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i64 3 ; SLM-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i64 3
; SLM-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB5]], i64 5 ; SLM-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB5]], i64 5
; SLM-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i64 6 ; SLM-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i64 6
; SLM-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i64 7 ; SLM-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i64 7
; SLM-NEXT: ret <8 x i32> [[R7]] ; SLM-NEXT: ret <8 x i32> [[R7]]
; ;
; AVX1-LABEL: @sdiv_v8i32_undefs( ; AVX1-LABEL: @sdiv_v8i32_undefs(
; AVX1-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A:%.*]], i64 1 ; AVX1-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A:%.*]], i64 1
; AVX1-NEXT: [[A2:%.*]] = extractelement <8 x i32> [[A]], i64 2 ; AVX1-NEXT: [[A2:%.*]] = extractelement <8 x i32> [[A]], i64 2
; AVX1-NEXT: [[A3:%.*]] = extractelement <8 x i32> [[A]], i64 3 ; AVX1-NEXT: [[A3:%.*]] = extractelement <8 x i32> [[A]], i64 3
; AVX1-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i64 5 ; AVX1-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i64 5
; AVX1-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i64 6 ; AVX1-NEXT: [[A6:%.*]] = extractelement <8 x i32> [[A]], i64 6
; AVX1-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i64 7 ; AVX1-NEXT: [[A7:%.*]] = extractelement <8 x i32> [[A]], i64 7
; AVX1-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4 ; AVX1-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4
; AVX1-NEXT: [[AB2:%.*]] = sdiv i32 [[A2]], 8 ; AVX1-NEXT: [[AB2:%.*]] = sdiv i32 [[A2]], 8
; AVX1-NEXT: [[AB3:%.*]] = sdiv i32 [[A3]], 16 ; AVX1-NEXT: [[AB3:%.*]] = sdiv i32 [[A3]], 16
; AVX1-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4 ; AVX1-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; AVX1-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8 ; AVX1-NEXT: [[AB6:%.*]] = sdiv i32 [[A6]], 8
; AVX1-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16 ; AVX1-NEXT: [[AB7:%.*]] = sdiv i32 [[A7]], 16
; AVX1-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, i32 [[AB1]], i64 1 ; AVX1-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i64 1
; AVX1-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i64 2 ; AVX1-NEXT: [[R2:%.*]] = insertelement <8 x i32> [[R1]], i32 [[AB2]], i64 2
; AVX1-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i64 3 ; AVX1-NEXT: [[R3:%.*]] = insertelement <8 x i32> [[R2]], i32 [[AB3]], i64 3
; AVX1-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB5]], i64 5 ; AVX1-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R3]], i32 [[AB5]], i64 5
; AVX1-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i64 6 ; AVX1-NEXT: [[R6:%.*]] = insertelement <8 x i32> [[R5]], i32 [[AB6]], i64 6
; AVX1-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i64 7 ; AVX1-NEXT: [[R7:%.*]] = insertelement <8 x i32> [[R6]], i32 [[AB7]], i64 7
; AVX1-NEXT: ret <8 x i32> [[R7]] ; AVX1-NEXT: ret <8 x i32> [[R7]]
; ;
; AVX2-LABEL: @sdiv_v8i32_undefs( ; AVX2-LABEL: @sdiv_v8i32_undefs(
; AVX2-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A:%.*]], i64 1 ; AVX2-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A:%.*]], i64 1
; AVX2-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i64 5 ; AVX2-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i64 5
; AVX2-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4 ; AVX2-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4
; AVX2-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <2 x i32> <i32 2, i32 3> ; AVX2-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <2 x i32> <i32 2, i32 3>
; AVX2-NEXT: [[TMP2:%.*]] = sdiv <2 x i32> [[TMP1]], <i32 8, i32 16> ; AVX2-NEXT: [[TMP2:%.*]] = sdiv <2 x i32> [[TMP1]], <i32 8, i32 16>
; AVX2-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4 ; AVX2-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; AVX2-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <2 x i32> <i32 6, i32 7> ; AVX2-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <2 x i32> <i32 6, i32 7>
; AVX2-NEXT: [[TMP4:%.*]] = sdiv <2 x i32> [[TMP3]], <i32 8, i32 16> ; AVX2-NEXT: [[TMP4:%.*]] = sdiv <2 x i32> [[TMP3]], <i32 8, i32 16>
; AVX2-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, i32 [[AB1]], i64 1 ; AVX2-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i64 1
aqjuneUnsubmitted
Not Done
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Do you have any idea about why the 5'th element is undef, not poison?

aqjune: Do you have any idea about why the 5'th element is undef, not poison?
; AVX2-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; AVX2-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 poison, i32 1, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison> ; AVX2-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 poison, i32 1, i32 8, i32 9, i32 4, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R32]], i32 [[AB5]], i64 5 ; AVX2-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R32]], i32 [[AB5]], i64 5
; AVX2-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; AVX2-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX2-NEXT: [[R71:%.*]] = shufflevector <8 x i32> [[R5]], <8 x i32> [[TMP6]], <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 8, i32 9> ; AVX2-NEXT: [[R71:%.*]] = shufflevector <8 x i32> [[R5]], <8 x i32> [[TMP6]], <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; AVX2-NEXT: ret <8 x i32> [[R71]] ; AVX2-NEXT: ret <8 x i32> [[R71]]
; ;
; AVX512-LABEL: @sdiv_v8i32_undefs( ; AVX512-LABEL: @sdiv_v8i32_undefs(
; AVX512-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A:%.*]], i64 1 ; AVX512-NEXT: [[A1:%.*]] = extractelement <8 x i32> [[A:%.*]], i64 1
; AVX512-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i64 5 ; AVX512-NEXT: [[A5:%.*]] = extractelement <8 x i32> [[A]], i64 5
; AVX512-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4 ; AVX512-NEXT: [[AB1:%.*]] = sdiv i32 [[A1]], 4
; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <2 x i32> <i32 2, i32 3> ; AVX512-NEXT: [[TMP1:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <2 x i32> <i32 2, i32 3>
; AVX512-NEXT: [[TMP2:%.*]] = sdiv <2 x i32> [[TMP1]], <i32 8, i32 16> ; AVX512-NEXT: [[TMP2:%.*]] = sdiv <2 x i32> [[TMP1]], <i32 8, i32 16>
; AVX512-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4 ; AVX512-NEXT: [[AB5:%.*]] = sdiv i32 [[A5]], 4
; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <2 x i32> <i32 6, i32 7> ; AVX512-NEXT: [[TMP3:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <2 x i32> <i32 6, i32 7>
; AVX512-NEXT: [[TMP4:%.*]] = sdiv <2 x i32> [[TMP3]], <i32 8, i32 16> ; AVX512-NEXT: [[TMP4:%.*]] = sdiv <2 x i32> [[TMP3]], <i32 8, i32 16>
; AVX512-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>, i32 [[AB1]], i64 1 ; AVX512-NEXT: [[R1:%.*]] = insertelement <8 x i32> <i32 poison, i32 poison, i32 poison, i32 poison, i32 undef, i32 poison, i32 poison, i32 poison>, i32 [[AB1]], i64 1
; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; AVX512-NEXT: [[TMP5:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX512-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 poison, i32 1, i32 8, i32 9, i32 poison, i32 poison, i32 poison, i32 poison> ; AVX512-NEXT: [[R32:%.*]] = shufflevector <8 x i32> [[R1]], <8 x i32> [[TMP5]], <8 x i32> <i32 poison, i32 1, i32 8, i32 9, i32 4, i32 poison, i32 poison, i32 poison>
; AVX512-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R32]], i32 [[AB5]], i64 5 ; AVX512-NEXT: [[R5:%.*]] = insertelement <8 x i32> [[R32]], i32 [[AB5]], i64 5
; AVX512-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison> ; AVX512-NEXT: [[TMP6:%.*]] = shufflevector <2 x i32> [[TMP4]], <2 x i32> poison, <8 x i32> <i32 0, i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
; AVX512-NEXT: [[R71:%.*]] = shufflevector <8 x i32> [[R5]], <8 x i32> [[TMP6]], <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 poison, i32 5, i32 8, i32 9> ; AVX512-NEXT: [[R71:%.*]] = shufflevector <8 x i32> [[R5]], <8 x i32> [[TMP6]], <8 x i32> <i32 poison, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
; AVX512-NEXT: ret <8 x i32> [[R71]] ; AVX512-NEXT: ret <8 x i32> [[R71]]
; ;
%a0 = extractelement <8 x i32> %a, i32 0 %a0 = extractelement <8 x i32> %a, i32 0
%a1 = extractelement <8 x i32> %a, i32 1 %a1 = extractelement <8 x i32> %a, i32 1
%a2 = extractelement <8 x i32> %a, i32 2 %a2 = extractelement <8 x i32> %a, i32 2
%a3 = extractelement <8 x i32> %a, i32 3 %a3 = extractelement <8 x i32> %a, i32 3
%a4 = extractelement <8 x i32> %a, i32 4 %a4 = extractelement <8 x i32> %a, i32 4
%a5 = extractelement <8 x i32> %a, i32 5 %a5 = extractelement <8 x i32> %a, i32 5
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llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux -mattr=+sse2 | FileCheck %s --check-prefixes=SSE ; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux -mattr=+sse2 | FileCheck %s --check-prefixes=SSE
; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx | FileCheck %s --check-prefixes=AVX ; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx | FileCheck %s --check-prefixes=AVX
; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx2 | FileCheck %s --check-prefixes=AVX2 ; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx2 | FileCheck %s --check-prefixes=AVX2
; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512F ; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512F
; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx512vl | FileCheck %s --check-prefixes=AVX512VL ; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux -mattr=+avx512vl | FileCheck %s --check-prefixes=AVX512VL
define void @gather_load(ptr noalias nocapture %0, ptr noalias nocapture readonly %1) { define void @gather_load(ptr noalias nocapture %0, ptr noalias nocapture readonly %1) {
; SSE-LABEL: @gather_load( ; SSE-LABEL: @gather_load(
; SSE-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i64 1 ; SSE-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i64 1
; SSE-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]] ; SSE-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]]
; SSE-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 11 ; SSE-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 11
; SSE-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !tbaa [[TBAA0]] ; SSE-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !tbaa [[TBAA0]]
; SSE-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4 ; SSE-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4
; SSE-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA0]] ; SSE-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA0]]
; SSE-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[TBAA0]] ; SSE-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[TBAA0]]
; SSE-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> undef, i32 [[TMP4]], i64 0 ; SSE-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i64 0
; SSE-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i64 1 ; SSE-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i64 1
; SSE-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i64 2 ; SSE-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i64 2
; SSE-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i64 3 ; SSE-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i64 3
; SSE-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], <i32 1, i32 2, i32 3, i32 4> ; SSE-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], <i32 1, i32 2, i32 3, i32 4>
; SSE-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP0:%.*]], align 4, !tbaa [[TBAA0]] ; SSE-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP0:%.*]], align 4, !tbaa [[TBAA0]]
; SSE-NEXT: ret void ; SSE-NEXT: ret void
; ;
; AVX-LABEL: @gather_load( ; AVX-LABEL: @gather_load(
; AVX-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i64 1 ; AVX-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i64 1
; AVX-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]] ; AVX-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]]
; AVX-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 11 ; AVX-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 11
; AVX-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !tbaa [[TBAA0]] ; AVX-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !tbaa [[TBAA0]]
; AVX-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4 ; AVX-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4
; AVX-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA0]] ; AVX-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA0]]
; AVX-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[TBAA0]] ; AVX-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[TBAA0]]
; AVX-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> undef, i32 [[TMP4]], i64 0 ; AVX-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i64 0
; AVX-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i64 1 ; AVX-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i64 1
; AVX-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i64 2 ; AVX-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i64 2
; AVX-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i64 3 ; AVX-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i64 3
; AVX-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], <i32 1, i32 2, i32 3, i32 4> ; AVX-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], <i32 1, i32 2, i32 3, i32 4>
; AVX-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP0:%.*]], align 4, !tbaa [[TBAA0]] ; AVX-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP0:%.*]], align 4, !tbaa [[TBAA0]]
; AVX-NEXT: ret void ; AVX-NEXT: ret void
; ;
; AVX2-LABEL: @gather_load( ; AVX2-LABEL: @gather_load(
; AVX2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i64 1 ; AVX2-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i64 1
; AVX2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]] ; AVX2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]]
; AVX2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 11 ; AVX2-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 11
; AVX2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !tbaa [[TBAA0]] ; AVX2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !tbaa [[TBAA0]]
; AVX2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4 ; AVX2-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4
; AVX2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA0]] ; AVX2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA0]]
; AVX2-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[TBAA0]] ; AVX2-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[TBAA0]]
; AVX2-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> undef, i32 [[TMP4]], i64 0 ; AVX2-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i64 0
; AVX2-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i64 1 ; AVX2-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i64 1
; AVX2-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i64 2 ; AVX2-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i64 2
; AVX2-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i64 3 ; AVX2-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i64 3
; AVX2-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], <i32 1, i32 2, i32 3, i32 4> ; AVX2-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], <i32 1, i32 2, i32 3, i32 4>
; AVX2-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP0:%.*]], align 4, !tbaa [[TBAA0]] ; AVX2-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP0:%.*]], align 4, !tbaa [[TBAA0]]
; AVX2-NEXT: ret void ; AVX2-NEXT: ret void
; ;
; AVX512F-LABEL: @gather_load( ; AVX512F-LABEL: @gather_load(
; AVX512F-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i64 1 ; AVX512F-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i64 1
; AVX512F-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]] ; AVX512F-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]]
; AVX512F-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 11 ; AVX512F-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 11
; AVX512F-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !tbaa [[TBAA0]] ; AVX512F-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !tbaa [[TBAA0]]
; AVX512F-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4 ; AVX512F-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4
; AVX512F-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA0]] ; AVX512F-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA0]]
; AVX512F-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[TBAA0]] ; AVX512F-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[TBAA0]]
; AVX512F-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> undef, i32 [[TMP4]], i64 0 ; AVX512F-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i64 0
; AVX512F-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i64 1 ; AVX512F-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i64 1
; AVX512F-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i64 2 ; AVX512F-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i64 2
; AVX512F-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i64 3 ; AVX512F-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i64 3
; AVX512F-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], <i32 1, i32 2, i32 3, i32 4> ; AVX512F-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], <i32 1, i32 2, i32 3, i32 4>
; AVX512F-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP0:%.*]], align 4, !tbaa [[TBAA0]] ; AVX512F-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP0:%.*]], align 4, !tbaa [[TBAA0]]
; AVX512F-NEXT: ret void ; AVX512F-NEXT: ret void
; ;
; AVX512VL-LABEL: @gather_load( ; AVX512VL-LABEL: @gather_load(
; AVX512VL-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i64 1 ; AVX512VL-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1:%.*]], i64 1
; AVX512VL-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]] ; AVX512VL-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP1]], align 4, !tbaa [[TBAA0:![0-9]+]]
; AVX512VL-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 11 ; AVX512VL-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 11
; AVX512VL-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !tbaa [[TBAA0]] ; AVX512VL-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4, !tbaa [[TBAA0]]
; AVX512VL-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4 ; AVX512VL-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4
; AVX512VL-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA0]] ; AVX512VL-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !tbaa [[TBAA0]]
; AVX512VL-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[TBAA0]] ; AVX512VL-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP3]], align 4, !tbaa [[TBAA0]]
; AVX512VL-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> undef, i32 [[TMP4]], i64 0 ; AVX512VL-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP4]], i64 0
; AVX512VL-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i64 1 ; AVX512VL-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i64 1
; AVX512VL-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i64 2 ; AVX512VL-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i64 2
; AVX512VL-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i64 3 ; AVX512VL-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP12]], i32 [[TMP9]], i64 3
; AVX512VL-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], <i32 1, i32 2, i32 3, i32 4> ; AVX512VL-NEXT: [[TMP14:%.*]] = add nsw <4 x i32> [[TMP13]], <i32 1, i32 2, i32 3, i32 4>
; AVX512VL-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP0:%.*]], align 4, !tbaa [[TBAA0]] ; AVX512VL-NEXT: store <4 x i32> [[TMP14]], ptr [[TMP0:%.*]], align 4, !tbaa [[TBAA0]]
; AVX512VL-NEXT: ret void ; AVX512VL-NEXT: ret void
; ;
%3 = getelementptr inbounds i32, ptr %1, i64 1 %3 = getelementptr inbounds i32, ptr %1, i64 1
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llvm/test/Transforms/SLPVectorizer/X86/pr47642.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=slp-vectorizer,instcombine -S < %s | FileCheck %s ; RUN: opt -passes=slp-vectorizer,instcombine -S < %s | FileCheck %s
; These code should be fully vectorized by D57059 patch ; These code should be fully vectorized by D57059 patch
target triple = "x86_64-unknown-linux-gnu" target triple = "x86_64-unknown-linux-gnu"
define <4 x i32> @foo(<4 x i32> %x, i32 %f) { define <4 x i32> @foo(<4 x i32> %x, i32 %f) {
; CHECK-LABEL: @foo( ; CHECK-LABEL: @foo(
; CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x i32> undef, i32 [[F:%.*]], i64 0 ; CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x i32> poison, i32 [[F:%.*]], i64 0
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[F]], 1 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[F]], 1
; CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x i32> [[VECINIT]], i32 [[ADD]], i64 1 ; CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x i32> [[VECINIT]], i32 [[ADD]], i64 1
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[F]], i64 0 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i32> poison, i32 [[F]], i64 0
; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer ; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> poison, <2 x i32> zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i32> [[TMP2]], <i32 2, i32 3> ; CHECK-NEXT: [[TMP3:%.*]] = add nsw <2 x i32> [[TMP2]], <i32 2, i32 3>
; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[VECINIT51:%.*]] = shufflevector <4 x i32> [[VECINIT1]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 5> ; CHECK-NEXT: [[VECINIT51:%.*]] = shufflevector <4 x i32> [[VECINIT1]], <4 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT: ret <4 x i32> [[VECINIT51]] ; CHECK-NEXT: ret <4 x i32> [[VECINIT51]]
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llvm/test/Transforms/SLPVectorizer/X86/pr49081.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=x86_64-- -passes=slp-vectorizer,instcombine -S < %s | FileCheck %s ; RUN: opt -mtriple=x86_64-- -passes=slp-vectorizer,instcombine -S < %s | FileCheck %s
; These conversions should be vectorized by reviews.llvm.org/D57059 ; These conversions should be vectorized by reviews.llvm.org/D57059
define dso_local <4 x float> @foo(<4 x i32> %0) { define dso_local <4 x float> @foo(<4 x i32> %0) {
; CHECK-LABEL: @foo( ; CHECK-LABEL: @foo(
; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP0:%.*]], i64 1 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[TMP0:%.*]], i64 1
; CHECK-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float ; CHECK-NEXT: [[TMP3:%.*]] = sitofp i32 [[TMP2]] to float
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> undef, float [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP4:%.*]] = insertelement <4 x float> poison, float [[TMP3]], i64 0
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x float> [[TMP4]], float [[TMP3]], i64 1 ; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <4 x float> [[TMP4]], <4 x float> poison, <4 x i32> <i32 0, i32 0, i32 poison, i32 poison>
aqjuneUnsubmitted
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This change looks interesting, I think it is worth investigating why this happened.

aqjune: This change looks interesting, I think it is worth investigating why this happened.
; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <2 x i32> <i32 2, i32 3> ; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i32> [[TMP0]], <4 x i32> poison, <2 x i32> <i32 2, i32 3>
; CHECK-NEXT: [[TMP7:%.*]] = sitofp <2 x i32> [[TMP6]] to <2 x float> ; CHECK-NEXT: [[TMP7:%.*]] = sitofp <2 x i32> [[TMP6]] to <2 x float>
; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP7]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison> ; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x float> [[TMP7]], <2 x float> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP8]], <4 x i32> <i32 0, i32 1, i32 4, i32 5> ; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> [[TMP8]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
; CHECK-NEXT: ret <4 x float> [[TMP9]] ; CHECK-NEXT: ret <4 x float> [[TMP9]]
; ;
%2 = extractelement <4 x i32> %0, i32 1 %2 = extractelement <4 x i32> %0, i32 1
%3 = sitofp i32 %2 to float %3 = sitofp i32 %2 to float
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