[RISCV] Merge RISCVMCInstLower.cpp into RISCVAsmPrinter.cpp.

[craig.topper]

Summary

The separation here doesn't make much sense. I think it's a
leftover from the creation of the MC layer that has been
replicated to new targets.

By merging them we can avoid passing the AsmPrinter to the
MCInstLowering functions. We can make them member functions instead.

I think we can still do more integration of lowerSymbolOperand
and lowerRISCVVMachineInstrToMCInst, but I wanted to get feedback
on the direction first.

[asb]

This is definitely something I just copied from other backends and I like the idea of merging it. There is some value in uniformity with other backends though, so if other targets were dead set against ever considering something similar then perhaps we'd consider if it's better to stay matching everyone else.

[craig.topper]

In D152311#4401941, @asb wrote:

This is definitely something I just copied from other backends and I like the idea of merging it. There is some value in uniformity with other backends though, so if other targets were dead set against ever considering something similar then perhaps we'd consider if it's better to stay matching everyone else.

I think there's already inconsistency in the structure of the files. I surveyed some of the targets.

X86 has a X86MCInstLower class that is instantiated on each call to X86AsmPrinter::emitInstruction. X86AsmPrinter::emitInstruction is implemented in X86MCInstLower.cpp

RISC-V does not have a MCInstLower class.

AArch64 has a AArch64MCInstLower object that is a member of AArch64AsmPrinter so its only instantiated once.

ARM, Hexagon, PowerPC, and SystemZ seem similar to RISC-V.

SystemZ has a SystemZMCInstLower instatiated from SystemZAsmPrinter::emitInstruction. SystemZAsmPrinter::emitInstruction is in SystemZAsmPrinter.cpp

AMDGPU has a AMDGPUMCInstLower instantiated from AMDGPUAsmPrinter::emitInstruction. AMDGPUAsmPrinter::emitInstruction lives in AMDGPUMCInstLower.cpp.

Mips has a MipsMCInstLower member of MipsAsmPrinter so it's only instantiated once.

[frasercrmck]

I'm in favour of this. I think you explained the inconsistencies well. I believe RISCV has served as an example for new backends (I don't know if that's still the case) so I think there's a good argument (given the aforementioned inconsistencies) to forge a path forward.

[asb]

In D152311#4402018, @craig.topper wrote:

In D152311#4401941, @asb wrote:

This is definitely something I just copied from other backends and I like the idea of merging it. There is some value in uniformity with other backends though, so if other targets were dead set against ever considering something similar then perhaps we'd consider if it's better to stay matching everyone else.

I think there's already inconsistency in the structure of the files. I surveyed some of the targets.
(snip)

Thanks - I upgrade my view from supportive to _very_ supportive!

[craig.topper]

In D152311#4402292, @asb wrote:

In D152311#4402018, @craig.topper wrote:

In D152311#4401941, @asb wrote:

This is definitely something I just copied from other backends and I like the idea of merging it. There is some value in uniformity with other backends though, so if other targets were dead set against ever considering something similar then perhaps we'd consider if it's better to stay matching everyone else.

I think there's already inconsistency in the structure of the files. I surveyed some of the targets.
(snip)

Thanks - I upgrade my view from supportive to _very_ supportive!

Anything else I need to do to move forward with this?

[barannikov88]

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

158–159

(nit) Can this be renamed to OutMI or OutInst or something more meaningful?

[asb]

LGTM

llvm/lib/Target/RISCV/CMakeLists.txt

add_llvm_target(RISCVCodeGen
   RISCVFrameLowering.cpp
   RISCVGatherScatterLowering.cpp
   RISCVInsertVSETVLI.cpp
   RISCVInstrInfo.cpp
   RISCVISelDAGToDAG.cpp
   RISCVISelLowering.cpp
   RISCVMachineFunctionInfo.cpp
   RISCVMacroFusion.cpp
-  RISCVMCInstLower.cpp
   RISCVMergeBaseOffset.cpp
   RISCVOptWInstrs.cpp
   RISCVRedundantCopyElimination.cpp
   RISCVRegisterInfo.cpp
   RISCVRVVInitUndef.cpp
   RISCVSubtarget.cpp
   RISCVTargetMachine.cpp
   RISCVTargetObjectFile.cpp

llvm/lib/Target/RISCV/RISCV.h

 class PassRegistry;
 class RISCVRegisterBankInfo;
 class RISCVSubtarget;
 class RISCVTargetMachine;
 
 FunctionPass *createRISCVCodeGenPreparePass();
 void initializeRISCVCodeGenPreparePass(PassRegistry &);
 
-bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
-                                    AsmPrinter &AP);
-bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
-                                         MCOperand &MCOp, const AsmPrinter &AP);
-
 FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
                                  CodeGenOpt::Level OptLevel);
 
 FunctionPass *createRISCVMakeCompressibleOptPass();
 void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
 
 FunctionPass *createRISCVGatherScatterLoweringPass();
 void initializeRISCVGatherScatterLoweringPass(PassRegistry &);

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
                                    const MachineInstr *MI);
 
   typedef std::tuple<unsigned, uint32_t> HwasanMemaccessTuple;
   std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
   void LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI);
   void EmitHwasanMemaccessSymbols(Module &M);
 
   // Wrapper needed for tblgenned pseudo lowering.
-  bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
-    return lowerRISCVMachineOperandToMCOperand(MO, MCOp, *this);
-  }
+  bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const;
 
   void emitStartOfAsmFile(Module &M) override;
   void emitEndOfAsmFile(Module &M) override;
 
   void emitFunctionEntryLabel() override;
 
 private:
   void emitAttributes();
 
   void emitNTLHint(const MachineInstr *MI);
+
+  bool lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
 };
 }
 
 void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {
   MCInst CInst;
   bool Res = RISCVRVC::compress(CInst, Inst, *STI);
   if (Res)
     ++RISCVNumInstrsCompressed;
case RISCV::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
     LowerHWASAN_CHECK_MEMACCESS(*MI);
     return;
   case RISCV::PseudoRVVInitUndefM1:
   case RISCV::PseudoRVVInitUndefM2:
   case RISCV::PseudoRVVInitUndefM4:
   case RISCV::PseudoRVVInitUndefM8:
     return;
   }
 
-  MCInst TmpInst;
-  if (!lowerRISCVMachineInstrToMCInst(MI, TmpInst, *this))
-    EmitToStreamer(*OutStreamer, TmpInst);
+  MCInst OutInst;
+  if (!lowerToMCInst(MI, OutInst))
+    EmitToStreamer(*OutStreamer, OutInst);
 }
 
 bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                       const char *ExtraCode, raw_ostream &OS) {
   // First try the generic code, which knows about modifiers like 'c' and 'n'.
   if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS))
     return false;
 
OutStreamer->emitInstruction(
             .addReg(RISCV::X0)
             .addImm(AccessInfo & HWASanAccessInfo::RuntimeMask),
         MCSTI);
 
     OutStreamer->emitInstruction(MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr),
                                  MCSTI);
   }
 }
+
+static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
+                                    const AsmPrinter &AP) {
+  MCContext &Ctx = AP.OutContext;
+  RISCVMCExpr::VariantKind Kind;
+
+  switch (MO.getTargetFlags()) {
+  default:
+    llvm_unreachable("Unknown target flag on GV operand");
+  case RISCVII::MO_None:
+    Kind = RISCVMCExpr::VK_RISCV_None;
+    break;
+  case RISCVII::MO_CALL:
+    Kind = RISCVMCExpr::VK_RISCV_CALL;
+    break;
+  case RISCVII::MO_PLT:
+    Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
+    break;
+  case RISCVII::MO_LO:
+    Kind = RISCVMCExpr::VK_RISCV_LO;
+    break;
+  case RISCVII::MO_HI:
+    Kind = RISCVMCExpr::VK_RISCV_HI;
+    break;
+  case RISCVII::MO_PCREL_LO:
+    Kind = RISCVMCExpr::VK_RISCV_PCREL_LO;
+    break;
+  case RISCVII::MO_PCREL_HI:
+    Kind = RISCVMCExpr::VK_RISCV_PCREL_HI;
+    break;
+  case RISCVII::MO_GOT_HI:
+    Kind = RISCVMCExpr::VK_RISCV_GOT_HI;
+    break;
+  case RISCVII::MO_TPREL_LO:
+    Kind = RISCVMCExpr::VK_RISCV_TPREL_LO;
+    break;
+  case RISCVII::MO_TPREL_HI:
+    Kind = RISCVMCExpr::VK_RISCV_TPREL_HI;
+    break;
+  case RISCVII::MO_TPREL_ADD:
+    Kind = RISCVMCExpr::VK_RISCV_TPREL_ADD;
+    break;
+  case RISCVII::MO_TLS_GOT_HI:
+    Kind = RISCVMCExpr::VK_RISCV_TLS_GOT_HI;
+    break;
+  case RISCVII::MO_TLS_GD_HI:
+    Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI;
+    break;
+  }
+
+  const MCExpr *ME =
+      MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
+
+  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
+    ME = MCBinaryExpr::createAdd(
+        ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
+
+  if (Kind != RISCVMCExpr::VK_RISCV_None)
+    ME = RISCVMCExpr::create(ME, Kind, Ctx);
+  return MCOperand::createExpr(ME);
+}
+
+bool RISCVAsmPrinter::lowerOperand(const MachineOperand &MO,
+                                   MCOperand &MCOp) const {
+  switch (MO.getType()) {
+  default:
+    report_fatal_error("lowerOperand: unknown operand type");
+  case MachineOperand::MO_Register:
+    // Ignore all implicit register operands.
+    if (MO.isImplicit())
+      return false;
+    MCOp = MCOperand::createReg(MO.getReg());
+    break;
+  case MachineOperand::MO_RegisterMask:
+    // Regmasks are like implicit defs.
+    return false;
+  case MachineOperand::MO_Immediate:
+    MCOp = MCOperand::createImm(MO.getImm());
+    break;
+  case MachineOperand::MO_MachineBasicBlock:
+    MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), *this);
+    break;
+  case MachineOperand::MO_GlobalAddress:
+    MCOp = lowerSymbolOperand(MO, getSymbolPreferLocal(*MO.getGlobal()), *this);
+    break;
+  case MachineOperand::MO_BlockAddress:
+    MCOp = lowerSymbolOperand(MO, GetBlockAddressSymbol(MO.getBlockAddress()),
+                              *this);
+    break;
+  case MachineOperand::MO_ExternalSymbol:
+    MCOp = lowerSymbolOperand(MO, GetExternalSymbolSymbol(MO.getSymbolName()),
+                              *this);
+    break;
+  case MachineOperand::MO_ConstantPoolIndex:
+    MCOp = lowerSymbolOperand(MO, GetCPISymbol(MO.getIndex()), *this);
+    break;
+  case MachineOperand::MO_JumpTableIndex:
+    MCOp = lowerSymbolOperand(MO, GetJTISymbol(MO.getIndex()), *this);
+    break;
+  case MachineOperand::MO_MCSymbol:
+    MCOp = lowerSymbolOperand(MO, MO.getMCSymbol(), *this);
+    break;
+  }
+  return true;
+}
+
+static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
+                                            MCInst &OutMI) {
+  const RISCVVPseudosTable::PseudoInfo *RVV =
+      RISCVVPseudosTable::getPseudoInfo(MI->getOpcode());
+  if (!RVV)
+    return false;
+
+  OutMI.setOpcode(RVV->BaseInstr);
+
+  const MachineBasicBlock *MBB = MI->getParent();
+  assert(MBB && "MI expected to be in a basic block");
+  const MachineFunction *MF = MBB->getParent();
+  assert(MF && "MBB expected to be in a machine function");
+
+  const TargetRegisterInfo *TRI =
+      MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
+
+  assert(TRI && "TargetRegisterInfo expected");
+
+  uint64_t TSFlags = MI->getDesc().TSFlags;
+  unsigned NumOps = MI->getNumExplicitOperands();
+
+  // Skip policy, VL and SEW operands which are the last operands if present.
+  if (RISCVII::hasVecPolicyOp(TSFlags))
+    --NumOps;
+  if (RISCVII::hasVLOp(TSFlags))
+    --NumOps;
+  if (RISCVII::hasSEWOp(TSFlags))
+    --NumOps;
+
+  bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);
+  for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
+    const MachineOperand &MO = MI->getOperand(OpNo);
+    // Skip vl ouput. It should be the second output.
+    if (hasVLOutput && OpNo == 1)
+      continue;
+
+    // Skip merge op. It should be the first operand after the result.
+    if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1U + hasVLOutput) {
+      assert(MI->getNumExplicitDefs() == 1U + hasVLOutput);
+      continue;
+    }
+
+    MCOperand MCOp;
+    switch (MO.getType()) {
+    default:
+      llvm_unreachable("Unknown operand type");
+    case MachineOperand::MO_Register: {
+      Register Reg = MO.getReg();
+
+      if (RISCV::VRM2RegClass.contains(Reg) ||
+          RISCV::VRM4RegClass.contains(Reg) ||
+          RISCV::VRM8RegClass.contains(Reg)) {
+        Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
+        assert(Reg && "Subregister does not exist");
+      } else if (RISCV::FPR16RegClass.contains(Reg)) {
+        Reg =
+            TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
+        assert(Reg && "Subregister does not exist");
+      } else if (RISCV::FPR64RegClass.contains(Reg)) {
+        Reg = TRI->getSubReg(Reg, RISCV::sub_32);
+        assert(Reg && "Superregister does not exist");
+      } else if (RISCV::VRN2M1RegClass.contains(Reg) ||
+                 RISCV::VRN2M2RegClass.contains(Reg) ||
+                 RISCV::VRN2M4RegClass.contains(Reg) ||
+                 RISCV::VRN3M1RegClass.contains(Reg) ||
+                 RISCV::VRN3M2RegClass.contains(Reg) ||
+                 RISCV::VRN4M1RegClass.contains(Reg) ||
+                 RISCV::VRN4M2RegClass.contains(Reg) ||
+                 RISCV::VRN5M1RegClass.contains(Reg) ||
+                 RISCV::VRN6M1RegClass.contains(Reg) ||
+                 RISCV::VRN7M1RegClass.contains(Reg) ||
+                 RISCV::VRN8M1RegClass.contains(Reg)) {
+        Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
+        assert(Reg && "Subregister does not exist");
+      }
+
+      MCOp = MCOperand::createReg(Reg);
+      break;
+    }
+    case MachineOperand::MO_Immediate:
+      MCOp = MCOperand::createImm(MO.getImm());
+      break;
+    }
+    OutMI.addOperand(MCOp);
+  }
+
+  // Unmasked pseudo instructions need to append dummy mask operand to
+  // V instructions. All V instructions are modeled as the masked version.
+  if (RISCVII::hasDummyMaskOp(TSFlags))
+    OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
+
+  return true;
+}
+
+bool RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
+  if (lowerRISCVVMachineInstrToMCInst(MI, OutMI))
+    return false;
+
+  OutMI.setOpcode(MI->getOpcode());
+
+  for (const MachineOperand &MO : MI->operands()) {
+    MCOperand MCOp;
+    if (lowerOperand(MO, MCOp))
+      OutMI.addOperand(MCOp);
+  }
+
+  switch (OutMI.getOpcode()) {
+  case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
+    const Function &F = MI->getParent()->getParent()->getFunction();
+    if (F.hasFnAttribute("patchable-function-entry")) {
+      unsigned Num;
+      if (F.getFnAttribute("patchable-function-entry")
+              .getValueAsString()
+              .getAsInteger(10, Num))
+        return false;
+      emitNops(Num);
+      return true;
+    }
+    break;
+  }
+  }
+  return false;
+}

llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

-//===-- RISCVMCInstLower.cpp - Convert RISC-V MachineInstr to an MCInst -----=//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains code to lower RISC-V MachineInstrs to their corresponding
-// MCInst records.
-//
-//===----------------------------------------------------------------------===//
-
-#include "RISCV.h"
-#include "RISCVSubtarget.h"
-#include "MCTargetDesc/RISCVMCExpr.h"
-#include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/Support/ErrorHandling.h"
-#include "llvm/Support/raw_ostream.h"
-
-using namespace llvm;
-
-static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
-                                    const AsmPrinter &AP) {
-  MCContext &Ctx = AP.OutContext;
-  RISCVMCExpr::VariantKind Kind;
-
-  switch (MO.getTargetFlags()) {
-  default:
-    llvm_unreachable("Unknown target flag on GV operand");
-  case RISCVII::MO_None:
-    Kind = RISCVMCExpr::VK_RISCV_None;
-    break;
-  case RISCVII::MO_CALL:
-    Kind = RISCVMCExpr::VK_RISCV_CALL;
-    break;
-  case RISCVII::MO_PLT:
-    Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
-    break;
-  case RISCVII::MO_LO:
-    Kind = RISCVMCExpr::VK_RISCV_LO;
-    break;
-  case RISCVII::MO_HI:
-    Kind = RISCVMCExpr::VK_RISCV_HI;
-    break;
-  case RISCVII::MO_PCREL_LO:
-    Kind = RISCVMCExpr::VK_RISCV_PCREL_LO;
-    break;
-  case RISCVII::MO_PCREL_HI:
-    Kind = RISCVMCExpr::VK_RISCV_PCREL_HI;
-    break;
-  case RISCVII::MO_GOT_HI:
-    Kind = RISCVMCExpr::VK_RISCV_GOT_HI;
-    break;
-  case RISCVII::MO_TPREL_LO:
-    Kind = RISCVMCExpr::VK_RISCV_TPREL_LO;
-    break;
-  case RISCVII::MO_TPREL_HI:
-    Kind = RISCVMCExpr::VK_RISCV_TPREL_HI;
-    break;
-  case RISCVII::MO_TPREL_ADD:
-    Kind = RISCVMCExpr::VK_RISCV_TPREL_ADD;
-    break;
-  case RISCVII::MO_TLS_GOT_HI:
-    Kind = RISCVMCExpr::VK_RISCV_TLS_GOT_HI;
-    break;
-  case RISCVII::MO_TLS_GD_HI:
-    Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI;
-    break;
-  }
-
-  const MCExpr *ME =
-      MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
-
-  if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
-    ME = MCBinaryExpr::createAdd(
-        ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
-
-  if (Kind != RISCVMCExpr::VK_RISCV_None)
-    ME = RISCVMCExpr::create(ME, Kind, Ctx);
-  return MCOperand::createExpr(ME);
-}
-
-bool llvm::lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
-                                               MCOperand &MCOp,
-                                               const AsmPrinter &AP) {
-  switch (MO.getType()) {
-  default:
-    report_fatal_error("LowerRISCVMachineInstrToMCInst: unknown operand type");
-  case MachineOperand::MO_Register:
-    // Ignore all implicit register operands.
-    if (MO.isImplicit())
-      return false;
-    MCOp = MCOperand::createReg(MO.getReg());
-    break;
-  case MachineOperand::MO_RegisterMask:
-    // Regmasks are like implicit defs.
-    return false;
-  case MachineOperand::MO_Immediate:
-    MCOp = MCOperand::createImm(MO.getImm());
-    break;
-  case MachineOperand::MO_MachineBasicBlock:
-    MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);
-    break;
-  case MachineOperand::MO_GlobalAddress:
-    MCOp = lowerSymbolOperand(MO, AP.getSymbolPreferLocal(*MO.getGlobal()), AP);
-    break;
-  case MachineOperand::MO_BlockAddress:
-    MCOp = lowerSymbolOperand(
-        MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);
-    break;
-  case MachineOperand::MO_ExternalSymbol:
-    MCOp = lowerSymbolOperand(
-        MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
-    break;
-  case MachineOperand::MO_ConstantPoolIndex:
-    MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
-    break;
-  case MachineOperand::MO_JumpTableIndex:
-    MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
-    break;
-  case MachineOperand::MO_MCSymbol:
-    MCOp = lowerSymbolOperand(MO, MO.getMCSymbol(), AP);
-    break;
-  }
-  return true;
-}
-
-static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
-                                            MCInst &OutMI) {
-  const RISCVVPseudosTable::PseudoInfo *RVV =
-      RISCVVPseudosTable::getPseudoInfo(MI->getOpcode());
-  if (!RVV)
-    return false;
-
-  OutMI.setOpcode(RVV->BaseInstr);
-
-  const MachineBasicBlock *MBB = MI->getParent();
-  assert(MBB && "MI expected to be in a basic block");
-  const MachineFunction *MF = MBB->getParent();
-  assert(MF && "MBB expected to be in a machine function");
-
-  const TargetRegisterInfo *TRI =
-      MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
-
-  assert(TRI && "TargetRegisterInfo expected");
-
-  uint64_t TSFlags = MI->getDesc().TSFlags;
-  unsigned NumOps = MI->getNumExplicitOperands();
-
-  // Skip policy, VL and SEW operands which are the last operands if present.
-  if (RISCVII::hasVecPolicyOp(TSFlags))
-    --NumOps;
-  if (RISCVII::hasVLOp(TSFlags))
-    --NumOps;
-  if (RISCVII::hasSEWOp(TSFlags))
-    --NumOps;
-
-  bool hasVLOutput = RISCV::isFaultFirstLoad(*MI);
-  for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
-    const MachineOperand &MO = MI->getOperand(OpNo);
-    // Skip vl ouput. It should be the second output.
-    if (hasVLOutput && OpNo == 1)
-      continue;
-
-    // Skip merge op. It should be the first operand after the result.
-    if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1U + hasVLOutput) {
-      assert(MI->getNumExplicitDefs() == 1U + hasVLOutput);
-      continue;
-    }
-
-    MCOperand MCOp;
-    switch (MO.getType()) {
-    default:
-      llvm_unreachable("Unknown operand type");
-    case MachineOperand::MO_Register: {
-      Register Reg = MO.getReg();
-
-      if (RISCV::VRM2RegClass.contains(Reg) ||
-          RISCV::VRM4RegClass.contains(Reg) ||
-          RISCV::VRM8RegClass.contains(Reg)) {
-        Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
-        assert(Reg && "Subregister does not exist");
-      } else if (RISCV::FPR16RegClass.contains(Reg)) {
-        Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
-        assert(Reg && "Subregister does not exist");
-      } else if (RISCV::FPR64RegClass.contains(Reg)) {
-        Reg = TRI->getSubReg(Reg, RISCV::sub_32);
-        assert(Reg && "Superregister does not exist");
-      } else if (RISCV::VRN2M1RegClass.contains(Reg) ||
-                 RISCV::VRN2M2RegClass.contains(Reg) ||
-                 RISCV::VRN2M4RegClass.contains(Reg) ||
-                 RISCV::VRN3M1RegClass.contains(Reg) ||
-                 RISCV::VRN3M2RegClass.contains(Reg) ||
-                 RISCV::VRN4M1RegClass.contains(Reg) ||
-                 RISCV::VRN4M2RegClass.contains(Reg) ||
-                 RISCV::VRN5M1RegClass.contains(Reg) ||
-                 RISCV::VRN6M1RegClass.contains(Reg) ||
-                 RISCV::VRN7M1RegClass.contains(Reg) ||
-                 RISCV::VRN8M1RegClass.contains(Reg)) {
-        Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
-        assert(Reg && "Subregister does not exist");
-      }
-
-      MCOp = MCOperand::createReg(Reg);
-      break;
-    }
-    case MachineOperand::MO_Immediate:
-      MCOp = MCOperand::createImm(MO.getImm());
-      break;
-    }
-    OutMI.addOperand(MCOp);
-  }
-
-  // Unmasked pseudo instructions need to append dummy mask operand to
-  // V instructions. All V instructions are modeled as the masked version.
-  if (RISCVII::hasDummyMaskOp(TSFlags))
-    OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
-
-  return true;
-}
-
-bool llvm::lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
-                                          AsmPrinter &AP) {
-  if (lowerRISCVVMachineInstrToMCInst(MI, OutMI))
-    return false;
-
-  OutMI.setOpcode(MI->getOpcode());
-
-  for (const MachineOperand &MO : MI->operands()) {
-    MCOperand MCOp;
-    if (lowerRISCVMachineOperandToMCOperand(MO, MCOp, AP))
-      OutMI.addOperand(MCOp);
-  }
-
-  switch (OutMI.getOpcode()) {
-  case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
-    const Function &F = MI->getParent()->getParent()->getFunction();
-    if (F.hasFnAttribute("patchable-function-entry")) {
-      unsigned Num;
-      if (F.getFnAttribute("patchable-function-entry")
-              .getValueAsString()
-              .getAsInteger(10, Num))
-        return false;
-      AP.emitNops(Num);
-      return true;
-    }
-    break;
-  }
-  }
-  return false;
-}