[RISCV] Set GenCrashDialog=false for various report_fatal_error calls in lib/Target/RISCV

[asb]

Summary

The GenCrashDialog parameter to report_fatal_error controls whether a backtrace and an invitation to submit a bug report are printed. As a number of our users of report_fatal_error really indicate an exit with an error message for improper input, it's more appropriate to just print the diagnostic and exit rather than suggest a bug report (especially true for handling of errors from RISCVISAInfo). D62236 is one patch I remember making a similar change.

This patch changes most report_fatal_error calls within lib/Target/RISCV to disable the backtrace and bug report suggestion. I've left it as the default (GenCrashDialog=true) for e.g. getRegisterByName, movImm as I think these are likely to represent an error on the LLVM side that deserves a bug report.

This came up in https://github.com/llvm/llvm-project/issues/62729. Happy to split out or change if people feel different criteria should be used. See also: D150669 which is needed for some of these changes to have the desired effect.

[MaskRay]

report_fatal_error is a lazy error reporting mechanism that should be avoided. Adding false (exit(1) instead of abort()) just papers over the issue...

[barannikov88]

I guess the description should read GenCrashDiag=false?

[asb]

In D150674#4346704, @MaskRay wrote:

report_fatal_error is a lazy error reporting mechanism that should be avoided. Adding false (exit(1) instead of abort()) just papers over the issue...

Yes, it would be good to have a better error reporting mechanism in many of these cases and excise these uses of report_fatal_error - but AFAIK the infrastructure just isn't there for many of these to report a proper error with context (corrections welcome!). I think we're in agreement this patch isn't fundamentally improving the situation, just making some minor incremental improvements on what we have today.

[arsenm]

This should be the universal default. report_fatal_error should not emit crash dialogs

[arsenm]

In D150674#4346704, @MaskRay wrote:

report_fatal_error is a lazy error reporting mechanism that should be avoided. Adding false (exit(1) instead of abort()) just papers over the issue...

It's appropriate for certain things. This isn't for issues end users should encounter. There are plenty of situations that need to be treated as not-an-assert and exit, such as situations only reachable through handwritten MIR

[asb]

In D150674#4346919, @arsenm wrote:

This should be the universal default. report_fatal_error should not emit crash dialogs

Thanks for taking a look. Just for the sake of clarity, is this a general comment or a request to invert the default behaviour of report_fatal_error rather than landing this patch? If the latter - I'd say I'm happy to help improve things here and even post an RFC on the issue, but I'm also well aware it's likely to take a long time to land (not least as it will re-raise the issue, as this patch has, of inadequacies in LLVM's error handling infrastructure). So my preference would be to land this incremental improvement and separate that from work to flip the default or make other broader changes.

[asb]

In D150674#4349305, @asb wrote:

In D150674#4346919, @arsenm wrote:

This should be the universal default. report_fatal_error should not emit crash dialogs

Thanks for taking a look. Just for the sake of clarity, is this a general comment or a request to invert the default behaviour of report_fatal_error rather than landing this patch? If the latter - I'd say I'm happy to help improve things here and even post an RFC on the issue, but I'm also well aware it's likely to take a long time to land (not least as it will re-raise the issue, as this patch has, of inadequacies in LLVM's error handling infrastructure). So my preference would be to land this incremental improvement and separate that from work to flip the default or make other broader changes.

This needs rebasing, but before doing that I wanted to ping again (@arsenm) on this question. It does make sense to me to improve the usage of report_fatal_error within lib/Target/RISCV according to its current interface, separate to any discussion about changing that interface. But let me know if you feel differently.

[MaskRay]

I agree that in lib/Target and lib/CodeGen, there are many report_fatal_error places that are difficult to switch to a better error reporting mechanism.
If lib/Target/RISCV does this, should other targets do similar things?

Perhaps you can start a thread on https://discourse.llvm.org/ whether GenCrashDiag should default to false, as I think it is worth bringing more attention. FWIW I support defaulting to false.

[arsenm]

In D150674#4456128, @asb wrote:

In D150674#4349305, @asb wrote:

In D150674#4346919, @arsenm wrote:

This should be the universal default. report_fatal_error should not emit crash dialogs

Thanks for taking a look. Just for the sake of clarity, is this a general comment or a request to invert the default behaviour of report_fatal_error rather than landing this patch? If the latter - I'd say I'm happy to help improve things here and even post an RFC on the issue, but I'm also well aware it's likely to take a long time to land (not least as it will re-raise the issue, as this patch has, of inadequacies in LLVM's error handling infrastructure). So my preference would be to land this incremental improvement and separate that from work to flip the default or make other broader changes.

This needs rebasing, but before doing that I wanted to ping again (@arsenm) on this question. It does make sense to me to improve the usage of report_fatal_error within lib/Target/RISCV according to its current interface, separate to any discussion about changing that interface. But let me know if you feel differently.

Yes. I really think the default needs to change, this has been majorly annoying for over 3 years now. Incrementally improving is fine

[asb]

Rebase. I held off on this due to the branch, but would like to progress now. I'll kick off a discourse thread now on the default - but I'm hopeful to get a review in order to land this as an incremental improvement.

[asb]

RFC thread https://discourse.llvm.org/t/rfc-report-fatal-error-and-the-default-value-of-gencrashdialog/73587

[asb]

Ping? I don't think anything in this patch is blocked on the RFC thread.

[mehdi_amini]

As a number of our users of report_fatal_error really indicate an exit with an error message for improper input

In D150674#4346910, @asb wrote:

In D150674#4346704, @MaskRay wrote:

report_fatal_error is a lazy error reporting mechanism that should be avoided. Adding false (exit(1) instead of abort()) just papers over the issue...

Yes, it would be good to have a better error reporting mechanism in many of these cases and excise these uses of report_fatal_error - but AFAIK the infrastructure just isn't there for many of these to report a proper error with context (corrections welcome!).

I'm not really buying the infrastructure argument: seems like a cultural issue in not spending enough design effort for each of these.
For example many of these seems to me like invariants of these components, and as such verification should happen upstream of getting through these code-paths (and thus not validating before become a bug in the tool...)

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

ABI computeTargetABI(const Triple &TT, const FeatureBitset &FeatureBits,
   }
 
   if (TargetABI != ABI_Unknown)
     return TargetABI;
 
   // If no explicit ABI is given, try to compute the default ABI.
   auto ISAInfo = RISCVFeatures::parseFeatureBits(IsRV64, FeatureBits);
   if (!ISAInfo)
-    report_fatal_error(ISAInfo.takeError());
+    report_fatal_error(ISAInfo.takeError(), false);
   return getTargetABI((*ISAInfo)->computeDefaultABI());
 }
 
 ABI getTargetABI(StringRef ABIName) {
   auto TargetABI = StringSwitch<ABI>(ABIName)
                        .Case("ilp32", ABI_ILP32)
                        .Case("ilp32f", ABI_ILP32F)
                        .Case("ilp32d", ABI_ILP32D)

 MCRegister getSCSPReg() { return RISCV::X3; }
 
 } // namespace RISCVABI
 
 namespace RISCVFeatures {
 
 void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
   if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit])
-    report_fatal_error("RV64 target requires an RV64 CPU");
+    report_fatal_error("RV64 target requires an RV64 CPU", false);
   if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit])
-    report_fatal_error("RV32 target requires an RV32 CPU");
+    report_fatal_error("RV32 target requires an RV32 CPU", false);
   if (FeatureBits[RISCV::Feature32Bit] &&
       FeatureBits[RISCV::Feature64Bit])
-    report_fatal_error("RV32 and RV64 can't be combined");
+    report_fatal_error("RV32 and RV64 can't be combined", false);
 }
 
 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
 parseFeatureBits(bool IsRV64, const FeatureBitset &FeatureBits) {
   unsigned XLen = IsRV64 ? 64 : 32;
   std::vector<std::string> FeatureVector;
   // Convert FeatureBitset to FeatureVector.
   for (auto Feature : RISCVFeatureKV) {

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

 void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
   assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialized target ABI");
   TargetABI = ABI;
 }
 
 void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI,
                                                bool EmitStackAlign) {
   if (STI.hasFeature(RISCV::FeatureRVE))
-    report_fatal_error("Codegen not yet implemented for RVE");
+    report_fatal_error("Codegen not yet implemented for RVE", false);
 
   if (EmitStackAlign)
     emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
 
   auto ParseResult = RISCVFeatures::parseFeatureBits(
       STI.hasFeature(RISCV::Feature64Bit), STI.getFeatureBits());
   if (!ParseResult) {
-    report_fatal_error(ParseResult.takeError());
+    report_fatal_error(ParseResult.takeError(), false);
   } else {
     auto &ISAInfo = *ParseResult;
     emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());
   }
 }
 
 // This part is for ascii assembly output
 RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

 void RISCVAsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
   Register Reg = MI.getOperand(0).getReg();
   uint32_t AccessInfo = MI.getOperand(1).getImm();
   MCSymbol *&Sym =
       HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, AccessInfo)];
   if (!Sym) {
     // FIXME: Make this work on non-ELF.
     if (!TM.getTargetTriple().isOSBinFormatELF())
-      report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF");
+      report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF",
+                         false);
 
     std::string SymName = "__hwasan_check_x" + utostr(Reg - RISCV::X0) + "_" +
                           utostr(AccessInfo) + "_short";
     Sym = OutContext.getOrCreateSymbol(SymName);
   }
   auto Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, OutContext);
   auto Expr = RISCVMCExpr::create(Res, RISCVMCExpr::VK_RISCV_CALL, OutContext);
 

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, bool IsMasked,
 
   assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
          "Element count mismatch");
 
   RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
   unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
   if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
     report_fatal_error("The V extension does not support EEW=64 for index "
-                       "values when XLEN=32");
+                       "values when XLEN=32",
+                       false);
   }
   const RISCV::VLXSEGPseudo *P = RISCV::getVLXSEGPseudo(
       NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL),
       static_cast<unsigned>(IndexLMUL));
   MachineSDNode *Load =
       CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other, Operands);
 
   if (auto *MemOp = dyn_cast<MemSDNode>(Node))
void RISCVDAGToDAGISel::selectVSXSEG(SDNode *Node, bool IsMasked,
 
   assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
          "Element count mismatch");
 
   RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
   unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
   if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
     report_fatal_error("The V extension does not support EEW=64 for index "
-                       "values when XLEN=32");
+                       "values when XLEN=32",
+                       false);
   }
   const RISCV::VSXSEGPseudo *P = RISCV::getVSXSEGPseudo(
       NF, IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL),
       static_cast<unsigned>(IndexLMUL));
   MachineSDNode *Store =
       CurDAG->getMachineNode(P->Pseudo, DL, Node->getValueType(0), Operands);
 
   if (auto *MemOp = dyn_cast<MemSDNode>(Node))
case Intrinsic::riscv_vluxei_mask: {
       assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
              "Element count mismatch");
 
       RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
       RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
       unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
       if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
         report_fatal_error("The V extension does not support EEW=64 for index "
-                           "values when XLEN=32");
+                           "values when XLEN=32",
+                           false);
       }
       const RISCV::VLX_VSXPseudo *P = RISCV::getVLXPseudo(
           IsMasked, IsOrdered, IndexLog2EEW, static_cast<unsigned>(LMUL),
           static_cast<unsigned>(IndexLMUL));
       MachineSDNode *Load =
           CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands);
 
       if (auto *MemOp = dyn_cast<MemSDNode>(Node))
case Intrinsic::riscv_vsuxei_mask: {
       assert(VT.getVectorElementCount() == IndexVT.getVectorElementCount() &&
              "Element count mismatch");
 
       RISCVII::VLMUL LMUL = RISCVTargetLowering::getLMUL(VT);
       RISCVII::VLMUL IndexLMUL = RISCVTargetLowering::getLMUL(IndexVT);
       unsigned IndexLog2EEW = Log2_32(IndexVT.getScalarSizeInBits());
       if (IndexLog2EEW == 6 && !Subtarget->is64Bit()) {
         report_fatal_error("The V extension does not support EEW=64 for index "
-                           "values when XLEN=32");
+                           "values when XLEN=32",
+                           false);
       }
       const RISCV::VLX_VSXPseudo *P = RISCV::getVSXPseudo(
           IsMasked, IsOrdered, IndexLog2EEW,
           static_cast<unsigned>(LMUL), static_cast<unsigned>(IndexLMUL));
       MachineSDNode *Store =
           CurDAG->getMachineNode(P->Pseudo, DL, Node->getVTList(), Operands);
 
       if (auto *MemOp = dyn_cast<MemSDNode>(Node))

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

FPImmCost(DEBUG_TYPE "-fpimm-cost", cl::Hidden,
                        "use for creating a floating-point immediate value"),
               cl::init(2));
 
 RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
                                          const RISCVSubtarget &STI)
     : TargetLowering(TM), Subtarget(STI) {
 
   if (Subtarget.isRVE())
-    report_fatal_error("Codegen not yet implemented for RVE");
+    report_fatal_error("Codegen not yet implemented for RVE", false);
 
   RISCVABI::ABI ABI = Subtarget.getTargetABI();
   assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
 
   if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) &&
       !Subtarget.hasStdExtF()) {
     errs() << "Hard-float 'f' ABI can't be used for a target that "
                 "doesn't support the F instruction set extension (ignoring "
case ISD::VSCALE: {
     MVT VT = Op.getSimpleValueType();
     SDLoc DL(Op);
     SDValue VLENB = DAG.getNode(RISCVISD::READ_VLENB, DL, VT);
     // We define our scalable vector types for lmul=1 to use a 64 bit known
     // minimum size. e.g. <vscale x 2 x i32>. VLENB is in bytes so we calculate
     // vscale as VLENB / 8.
     static_assert(RISCV::RVVBitsPerBlock == 64, "Unexpected bits per block!");
     if (Subtarget.getRealMinVLen() < RISCV::RVVBitsPerBlock)
-      report_fatal_error("Support for VLEN==32 is incomplete.");
+      report_fatal_error("Support for VLEN==32 is incomplete.", false);
     // We assume VLENB is a multiple of 8. We manually choose the best shift
     // here because SimplifyDemandedBits isn't always able to simplify it.
     uint64_t Val = Op.getConstantOperandVal(0);
     if (isPowerOf2_64(Val)) {
       uint64_t Log2 = Log2_64(Val);
       if (Log2 < 3)
         return DAG.getNode(ISD::SRL, DL, VT, VLENB,
                            DAG.getConstant(3 - Log2, DL, VT));
if (isPositionIndependent() || Subtarget.allowTaggedGlobals()) {
     SDValue Load =
         DAG.getMemIntrinsicNode(RISCVISD::LGA, DL, DAG.getVTList(Ty, MVT::Other),
                                 {DAG.getEntryNode(), Addr}, Ty, MemOp);
     return Load;
   }
 
   switch (getTargetMachine().getCodeModel()) {
   default:
-    report_fatal_error("Unsupported code model for lowering");
+    report_fatal_error("Unsupported code model for lowering", false);
   case CodeModel::Small: {
     // Generate a sequence for accessing addresses within the first 2 GiB of
     // address space. This generates the pattern (addi (lui %hi(sym)) %lo(sym)).
     SDValue AddrHi = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_HI);
     SDValue AddrLo = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_LO);
     SDValue MNHi = DAG.getNode(RISCVISD::HI, DL, Ty, AddrHi);
     return DAG.getNode(RISCVISD::ADD_LO, DL, Ty, MNHi, AddrLo);
   }
SDValue RISCVTargetLowering::lowerGlobalTLSAddress(SDValue Op,
 
   if (DAG.getTarget().useEmulatedTLS())
     return LowerToTLSEmulatedModel(N, DAG);
 
   TLSModel::Model Model = getTargetMachine().getTLSModel(N->getGlobal());
 
   if (DAG.getMachineFunction().getFunction().getCallingConv() ==
       CallingConv::GHC)
-    report_fatal_error("In GHC calling convention TLS is not supported");
+    report_fatal_error("In GHC calling convention TLS is not supported", false);
 
   SDValue Addr;
   switch (Model) {
   case TLSModel::LocalExec:
     Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/false);
     break;
   case TLSModel::InitialExec:
     Addr = getStaticTLSAddr(N, DAG, /*UseGOT=*/true);
bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
   return true; // CC didn't match.
 }
 
 bool RISCV::CC_RISCV_GHC(unsigned ValNo, MVT ValVT, MVT LocVT,
                          CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {
   if (ArgFlags.isNest()) {
     report_fatal_error(
-        "Attribute 'nest' is not supported in GHC calling convention");
+        "Attribute 'nest' is not supported in GHC calling convention", false);
   }
 
   static const MCPhysReg GPRList[] = {
       RISCV::X9,  RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22,
       RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27};
 
   if (LocVT == MVT::i32 || LocVT == MVT::i64) {
     // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, R7, SpLim
if ((LocVT == MVT::f32 && Subtarget.hasStdExtZfinx()) ||
       (LocVT == MVT::f64 && Subtarget.hasStdExtZdinx() &&
        Subtarget.is64Bit())) {
     if (unsigned Reg = State.AllocateReg(GPRList)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
     }
   }
 
-  report_fatal_error("No registers left in GHC calling convention");
+  report_fatal_error("No registers left in GHC calling convention", false);
   return true;
 }
 
 // Transform physical registers into virtual registers.
 SDValue RISCVTargetLowering::LowerFormalArguments(
     SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
 
   MachineFunction &MF = DAG.getMachineFunction();
 
   switch (CallConv) {
   default:
     report_fatal_error("Unsupported calling convention");
   case CallingConv::C:
   case CallingConv::Fast:
     break;
   case CallingConv::GHC:
     if (!Subtarget.hasStdExtFOrZfinx() || !Subtarget.hasStdExtDOrZdinx())
       report_fatal_error("GHC calling convention requires the (Zfinx/F) and "
-                         "(Zdinx/D) instruction set extensions");
+                         "(Zdinx/D) instruction set extensions",
+                         false);
   }
 
   const Function &Func = MF.getFunction();
   if (Func.hasFnAttribute("interrupt")) {
     if (!Func.arg_empty())
       report_fatal_error(
-        "Functions with the interrupt attribute cannot have arguments!");
+          "Functions with the interrupt attribute cannot have arguments!",
+          false);
 
     StringRef Kind =
       MF.getFunction().getFnAttribute("interrupt").getValueAsString();
 
     if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine"))
-      report_fatal_error(
-        "Function interrupt attribute argument not supported!");
+      report_fatal_error("Function interrupt attribute argument not supported!",
+                         false);
   }
 
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
   MVT XLenVT = Subtarget.getXLenVT();
   unsigned XLenInBytes = Subtarget.getXLen() / 8;
   // Used with vargs to acumulate store chains.
   std::vector<SDValue> OutChains;
 
SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
   // Check if it's really possible to do a tail call.
   if (IsTailCall)
     IsTailCall = isEligibleForTailCallOptimization(ArgCCInfo, CLI, MF, ArgLocs);
 
   if (IsTailCall)
     ++NumTailCalls;
   else if (CLI.CB && CLI.CB->isMustTailCall())
     report_fatal_error("failed to perform tail call elimination on a call "
-                       "site marked musttail");
+                       "site marked musttail",
+                       false);
 
   // Get a count of how many bytes are to be pushed on the stack.
   unsigned NumBytes = ArgCCInfo.getStackSize();
 
   // Create local copies for byval args
   SmallVector<SDValue, 8> ByValArgs;
   for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
     ISD::ArgFlagsTy Flags = Outs[i].Flags;
RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
   // Info about the registers and stack slot.
   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
                  *DAG.getContext());
 
   analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true,
                     nullptr, RISCV::CC_RISCV);
 
   if (CallConv == CallingConv::GHC && !RVLocs.empty())
-    report_fatal_error("GHC functions return void only");
+    report_fatal_error("GHC functions return void only", false);
 
   SDValue Glue;
   SmallVector<SDValue, 4> RetOps(1, Chain);
 
   // Copy the result values into the output registers.
   for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
     SDValue Val = OutVals[i];
     CCValAssign &VA = RVLocs[i];
if (any_of(RVLocs,
     MF.getInfo<RISCVMachineFunctionInfo>()->setIsVectorCall();
 
   unsigned RetOpc = RISCVISD::RET_GLUE;
   // Interrupt service routines use different return instructions.
   const Function &Func = DAG.getMachineFunction().getFunction();
   if (Func.hasFnAttribute("interrupt")) {
     if (!Func.getReturnType()->isVoidTy())
       report_fatal_error(
-          "Functions with the interrupt attribute must have void return type!");
+          "Functions with the interrupt attribute must have void return type!",
+          false);
 
     MachineFunction &MF = DAG.getMachineFunction();
     StringRef Kind =
       MF.getFunction().getFnAttribute("interrupt").getValueAsString();
 
     if (Kind == "supervisor")
       RetOpc = RISCVISD::SRET_GLUE;
     else

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

assert(ScalableValue % 8 == 0 &&
            "Scalable offset is not a multiple of a single vector size.");
     int64_t NumOfVReg = ScalableValue / 8;
     int64_t VLENB = ST.getRealMinVLen() / 8;
     Offset = StackOffset::getFixed(FixedValue + NumOfVReg * VLENB);
   }
 
   if (!isInt<32>(Offset.getFixed())) {
     report_fatal_error(
-        "Frame offsets outside of the signed 32-bit range not supported");
+        "Frame offsets outside of the signed 32-bit range not supported",
+        false);
   }
 
   if (!IsRVVSpill) {
     if (MI.getOpcode() == RISCV::ADDI && !isInt<12>(Offset.getFixed())) {
       // We chose to emit the canonical immediate sequence rather than folding
       // the offset into the using add under the theory that doing so doesn't
       // save dynamic instruction count and some target may fuse the canonical
       // 32 bit immediate sequence.  We still need to clear the portion of the

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
   assert(hasVInstructions() &&
          "Tried to get vector length without Zve or V extension support!");
 
   // ZvlLen specifies the minimum required vlen. The upper bound provided by
   // riscv-v-vector-bits-max should be no less than it.
   if (RVVVectorBitsMax != 0 && RVVVectorBitsMax < ZvlLen)
     report_fatal_error("riscv-v-vector-bits-max specified is lower "
-                       "than the Zvl*b limitation");
+                       "than the Zvl*b limitation",
+                       false);
 
   return RVVVectorBitsMax;
 }
 
 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
   assert(hasVInstructions() &&
          "Tried to get vector length without Zve or V extension support!");
 
   if (RVVVectorBitsMin == -1U)
     return ZvlLen;
 
   // ZvlLen specifies the minimum required vlen. The lower bound provided by
   // riscv-v-vector-bits-min should be no less than it.
   if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
     report_fatal_error("riscv-v-vector-bits-min specified is lower "
-                       "than the Zvl*b limitation");
+                       "than the Zvl*b limitation",
+                       false);
 
   return RVVVectorBitsMin;
 }
 
 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
   assert(hasVInstructions() &&
          "Tried to get vector length without Zve or V extension support!");
   assert(RVVVectorLMULMax <= 8 &&

llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
       TLOF(std::make_unique<RISCVELFTargetObjectFile>()) {
   initAsmInfo();
 
   // RISC-V supports the MachineOutliner.
   setMachineOutliner(true);
   setSupportsDefaultOutlining(true);
 
   if (TT.isOSFuchsia() && !TT.isArch64Bit())
-    report_fatal_error("Fuchsia is only supported for 64-bit");
+    report_fatal_error("Fuchsia is only supported for 64-bit", false);
 }
 
 const RISCVSubtarget *
 RISCVTargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
if (!I) {
     // function that reside in TargetOptions.
     resetTargetOptions(F);
     auto ABIName = Options.MCOptions.getABIName();
     if (const MDString *ModuleTargetABI = dyn_cast_or_null<MDString>(
             F.getParent()->getModuleFlag("target-abi"))) {
       auto TargetABI = RISCVABI::getTargetABI(ABIName);
       if (TargetABI != RISCVABI::ABI_Unknown &&
           ModuleTargetABI->getString() != ABIName) {
-        report_fatal_error("-target-abi option != target-abi module flag");
+        report_fatal_error("-target-abi option != target-abi module flag",
+                           false);
       }
       ABIName = ModuleTargetABI->getString();
     }
     I = std::make_unique<RISCVSubtarget>(
         TargetTriple, CPU, TuneCPU, FS, ABIName, RVVBitsMin, RVVBitsMax, *this);
   }
   return I.get();
 }