[M68k] Add new calling convention M68k_RTD

[myhsu]

Summary

M68k_RTD is really similar to X86's stdcall, in which callee pops the arguments from the stack. In LLVM IR it can be written as m68k_rtdcc.
This patch also improves how ExpandPseudo Pass handles popping stack at function returns in the absent of the RTD instruction.

[RKSimon]

llvm/lib/Target/M68k/M68kExpandPseudo.cpp

262

This comment seems to be for code that doesn't currently exist?

[myhsu]

Update code comments.

llvm/lib/Target/M68k/M68kExpandPseudo.cpp

262

you're right, I'll remove it (and maybe add it back when we have RTD).

[0x59616e]

llvm/lib/Target/M68k/M68kExpandPseudo.cpp

262

I don't see any issue in this comment. Doesn't it illustrate what #265 is doing ? Am I missing something ?

[myhsu]

llvm/lib/Target/M68k/M68kExpandPseudo.cpp

262

The original comment said that code in this block is the fallback implementation in the absent of RTD instruction. The comment only makes sense if we already have RTD and emit RTD in one of the code path here, which is not the case (yet).

[myhsu]

Introduce m68k_rtdcc the textual LLVM IR designation for M68k_RTD

[0x59616e]

llvm/lib/Target/M68k/M68kExpandPseudo.cpp

262

OhOh I saw the comment you were refering to (which is not the comment I'm thinking about). You are right. No question here ;)

[0x59616e]

llvm/include/llvm/AsmParser/LLToken.h

178

This is awesome. Thanks !

[0x59616e]

I didn't see any issue here. Let's wait for the approval from other (more senior) reviewers.

[jrtc27]

You need a test for calling a variadic function which, by my reading of GCC's manage and comparing it to X86, should be unaffected

llvm/test/CodeGen/M68k/CConv/rtd-call.ll

2

I don't know if the M68k backend tests do this as religiously as RISCV, but you should probably be using update_mir_test_checks.py for your MIR output tests.

llvm/test/CodeGen/M68k/CConv/rtd-ret.ll

7

nounwind?

[myhsu]

• Handle vararg calls and returns.
• Use update_mir_test_checks for MIR tests.

llvm/test/CodeGen/M68k/CConv/rtd-call.ll

2

Thanks, I didn't know there is a UTC for MIR.

[myhsu]

ping

[0x59616e]

I think we're good to go. Thanks !

llvm/include/llvm/AsmParser/LLToken.h

enum Kind {
   kw_amdgpu_gs,
   kw_amdgpu_ps,
   kw_amdgpu_cs,
   kw_amdgpu_cs_chain,
   kw_amdgpu_cs_chain_preserve,
   kw_amdgpu_kernel,
   kw_amdgpu_gfx,
   kw_tailcc,
+  kw_m68k_rtdcc,
 
   // Attributes:
   kw_attributes,
   kw_sync,
   kw_async,
 #define GET_ATTR_NAMES
 #define ATTRIBUTE_ENUM(ENUM_NAME, DISPLAY_NAME) \
   kw_##DISPLAY_NAME,

llvm/include/llvm/IR/CallingConv.h

enum {
     /// Used on AMDGPUs to give the middle-end more control over argument
     /// placement.
     AMDGPU_CS_Chain = 104,
 
     /// Used on AMDGPUs to give the middle-end more control over argument
     /// placement. Preserves active lane values for input VGPRs.
     AMDGPU_CS_ChainPreserve = 105,
 
+    /// Used for M68k rtd-based CC (similar to X86's stdcall).
+    M68k_RTD = 106,
+
     /// The highest possible ID. Must be some 2^k - 1.
     MaxID = 1023
   };
 
 } // end namespace CallingConv
 
 } // end namespace llvm
 
 #endif // LLVM_IR_CALLINGCONV_H

llvm/lib/AsmParser/LLLexer.cpp

#define KEYWORD(STR)                                                           \
   KEYWORD(amdgpu_gs);
   KEYWORD(amdgpu_ps);
   KEYWORD(amdgpu_cs);
   KEYWORD(amdgpu_cs_chain);
   KEYWORD(amdgpu_cs_chain_preserve);
   KEYWORD(amdgpu_kernel);
   KEYWORD(amdgpu_gfx);
   KEYWORD(tailcc);
+  KEYWORD(m68k_rtdcc);
 
   KEYWORD(cc);
   KEYWORD(c);
 
   KEYWORD(attributes);
   KEYWORD(sync);
   KEYWORD(async);
 

llvm/lib/AsmParser/LLParser.cpp

 ///   ::= 'amdgpu_es'
 ///   ::= 'amdgpu_gs'
 ///   ::= 'amdgpu_ps'
 ///   ::= 'amdgpu_cs'
 ///   ::= 'amdgpu_cs_chain'
 ///   ::= 'amdgpu_cs_chain_preserve'
 ///   ::= 'amdgpu_kernel'
 ///   ::= 'tailcc'
+///   ::= 'm68k_rtdcc'
 ///   ::= 'cc' UINT
 ///
 bool LLParser::parseOptionalCallingConv(unsigned &CC) {
   switch (Lex.getKind()) {
   default:                       CC = CallingConv::C; return false;
   case lltok::kw_ccc:            CC = CallingConv::C; break;
   case lltok::kw_fastcc:         CC = CallingConv::Fast; break;
   case lltok::kw_coldcc:         CC = CallingConv::Cold; break;
bool LLParser::parseOptionalCallingConv(unsigned &CC) {
   case lltok::kw_amdgpu_cs_chain:
     CC = CallingConv::AMDGPU_CS_Chain;
     break;
   case lltok::kw_amdgpu_cs_chain_preserve:
     CC = CallingConv::AMDGPU_CS_ChainPreserve;
     break;
   case lltok::kw_amdgpu_kernel:  CC = CallingConv::AMDGPU_KERNEL; break;
   case lltok::kw_tailcc:         CC = CallingConv::Tail; break;
+  case lltok::kw_m68k_rtdcc:     CC = CallingConv::M68k_RTD; break;
   case lltok::kw_cc: {
       Lex.Lex();
       return parseUInt32(CC);
     }
   }
 
   Lex.Lex();
   return false;

llvm/lib/IR/AsmWriter.cpp

static void PrintCallingConv(unsigned cc, raw_ostream &Out) {
   case CallingConv::AMDGPU_CS_Chain:
     Out << "amdgpu_cs_chain";
     break;
   case CallingConv::AMDGPU_CS_ChainPreserve:
     Out << "amdgpu_cs_chain_preserve";
     break;
   case CallingConv::AMDGPU_KERNEL: Out << "amdgpu_kernel"; break;
   case CallingConv::AMDGPU_Gfx:    Out << "amdgpu_gfx"; break;
+  case CallingConv::M68k_RTD:      Out << "m68k_rtdcc"; break;
   }
 }
 
 enum PrefixType {
   GlobalPrefix,
   ComdatPrefix,
   LabelPrefix,
   LocalPrefix,

llvm/lib/Target/M68k/M68kExpandPseudo.cpp

bool M68kExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
   }
   case M68k::RET: {
     // Adjust stack to erase error code
     int64_t StackAdj = MBBI->getOperand(0).getImm();
     MachineInstrBuilder MIB;
 
     if (StackAdj == 0) {
       MIB = BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
-    } else if (isUInt<16>(StackAdj)) {
-
-      if (STI->atLeastM68020()) {
-        llvm_unreachable("RTD is not implemented");
-      } else {
-        // Copy PC from stack to a free address(A0 or A1) register
-        // TODO check if pseudo expand uses free address register
-        BuildMI(MBB, MBBI, DL, TII->get(M68k::MOV32aj), M68k::A1)
-            .addReg(M68k::SP);
+      // Copy return address from stack to a free address(A0 or A1) register
 
-        // Adjust SP
-        FL->emitSPUpdate(MBB, MBBI, StackAdj, /*InEpilogue=*/true);
 
-        // Put the return address on stack
-        BuildMI(MBB, MBBI, DL, TII->get(M68k::MOV32ja))
-            .addReg(M68k::SP)
-            .addReg(M68k::A1);
 
-        // RTS
-        BuildMI(MBB, MBBI, DL, TII->get(M68k::RTS));
-      }
-    } else {
-      // TODO: RTD can only handle immediates as big as 2**16-1.
-      // If we need to pop off bytes before the return address, we
-      // must do it manually.
-      llvm_unreachable("Stack adjustment size not supported");
-    }
 
     // FIXME: Can rest of the operands be ignored, if there is any?
     MBB.erase(MBBI);
     return true;
   }
   }
   llvm_unreachable("Previous switch has a fallthrough?");
 }

llvm/lib/Target/M68k/M68kISelLowering.cpp

if (Constraint.size() == 1) {
     }
   }
 
   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
 }
 
 /// Determines whether the callee is required to pop its own arguments.
 /// Callee pop is necessary to support tail calls.
-bool M68k::isCalleePop(CallingConv::ID CallingConv, bool IsVarArg,
-                       bool GuaranteeTCO) {
-  return false;
+bool M68k::isCalleePop(CallingConv::ID CC, bool IsVarArg, bool GuaranteeTCO) {
+  return CC == CallingConv::M68k_RTD && !IsVarArg;
 }
 
 // Return true if it is OK for this CMOV pseudo-opcode to be cascaded
 // together with other CMOV pseudo-opcodes into a single basic-block with
 // conditional jump around it.
 static bool isCMOVPseudo(MachineInstr &MI) {
   switch (MI.getOpcode()) {
   case M68k::CMOV8d:

llvm/test/CodeGen/M68k/CConv/rtd-call.ll

+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=m68k %s -stop-after=finalize-isel -o - | FileCheck %s
+
+; We want to make sure caller doesn't pop the stack for callees using
+; the M68k_RTD CC. However, we've implemented some frame optimization
+; techniques to eliminate as many as frame setup/destroy instructions.
+; Therefore, to make test case small and concise, we check the MIR generated
+; after ISel instead.
+
+declare dso_local m68k_rtdcc void @callee(i32 noundef)
+declare dso_local m68k_rtdcc void @va_callee(i32 noundef, ...)
+
+define dso_local i32 @caller(ptr noundef %y) {
+  ; CHECK-LABEL: name: caller
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   [[MOV32rp:%[0-9]+]]:ar32 = MOV32rp 0, %fixed-stack.0, implicit-def dead $ccr :: (load (s32) from %fixed-stack.0, align 8)
+  ; CHECK-NEXT:   [[MOV32rj:%[0-9]+]]:xr32 = MOV32rj killed [[MOV32rp]], implicit-def dead $ccr :: (load (s32) from %ir.y)
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN 4, 0, implicit-def dead $sp, implicit-def dead $ccr, implicit $sp
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:ar32 = COPY $sp
+  ; CHECK-NEXT:   MOV32jr [[COPY]], [[MOV32rj]], implicit-def dead $ccr :: (store (s32) into stack, align 2)
+  ; CHECK-NEXT:   CALLb @callee, csr_std, implicit $sp, implicit-def $sp
+  ; CHECK-NEXT:   ADJCALLSTACKUP 4, 4, implicit-def dead $sp, implicit-def dead $ccr, implicit $sp
+  ; CHECK-NEXT:   $d0 = COPY [[MOV32rj]]
+  ; CHECK-NEXT:   RET 0, $d0
+entry:
+  %0 = load i32, ptr %y, align 4
+  call m68k_rtdcc void @callee(i32 noundef %0)
+  ret i32 %0
+}
+
+define dso_local i32 @va_caller(ptr noundef %y) {
+  ; CHECK-LABEL: name: va_caller
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   [[MOV32rp:%[0-9]+]]:ar32 = MOV32rp 0, %fixed-stack.0, implicit-def dead $ccr :: (load (s32) from %fixed-stack.0, align 8)
+  ; CHECK-NEXT:   [[MOV32rj:%[0-9]+]]:xr32 = MOV32rj killed [[MOV32rp]], implicit-def dead $ccr :: (load (s32) from %ir.y)
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN 4, 0, implicit-def dead $sp, implicit-def dead $ccr, implicit $sp
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:ar32 = COPY $sp
+  ; CHECK-NEXT:   MOV32jr [[COPY]], [[MOV32rj]], implicit-def dead $ccr :: (store (s32) into stack, align 2)
+  ; CHECK-NEXT:   CALLb @va_callee, csr_std, implicit $sp, implicit-def $sp
+  ; CHECK-NEXT:   ADJCALLSTACKUP 4, 0, implicit-def dead $sp, implicit-def dead $ccr, implicit $sp
+  ; CHECK-NEXT:   $d0 = COPY [[MOV32rj]]
+  ; CHECK-NEXT:   RET 0, $d0
+entry:
+  %0 = load i32, ptr %y, align 4
+  call m68k_rtdcc void (i32, ...) @va_callee(i32 noundef %0)
+  ret i32 %0
+}
+

llvm/test/CodeGen/M68k/CConv/rtd-ret.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=m68k < %s | FileCheck %s
+
+define dso_local m68k_rtdcc i32 @ret(i32 noundef %a, i32 noundef %b, i32 noundef %c) nounwind {
+; CHECK-LABEL: ret:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    move.l (8,%sp), %d0
+; CHECK-NEXT:    add.l (4,%sp), %d0
+; CHECK-NEXT:    add.l (12,%sp), %d0
+; CHECK-NEXT:    move.l (%sp), %a1
+; CHECK-NEXT:    adda.l #12, %sp
+; CHECK-NEXT:    move.l %a1, (%sp)
+; CHECK-NEXT:    rts
+entry:
+  %add = add nsw i32 %b, %a
+  %add1 = add nsw i32 %add, %c
+  ret i32 %add1
+}
+
+define dso_local m68k_rtdcc i32 @va_ret(i32 noundef %a, i32 noundef %b, i32 noundef %c, ...) nounwind {
+; CHECK-LABEL: va_ret:
+; CHECK:       ; %bb.0: ; %entry
+; CHECK-NEXT:    move.l (8,%sp), %d0
+; CHECK-NEXT:    add.l (4,%sp), %d0
+; CHECK-NEXT:    add.l (12,%sp), %d0
+; CHECK-NEXT:    rts
+entry:
+  %add = add nsw i32 %b, %a
+  %add1 = add nsw i32 %add, %c
+  ret i32 %add1
+}