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0x59616e (Sheng)
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User Since
Nov 15 2021, 11:20 PM (71 w, 2 d)

Recent Activity

Mon, Mar 27

0x59616e updated the diff for D144941: [m68k] Add TLS Support.

address feedbacks

Mon, Mar 27, 12:43 AM · Restricted Project, Restricted Project

Sun, Mar 26

0x59616e abandoned D146896: [M68k] Enable returning pointer in address register..

I was confused with the absence of some of my fix in the test after rebasing to master. It turns out that this has been done by Min.

Sun, Mar 26, 11:46 PM · Restricted Project, Restricted Project
0x59616e updated the diff for D146896: [M68k] Enable returning pointer in address register..
Sun, Mar 26, 11:40 PM · Restricted Project, Restricted Project
0x59616e updated the diff for D146896: [M68k] Enable returning pointer in address register..

update diff

Sun, Mar 26, 10:57 PM · Restricted Project, Restricted Project

Sat, Mar 25

0x59616e planned changes to D146896: [M68k] Enable returning pointer in address register..
Sat, Mar 25, 8:25 PM · Restricted Project, Restricted Project
0x59616e updated the diff for D146896: [M68k] Enable returning pointer in address register..

remove comments

Sat, Mar 25, 8:19 PM · Restricted Project, Restricted Project
0x59616e requested review of D146896: [M68k] Enable returning pointer in address register..
Sat, Mar 25, 8:16 PM · Restricted Project, Restricted Project

Thu, Mar 23

0x59616e added a comment to D143315: [m68k] Implement BSR Instruction.

Sorry for holding this for so long. I will come back next week since we have a a 5-day holiday in Taiwan.

Thu, Mar 23, 10:02 PM · Restricted Project, Restricted Project
0x59616e added a comment to D144941: [m68k] Add TLS Support.
Thu, Mar 23, 10:02 PM · Restricted Project, Restricted Project

Wed, Mar 1

0x59616e added inline comments to D144941: [m68k] Add TLS Support.
Wed, Mar 1, 7:15 AM · Restricted Project, Restricted Project
0x59616e added inline comments to D144941: [m68k] Add TLS Support.
Wed, Mar 1, 7:13 AM · Restricted Project, Restricted Project
0x59616e updated the diff for D144941: [m68k] Add TLS Support.

Add some comments

Wed, Mar 1, 5:05 AM · Restricted Project, Restricted Project

Tue, Feb 28

0x59616e planned changes to D144941: [m68k] Add TLS Support.

A few minor adjustments are required.

Tue, Feb 28, 9:39 PM · Restricted Project, Restricted Project
0x59616e accepted D143529: [M68k] Add support for basic memory constraints in inline asm.

Shoot. I mixed it up with my own one. I'm sorry.

Tue, Feb 28, 9:39 PM · Restricted Project, Restricted Project, Restricted Project

Feb 28 2023

0x59616e requested changes to D143529: [M68k] Add support for basic memory constraints in inline asm.

A few minor adjustments are required.

Feb 28 2023, 7:24 PM · Restricted Project, Restricted Project, Restricted Project
0x59616e updated the summary of D144941: [m68k] Add TLS Support.
Feb 28 2023, 4:05 PM · Restricted Project, Restricted Project
0x59616e accepted D143528: [M68k] Factoring out memory operand printer into a separate file.

LGTM. Thanks

Feb 28 2023, 3:23 AM · Restricted Project, Restricted Project

Feb 27 2023

0x59616e requested review of D144941: [m68k] Add TLS Support.
Feb 27 2023, 9:21 PM · Restricted Project, Restricted Project

Feb 16 2023

0x59616e abandoned D143317: [m68k] Add TLS support.
Feb 16 2023, 4:00 AM · Restricted Project, Restricted Project

Feb 15 2023

0x59616e updated the diff for D143317: [m68k] Add TLS support.

The access model type is disambiguated at ISelLowering, but it still needs to be expanded in AsmPrinter. I am uncertain how to express the Global Offset Table in MachineInstr.

Feb 15 2023, 5:04 PM · Restricted Project, Restricted Project

Feb 14 2023

0x59616e updated the diff for D143315: [m68k] Implement BSR Instruction.

Add disassembler test

Feb 14 2023, 4:43 AM · Restricted Project, Restricted Project
0x59616e updated the diff for D143316: [m68k] Implement absolution long addressing mode for ADDA instruction.
  • Add disassembler test
  • Move assembler test into MxBiArOp_RFRM.s
Feb 14 2023, 4:33 AM · Restricted Project, Restricted Project

Feb 5 2023

0x59616e planned changes to D143317: [m68k] Add TLS support.

Plan to update the code per the advice received

Feb 5 2023, 11:15 PM · Restricted Project, Restricted Project
0x59616e added a comment to D143317: [m68k] Add TLS support.

Doesn't seem to build at the moment:

Feb 5 2023, 2:45 AM · Restricted Project, Restricted Project

Feb 4 2023

0x59616e updated the summary of D143317: [m68k] Add TLS support.
Feb 4 2023, 6:08 PM · Restricted Project, Restricted Project
0x59616e updated the summary of D143317: [m68k] Add TLS support.
Feb 4 2023, 6:05 PM · Restricted Project, Restricted Project
0x59616e requested review of D143317: [m68k] Add TLS support.
Feb 4 2023, 4:06 AM · Restricted Project, Restricted Project
0x59616e requested review of D143316: [m68k] Implement absolution long addressing mode for ADDA instruction.
Feb 4 2023, 4:01 AM · Restricted Project, Restricted Project
0x59616e requested review of D143315: [m68k] Implement BSR Instruction.
Feb 4 2023, 3:58 AM · Restricted Project, Restricted Project

Jan 24 2023

0x59616e accepted D142079: [TableGen] Support custom decoders for variable length instructions.

LGTM. Thanks for this amazing work ;)

Jan 24 2023, 6:24 AM · Restricted Project, Restricted Project

Jan 19 2023

0x59616e abandoned D135947: [NFC][lit] Fix typo.
Jan 19 2023, 8:32 PM · Restricted Project, Restricted Project
0x59616e accepted D137902: [M68k][MC] Make immediate operands relocatable.

This amazing work LGTM. Thanks !

Jan 19 2023, 8:30 PM · Restricted Project, Restricted Project
0x59616e added inline comments to D142079: [TableGen] Support custom decoders for variable length instructions.
Jan 19 2023, 8:20 PM · Restricted Project, Restricted Project
0x59616e added inline comments to D142079: [TableGen] Support custom decoders for variable length instructions.
Jan 19 2023, 8:12 PM · Restricted Project, Restricted Project
0x59616e added inline comments to D142079: [TableGen] Support custom decoders for variable length instructions.
Jan 19 2023, 8:05 PM · Restricted Project, Restricted Project

Dec 29 2022

0x59616e accepted D140695: [M68k] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros.

The CI seems OK. My first LGTM is given to you.

Dec 29 2022, 1:04 AM · Restricted Project, Restricted Project

Dec 27 2022

0x59616e added a comment to D140695: [M68k] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros.

Also, could you add "Fixes #58974" in the commit message so that the item will be closed automatically upon commiting ? Thanks

Dec 27 2022, 9:52 PM · Restricted Project, Restricted Project
0x59616e added a comment to D140695: [M68k] Define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros.

FYI the pre-merge checks seem to have some issues. Here is the output:

Command Output (stderr):
--
/var/lib/buildkite-agent/builds/llvm-project/clang/test/Preprocessor/predefined-arch-macros.c:4322:28: error: CHECK_M68K_GCC_ATOMICS: expected string not found in input
// CHECK_M68K_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
                           ^
<stdin>:1:1: note: scanning from here
#define _ILP32 1
^
<stdin>:62:1: note: possible intended match here
#define __GCC_ATOMIC_CHAR_LOCK_FREE 1
^
Dec 27 2022, 9:45 PM · Restricted Project, Restricted Project

Nov 23 2022

0x59616e added a comment to D138323: [TableGen] RegisterInfo backend - Add abstraction layer between code generation logic and syntax output.

I like your idea, but I'm not a big fan of the code structure. It seems that we have to add a plethora of virtual functions for every backend in a single PrinterInterface class ? Wouldn't this break the 'open-close principle' and 'Interface segregation principle' ?

Nov 23 2022, 5:58 PM · Restricted Project, Restricted Project

Nov 9 2022

0x59616e committed rGe086b24d1530: [M68k] Add support for atomic instructions (authored by 0x59616e).
[M68k] Add support for atomic instructions
Nov 9 2022, 2:39 AM · Restricted Project, Restricted Project
0x59616e closed D136525: [M68k] Add codegen pattern for atomic load / store.
Nov 9 2022, 2:38 AM · Restricted Project, Restricted Project
0x59616e committed rGc7d6a0f6bfff: [M68k] Replace `IsM680x0` with predicates `AtLeastM680x0` (authored by 0x59616e).
[M68k] Replace `IsM680x0` with predicates `AtLeastM680x0`
Nov 9 2022, 2:32 AM · Restricted Project, Restricted Project
0x59616e closed D137425: [M68k] Add predicates `AtLeastM680x0`.
Nov 9 2022, 2:32 AM · Restricted Project, Restricted Project
0x59616e added a comment to D136525: [M68k] Add codegen pattern for atomic load / store.

Thanks a lot for all of your benign help ;)

Nov 9 2022, 2:28 AM · Restricted Project, Restricted Project
0x59616e added a comment to D137425: [M68k] Add predicates `AtLeastM680x0`.

Thanks a lot ;)

Nov 9 2022, 2:23 AM · Restricted Project, Restricted Project

Nov 8 2022

0x59616e updated the diff for D136525: [M68k] Add codegen pattern for atomic load / store.

update diff:

  • Expand atomic-rmw to atomic-compare-and-swap on target >= M68020
  • address feedbacks
Nov 8 2022, 12:24 AM · Restricted Project, Restricted Project
0x59616e updated the diff for D137425: [M68k] Add predicates `AtLeastM680x0`.

Replace IsM680x0 with AtLeastM680x0

Nov 8 2022, 12:22 AM · Restricted Project, Restricted Project

Nov 6 2022

0x59616e added inline comments to D136525: [M68k] Add codegen pattern for atomic load / store.
Nov 6 2022, 11:19 PM · Restricted Project, Restricted Project

Nov 4 2022

0x59616e added inline comments to D136525: [M68k] Add codegen pattern for atomic load / store.
Nov 4 2022, 7:34 AM · Restricted Project, Restricted Project
0x59616e requested review of D137425: [M68k] Add predicates `AtLeastM680x0`.
Nov 4 2022, 7:32 AM · Restricted Project, Restricted Project
0x59616e updated the diff for D136525: [M68k] Add codegen pattern for atomic load / store.

update diff:

  • We transform all atomic instruction to __atomic_* for sizes > 32
  • Otherwise, lower to either native instruction or __sync_* function call.
Nov 4 2022, 7:29 AM · Restricted Project, Restricted Project

Nov 2 2022

0x59616e added a comment to D136525: [M68k] Add codegen pattern for atomic load / store.

Thanks for all of your edifying comments. The path is getting clearer. Here is my understanding. Correct me if I'm wrong.

Nov 2 2022, 2:21 AM · Restricted Project, Restricted Project

Nov 1 2022

0x59616e added a comment to D136525: [M68k] Add codegen pattern for atomic load / store.

one more question :

Nov 1 2022, 6:56 PM · Restricted Project, Restricted Project
0x59616e added a comment to D136525: [M68k] Add codegen pattern for atomic load / store.

The atomic width is never a property of a specific instruction. Either *all* atomic ops of a given width are lock-free, or *all* atomic ops of a given width need to be transformed into __atomic_* libcalls.

Nov 1 2022, 6:43 PM · Restricted Project, Restricted Project
0x59616e added inline comments to D136525: [M68k] Add codegen pattern for atomic load / store.
Nov 1 2022, 9:11 AM · Restricted Project, Restricted Project
0x59616e added inline comments to D136525: [M68k] Add codegen pattern for atomic load / store.
Nov 1 2022, 8:52 AM · Restricted Project, Restricted Project
0x59616e added inline comments to D136525: [M68k] Add codegen pattern for atomic load / store.
Nov 1 2022, 8:33 AM · Restricted Project, Restricted Project
0x59616e added inline comments to D136525: [M68k] Add codegen pattern for atomic load / store.
Nov 1 2022, 5:46 AM · Restricted Project, Restricted Project
0x59616e added inline comments to D136525: [M68k] Add codegen pattern for atomic load / store.
Nov 1 2022, 5:44 AM · Restricted Project, Restricted Project
0x59616e added inline comments to D136525: [M68k] Add codegen pattern for atomic load / store.
Nov 1 2022, 5:37 AM · Restricted Project, Restricted Project

Oct 31 2022

0x59616e added inline comments to D136525: [M68k] Add codegen pattern for atomic load / store.
Oct 31 2022, 3:22 AM · Restricted Project, Restricted Project
0x59616e updated the diff for D136525: [M68k] Add codegen pattern for atomic load / store.

address feedbacks

Oct 31 2022, 3:22 AM · Restricted Project, Restricted Project

Oct 30 2022

0x59616e added inline comments to D136525: [M68k] Add codegen pattern for atomic load / store.
Oct 30 2022, 6:13 PM · Restricted Project, Restricted Project
0x59616e updated the diff for D136525: [M68k] Add codegen pattern for atomic load / store.

address feedbacks

Oct 30 2022, 6:13 PM · Restricted Project, Restricted Project
0x59616e committed rGdbfa4a0aa561: [NFC][m68k] Add pipeline.ll (authored by 0x59616e).
[NFC][m68k] Add pipeline.ll
Oct 30 2022, 5:53 PM · Restricted Project, Restricted Project

Oct 28 2022

0x59616e updated the diff for D136525: [M68k] Add codegen pattern for atomic load / store.

Add pipeline.ll

Oct 28 2022, 10:35 PM · Restricted Project, Restricted Project
0x59616e updated the diff for D136525: [M68k] Add codegen pattern for atomic load / store.

Add support for atomicrmw and cmpxchg

Oct 28 2022, 10:31 PM · Restricted Project, Restricted Project

Oct 27 2022

0x59616e added inline comments to D136525: [M68k] Add codegen pattern for atomic load / store.
Oct 27 2022, 4:34 AM · Restricted Project, Restricted Project
0x59616e added a comment to D136525: [M68k] Add codegen pattern for atomic load / store.

I dig into the libatomic.a, here is part of the result:

00000000 <__atomic_store_4>:
   0:   206f 0004       moveal %sp@(4),%a0
   4:   20af 0008       movel %sp@(8),%a0@
   8:   4e75            rts
Oct 27 2022, 4:18 AM · Restricted Project, Restricted Project
0x59616e added a comment to D136808: Refactor Tblgen DecoderEmitter to allow multiple language output.

Thanks for this patch !

Oct 27 2022, 3:51 AM · Restricted Project, Restricted Project

Oct 26 2022

0x59616e added reviewers for D136808: Refactor Tblgen DecoderEmitter to allow multiple language output: craig.topper, myhsu.
Oct 26 2022, 11:59 PM · Restricted Project, Restricted Project

Oct 25 2022

0x59616e added a comment to D136525: [M68k] Add codegen pattern for atomic load / store.

Are multi-processor m68k computers a thing? I can't find any reference to such a thing existing, but the manual indicates that the processor was designed to allow it. If it does exist, m68k probably needs to use sequences similar to x86. (x86 didn't have any barrier instruction for a long time, but a "lock" instruction has the right semantics.)

Take my word with a pinch of salt

Oct 25 2022, 4:56 AM · Restricted Project, Restricted Project

Oct 23 2022

0x59616e committed rGfb937c49135e: [NFC][X86] Fix typo: stric => strict (authored by 0x59616e).
[NFC][X86] Fix typo: stric => strict
Oct 23 2022, 9:57 PM · Restricted Project, Restricted Project
0x59616e committed rG9cedab654d58: [NFC][M68k] Update the status of ISA implementation (authored by 0x59616e).
[NFC][M68k] Update the status of ISA implementation
Oct 23 2022, 6:38 PM · Restricted Project, Restricted Project
0x59616e planned changes to D136525: [M68k] Add codegen pattern for atomic load / store.

Embark on the CAS/RMW instruction.

Oct 23 2022, 6:07 PM · Restricted Project, Restricted Project
0x59616e added a comment to D136525: [M68k] Add codegen pattern for atomic load / store.

Preferably this should also include the implementation for atomic RMW/CAS instructions to prove that this lowering is legal. If native or at least kernel-supported CAS is not available, then atomic load/store needs to use libatomic (possibly subtarget dependent).

It would also be good to include relevant quotes from the ISA manual -- atomicity of load/store is usually a given, but do they also guarantee a seq_cst ordering without a memory barrier?

(Disclaimer: I'm not familiar with m68k, just covering the usual atomic lowering legality questions.)

Oct 23 2022, 6:07 PM · Restricted Project, Restricted Project

Oct 22 2022

0x59616e updated the diff for D136525: [M68k] Add codegen pattern for atomic load / store.
Oct 22 2022, 7:42 PM · Restricted Project, Restricted Project
0x59616e requested review of D136525: [M68k] Add codegen pattern for atomic load / store.
Oct 22 2022, 5:56 AM · Restricted Project, Restricted Project

Oct 21 2022

0x59616e added inline comments to D129531: [clang][C++20] P0960R3 and P1975R0: Allow initializing aggregates from a parenthesized list of values.
Oct 21 2022, 1:59 AM · Restricted Project, Restricted Project

Oct 20 2022

0x59616e added a comment to D129531: [clang][C++20] P0960R3 and P1975R0: Allow initializing aggregates from a parenthesized list of values.

I can only nitpick some of the peripheral issues since I have no knowledge in most of the part of clang. Perhaps implementing the new standard feature is too arduous for a tyro like me. It's great to see the real expert to complete this.

Oct 20 2022, 7:00 PM · Restricted Project, Restricted Project

Oct 17 2022

0x59616e committed rG6dcd15aed121: [NFC][mlir] Remove redundant wording (authored by 0x59616e).
[NFC][mlir] Remove redundant wording
Oct 17 2022, 10:19 PM · Restricted Project, Restricted Project

Oct 14 2022

0x59616e requested review of D135947: [NFC][lit] Fix typo.
Oct 14 2022, 12:48 AM · Restricted Project, Restricted Project

Oct 13 2022

0x59616e committed rG62fc58a61d15: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases (authored by 0x59616e).
[AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases
Oct 13 2022, 4:09 AM · Restricted Project, Restricted Project
0x59616e closed D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.
Oct 13 2022, 4:09 AM · Restricted Project, Restricted Project

Oct 12 2022

0x59616e added a comment to D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.

Thanks for all of your kindly help ;)

Oct 12 2022, 10:50 PM · Restricted Project, Restricted Project

Oct 11 2022

0x59616e added a comment to D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.

Hi, I realize D133280 is a diffbase from the 'stack' UI, and actually I never figured out how to send stack reviews over others' patches, so didn't know if a) or b) is a simpler procedure
a) for me to submit D133280 first b) you could just commit all changes reviewed in this patch.

Since this patch supersedes the test-only patch, I'm fine with a) or b), whichever makes the procedure simpler. Just let me know :)

Oct 11 2022, 6:08 PM · Restricted Project, Restricted Project
0x59616e added inline comments to D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.
Oct 11 2022, 6:01 PM · Restricted Project, Restricted Project
0x59616e updated the diff for D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.

Address friendly feedbacks

Oct 11 2022, 5:59 PM · Restricted Project, Restricted Project

Oct 10 2022

0x59616e updated the diff for D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.

Address friendly feedback and update all the affected tests

Oct 10 2022, 12:13 AM · Restricted Project, Restricted Project

Sep 30 2022

0x59616e added inline comments to D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.
Sep 30 2022, 8:11 PM · Restricted Project, Restricted Project
0x59616e updated the diff for D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.

Address kindly feedbacks. No major change in the core algorithm.

Sep 30 2022, 8:11 PM · Restricted Project, Restricted Project
0x59616e added a comment to D129531: [clang][C++20] P0960R3 and P1975R0: Allow initializing aggregates from a parenthesized list of values.

There's no update on my side.

Sep 30 2022, 6:22 PM · Restricted Project, Restricted Project

Sep 27 2022

0x59616e added a comment to D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.

bitcast is handled in this diff.

To handle bitcast, we need this observation: uzp1 is just a xtn that operates on two registers simultaneously.

For example, given the following register with type v2i64:

LSB______MSB

x0 x1x2 x3

Applying xtn on it we get:

x0x2

This is equivalent to bitcast it to v4i32, and then applying uzp1 on it:

x0x1x2x3

=== uzp1 ===>

x0x2<value from other register>

We can transform xtn to uzp1 by this observation, and vice versa.

This observation only works on little endian target. Big endian target has a problem: the uzp1 cannot be replaced by xtn since there is a discrepancy in the behavior of uzp1 between the little endian and big endian. To illustrate, take the following for example:

LSB________MSB

x0x1x2x3

On little endian, uzp1 grabs x0 and x2, which is right; on big endian, it grabs x3 and x1, which doesn't match what I saw on the document. But, since I'm new to AArch64, take my word with a pinch of salt. This bevavior is observed on gdb, maybe there's issue in the order of the value printed by it ?

Whatever the reason is, the execution result given by qemu just doesn't match. So I disable this on big endian target temporarily until we find the crux.

Take this with a grain of salt

My understanding is that, 'BITCAST' on little-endian works in this context since the element order and byte order is consistent that 'bitcast' won't change the relative order of bytes before and after the cast.

Use LLVM IR <2 x i64> as an example, we refer to element 0 as A0 and element 1 as A1, refer to the higher half (MSB) as A0H, and lower half as A0L

For little-endian,

  1. A0 is in lane 0 of the register and A1 is in lane1 of the register, with memory representation as
0x0 0x4  0x8  0xc
A0L A0H A1L A1H
  1. After bitcast <2 x i64> to <4 x i32> (which is a store followed by a load), the q0 register is still A0L A0H A1L A1H and LLVM IR <4 x i32> element 0 is A0L

For big-endian, the memory layout of <2 x i64> is

0x0 0x4 0x8 0xc
A0H A0L A1H A1L

So after a bitcast to <4 x i32>, q0 register becomes A0H A0L A1H A1L -> for LLVM IR <4 x i32>, element 0 is A0H -> this changes the shuffle result.

p.s. I use small functions like https://godbolt.org/z/63h9xja5e and https://gcc.godbolt.org/z/EsE3eWW71 to wrap my head around the mapping among {LLVM IR, register lanes, memory layout}.

Sep 27 2022, 8:17 PM · Restricted Project, Restricted Project
0x59616e added inline comments to D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.
Sep 27 2022, 8:13 PM · Restricted Project, Restricted Project
0x59616e added inline comments to D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.
Sep 27 2022, 8:12 PM · Restricted Project, Restricted Project
0x59616e updated the diff for D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.

Address kindly feedback.

Sep 27 2022, 8:12 PM · Restricted Project, Restricted Project

Sep 25 2022

0x59616e updated the diff for D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.

bitcast is handled in this diff.

Sep 25 2022, 3:44 PM · Restricted Project, Restricted Project

Sep 23 2022

0x59616e added a comment to D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.

I have no idea regarding how gdb decides to print it... but for the general issue, hopefully https://llvm.org/docs/BigEndianNEON.html helps?

Sep 23 2022, 3:57 AM · Restricted Project, Restricted Project

Sep 22 2022

0x59616e added a comment to D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.

I have a question : how does the SIMD instruction view the vector register in big endian mode ?

Sep 22 2022, 9:53 AM · Restricted Project, Restricted Project

Sep 19 2022

0x59616e planned changes to D133850: [AArch64] Improve codegen for "trunc <4 x i64> to <4 x i8>" for all cases.
Sep 19 2022, 5:02 PM · Restricted Project, Restricted Project