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Differential D146946

[RISCV][MC] Add support for experimental zicond extension
ClosedPublic

Authored by asb on Mar 27 2023, 4:32 AM.

Details

Reviewers
reames
craig.topper
Commits
rGd3291c692c0a: [RISCV][MC] Add support for the experimental zicond extension
Summary

This patch adds the basic MC layer support for Zicond, based on 1.0-rc1. As with other extensions, if there are additional changes between release candidates without incrementing the version number we won't be able to reflect that in the version number. I believe we've previously decided this is not a problem for extensions still considered experimental (i.e. not yet ratified).

Diff Detail

Event Timeline

asb created this revision.Mar 27 2023, 4:32 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 27 2023, 4:32 AM
Herald added subscribers: jobnoorman, luke, wingo and 31 others. · View Herald Transcript
asb requested review of this revision.Mar 27 2023, 4:32 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptMar 27 2023, 4:32 AM
Herald added subscribers: cfe-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
craig.topper accepted this revision.Mar 27 2023, 9:31 AM

LGTM

This revision is now accepted and ready to land.Mar 27 2023, 9:31 AM
Harbormaster completed remote builds in B221951: Diff 508572.Mar 27 2023, 8:09 PM
This revision was landed with ongoing or failed builds.Mar 29 2023, 4:18 AM
Closed by commit rGd3291c692c0a: [RISCV][MC] Add support for the experimental zicond extension (authored by asb). · Explain Why
This revision was automatically updated to reflect the committed changes.
asb added a commit: rGd3291c692c0a: [RISCV][MC] Add support for the experimental zicond extension.

Revision Contents

PathSize
clang/
test/
Preprocessor/
9 lines
llvm/
docs/
3 lines
2 lines
lib/
Support/
1 line
Target/
RISCV/
7 lines
1 line
25 lines
test/
CodeGen/
RISCV/
4 lines
MC/
RISCV/
3 lines
18 lines
18 lines

Diff 509299

clang/test/Preprocessor/riscv-target-features.c

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// CHECK-NOT: __riscv_zvkg {{.*$}} // CHECK-NOT: __riscv_zvkg {{.*$}}
// CHECK-NOT: __riscv_zvkn {{.*$}} // CHECK-NOT: __riscv_zvkn {{.*$}}
// CHECK-NOT: __riscv_zvknha {{.*$}} // CHECK-NOT: __riscv_zvknha {{.*$}}
// CHECK-NOT: __riscv_zvknhb {{.*$}} // CHECK-NOT: __riscv_zvknhb {{.*$}}
// CHECK-NOT: __riscv_zvkned {{.*$}} // CHECK-NOT: __riscv_zvkned {{.*$}}
// CHECK-NOT: __riscv_zvks {{.*$}} // CHECK-NOT: __riscv_zvks {{.*$}}
// CHECK-NOT: __riscv_zvksed {{.*$}} // CHECK-NOT: __riscv_zvksed {{.*$}}
// CHECK-NOT: __riscv_zvksh {{.*$}} // CHECK-NOT: __riscv_zvksh {{.*$}}
// CHECK-NOT: __riscv_zicond {{.*$}}
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \ // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32i -x c -E -dM %s \
// RUN: -o - | FileCheck %s // RUN: -o - | FileCheck %s
// RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \ // RUN: %clang -target riscv64-unknown-linux-gnu -march=rv64i -x c -E -dM %s \
// RUN: -o - | FileCheck %s // RUN: -o - | FileCheck %s
// CHECK: __riscv_i 2000000{{$}} // CHECK: __riscv_i 2000000{{$}}
// RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \ // RUN: %clang -target riscv32-unknown-linux-gnu -march=rv32im -x c -E -dM %s \
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// RUN: %clang -target riscv32 -menable-experimental-extensions \ // RUN: %clang -target riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zve32x_zvksh0p3 -x c -E -dM %s \ // RUN: -march=rv32i_zve32x_zvksh0p3 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \ // RUN: %clang -target riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_zve32x_zvksh0p3 -x c -E -dM %s \ // RUN: -march=rv64i_zve32x_zvksh0p3 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s // RUN: -o - | FileCheck --check-prefix=CHECK-ZVKSH-EXT %s
// CHECK-ZVKSH-EXT: __riscv_zvksh 3000{{$}} // CHECK-ZVKSH-EXT: __riscv_zvksh 3000{{$}}
// RUN: %clang -target riscv32 -menable-experimental-extensions \
// RUN: -march=rv32i_zicond1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
// RUN: %clang -target riscv64 -menable-experimental-extensions \
// RUN: -march=rv64i_zicond1p0 -x c -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICOND-EXT %s
// CHECK-ZICOND-EXT: __riscv_zicond 1000000{{$}}

llvm/docs/RISCVUsage.rst

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines``experimental-zcd``
LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`_. LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`_.
``experimental-zcf`` ``experimental-zcf``
LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`_. LLVM implements the `1.0.1 draft specification <https://github.com/riscv/riscv-code-size-reduction/releases/tag/v1.0.1>`_.
``experimental-zfa`` ``experimental-zfa``
LLVM implements a subset of `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf>`_ (see Chapter 25). Load-immediate instructions (fli.s/fli.d/fli.h) haven't been implemented yet. LLVM implements a subset of `0.1 draft specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf>`_ (see Chapter 25). Load-immediate instructions (fli.s/fli.d/fli.h) haven't been implemented yet.
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zicond/releases/tag/v1.0-rc1`>_.
``experimental-zihintntl`` ``experimental-zihintntl``
LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`_. LLVM implements the `0.2 draft specification <https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220831-bf5a151>`_.
``experimental-ztso`` ``experimental-ztso``
LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`_ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware. LLVM implements the `v0.1 proposed specification <https://github.com/riscv/riscv-isa-manual/releases/download/draft-20220723-10eea63/riscv-spec.pdf>`_ (see Chapter 25). The mapping from the C/C++ memory model to Ztso has not yet been ratified in any standards document. There are multiple possible mappings, and they are *not* mutually ABI compatible. The mapping LLVM implements is ABI compatible with the default WMO mapping. This mapping may change and there is *explicitly* no ABI stability offered while the extension remains in experimental status. User beware.
``experimental-zvfh`` ``experimental-zvfh``
LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`_. LLVM implements `this draft text <https://github.com/riscv/riscv-v-spec/pull/780>`_.
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llvm/docs/ReleaseNotes.rst

Show First 20 Lines • Show All 145 Lines • ▼ Show 20 Lines* Added support for the vendor-defined XTHeadMemPair (two-GPR memory operations)
extension disassembler/assembler. extension disassembler/assembler.
* Added support for the vendor-defined XTHeadMemIdx (indexed memory operations) * Added support for the vendor-defined XTHeadMemIdx (indexed memory operations)
extension disassembler/assembler. extension disassembler/assembler.
* Support for the now-ratified Zawrs extension is no longer experimental. * Support for the now-ratified Zawrs extension is no longer experimental.
* Adds support for the vendor-defined XTHeadCmo (cache management operations) extension. * Adds support for the vendor-defined XTHeadCmo (cache management operations) extension.
* Adds support for the vendor-defined XTHeadSync (multi-core synchronization instructions) extension. * Adds support for the vendor-defined XTHeadSync (multi-core synchronization instructions) extension.
* Added support for the vendor-defined XTHeadFMemIdx (indexed memory operations for floating point) extension. * Added support for the vendor-defined XTHeadFMemIdx (indexed memory operations for floating point) extension.
* Assembler support for RV64E was added. * Assembler support for RV64E was added.
* Assembler support was added for the experimental Zicond (integer conditional
operations) extension.
Changes to the WebAssembly Backend Changes to the WebAssembly Backend
---------------------------------- ----------------------------------
* ... * ...
Changes to the Windows Target Changes to the Windows Target
----------------------------- -----------------------------
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llvm/lib/Support/RISCVISAInfo.cpp

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static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zihintntl", RISCVExtensionVersion{0, 2}}, {"zihintntl", RISCVExtensionVersion{0, 2}},
{"zca", RISCVExtensionVersion{1, 0}}, {"zca", RISCVExtensionVersion{1, 0}},
{"zcb", RISCVExtensionVersion{1, 0}}, {"zcb", RISCVExtensionVersion{1, 0}},
{"zcd", RISCVExtensionVersion{1, 0}}, {"zcd", RISCVExtensionVersion{1, 0}},
{"zcf", RISCVExtensionVersion{1, 0}}, {"zcf", RISCVExtensionVersion{1, 0}},
{"zfa", RISCVExtensionVersion{0, 1}}, {"zfa", RISCVExtensionVersion{0, 1}},
{"zicond", RISCVExtensionVersion{1, 0}},
{"zvfh", RISCVExtensionVersion{0, 1}}, {"zvfh", RISCVExtensionVersion{0, 1}},
{"ztso", RISCVExtensionVersion{0, 1}}, {"ztso", RISCVExtensionVersion{0, 1}},
// vector crypto // vector crypto
{"zvkb", RISCVExtensionVersion{0, 3}}, {"zvkb", RISCVExtensionVersion{0, 3}},
{"zvkg", RISCVExtensionVersion{0, 3}}, {"zvkg", RISCVExtensionVersion{0, 3}},
{"zvkn", RISCVExtensionVersion{0, 3}}, {"zvkn", RISCVExtensionVersion{0, 3}},
{"zvknha", RISCVExtensionVersion{0, 3}}, {"zvknha", RISCVExtensionVersion{0, 3}},
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llvm/lib/Target/RISCV/RISCVFeatures.td

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def FeatureStdExtZvksh def FeatureStdExtZvksh
: SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true", : SubtargetFeature<"experimental-zvksh", "HasStdExtZvksh", "true",
"'Zvksh' (SM3 Hash Function Instructions.)">; "'Zvksh' (SM3 Hash Function Instructions.)">;
def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">, def HasStdExtZvksh : Predicate<"Subtarget->hasStdExtZvksh()">,
AssemblerPredicate<(all_of FeatureStdExtZvksh), AssemblerPredicate<(all_of FeatureStdExtZvksh),
"'Zvksh' (SM3 Hash Function Instructions.)">; "'Zvksh' (SM3 Hash Function Instructions.)">;
def FeatureStdExtZicond
: SubtargetFeature<"experimental-zicond", "HasStdExtZicond", "true",
"'Zicond' (Integer Conditional Operations)">;
def HasStdExtZicond : Predicate<"Subtarget->hasStdExtZicond()">,
AssemblerPredicate<(all_of FeatureStdExtZicond),
"'Zicond' (Integer Conditional Operations)">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Vendor extensions // Vendor extensions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def FeatureVendorXVentanaCondOps def FeatureVendorXVentanaCondOps
: SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true", : SubtargetFeature<"xventanacondops", "HasVendorXVentanaCondOps", "true",
"'XVentanaCondOps' (Ventana Conditional Ops)">; "'XVentanaCondOps' (Ventana Conditional Ops)">;
def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">, def HasVendorXVentanaCondOps : Predicate<"Subtarget->hasVendorXVentanaCondOps()">,
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llvm/lib/Target/RISCV/RISCVInstrInfo.td

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include "RISCVInstrInfoC.td" include "RISCVInstrInfoC.td"
include "RISCVInstrInfoZb.td" include "RISCVInstrInfoZb.td"
include "RISCVInstrInfoZc.td" include "RISCVInstrInfoZc.td"
include "RISCVInstrInfoZk.td" include "RISCVInstrInfoZk.td"
include "RISCVInstrInfoV.td" include "RISCVInstrInfoV.td"
include "RISCVInstrInfoZfa.td" include "RISCVInstrInfoZfa.td"
include "RISCVInstrInfoZfh.td" include "RISCVInstrInfoZfh.td"
include "RISCVInstrInfoZicbo.td" include "RISCVInstrInfoZicbo.td"
include "RISCVInstrInfoZicond.td"
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Vendor extensions // Vendor extensions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
include "RISCVInstrInfoXVentana.td" include "RISCVInstrInfoXVentana.td"
include "RISCVInstrInfoXTHead.td" include "RISCVInstrInfoXTHead.td"

llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td

  • This file was added.
//===-- RISCVInstrInfoZicond.td ----------------------------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file describes the RISC-V instructions from the standard Integer
// Conditional operations extension (Zicond).
// This version is still experimental as the 'Zicond' extension hasn't been
// ratified yet. It is based on v1.0-rc1 of the specification.
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtZicond] in {
def CZERO_EQZ : ALU_rr<0b0000111, 0b101, "czero.eqz">,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def CZERO_NEZ : ALU_rr<0b0000111, 0b111, "czero.nez">,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
} // Predicates = [HasStdExtZicond]

llvm/test/CodeGen/RISCV/attributes.ll

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; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV32ZVKG %s
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV32ZVKN %s ; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV32ZVKN %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV32ZVKNHA %s
; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s ; RUN: llc -mtriple=riscv32 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV32ZVKNHB %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV32ZVKNED %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV32ZVKNED %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s ; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s
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; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkg %s -o - | FileCheck --check-prefix=RV64ZVKG %s
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV64ZVKN %s ; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvkn %s -o - | FileCheck --check-prefix=RV64ZVKN %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvknha %s -o - | FileCheck --check-prefix=RV64ZVKNHA %s
; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s ; RUN: llc -mtriple=riscv64 -mattr=+zve64x -mattr=+experimental-zvknhb %s -o - | FileCheck --check-prefix=RV64ZVKNHB %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV64ZVKNED %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkned %s -o - | FileCheck --check-prefix=RV64ZVKNED %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
; CHECK: .attribute 4, 16 ; CHECK: .attribute 4, 16
; RV32M: .attribute 5, "rv32i2p0_m2p0" ; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0" ; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
; RV32MZMMUL: .attribute 5, "rv32i2p0_m2p0_zmmul1p0" ; RV32MZMMUL: .attribute 5, "rv32i2p0_m2p0_zmmul1p0"
; RV32A: .attribute 5, "rv32i2p0_a2p0" ; RV32A: .attribute 5, "rv32i2p0_a2p0"
; RV32F: .attribute 5, "rv32i2p0_f2p0" ; RV32F: .attribute 5, "rv32i2p0_f2p0"
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; RV32ZVKG: .attribute 5, "rv32i2p0_zve32x1p0_zvkg0p3_zvl32b1p0" ; RV32ZVKG: .attribute 5, "rv32i2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
; RV32ZVKN: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" ; RV32ZVKN: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
; RV32ZVKNHA: .attribute 5, "rv32i2p0_zve32x1p0_zvknha0p3_zvl32b1p0" ; RV32ZVKNHA: .attribute 5, "rv32i2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
; RV32ZVKNHB: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" ; RV32ZVKNHB: .attribute 5, "rv32i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
; RV32ZVKNED: .attribute 5, "rv32i2p0_zve32x1p0_zvkned0p3_zvl32b1p0" ; RV32ZVKNED: .attribute 5, "rv32i2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
; RV32ZVKS: .attribute 5, "rv32i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0" ; RV32ZVKS: .attribute 5, "rv32i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
; RV32ZVKSED: .attribute 5, "rv32i2p0_zve32x1p0_zvksed0p3_zvl32b1p0" ; RV32ZVKSED: .attribute 5, "rv32i2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
; RV32ZVKSH: .attribute 5, "rv32i2p0_zve32x1p0_zvksh0p3_zvl32b1p0" ; RV32ZVKSH: .attribute 5, "rv32i2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
; RV32ZICOND: .attribute 5, "rv32i2p0_zicond1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0" ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
; RV64MZMMUL: .attribute 5, "rv64i2p0_m2p0_zmmul1p0" ; RV64MZMMUL: .attribute 5, "rv64i2p0_m2p0_zmmul1p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0" ; RV64A: .attribute 5, "rv64i2p0_a2p0"
; RV64F: .attribute 5, "rv64i2p0_f2p0" ; RV64F: .attribute 5, "rv64i2p0_f2p0"
; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
; RV64C: .attribute 5, "rv64i2p0_c2p0" ; RV64C: .attribute 5, "rv64i2p0_c2p0"
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; RV64ZVKG: .attribute 5, "rv64i2p0_zve32x1p0_zvkg0p3_zvl32b1p0" ; RV64ZVKG: .attribute 5, "rv64i2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
; RV64ZVKN: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" ; RV64ZVKN: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
; RV64ZVKNHA: .attribute 5, "rv64i2p0_zve32x1p0_zvknha0p3_zvl32b1p0" ; RV64ZVKNHA: .attribute 5, "rv64i2p0_zve32x1p0_zvknha0p3_zvl32b1p0"
; RV64ZVKNHB: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0" ; RV64ZVKNHB: .attribute 5, "rv64i2p0_zve32x1p0_zve64x1p0_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
; RV64ZVKNED: .attribute 5, "rv64i2p0_zve32x1p0_zvkned0p3_zvl32b1p0" ; RV64ZVKNED: .attribute 5, "rv64i2p0_zve32x1p0_zvkned0p3_zvl32b1p0"
; RV64ZVKS: .attribute 5, "rv64i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0" ; RV64ZVKS: .attribute 5, "rv64i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
; RV64ZVKSED: .attribute 5, "rv64i2p0_zve32x1p0_zvksed0p3_zvl32b1p0" ; RV64ZVKSED: .attribute 5, "rv64i2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
; RV64ZVKSH: .attribute 5, "rv64i2p0_zve32x1p0_zvksh0p3_zvl32b1p0" ; RV64ZVKSH: .attribute 5, "rv64i2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
; RV64ZICOND: .attribute 5, "rv64i2p0_zicond1p0"
define i32 @addi(i32 %a) { define i32 @addi(i32 %a) {
%1 = add i32 %a, 1 %1 = add i32 %a, 1
ret i32 %1 ret i32 %1
} }

llvm/test/MC/RISCV/attribute-arch.s

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.attribute arch, "rv32izicsr2p0" .attribute arch, "rv32izicsr2p0"
# CHECK: attribute 5, "rv32i2p0_zicsr2p0" # CHECK: attribute 5, "rv32i2p0_zicsr2p0"
.attribute arch, "rv32izifencei2p0" .attribute arch, "rv32izifencei2p0"
# CHECK: attribute 5, "rv32i2p0_zifencei2p0" # CHECK: attribute 5, "rv32i2p0_zifencei2p0"
.attribute arch, "rv32izfa0p1" .attribute arch, "rv32izfa0p1"
# CHECK: attribute 5, "rv32i2p0_f2p0_zfa0p1" # CHECK: attribute 5, "rv32i2p0_f2p0_zfa0p1"
.attribute arch, "rv32izicond1p0"
# CHECK: attribute 5, "rv32i2p0_zicond1p0"

llvm/test/MC/RISCV/rv32zicond-invalid.s

  • This file was added.
# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
# Use of operand modifier on register name
czero.eqz t1, %lo(t2), t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
# Invalid register name
czero.nez a4, a3, foo # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
# Invalid operand type
czero.eqz t1, 2, t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
# Too many operands
czero.eqz t1, t2, t3, t4 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
czero.nez t1, t2, t3, 4 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
# Too few operands
czero.eqz t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction

llvm/test/MC/RISCV/rv32zicond-valid.s

  • This file was added.
# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicond -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicond -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicond < %s \
# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicond < %s \
# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
# CHECK-ASM-AND-OBJ: czero.eqz t0, a3, ra
# CHECK-ASM: encoding: [0xb3,0xd2,0x16,0x0e]
czero.eqz t0, a3, ra
# CHECK-ASM-AND-OBJ: czero.nez a1, gp, t6
# CHECK-ASM: encoding: [0xb3,0xf5,0xf1,0x0f]
czero.nez a1, gp, t6