[BOLT] Add minimal RISC-V 64-bit support

[jobnoorman]

Summary

Just enough features are implemented to process a simple "hello world"
executable and produce something that still runs (including libc calls).
This was mainly a matter of implementing support for various
relocations. Currently, the following are handled:

• R_RISCV_JAL
• R_RISCV_CALL
• R_RISCV_CALL_PLT
• R_RISCV_BRANCH
• R_RISCV_RVC_BRANCH
• R_RISCV_RVC_JUMP
• R_RISCV_GOT_HI20
• R_RISCV_PCREL_HI20
• R_RISCV_PCREL_LO12_I
• R_RISCV_RELAX
• R_RISCV_NONE

Note that in order to implement some of these relocations, this patch
relies on another patch for RuntimeDyld (D145686). However, it has been pointed
out in the past (D98560) that it might be better to switch to JITLink.
That change would be a lot more involved, though, so using RuntimeDyld
for the time being seems to be easiest way forward for getting RISC-V
support in BOLT.

Executables linked with linker relaxation will probably fail to be
processed. BOLT relocates .text to a high address while leaving .plt at
its original (low) address. This causes PC-relative PLT calls that were
relaxed to a JAL to not fit their offset in an I-immediate anymore. This
is something that will be addressed in a later patch.

Changes to the BOLT core are relatively minor. Two things were tricky to
implement and needed slightly larger changes. I'll explain those below.

The R_RISCV_CALL(_PLT) relocation is put on the first instruction of a
AUIPC/JALR pair, the second does not get any relocation (unlike other
PCREL pairs). This causes issues with the combinations of the way BOLT
processes binaries and the RISC-V MC-layer handles relocations:

• BOLT reassembles instructions one by one and since the JALR doesn't have a relocation, it simply gets copied without modification;
• Even though the MC-layer handles R_RISCV_CALL properly (adjusts both the AUIPC and the JALR), it assumes the immediates of both instructions are 0 (to be able to or-in a new value). This will most likely not be the case for the JALR that got copied over.

To handle this difficulty without resorting to RISC-V-specific hacks in
the BOLT core, a new binary pass was added that searches for
AUIPC/JALR pairs and zeroes-out the immediate of the JALR.

A second difficulty was supporting ABS symbols. As far as I can tell,
ABS symbols were not handled at all, causing __global_pointer$ to break.
RewriteInstance::analyzeRelocation was updated to handle these
generically.

Tests are provided for all supported relocations. Note that in order to
test the correct handling of PLT entries, an ELF file produced by GCC
had to be used. While I tried to strip the YAML representation, it's
still quite large. Any suggestions on how to improve this would be
appreciated.

[jobnoorman]

Fix failing test.

[yota9]

Thank you for this patch :)

bolt/lib/Rewrite/RewriteInstance.cpp

1480

Is it first PLT entry skipped? I don't think it is good idea to set constant size here in that case. Maybe it is possible to make more universal like it is done in aarch64? there are no PLT entry size assumptions too as I remember

2112

Please add || for aarch64 above

2636

We would need to check this code. Please provide more info about example of such symbols, sections it is contained/referenced in and segments.
Is there any chance that the problem might be solved by this commit https://github.com/llvm/llvm-project/commit/0776fc32b15dc76c6b43c41fc4471552833265de ?

3273

Probably better to move it to arch-specific pass like it is currently done in ADRRelaxationPass or VeneerElimination for example

[craig.topper]

bolt/include/bolt/Core/BinaryContext.h

730

Should this be isRISCV64()?

bolt/lib/Core/Relocation.cpp

505

What about PCREL_LO12_S?

bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp

40

Does this need to support c.nop?

254

This references R_RISCV_PCREL_LO12_S but nothing else in this patch does.

[jobnoorman]

Address some of the reviewer comments:

• Remove references to PCREL_LO12_S. It was only partially implemented so I'll keep the full implementation for a later patch;
• Collapse two separate ifs in one;
• Invoke call-fixing code from binary pass;
• Detect c.nop in isNoop()

[jobnoorman]

bolt/include/bolt/Core/BinaryContext.h

730

This would technically be more correct at the moment. However, I don't think anything in this patch is actually RV64 specific. The only reason we cannot currently handle RV32 is that BOLT rejects ELF32 files. Once that's fixed, I believe this patch could also handle RV32. For this reason, I would propose to keep the current naming. Would you agree?

bolt/lib/Core/Relocation.cpp

505

I will leave the implementation of PCREL_LO12_S to a future patch.

bolt/lib/Rewrite/RewriteInstance.cpp

1480

It's not really the first entry that's skipped, but a special entry at the beginning of the PLT section. The riscv psabi defines the layout of the PLT section:

• First 32 bytes: a special entry that calls _dl_runtime_resolve to resolve GOT entries. Initially, all GOT entries point here.
• Then, 16 bytes per "normal" PLT entry.

So since the sizes of these entries are standardized, I think it's OK to keep the as constants here. Would you agree?

2636

The symbol looks like this:

Num:    Value          Size Type    Bind   Vis      Ndx Name
 86: 0000000000002800     0 NOTYPE  GLOBAL DEFAULT  ABS __global_pointer$

It is used in RISC-V to initialize the gp register using a pair of R_RISCV_PCREL_HI20/R_RISCV_PCREL_LO12 relocations.

Since ABS symbols don't reference/belong to any section, I believe that commit doesn't solve the problem?

3273

I moved this to a separate pass but I left the implementation in a MCPlusBuilder method. I did this because trying to implement the logic directly in a pass is quite difficult because passes don't have access to a target's MC interface. I would have needed to add methods like isCallAuipc/isJalr to MCPlusBuilder which feels wrong since it's supposed to be a generic interface.

Would it be a good idea to allow targets to register their own passes (e.g., MCPlusBuilder::registerPasses()) so that they can be implemented in a target-specific subfolder and have access to their MC interface? This might allow us to remove some target-specific methods from MCPlusBuilder. If you agree with this idea, I could give it a shot.

bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp

40

It does, added!

254

Removed.

[rafauler]

Awesome!

bolt/lib/Core/BinaryContext.cpp

750–752

Why are we creating a new method to do the same thing as the above one?

bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp

297

BOLT's libTarget is designed in a way such that it doesn't know about BOLT's core data structures other than MCInst and the MCPlusBuilder class (see the other backend implementations). libBOLTCore depends on libBOLTTarget, but not vice-versa (except for the MCPlusBuilder base class itself, which is in BOLTCore).

So the way forward here would be to implement this loop over all instructions in the pass itself, and only call the target backend for specific target-specific actions on MCInsts. For example, only the body of the loop here would be in "fixCalls".

Another thing we could do is to rename fixCalls to fixRISCVCall, so it is obvious to other backends that this function is exclusive of RISCV and that they don't have to implement it.

[Amir]

Thank you for working on it! Would you want to add a line to bolt/CODE_OWNERS.TXT?

bolt/include/bolt/Core/BinaryFunction.h

1311 ↗

(On Diff #505024)

Please move it to RISCVMCPlusBuilder, similar to D131813.

bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp

36

Feel free to remove these per D145972

[jobnoorman]

Rebase and address reviewer comments:

• Adapt to D131813 and D145972
• Remove duplicated method getOrCreateAbsoluteSymbol
• Do not depend on libBOLTCore in libBOLTTarget: have the pass loop over instructions and only call back to MCPlusBuilder for target-specific info
• Update bolt/CODE_OWNERS.TXT

[jobnoorman]

bolt/lib/Core/BinaryContext.cpp

750–752

Nice catch! I think this method went through several rounds of refactoring and ended up the same as another one without me noticing :) Removed.

bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp

297

Fair point, I gave it a shot: the pass now loops over all instructions, calls a new method MCPlusBuilder::isRISCVCall to identify AUIPC/JALR pairs and then fixes-up the JALR.

It still feels unfortunate to have target-specific methods in MCPlusBuilder though. I wonder of some of them (like this one) could be prevented by allowing passes to be implemented in the backend library. Not something to be addressed by this patch though.

[jobnoorman]

Friendly ping.

[rafauler]

bolt/lib/Rewrite/RewriteInstance.cpp

2639

Maybe convert this TODO into a regular comment saying this also passes for UND symbols, even though the intent is to capture ABS symbols that land outside any section.

2642

I'm probably not getting the full picture here, so correct my thinking below.

So, if I understand correctly, you have an ABS __global_pointer$ symbol that points outside any section that BOLT has loaded (otherwise ReferencedSection wouldn't be null here). Therefore, BOLT won't change the location of this symbol (if it is pointing to some unknown region of memory that is not covered by any section known by BC->getSectionForAddress(SymbolAddress).

So why register this reloc, if we are not changing this symbol? We will arrive at link step and RuntimeDyld will resolve this unknown symbol to zero, no? How do we know the correct value of this symbol?

If we don't create the relocation here (with addRelocation), we will disassemble the original code that is already patched with the correct value for this symbol -- at least for X86. For RISC, this is harder to do if the real address is split in different instructions, and we don't have the luxury of ignoring the relocation. So my feeling is that, at the very least, this code is RISC-only, but you didn't protect this code from running in the X86 backend.

[jobnoorman]

bolt/lib/Rewrite/RewriteInstance.cpp

2642

Thanks for the extensive review!

So, if I understand correctly, you have an ABS __global_pointer$ symbol that points outside any section that BOLT has loaded (otherwise ReferencedSection wouldn't be null here). Therefore, BOLT won't change the location of this symbol (if it is pointing to some unknown region of memory that is not covered by any section known by BC->getSectionForAddress(SymbolAddress).

Correct. Except that __global_pointer$ should be handled even if it happens to point to a section. I'll look into a way to fix this.

So why register this reloc, if we are not changing this symbol? We will arrive at link step and RuntimeDyld will resolve this unknown symbol to zero, no? How do we know the correct value of this symbol?

The current behavior of this patch is that __global_pointer$ keeps its original value. I just noticed that this works kind of accidentally because symbols that don't reference a section are registered for "pretty printing" here.

Now, whether this is correct or not is a good question. The linker is supposed to pick the value for __global_pointer$ when performing Global-pointer relaxation. Since linker relaxation is not addressed by this patch (-Wl,--no-relax is currently mandatory to use it), I don't have an answer to this question yet. (*)

If we don't create the relocation here (with addRelocation), we will disassemble the original code that is already patched with the correct value for this symbol -- at least for X86. For RISC, this is harder to do if the real address is split in different instructions, and we don't have the luxury of ignoring the relocation.

The problem is that the relocation against __global_pointer$ is typically used by a PC-relative code sequence like this (copied from the link above):

1:  auipc gp, %pcrel_hi(__global_pointer$) # R_RISCV_HI20
    addi  gp, gp, %pcrel_lo(1b)            # R_RISCV_LO12_I

So even though we don't change the value of __global_pointer$, the location of this code sequence *can* change and hence the immediate values in it need to be patched again. Therefore, I think adding this relocation is necessary.

So my feeling is that, at the very least, this code is RISC-only, but you didn't protect this code from running in the X86 backend.

I think it's true this code will currently only ever get triggered on RISC-V and I don't mind protecting it as such. However, do you think it will do the wrong thing for an X86 binary containing an ABS symbol? If not, it might make sense to not protect this code to reduce the number of target-specific code paths.

(*) The fact that we don't support linker relaxation yet got me thinking about whether we could skip handling of __global_pointer$ altogether in this patch. This should work in principle since the only place it's used in the binaries I've tested is during the initialization of gp in GCC's startup routines; gp is never actually read from in the rest of the binary. The problem is that we then should also ignore the second relocation (R_RISCV_LO12_I) in the example above or else RuntimeDyld gets angry. It feels like any way to filter-out this particular case of R_RISCV_LO12_I would be quite hacky so it will probably be preferable to not do this. I'll look into it though.

[jobnoorman]

Hi all, I just got the following comment on the RuntimeDyLd part of this patch:

In D145686#4222642, @lhames wrote:

Is there something preventing Bolt from moving to ORC / JITLink? If Bolt is able to move over then the aim should be to do that. If Bolt is unable to move over then we need to know why so that we can address the issue. RuntimeDyld is very much in maintenance mode at the moment, and we're working hard to reach parity in backend coverage so that we can officially deprecate it.

None of that is a total blocker to landing this, but the bar is high, and it should be understood that Bolt will need to migrate in the future.

Since I cannot speak for BOLT's plans of migrating to JITLink, I was wondering if one of the BOLT devs could chip in here?

[rafauler]

bolt/lib/Rewrite/RewriteInstance.cpp

2642

Oh I see, thanks for explaining. I was afraid to push this because I thought we would resolve these symbols to zero, but since we're loading them correctly in discoverFileObjects, then it makes sense to push this to X86 too. Can you update the pretty printing comment to reference this patch and how it is important to handle relocs against these symbols?

To push this to X86, I would like this code to be more guardrails. First, is there a way to check that no undefined symbols are being handled here? Second, I really don't like the name "getOrCreateUndefinedGlobalSymbol" because this symbol is supposedly defined. Can you use "BC.Ctx->lookupSymbol()" and explicitly search for the symbol you need, and drop the relocation in case the symbol is not there? That's because, in case the symbol is not there, you will create an undefined symbol, which ideally we shouldn't have. You can even add an assertion here for RISCV only, in case it is global_pointer and you couldn't find it., to keep track of your support for it.

[jobnoorman]

• Rebase
• Improve ABS symbol handling:
  • Reuse existing symbol-lookup code when handling relocations so we don't need to create new undefined symbols.
  • Also handle ABS symbol relocation if their value happens to point to a section.

[jobnoorman]

bolt/lib/Rewrite/RewriteInstance.cpp

2642

Oh I see, thanks for explaining. I was afraid to push this because I thought we would resolve these symbols to zero, but since we're loading them correctly in discoverFileObjects, then it makes sense to push this to X86 too. Can you update the pretty printing comment to reference this patch and how it is important to handle relocs against these symbols?

Done!

To push this to X86, I would like this code to be more guardrails.

I rewrote the implementation of ABS symbol handling and I believe it's more robust now. Note that it moved a bit up because of this so you won't find the implementation here anymore.

First, is there a way to check that no undefined symbols are being handled here?

The code will now not trigger anymore for symbols that were never registered in discoverFileObjects. However, I believe that the way ABS symbols are detected there (checking if they don't have a section) would also match UND symbols. I'm not even sure if it's possible to make the distinction between ABS and UND symbols here. I feel like this shouldn't be a big problem though as UND symbols shouldn't happen in practice. Would you agree?

Second, I really don't like the name "getOrCreateUndefinedGlobalSymbol" because this symbol is supposedly defined. Can you use "BC.Ctx->lookupSymbol()" and explicitly search for the symbol you need, and drop the relocation in case the symbol is not there? That's because, in case the symbol is not there, you will create an undefined symbol, which ideally we shouldn't have. You can even add an assertion here for RISCV only, in case it is global_pointer and you couldn't find it., to keep track of your support for it.

I managed to remove the need to create symbols entirely by reusing the symbol lookup that already happened earlier in the handleRelocation method.

[rafauler]

bolt/lib/Rewrite/RewriteInstance.cpp

2590–2596

The new solution is triggering a lot more than the previous one, now we're definitely getting undefined symbols. In one X86 input we're getting these entries now being used to generate relocs:

714106: 0000000000000000 0 NOTYPE WEAK DEFAULT UND symbol1
714107: 0000000000000000 0 NOTYPE WEAK DEFAULT UND symbol2

Unless we plan to define symbols in BOLT, which I can't think why we would do that, I think we should explicitly filter out undefined syms when adding relocations to functions.

[jobnoorman]

Don't add relocations against UND symbols.

[jobnoorman]

bolt/lib/Rewrite/RewriteInstance.cpp

2590–2596

Interesting! I found a way to check that the symbol is actually an ABS one.

Note that I wasn't able to reproduce this issue (I might've misunderstood/done something wrong though). If you're still seeing issues with this, could you maybe point me to an input file to reproduce it?

[rafauler]

LGTM

[jobnoorman]

Thanks a lot for the reviews and help improving this patch, @rafauler.

The main roadblock in getting this landed seems to be the issue around RuntimeDyLd. Since it's deprecated, I've been playing around with porting BOLT to JITLink and the results are starting to look quite promising (just 24 failing tests to solve). I hope to be able to post an RFC patch for this at some point next week.

[jobnoorman]

Rebase: integrate CMake changes from D148847.

bolt/CODE_OWNERS.TXT

 
 N: Alexander Yermolovich
 E: [e-mail]
 D: DWARF support
 
 N: Vladislav Khmelevsky
 E: [e-mail]
 D: AArch64 backend
+
+N: Job Noorman
+E: [e-mail]
+D: RISC-V backend

bolt/include/bolt/Core/BinaryContext.h

bool isAArch64() const {
     return TheTriple->getArch() == llvm::Triple::aarch64;
   }
 
   bool isX86() const {
     return TheTriple->getArch() == llvm::Triple::x86 ||
            TheTriple->getArch() == llvm::Triple::x86_64;
   }
 
+  bool isRISCV() const { return TheTriple->getArch() == llvm::Triple::riscv64; }
+
   // AArch64-specific functions to check if symbol is used to delimit
   // code/data in .text. Code is marked by $x, data by $d.
   MarkerSymType getMarkerType(const SymbolRef &Symbol) const;
   bool isMarker(const SymbolRef &Symbol) const;
 
   /// Iterate over all BinaryData.
   iterator_range<binary_data_const_iterator> getBinaryData() const {
     return make_range(BinaryDataMap.begin(), BinaryDataMap.end());

bolt/include/bolt/Core/MCPlusBuilder.h

virtual bool isCleanRegXOR(const MCInst &Inst) const {
     return false;
   }
 
   virtual bool isPacked(const MCInst &Inst) const {
     llvm_unreachable("not implemented");
     return false;
   }
 
+  /// Returns true if First/Second is a AUIPC/JALR call pair.
+  virtual bool isRISCVCall(const MCInst &First, const MCInst &Second) const {
+    llvm_unreachable("not implemented");
+    return false;
+  }
+
   /// If non-zero, this is used to fill the executable space with instructions
   /// that will trap. Defaults to 0.
   virtual unsigned getTrapFillValue() const { return 0; }
 
   /// Interface and basic functionality of a MCInstMatcher. The idea is to make
   /// it easy to match one or more MCInsts against a tree-like pattern and
   /// extract the fragment operands. Example:
   ///

 MCPlusBuilder *createX86MCPlusBuilder(const MCInstrAnalysis *,
                                       const MCInstrInfo *,
                                       const MCRegisterInfo *);
 
 MCPlusBuilder *createAArch64MCPlusBuilder(const MCInstrAnalysis *,
                                           const MCInstrInfo *,
                                           const MCRegisterInfo *);
 
+MCPlusBuilder *createRISCVMCPlusBuilder(const MCInstrAnalysis *,
+                                        const MCInstrInfo *,
+                                        const MCRegisterInfo *);
+
 } // namespace bolt
 } // namespace llvm
 
 #endif

bolt/include/bolt/Passes/FixRISCVCallsPass.h

+//===- bolt/Passes/FixRISCVCallsPass.h --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the FixRISCVCallsPass class, which sets the JALR immediate
+// to 0 for AUIPC/JALR pairs with a R_RISCV_CALL(_PLT) relocation. This is
+// necessary since MC expects it to be zero in order to or-in fixups.
+//===----------------------------------------------------------------------===//
+
+#ifndef BOLT_PASSES_FIXRISCVCALLSPASS_H
+#define BOLT_PASSES_FIXRISCVCALLSPASS_H
+
+#include "bolt/Passes/BinaryPasses.h"
+
+namespace llvm {
+namespace bolt {
+
+class FixRISCVCallsPass : public BinaryFunctionPass {
+  void runOnFunction(BinaryFunction &Function);
+
+public:
+  explicit FixRISCVCallsPass(const cl::opt<bool> &PrintPass)
+      : BinaryFunctionPass(PrintPass) {}
+
+  const char *getName() const override { return "fix-riscv-calls"; }
+
+  /// Pass entry point
+  void runOnFunctions(BinaryContext &BC) override;
+};
+
+} // namespace bolt
+} // namespace llvm
+
+#endif

bolt/include/bolt/Rewrite/RewriteInstance.h

private:
 
   /// Disassemble aarch64-specific .plt \p Section auxiliary function
   void disassemblePLTSectionAArch64(BinarySection &Section);
 
   /// Disassemble X86-specific .plt \p Section auxiliary function. \p EntrySize
   /// is the expected .plt \p Section entry function size.
   void disassemblePLTSectionX86(BinarySection &Section, uint64_t EntrySize);
 
+  /// Disassemble riscv-specific .plt \p Section auxiliary function
+  void disassemblePLTSectionRISCV(BinarySection &Section);
+
   /// ELF-specific part. TODO: refactor into new class.
 #define ELF_FUNCTION(TYPE, FUNC)                                               \
   template <typename ELFT> TYPE FUNC(object::ELFObjectFile<ELFT> *Obj);        \
   TYPE FUNC() {                                                                \
     if (auto *ELF32LE = dyn_cast<object::ELF32LEObjectFile>(InputFile))        \
       return FUNC(ELF32LE);                                                    \
     if (auto *ELF64LE = dyn_cast<object::ELF64LEObjectFile>(InputFile))        \
       return FUNC(ELF64LE);                                                    \
const PLTSectionInfo X86_64_PLTSections[4] = {
       { ".plt.sec", 8 },
       { nullptr, 0 }
   };
 
   /// AArch64 PLT sections.
   const PLTSectionInfo AArch64_PLTSections[3] = {
       {".plt"}, {".iplt"}, {nullptr}};
 
+  /// RISCV PLT sections.
+  const PLTSectionInfo RISCV_PLTSections[3] = {{".plt"}, {nullptr}};
+
   /// Return PLT information for a section with \p SectionName or nullptr
   /// if the section is not PLT.
   const PLTSectionInfo *getPLTSectionInfo(StringRef SectionName) {
     const PLTSectionInfo *PLTSI = nullptr;
     switch (BC->TheTriple->getArch()) {
     default:
       break;
     case Triple::x86_64:
       PLTSI = X86_64_PLTSections;
       break;
     case Triple::aarch64:
       PLTSI = AArch64_PLTSections;
       break;
+    case Triple::riscv64:
+      PLTSI = RISCV_PLTSections;
+      break;
     }
     for (; PLTSI && PLTSI->Name; ++PLTSI)
       if (SectionName == PLTSI->Name)
         return PLTSI;
 
     return nullptr;
   }
 

bolt/lib/Core/BinaryContext.cpp

BinaryContext::createBinaryContext(const ObjectFile *File, bool IsPIC,
   case llvm::Triple::x86_64:
     ArchName = "x86-64";
     FeaturesStr = "+nopl";
     break;
   case llvm::Triple::aarch64:
     ArchName = "aarch64";
     FeaturesStr = "+all";
     break;
+  case llvm::Triple::riscv64:
+    ArchName = "riscv64";
+    // RV64GC
+    FeaturesStr = "+m,+a,+f,+d,+zicsr,+zifencei,+c";
+    break;
   default:
     return createStringError(std::errc::not_supported,
                              "BOLT-ERROR: Unrecognized machine in ELF file");
   }
 
   auto TheTriple = std::make_unique<Triple>(File->makeTriple());
   const std::string TripleName = TheTriple->str();
 
MCSymbol *BinaryContext::getOrCreateGlobalSymbol(uint64_t Address, Twine Prefix,
   assert(!GlobalSymbols.count(Name) && "created name is not unique");
   return registerNameAtAddress(Name, Address, Size, Alignment, Flags);
 }
 
 MCSymbol *BinaryContext::getOrCreateUndefinedGlobalSymbol(StringRef Name) {
   return Ctx->getOrCreateSymbol(Name);
 }
 
 BinaryFunction *BinaryContext::createBinaryFunction(
     const std::string &Name, BinarySection &Section, uint64_t Address,
     uint64_t Size, uint64_t SymbolSize, uint16_t Alignment) {
   auto Result = BinaryFunctions.emplace(
       Address, BinaryFunction(Name, Section, Address, Size, *this));
   assert(Result.second == true && "unexpected duplicate function");
   BinaryFunction *BF = &Result.first->second;
   registerNameAtAddress(Name, Address, SymbolSize ? SymbolSize : Size,
                         Alignment);
   setSymbolToFunctionMap(BF->getSymbol(), BF);
   return BF;

bolt/lib/Core/BinaryFunction.cpp

if (MIB->isBranch(Instruction) || MIB->isCall(Instruction)) {
           handleIndirectBranch(Instruction, Size, Offset);
         // Indirect call. We only need to fix it if the operand is RIP-relative.
         if (IsSimple && MIB->hasPCRelOperand(Instruction))
           handlePCRelOperand(Instruction, AbsoluteInstrAddr, Size);
 
         if (BC.isAArch64())
           handleAArch64IndirectCall(Instruction, Offset);
       }
-    } else if (BC.isAArch64()) {
+    } else if (BC.isAArch64() || BC.isRISCV()) {
       // Check if there's a relocation associated with this instruction.
       bool UsedReloc = false;
       for (auto Itr = Relocations.lower_bound(Offset),
                 ItrE = Relocations.lower_bound(Offset + Size);
            Itr != ItrE; ++Itr) {
         const Relocation &Relocation = Itr->second;
         int64_t Value = Relocation.Value;
         const bool Result = BC.MIB->replaceImmWithSymbolRef(
             Instruction, Relocation.Symbol, Relocation.Addend, Ctx.get(), Value,
             Relocation.Type);
         (void)Result;
         assert(Result && "cannot replace immediate with relocation");
 
         // For aarch64, if we replaced an immediate with a symbol from a
         // relocation, we mark it so we do not try to further process a
         // pc-relative operand. All we need is the symbol.
         UsedReloc = true;
       }
 
-      if (MIB->hasPCRelOperand(Instruction) && !UsedReloc)
+      if (!BC.isRISCV() && MIB->hasPCRelOperand(Instruction) && !UsedReloc)
         handlePCRelOperand(Instruction, AbsoluteInstrAddr, Size);
     }
 
 add_instruction:
     if (getDWARFLineTable()) {
       Instruction.setLoc(findDebugLineInformationForInstructionAt(
           AbsoluteInstrAddr, getDWARFUnit(), getDWARFLineTable()));
     }

bolt/lib/Core/Relocation.cpp

static bool isSupportedAArch64(uint64_t Type) {
   case ELF::R_AARCH64_MOVW_UABS_G1_NC:
   case ELF::R_AARCH64_MOVW_UABS_G2:
   case ELF::R_AARCH64_MOVW_UABS_G2_NC:
   case ELF::R_AARCH64_MOVW_UABS_G3:
     return true;
   }
 }
 
+static bool isSupportedRISCV(uint64_t Type) {
+  switch (Type) {
+  default:
+    return false;
+  case ELF::R_RISCV_JAL:
+  case ELF::R_RISCV_CALL:
+  case ELF::R_RISCV_CALL_PLT:
+  case ELF::R_RISCV_BRANCH:
+  case ELF::R_RISCV_RELAX:
+  case ELF::R_RISCV_GOT_HI20:
+  case ELF::R_RISCV_PCREL_HI20:
+  case ELF::R_RISCV_PCREL_LO12_I:
+  case ELF::R_RISCV_RVC_JUMP:
+  case ELF::R_RISCV_RVC_BRANCH:
+    return true;
+  }
+}
+
 static size_t getSizeForTypeX86(uint64_t Type) {
   switch (Type) {
   default:
     errs() << object::getELFRelocationTypeName(ELF::EM_X86_64, Type) << '\n';
     llvm_unreachable("unsupported relocation type");
   case ELF::R_X86_64_8:
   case ELF::R_X86_64_PC8:
     return 1;
static size_t getSizeForTypeAArch64(uint64_t Type) {
   case ELF::R_AARCH64_ABS32:
     return 4;
   case ELF::R_AARCH64_ABS64:
   case ELF::R_AARCH64_PREL64:
     return 8;
   }
 }
 
+static size_t getSizeForTypeRISCV(uint64_t Type) {
+  switch (Type) {
+  default:
+    errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n';
+    llvm_unreachable("unsupported relocation type");
+  case ELF::R_RISCV_RVC_JUMP:
+  case ELF::R_RISCV_RVC_BRANCH:
+    return 2;
+  case ELF::R_RISCV_JAL:
+  case ELF::R_RISCV_BRANCH:
+  case ELF::R_RISCV_PCREL_HI20:
+  case ELF::R_RISCV_PCREL_LO12_I:
+  case ELF::R_RISCV_32_PCREL:
+  case ELF::R_RISCV_CALL:
+  case ELF::R_RISCV_CALL_PLT:
+    return 4;
+  case ELF::R_RISCV_GOT_HI20:
+    // See extractValueRISCV for why this is necessary.
+    return 8;
+  }
+}
+
 static bool skipRelocationTypeX86(uint64_t Type) {
   return Type == ELF::R_X86_64_NONE;
 }
 
 static bool skipRelocationTypeAArch64(uint64_t Type) {
   return Type == ELF::R_AARCH64_NONE || Type == ELF::R_AARCH64_LD_PREL_LO19;
 }
 
+static bool skipRelocationTypeRISCV(uint64_t Type) {
+  switch (Type) {
+  default:
+    return false;
+  case ELF::R_RISCV_NONE:
+  case ELF::R_RISCV_RELAX:
+    return true;
+  }
+}
+
 static bool skipRelocationProcessX86(uint64_t &Type, uint64_t Contents) {
   return false;
 }
 
 static bool skipRelocationProcessAArch64(uint64_t &Type, uint64_t Contents) {
   auto IsMov = [](uint64_t Contents) -> bool {
     // The bits 28-23 are 0b100101
     return (Contents & 0x1f800000) == 0x12800000;
static bool skipRelocationProcessAArch64(uint64_t &Type, uint64_t Contents) {
   case ELF::R_AARCH64_LD64_GOT_LO12_NC:
     if (IsAdr(Contents))
       return true;
   }
 
   return false;
 }
 
+static bool skipRelocationProcessRISCV(uint64_t &Type, uint64_t Contents) {
+  return false;
+}
+
 static uint64_t adjustValueX86(uint64_t Type, uint64_t Value, uint64_t PC) {
   switch (Type) {
   default:
     llvm_unreachable("not supported relocation");
   case ELF::R_X86_64_32:
     break;
   case ELF::R_X86_64_PC32:
     Value -= PC;
case ELF::R_AARCH64_MOVW_UABS_G0:
     // The shift goest in bits 22:21 of MOV* instructions
     uint8_t Shift = (Contents >> 21) & 0x3;
     // Immediate goes in bits 20:5
     Contents = (Contents >> 5) & 0xffff;
     return Contents << (16 * Shift);
   }
 }
 
+static uint64_t extractUImmRISCV(uint32_t Contents) {
+  return SignExtend64<32>(Contents & 0xfffff000);
+}
+
+static uint64_t extractIImmRISCV(uint32_t Contents) {
+  return SignExtend64<12>(Contents >> 20);
+}
+
+static uint64_t extractJImmRISCV(uint32_t Contents) {
+  return SignExtend64<21>(
+      (((Contents >> 21) & 0x3ff) << 1) | (((Contents >> 20) & 0x1) << 11) |
+      (((Contents >> 12) & 0xff) << 12) | (((Contents >> 31) & 0x1) << 20));
+}
+
+static uint64_t extractBImmRISCV(uint32_t Contents) {
+  return SignExtend64<13>(
+      (((Contents >> 8) & 0xf) << 1) | (((Contents >> 25) & 0x3f) << 5) |
+      (((Contents >> 7) & 0x1) << 11) | (((Contents >> 31) & 0x1) << 12));
+}
+
+static uint64_t extractValueRISCV(uint64_t Type, uint64_t Contents,
+                                  uint64_t PC) {
+  switch (Type) {
+  default:
+    errs() << object::getELFRelocationTypeName(ELF::EM_RISCV, Type) << '\n';
+    llvm_unreachable("unsupported relocation type");
+  case ELF::R_RISCV_JAL:
+    return extractJImmRISCV(Contents);
+  case ELF::R_RISCV_CALL:
+  case ELF::R_RISCV_CALL_PLT:
+    return extractUImmRISCV(Contents);
+  case ELF::R_RISCV_BRANCH:
+    return extractBImmRISCV(Contents);
+  case ELF::R_RISCV_GOT_HI20:
+    // We need to know the exact address of the GOT entry so we extract the
+    // value from both the AUIPC and L[D|W]. We cannot rely on the symbol in the
+    // relocation for this since it simply refers to the object that is stored
+    // in the GOT entry, not to the entry itself.
+    return extractUImmRISCV(Contents & 0xffffffff) +
+           extractIImmRISCV(Contents >> 32);
+  case ELF::R_RISCV_PCREL_HI20:
+    return extractUImmRISCV(Contents);
+  case ELF::R_RISCV_PCREL_LO12_I:
+    return extractIImmRISCV(Contents);
+  case ELF::R_RISCV_RVC_JUMP:
+    return SignExtend64<11>(Contents >> 2);
+  case ELF::R_RISCV_RVC_BRANCH:
+    return SignExtend64<8>(((Contents >> 2) & 0x1f) | ((Contents >> 5) & 0xe0));
+  }
+}
+
 static bool isGOTX86(uint64_t Type) {
   switch (Type) {
   default:
     return false;
   case ELF::R_X86_64_GOT32:
   case ELF::R_X86_64_GOTPCREL:
   case ELF::R_X86_64_GOTTPOFF:
   case ELF::R_X86_64_GOTOFF64:
static bool isGOTAArch64(uint64_t Type) {
   case ELF::R_AARCH64_TLSDESC_ADR_PAGE21:
   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
   case ELF::R_AARCH64_TLSDESC_CALL:
     return true;
   }
 }
 
+static bool isGOTRISCV(uint64_t Type) {
+  switch (Type) {
+  default:
+    return false;
+  case ELF::R_RISCV_GOT_HI20:
+    return true;
+  }
+}
+
 static bool isTLSX86(uint64_t Type) {
   switch (Type) {
   default:
     return false;
   case ELF::R_X86_64_TPOFF32:
   case ELF::R_X86_64_TPOFF64:
   case ELF::R_X86_64_GOTTPOFF:
     return true;
static bool isTLSAArch64(uint64_t Type) {
   case ELF::R_AARCH64_TLSDESC_LD64_LO12:
   case ELF::R_AARCH64_TLSDESC_ADD_LO12:
   case ELF::R_AARCH64_TLSDESC_CALL:
   case ELF::R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
     return true;
   }
 }
 
+static bool isTLSRISCV(uint64_t Type) {
+  switch (Type) {
+  default:
+    return false;
+  }
+}
+
 static bool isPCRelativeX86(uint64_t Type) {
   switch (Type) {
   default:
     llvm_unreachable("Unknown relocation type");
   case ELF::R_X86_64_64:
   case ELF::R_X86_64_32:
   case ELF::R_X86_64_32S:
   case ELF::R_X86_64_16:
static bool isPCRelativeAArch64(uint64_t Type) {
   case ELF::R_AARCH64_TLSDESC_ADR_PAGE21:
   case ELF::R_AARCH64_PREL16:
   case ELF::R_AARCH64_PREL32:
   case ELF::R_AARCH64_PREL64:
     return true;
   }
 }
 
+static bool isPCRelativeRISCV(uint64_t Type) {
+  switch (Type) {
+  default:
+    llvm_unreachable("Unknown relocation type");
+  case ELF::R_RISCV_JAL:
+  case ELF::R_RISCV_CALL:
+  case ELF::R_RISCV_CALL_PLT:
+  case ELF::R_RISCV_BRANCH:
+  case ELF::R_RISCV_GOT_HI20:
+  case ELF::R_RISCV_PCREL_HI20:
+  case ELF::R_RISCV_PCREL_LO12_I:
+  case ELF::R_RISCV_RVC_JUMP:
+  case ELF::R_RISCV_RVC_BRANCH:
+  case ELF::R_RISCV_32_PCREL:
+    return true;
+  }
+}
+
 bool Relocation::isSupported(uint64_t Type) {
   if (Arch == Triple::aarch64)
     return isSupportedAArch64(Type);
+  if (Arch == Triple::riscv64)
+    return isSupportedRISCV(Type);
   return isSupportedX86(Type);
 }
 
 size_t Relocation::getSizeForType(uint64_t Type) {
   if (Arch == Triple::aarch64)
     return getSizeForTypeAArch64(Type);
+  if (Arch == Triple::riscv64)
+    return getSizeForTypeRISCV(Type);
   return getSizeForTypeX86(Type);
 }
 
 bool Relocation::skipRelocationType(uint64_t Type) {
   if (Arch == Triple::aarch64)
     return skipRelocationTypeAArch64(Type);
+  if (Arch == Triple::riscv64)
+    return skipRelocationTypeRISCV(Type);
   return skipRelocationTypeX86(Type);
 }
 
 bool Relocation::skipRelocationProcess(uint64_t &Type, uint64_t Contents) {
   if (Arch == Triple::aarch64)
     return skipRelocationProcessAArch64(Type, Contents);
+  if (Arch == Triple::riscv64)
+    skipRelocationProcessRISCV(Type, Contents);
   return skipRelocationProcessX86(Type, Contents);
 }
 
 uint64_t Relocation::adjustValue(uint64_t Type, uint64_t Value,
                                  uint64_t PC) {
   if (Arch == Triple::aarch64)
     return adjustValueAArch64(Type, Value, PC);
+  if (Arch == Triple::riscv64)
+    llvm_unreachable("not implemented");
   return adjustValueX86(Type, Value, PC);
 }
 
 uint64_t Relocation::extractValue(uint64_t Type, uint64_t Contents,
                                   uint64_t PC) {
   if (Arch == Triple::aarch64)
     return extractValueAArch64(Type, Contents, PC);
+  if (Arch == Triple::riscv64)
+    return extractValueRISCV(Type, Contents, PC);
   return extractValueX86(Type, Contents, PC);
 }
 
 bool Relocation::isGOT(uint64_t Type) {
   if (Arch == Triple::aarch64)
     return isGOTAArch64(Type);
+  if (Arch == Triple::riscv64)
+    return isGOTRISCV(Type);
   return isGOTX86(Type);
 }
 
 bool Relocation::isX86GOTPCRELX(uint64_t Type) {
   if (Arch != Triple::x86_64)
     return false;
   return Type == ELF::R_X86_64_GOTPCRELX || Type == ELF::R_X86_64_REX_GOTPCRELX;
 }
 
 bool Relocation::isNone(uint64_t Type) { return Type == getNone(); }
 
 bool Relocation::isRelative(uint64_t Type) {
   if (Arch == Triple::aarch64)
     return Type == ELF::R_AARCH64_RELATIVE;
+  if (Arch == Triple::riscv64)
+    return Type == ELF::R_RISCV_RELATIVE;
   return Type == ELF::R_X86_64_RELATIVE;
 }
 
 bool Relocation::isIRelative(uint64_t Type) {
   if (Arch == Triple::aarch64)
     return Type == ELF::R_AARCH64_IRELATIVE;
+  if (Arch == Triple::riscv64)
+    llvm_unreachable("not implemented");
   return Type == ELF::R_X86_64_IRELATIVE;
 }
 
 bool Relocation::isTLS(uint64_t Type) {
   if (Arch == Triple::aarch64)
     return isTLSAArch64(Type);
+  if (Arch == Triple::riscv64)
+    return isTLSRISCV(Type);
   return isTLSX86(Type);
 }
 
 uint64_t Relocation::getNone() {
   if (Arch == Triple::aarch64)
     return ELF::R_AARCH64_NONE;
+  if (Arch == Triple::riscv64)
+    return ELF::R_RISCV_NONE;
   return ELF::R_X86_64_NONE;
 }
 
 uint64_t Relocation::getPC32() {
   if (Arch == Triple::aarch64)
     return ELF::R_AARCH64_PREL32;
+  if (Arch == Triple::riscv64)
+    return ELF::R_RISCV_32_PCREL;
   return ELF::R_X86_64_PC32;
 }
 
 uint64_t Relocation::getPC64() {
   if (Arch == Triple::aarch64)
     return ELF::R_AARCH64_PREL64;
+  if (Arch == Triple::riscv64)
+    llvm_unreachable("not implemented");
   return ELF::R_X86_64_PC64;
 }
 
 bool Relocation::isPCRelative(uint64_t Type) {
   if (Arch == Triple::aarch64)
     return isPCRelativeAArch64(Type);
+  if (Arch == Triple::riscv64)
+    return isPCRelativeRISCV(Type);
   return isPCRelativeX86(Type);
 }
 
 uint64_t Relocation::getAbs64() {
   if (Arch == Triple::aarch64)
     return ELF::R_AARCH64_ABS64;
   return ELF::R_X86_64_64;
 }
void Relocation::print(raw_ostream &OS) const {
   static const char *X86RelocNames[] = {
 #include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
   };
   static const char *AArch64RelocNames[] = {
 #include "llvm/BinaryFormat/ELFRelocs/AArch64.def"
   };
   if (Arch == Triple::aarch64)
     OS << AArch64RelocNames[Type];
-  else
+  else if (Arch == Triple::riscv64) {
+    // RISC-V relocations are not sequentially numbered so we cannot use an
+    // array
+    switch (Type) {
+    default:
+      llvm_unreachable("illegal RISC-V relocation");
+#undef ELF_RELOC
+#define ELF_RELOC(name, value)                                                 \
+  case value:                                                                  \
+    OS << #name;                                                               \
+    break;
+#include "llvm/BinaryFormat/ELFRelocs/RISCV.def"
+    }
+  } else
     OS << X86RelocNames[Type];
   OS << ", 0x" << Twine::utohexstr(Offset);
   if (Symbol) {
     OS << ", " << Symbol->getName();
   }
   if (int64_t(Addend) < 0)
     OS << ", -0x" << Twine::utohexstr(-int64_t(Addend));
   else
     OS << ", 0x" << Twine::utohexstr(Addend);
   OS << ", 0x" << Twine::utohexstr(Value);
 }

bolt/lib/Passes/CMakeLists.txt

 add_llvm_library(LLVMBOLTPasses
   ADRRelaxationPass.cpp
   Aligner.cpp
   AllocCombiner.cpp
   AsmDump.cpp
   BinaryPasses.cpp
   BinaryFunctionCallGraph.cpp
   CMOVConversion.cpp
   CacheMetrics.cpp
   CallGraph.cpp
   CallGraphWalker.cpp
   DataflowAnalysis.cpp
   DataflowInfoManager.cpp
   FrameAnalysis.cpp
   FrameOptimizer.cpp
   FixRelaxationPass.cpp
+  FixRISCVCallsPass.cpp
   HFSort.cpp
   HFSortPlus.cpp
   Hugify.cpp
   IdenticalCodeFolding.cpp
   IndirectCallPromotion.cpp
   Inliner.cpp
   Instrumentation.cpp
   JTFootprintReduction.cpp

bolt/lib/Passes/FixRISCVCallsPass.cpp

+#include "bolt/Passes/FixRISCVCallsPass.h"
+#include "bolt/Core/ParallelUtilities.h"
+
+#include <iterator>
+
+using namespace llvm;
+
+namespace llvm {
+namespace bolt {
+
+void FixRISCVCallsPass::runOnFunction(BinaryFunction &BF) {
+  auto &BC = BF.getBinaryContext();
+
+  for (auto &BB : BF) {
+    for (auto II = BB.begin(), IE = BB.end(); II != IE; ++II) {
+      auto NextII = std::next(II);
+
+      if (NextII == IE)
+        break;
+
+      if (!BC.MIB->isRISCVCall(*II, *NextII))
+        continue;
+
+      auto L = BC.scopeLock();
+
+      // The MC layer handles R_RISCV_CALL_PLT but assumes that the immediate
+      // in the JALR is zero (fixups are or'ed into instructions). Note that
+      // NextII is guaranteed to point to a JALR by isRISCVCall.
+      NextII->getOperand(2).setImm(0);
+    }
+  }
+}
+
+void FixRISCVCallsPass::runOnFunctions(BinaryContext &BC) {
+  if (!BC.isRISCV() || !BC.HasRelocations)
+    return;
+
+  ParallelUtilities::WorkFuncTy WorkFun = [&](BinaryFunction &BF) {
+    runOnFunction(BF);
+  };
+
+  ParallelUtilities::runOnEachFunction(
+      BC, ParallelUtilities::SchedulingPolicy::SP_INST_LINEAR, WorkFun, nullptr,
+      "FixRISCVCalls");
+}
+
+} // namespace bolt
+} // namespace llvm

bolt/lib/Rewrite/BinaryPassManager.cpp

 //===- bolt/Rewrite/BinaryPassManager.cpp - Binary-level pass manager -----===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "bolt/Rewrite/BinaryPassManager.h"
 #include "bolt/Passes/ADRRelaxationPass.h"
 #include "bolt/Passes/Aligner.h"
 #include "bolt/Passes/AllocCombiner.h"
 #include "bolt/Passes/AsmDump.h"
 #include "bolt/Passes/CMOVConversion.h"
+#include "bolt/Passes/FixRISCVCallsPass.h"
 #include "bolt/Passes/FixRelaxationPass.h"
 #include "bolt/Passes/FrameOptimizer.h"
 #include "bolt/Passes/Hugify.h"
 #include "bolt/Passes/IdenticalCodeFolding.h"
 #include "bolt/Passes/IndirectCallPromotion.h"
 #include "bolt/Passes/Inliner.h"
 #include "bolt/Passes/Instrumentation.h"
 #include "bolt/Passes/JTFootprintReduction.h"
static cl::opt<bool>
     PrintStoke("print-stoke", cl::desc("print functions after stoke analysis"),
                cl::cat(BoltOptCategory));
 
 static cl::opt<bool>
     PrintFixRelaxations("print-fix-relaxations",
                         cl::desc("print functions after fix relaxations pass"),
                         cl::cat(BoltOptCategory));
 
+static cl::opt<bool>
+    PrintFixRISCVCalls("print-fix-riscv-calls",
+                       cl::desc("print functions after fix RISCV calls pass"),
+                       cl::cat(BoltOptCategory));
+
 static cl::opt<bool> PrintVeneerElimination(
     "print-veneer-elimination",
     cl::desc("print functions after veneer elimination pass"),
     cl::cat(BoltOptCategory));
 
 static cl::opt<bool>
     PrintUCE("print-uce",
              cl::desc("print functions after unreachable code elimination"),
void BinaryFunctionPassManager::runAllPasses(BinaryContext &BC) {
 
   if (BC.isAArch64()) {
     Manager.registerPass(std::make_unique<FixRelaxations>(PrintFixRelaxations));
 
     Manager.registerPass(
         std::make_unique<VeneerElimination>(PrintVeneerElimination));
   }
 
+  if (BC.isRISCV()) {
+    Manager.registerPass(
+        std::make_unique<FixRISCVCallsPass>(PrintFixRISCVCalls));
+  }
+
   // Here we manage dependencies/order manually, since passes are run in the
   // order they're registered.
 
   // Run this pass first to use stats for the original functions.
   Manager.registerPass(std::make_unique<PrintProgramStats>(NeverPrint));
 
   if (opts::PrintProfileStats)
     Manager.registerPass(std::make_unique<PrintProfileStats>(NeverPrint));

bolt/lib/Rewrite/CMakeLists.txt

if ("AArch64" IN_LIST LLVM_TARGETS_TO_BUILD)
   set(BOLT_AArch64 On)
 endif()
 
 if ("X86" IN_LIST LLVM_TARGETS_TO_BUILD)
   list(APPEND TARGET_LINK_LIBRARIES LLVMBOLTTargetX86)
   set(BOLT_X64 On)
 endif()
 
+if ("RISCV" IN_LIST LLVM_TARGETS_TO_BUILD)
+  list(APPEND TARGET_LINK_LIBRARIES LLVMBOLTTargetRISCV)
+  set(BOLT_RISCV On)
+endif()
+
 add_llvm_library(LLVMBOLTRewrite
   BinaryPassManager.cpp
   BoltDiff.cpp
   DWARFRewriter.cpp
   ExecutableFileMemoryManager.cpp
   MachORewriteInstance.cpp
   RewriteInstance.cpp
 

 
 if (DEFINED BOLT_AArch64)
   target_compile_definitions(LLVMBOLTRewrite PRIVATE AARCH64_AVAILABLE)
 endif()
 
 if (DEFINED BOLT_X64)
   target_compile_definitions(LLVMBOLTRewrite PRIVATE X86_AVAILABLE)
 endif()
+
+if (DEFINED BOLT_RISCV)
+  target_compile_definitions(LLVMBOLTRewrite PRIVATE RISCV_AVAILABLE)
+endif()

bolt/lib/Rewrite/RewriteInstance.cpp

if (Arch == Triple::x86_64)
     return createX86MCPlusBuilder(Analysis, Info, RegInfo);
 #endif
 
 #ifdef AARCH64_AVAILABLE
   if (Arch == Triple::aarch64)
     return createAArch64MCPlusBuilder(Analysis, Info, RegInfo);
 #endif
 
+#ifdef RISCV_AVAILABLE
+  if (Arch == Triple::riscv64)
+    return createRISCVMCPlusBuilder(Analysis, Info, RegInfo);
+#endif
+
   llvm_unreachable("architecture unsupported by MCPlusBuilder");
 }
 
 } // namespace bolt
 } // namespace llvm
 
 namespace {
 
while (InstrOffset < SectionSize) {
       if (!BC->MIB->isNoop(Instruction))
         break;
 
       InstrOffset += InstrSize;
     }
   }
 }
 
+void RewriteInstance::disassemblePLTSectionRISCV(BinarySection &Section) {
+  const uint64_t SectionAddress = Section.getAddress();
+  const uint64_t SectionSize = Section.getSize();
+  StringRef PLTContents = Section.getContents();
+  ArrayRef<uint8_t> PLTData(
+      reinterpret_cast<const uint8_t *>(PLTContents.data()), SectionSize);
+
+  auto disassembleInstruction = [&](uint64_t InstrOffset, MCInst &Instruction,
+                                    uint64_t &InstrSize) {
+    const uint64_t InstrAddr = SectionAddress + InstrOffset;
+    if (!BC->DisAsm->getInstruction(Instruction, InstrSize,
+                                    PLTData.slice(InstrOffset), InstrAddr,
+                                    nulls())) {
+      errs() << "BOLT-ERROR: unable to disassemble instruction in PLT section "
+             << Section.getName() << " at offset 0x"
+             << Twine::utohexstr(InstrOffset) << '\n';
+      exit(1);
+    }
+  };
+
+  // Skip the first special entry since no relocation points to it.
+  uint64_t InstrOffset = 32;
+
+  while (InstrOffset < SectionSize) {
+    InstructionListType Instructions;
+    MCInst Instruction;
+    const uint64_t EntryOffset = InstrOffset;
+    const uint64_t EntrySize = 16;
+    uint64_t InstrSize;
+
+    while (InstrOffset < EntryOffset + EntrySize) {
+      disassembleInstruction(InstrOffset, Instruction, InstrSize);
+      Instructions.emplace_back(Instruction);
+      InstrOffset += InstrSize;
+    }
+
+    const uint64_t EntryAddress = SectionAddress + EntryOffset;
+    const uint64_t TargetAddress = BC->MIB->analyzePLTEntry(
+        Instruction, Instructions.begin(), Instructions.end(), EntryAddress);
+
+    createPLTBinaryFunction(TargetAddress, EntryAddress, EntrySize);
+  }
+}
+
 void RewriteInstance::disassemblePLTSectionX86(BinarySection &Section,
                                                uint64_t EntrySize) {
   const uint64_t SectionAddress = Section.getAddress();
   const uint64_t SectionSize = Section.getSize();
   StringRef PLTContents = Section.getContents();
   ArrayRef<uint8_t> PLTData(
       reinterpret_cast<const uint8_t *>(PLTContents.data()), SectionSize);
 
createPLTBinaryFunction(TargetAddress, SectionAddress + EntryOffset,
                             EntrySize);
   }
 }
 
 void RewriteInstance::disassemblePLT() {
   auto analyzeOnePLTSection = [&](BinarySection &Section, uint64_t EntrySize) {
     if (BC->isAArch64())
       return disassemblePLTSectionAArch64(Section);
+    if (BC->isRISCV())
+      return disassemblePLTSectionRISCV(Section);
     return disassemblePLTSectionX86(Section, EntrySize);
   };
 
   for (BinarySection &Section : BC->allocatableSections()) {
     const PLTSectionInfo *PLTSI = getPLTSectionInfo(Section.getName());
     if (!PLTSI)
       continue;
 
bool RewriteInstance::analyzeRelocation(
   } else {
     const SymbolRef &Symbol = *SymbolIter;
     SymbolName = std::string(cantFail(Symbol.getName()));
     SymbolAddress = cantFail(Symbol.getAddress());
     SkipVerification = (cantFail(Symbol.getType()) == SymbolRef::ST_Other);
     // Section symbols are marked as ST_Debug.
     IsSectionRelocation = (cantFail(Symbol.getType()) == SymbolRef::ST_Debug);
     // Check for PLT entry registered with symbol name
-    if (!SymbolAddress && IsAArch64) {
+    if (!SymbolAddress && (IsAArch64 || BC->isRISCV())) {
       const BinaryData *BD = BC->getPLTBinaryDataByName(SymbolName);
       SymbolAddress = BD ? BD->getAddress() : 0;
     }
   }
   // For PIE or dynamic libs, the linker may choose not to put the relocation
   // result at the address if it is a X86_64_64 one because it will emit a
   // dynamic relocation (X86_RELATIVE) for the dynamic linker and loader to
   // resolve it at run time. The static relocation result goes as the addend
if (ExtractedValue || Addend == 0 || IsPCRelative) {
       return true;
     }
   }
 
   auto verifyExtractedValue = [&]() {
     if (SkipVerification)
       return true;
 
-    if (IsAArch64)
+    if (IsAArch64 || BC->isRISCV())
       return true;
 
     if (SymbolName == "__hot_start" || SymbolName == "__hot_end")
       return true;
 
     if (RType == ELF::R_X86_64_PLT32)
       return true;
 
     return truncateToSize(ExtractedValue, RelSize) ==
            truncateToSize(SymbolAddress + Addend - PCRelOffset, RelSize);
   };
 
void RewriteInstance::processDynamicRelocations() {
 
   // The rest of dynamic relocations - DT_RELA.
   if (DynamicRelocationsSize > 0) {
     ErrorOr<BinarySection &> DynamicRelSectionOrErr =
         BC->getSectionForAddress(*DynamicRelocationsAddress);
     if (!DynamicRelSectionOrErr)
       report_error("unable to find section corresponding to DT_RELA",
                    DynamicRelSectionOrErr.getError());
-    if (DynamicRelSectionOrErr->getSize() != DynamicRelocationsSize)
+    auto DynamicRelSectionSize = DynamicRelSectionOrErr->getSize();
+    // On RISC-V DT_RELASZ seems to include both .rela.dyn and .rela.plt
+    if (DynamicRelocationsSize == DynamicRelSectionSize + PLTRelocationsSize)
+      DynamicRelocationsSize = DynamicRelSectionSize;
+    if (DynamicRelSectionSize != DynamicRelocationsSize)
       report_error("section size mismatch for DT_RELASZ",
                    errc::executable_format_error);
     readDynamicRelocations(DynamicRelSectionOrErr->getSectionRef(),
                            /*IsJmpRel*/ false);
   }
 }
 
 void RewriteInstance::processRelocations() {
void RewriteInstance::handleRelocation(const SectionRef &RelocatedSection,
   if (SymbolIter != InputFile->symbol_end()) {
     SymbolRef Symbol = *SymbolIter;
     section_iterator Section =
         cantFail(Symbol.getSection(), "cannot get symbol section");
     if (Section != InputFile->section_end()) {
       Expected<StringRef> SectionName = Section->getName();
       if (SectionName && !SectionName->empty())
         ReferencedSection = BC->getUniqueSectionByName(*SectionName);
     }
   }
 
   if (!ReferencedSection)
     ReferencedSection = BC->getSectionForAddress(SymbolAddress);
 
   const bool IsToCode = ReferencedSection && ReferencedSection->isText();
 
   // Special handling of PC-relative relocations.
-  if (!IsAArch64 && Relocation::isPCRelative(RType)) {
+  if (!IsAArch64 && !BC->isRISCV() && Relocation::isPCRelative(RType)) {
     if (!IsFromCode && IsToCode) {
       // PC-relative relocations from data to code are tricky since the
       // original information is typically lost after linking, even with
       // '--emit-relocs'. Such relocations are normally used by PIC-style
       // jump tables and they reference both the jump table and jump
       // targets by computing the difference between the two. If we blindly
       // apply the relocation, it will appear that it references an arbitrary
       // location in the code, possibly in a different function from the one
if (!IsFromCode && IsToCode) {
                << formatv("{0:x} for {1}\n", Rel.getOffset(), SymbolName);
       });
     }
 
     return;
   }
 
   bool ForceRelocation = BC->forceSymbolRelocations(SymbolName);
-  if (BC->isAArch64() && Relocation::isGOT(RType))
+  if ((BC->isAArch64() || BC->isRISCV()) && Relocation::isGOT(RType))
     ForceRelocation = true;
 
   if (!ReferencedSection && !ForceRelocation) {
+    // Check for ABS symbols. Used e.g., for __global_pointer$ on RISC-V
+    auto RelSymbol = Rel.getSymbol();
+    if (ContainingBF && RelSymbol != InputFile->symbol_end() &&
+        // TODO is this good enough? Could also pass for UND symbols.
+        cantFail(RelSymbol->getSection()) ==
+            RelSymbol->getObject()->section_end()) {
+      auto *Symbol = BC->getOrCreateUndefinedGlobalSymbol(SymbolName);
+      ContainingBF->addRelocation(Rel.getOffset(), Symbol, Rel.getType(), 0,
+                                  cantFail(RelSymbol->getValue()));
+      return;
+    }
+
     LLVM_DEBUG(dbgs() << "BOLT-DEBUG: cannot determine referenced section.\n");
     return;
   }
 
   // Occasionally we may see a reference past the last byte of the function
   // typically as a result of __builtin_unreachable(). Check it here.
   BinaryFunction *ReferencedBF = BC->getBinaryFunctionContainingAddress(
       Address, /*CheckPastEnd*/ true, /*UseMaxSize*/ IsAArch64);
if (BinaryData *BD = BC->getBinaryDataContainingAddress(SymbolAddress)) {
       ReferencedSymbol = BD->getSymbol();
       Addend += (SymbolAddress - BD->getAddress());
       SymbolAddress = BD->getAddress();
       assert(Address == SymbolAddress + Addend);
     } else {
       // These are mostly local data symbols but undefined symbols
       // in relocation sections can get through here too, from .plt.
       assert(
-          (IsAArch64 || IsSectionRelocation ||
+          (IsAArch64 || BC->isRISCV() || IsSectionRelocation ||
            BC->getSectionNameForAddress(SymbolAddress)->startswith(".plt")) &&
           "known symbols should not resolve to anonymous locals");
 
       if (IsSectionRelocation) {
         ReferencedSymbol =
             BC->getOrCreateGlobalSymbol(SymbolAddress, "SYMBOLat");
       } else {
         SymbolRef Symbol = *Rel.getSymbol();
for (auto &BFI : BC->getBinaryFunctions()) {
     // e.g. function splitting is unsupported.
     if (Function.hasDynamicRelocationAtIsland())
       Function.setSimple(false);
 
     if (Function.empty())
       continue;
 
     Function.postProcessCFG();
 
     if (opts::PrintAll || opts::PrintCFG)
       Function.print(outs(), "after building cfg");
 
     if (opts::DumpDotAll)
       Function.dumpGraphForPass("00_build-cfg");
 
     if (opts::PrintLoopInfo) {
       Function.calculateLoopInfo();

bolt/lib/Target/CMakeLists.txt

 if ("X86" IN_LIST LLVM_TARGETS_TO_BUILD)
   message(STATUS "Targeting X86 in llvm-bolt")
   add_subdirectory(X86)
 endif()
 
 if ("AArch64" IN_LIST LLVM_TARGETS_TO_BUILD)
   message(STATUS "Targeting AArch64 in llvm-bolt")
   add_subdirectory(AArch64)
 endif()
+
+if ("RISCV" IN_LIST LLVM_TARGETS_TO_BUILD)
+  message(STATUS "Targeting RISCV in llvm-bolt")
+  add_subdirectory(RISCV)
+endif()

bolt/lib/Target/RISCV/CMakeLists.txt

+set(LLVM_LINK_COMPONENTS
+  MC
+  Support
+  RISCVDesc
+  )
+
+add_llvm_library(LLVMBOLTTargetRISCV
+  RISCVMCPlusBuilder.cpp
+
+  DISABLE_LLVM_LINK_LLVM_DYLIB
+
+  DEPENDS
+  RISCVCommonTableGen
+  )
+
+target_link_libraries(LLVMBOLTTargetRISCV PRIVATE LLVMBOLTCore)
+
+include_directories(
+  ${LLVM_MAIN_SRC_DIR}/lib/Target/RISCV
+  ${LLVM_BINARY_DIR}/lib/Target/RISCV
+  )

bolt/lib/Target/RISCV/RISCVMCPlusBuilder.cpp

+//===- bolt/Target/RISCV/RISCVMCPlusBuilder.cpp -----------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides RISCV-specific MCPlus builder.
+//
+//===----------------------------------------------------------------------===//
+
+#include "MCTargetDesc/RISCVMCExpr.h"
+#include "MCTargetDesc/RISCVMCTargetDesc.h"
+#include "bolt/Core/MCPlusBuilder.h"
+#include "llvm/BinaryFormat/ELF.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/Format.h"
+#include "llvm/Support/raw_ostream.h"
+
+#define DEBUG_TYPE "mcplus"
+
+using namespace llvm;
+using namespace bolt;
+
+namespace {
+
+class RISCVMCPlusBuilder : public MCPlusBuilder {
+public:
+  using MCPlusBuilder::MCPlusBuilder;
+
+  bool shouldRecordCodeRelocation(uint64_t RelType) const override {
+    switch (RelType) {
+    case ELF::R_RISCV_JAL:
+    case ELF::R_RISCV_CALL:
+    case ELF::R_RISCV_CALL_PLT:
+    case ELF::R_RISCV_BRANCH:
+    case ELF::R_RISCV_RVC_BRANCH:
+    case ELF::R_RISCV_RVC_JUMP:
+    case ELF::R_RISCV_GOT_HI20:
+    case ELF::R_RISCV_PCREL_HI20:
+    case ELF::R_RISCV_PCREL_LO12_I:
+      return true;
+    default:
+      llvm_unreachable("Unexpected RISCV relocation type in code");
+    }
+  }
+
+  bool isNop(const MCInst &Inst) const {
+    return Inst.getOpcode() == RISCV::ADDI &&
+           Inst.getOperand(0).getReg() == RISCV::X0 &&
+           Inst.getOperand(1).getReg() == RISCV::X0 &&
+           Inst.getOperand(2).getImm() == 0;
+  }
+
+  bool isCNop(const MCInst &Inst) const {
+    return Inst.getOpcode() == RISCV::C_NOP;
+  }
+
+  bool isNoop(const MCInst &Inst) const override {
+    return isNop(Inst) || isCNop(Inst);
+  }
+
+  bool hasPCRelOperand(const MCInst &Inst) const override {
+    switch (Inst.getOpcode()) {
+    default:
+      return false;
+    case RISCV::JAL:
+    case RISCV::AUIPC:
+      return true;
+    }
+  }
+
+  bool replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
+                           MCContext *Ctx) const override {
+    assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) &&
+           "Invalid instruction");
+
+    unsigned SymOpIndex;
+
+    switch (Inst.getOpcode()) {
+    default:
+      llvm_unreachable("not implemented");
+    case RISCV::C_J:
+      SymOpIndex = 0;
+      break;
+    case RISCV::JAL:
+    case RISCV::C_BEQZ:
+    case RISCV::C_BNEZ:
+      SymOpIndex = 1;
+      break;
+    case RISCV::BEQ:
+    case RISCV::BGE:
+      SymOpIndex = 2;
+      break;
+    }
+
+    Inst.getOperand(SymOpIndex) = MCOperand::createExpr(
+        MCSymbolRefExpr::create(TBB, MCSymbolRefExpr::VK_None, *Ctx));
+    return true;
+  }
+
+  IndirectBranchType analyzeIndirectBranch(
+      MCInst &Instruction, InstructionIterator Begin, InstructionIterator End,
+      const unsigned PtrSize, MCInst *&MemLocInstr, unsigned &BaseRegNum,
+      unsigned &IndexRegNum, int64_t &DispValue, const MCExpr *&DispExpr,
+      MCInst *&PCRelBaseOut) const override {
+    MemLocInstr = nullptr;
+    BaseRegNum = 0;
+    IndexRegNum = 0;
+    DispValue = 0;
+    DispExpr = nullptr;
+    PCRelBaseOut = nullptr;
+    return IndirectBranchType::UNKNOWN;
+  }
+
+  bool convertJmpToTailCall(MCInst &Inst) override {
+    if (isTailCall(Inst))
+      return false;
+
+    switch (Inst.getOpcode()) {
+    default:
+      llvm_unreachable("unsupported tail call opcode");
+    case RISCV::C_J:
+    case RISCV::C_JR:
+      break;
+    }
+
+    setTailCall(Inst);
+    return true;
+  }
+
+  bool analyzeBranch(InstructionIterator Begin, InstructionIterator End,
+                     const MCSymbol *&TBB, const MCSymbol *&FBB,
+                     MCInst *&CondBranch,
+                     MCInst *&UncondBranch) const override {
+    auto I = End;
+
+    while (I != Begin) {
+      --I;
+
+      // Ignore nops and CFIs
+      if (isPseudo(*I) || isNoop(*I))
+        continue;
+
+      // Stop when we find the first non-terminator
+      if (!isTerminator(*I) || isTailCall(*I) || !isBranch(*I))
+        break;
+
+      // Handle unconditional branches.
+      if (isUnconditionalBranch(*I)) {
+        // If any code was seen after this unconditional branch, we've seen
+        // unreachable code. Ignore them.
+        CondBranch = nullptr;
+        UncondBranch = &*I;
+        const MCSymbol *Sym = getTargetSymbol(*I);
+        assert(Sym != nullptr &&
+               "Couldn't extract BB symbol from jump operand");
+        TBB = Sym;
+        continue;
+      }
+
+      // Handle conditional branches and ignore indirect branches
+      if (isIndirectBranch(*I))
+        return false;
+
+      if (CondBranch == nullptr) {
+        const MCSymbol *TargetBB = getTargetSymbol(*I);
+        if (TargetBB == nullptr) {
+          // Unrecognized branch target
+          return false;
+        }
+        FBB = TBB;
+        TBB = TargetBB;
+        CondBranch = &*I;
+        continue;
+      }
+
+      llvm_unreachable("multiple conditional branches in one BB");
+    }
+
+    return true;
+  }
+
+  const MCSymbol *getTargetSymbol(const MCInst &Inst,
+                                  unsigned OpNum = 0) const override {
+    const MCOperand &Op = Inst.getOperand(OpNum);
+    if (!Op.isExpr())
+      return nullptr;
+
+    return MCPlusBuilder::getTargetSymbol(Op.getExpr());
+  }
+
+  bool lowerTailCall(MCInst &Inst) override {
+    removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall);
+    if (getConditionalTailCall(Inst))
+      unsetConditionalTailCall(Inst);
+    return true;
+  }
+
+  uint64_t analyzePLTEntry(MCInst &Instruction, InstructionIterator Begin,
+                           InstructionIterator End,
+                           uint64_t BeginPC) const override {
+    auto I = Begin;
+
+    assert(I != End);
+    auto &AUIPC = *I++;
+    assert(AUIPC.getOpcode() == RISCV::AUIPC);
+    assert(AUIPC.getOperand(0).getReg() == RISCV::X28);
+
+    assert(I != End);
+    auto &LD = *I++;
+    assert(LD.getOpcode() == RISCV::LD);
+    assert(LD.getOperand(0).getReg() == RISCV::X28);
+    assert(LD.getOperand(1).getReg() == RISCV::X28);
+
+    assert(I != End);
+    auto &JALR = *I++;
+    (void)JALR;
+    assert(JALR.getOpcode() == RISCV::JALR);
+    assert(JALR.getOperand(0).getReg() == RISCV::X6);
+    assert(JALR.getOperand(1).getReg() == RISCV::X28);
+
+    assert(I != End);
+    auto &NOP = *I++;
+    (void)NOP;
+    assert(isNoop(NOP));
+
+    assert(I == End);
+
+    auto AUIPCOffset = AUIPC.getOperand(1).getImm() << 12;
+    auto LDOffset = LD.getOperand(2).getImm();
+    return BeginPC + AUIPCOffset + LDOffset;
+  }
+
+  bool replaceImmWithSymbolRef(MCInst &Inst, const MCSymbol *Symbol,
+                               int64_t Addend, MCContext *Ctx, int64_t &Value,
+                               uint64_t RelType) const override {
+    unsigned ImmOpNo = -1U;
+
+    for (unsigned Index = 0; Index < MCPlus::getNumPrimeOperands(Inst);
+         ++Index) {
+      if (Inst.getOperand(Index).isImm()) {
+        ImmOpNo = Index;
+        break;
+      }
+    }
+
+    if (ImmOpNo == -1U)
+      return false;
+
+    Value = Inst.getOperand(ImmOpNo).getImm();
+    setOperandToSymbolRef(Inst, ImmOpNo, Symbol, Addend, Ctx, RelType);
+    return true;
+  }
+
+  const MCExpr *getTargetExprFor(MCInst &Inst, const MCExpr *Expr,
+                                 MCContext &Ctx,
+                                 uint64_t RelType) const override {
+    switch (RelType) {
+    default:
+      return Expr;
+    case ELF::R_RISCV_GOT_HI20:
+      // The GOT is reused so no need to create GOT relocations
+    case ELF::R_RISCV_PCREL_HI20:
+      return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_RISCV_PCREL_HI, Ctx);
+    case ELF::R_RISCV_PCREL_LO12_I:
+      return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx);
+    case ELF::R_RISCV_CALL:
+      return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_RISCV_CALL, Ctx);
+    case ELF::R_RISCV_CALL_PLT:
+      return RISCVMCExpr::create(Expr, RISCVMCExpr::VK_RISCV_CALL_PLT, Ctx);
+    }
+  }
+
+  bool evaluateMemOperandTarget(const MCInst &Inst, uint64_t &Target,
+                                uint64_t Address,
+                                uint64_t Size) const override {
+    return false;
+  }
+
+  bool isCallAuipc(const MCInst &Inst) const {
+    if (Inst.getOpcode() != RISCV::AUIPC)
+      return false;
+
+    const auto &ImmOp = Inst.getOperand(1);
+    if (!ImmOp.isExpr())
+      return false;
+
+    const auto *ImmExpr = ImmOp.getExpr();
+    if (!isa<RISCVMCExpr>(ImmExpr))
+      return false;
+
+    switch (cast<RISCVMCExpr>(ImmExpr)->getKind()) {
+    default:
+      return false;
+    case RISCVMCExpr::VK_RISCV_CALL:
+    case RISCVMCExpr::VK_RISCV_CALL_PLT:
+      return true;
+    }
+  }
+
+  bool isRISCVCall(const MCInst &First, const MCInst &Second) const override {
+    if (!isCallAuipc(First))
+      return false;
+
+    assert(Second.getOpcode() == RISCV::JALR);
+    return true;
+  }
+};
+
+} // end anonymous namespace
+
+namespace llvm {
+namespace bolt {
+
+MCPlusBuilder *createRISCVMCPlusBuilder(const MCInstrAnalysis *Analysis,
+                                        const MCInstrInfo *Info,
+                                        const MCRegisterInfo *RegInfo) {
+  return new RISCVMCPlusBuilder(Analysis, Info, RegInfo);
+}
+
+} // namespace bolt
+} // namespace llvm

bolt/test/RISCV/Inputs/plt-gnu-ld.yaml

+--- !ELF
+FileHeader:
+  Class:           ELFCLASS64
+  Data:            ELFDATA2LSB
+  Type:            ET_DYN
+  Machine:         EM_RISCV
+  Flags:           [ EF_RISCV_RVC, EF_RISCV_FLOAT_ABI_DOUBLE ]
+  Entry:           0x5B0
+ProgramHeaders:
+  - Type:            PT_PHDR
+    Flags:           [ PF_R ]
+    VAddr:           0x40
+    Align:           0x8
+  - Type:            PT_INTERP
+    Flags:           [ PF_R ]
+    FirstSec:        .interp
+    LastSec:         .interp
+    VAddr:           0x270
+  - Type:            0x70000003
+    Flags:           [ PF_R ]
+    FirstSec:        .riscv.attributes
+    LastSec:         .riscv.attributes
+  - Type:            PT_LOAD
+    Flags:           [ PF_X, PF_R ]
+    FirstSec:        .interp
+    LastSec:         .eh_frame
+    Align:           0x1000
+    Offset:          0x0
+  - Type:            PT_LOAD
+    Flags:           [ PF_W, PF_R ]
+    FirstSec:        .preinit_array
+    LastSec:         .bss
+    VAddr:           0x1E08
+    Align:           0x1000
+  - Type:            PT_DYNAMIC
+    Flags:           [ PF_W, PF_R ]
+    FirstSec:        .dynamic
+    LastSec:         .dynamic
+    VAddr:           0x1E20
+    Align:           0x8
+  - Type:            PT_GNU_EH_FRAME
+    Flags:           [ PF_R ]
+    FirstSec:        .eh_frame_hdr
+    LastSec:         .eh_frame_hdr
+    VAddr:           0x6AC
+    Align:           0x4
+  - Type:            PT_GNU_STACK
+    Flags:           [ PF_W, PF_R ]
+    Align:           0x10
+  - Type:            PT_GNU_RELRO
+    Flags:           [ PF_R ]
+    FirstSec:        .preinit_array
+    LastSec:         .dynamic
+    VAddr:           0x1E08
+Sections:
+  - Name:            .interp
+    Type:            SHT_PROGBITS
+    Flags:           [ SHF_ALLOC ]
+    Address:         0x270
+    AddressAlign:    0x1
+    Content:         2F6C69622F6C642D6C696E75782D726973637636342D6C703634642E736F2E3100
+  - Name:            .dynsym
+    Type:            SHT_DYNSYM
+    Flags:           [ SHF_ALLOC ]
+    Address:         0x300
+    Link:            .dynstr
+    AddressAlign:    0x8
+  - Name:            .dynstr
+    Type:            SHT_STRTAB
+    Flags:           [ SHF_ALLOC ]
+    Address:         0x3C0
+    AddressAlign:    0x1
+  - Name:            .rela.dyn
+    Type:            SHT_RELA
+    Flags:           [ SHF_ALLOC ]
+    Address:         0x480
+    Link:            .dynsym
+    AddressAlign:    0x8
+    Relocations:
+      - Offset:          0x1E08
+        Type:            R_RISCV_RELATIVE
+        Addend:          1498
+      - Offset:          0x1E10
+        Type:            R_RISCV_RELATIVE
+        Addend:          1650
+      - Offset:          0x1E18
+        Type:            R_RISCV_RELATIVE
+        Addend:          1588
+      - Offset:          0x2000
+        Type:            R_RISCV_RELATIVE
+        Addend:          8192
+      - Offset:          0x2038
+        Type:            R_RISCV_RELATIVE
+        Addend:          1658
+      - Offset:          0x2030
+        Symbol:          _ITM_deregisterTMCloneTable
+        Type:            R_RISCV_64
+      - Offset:          0x2040
+        Symbol:          __cxa_finalize
+        Type:            R_RISCV_64
+      - Offset:          0x2048
+        Symbol:          _ITM_registerTMCloneTable
+        Type:            R_RISCV_64
+  - Name:            .rela.plt
+    Type:            SHT_RELA
+    Flags:           [ SHF_ALLOC, SHF_INFO_LINK ]
+    Address:         0x540
+    Link:            .dynsym
+    AddressAlign:    0x8
+    Info:            .got
+    Relocations:
+      - Offset:          0x2018
+        Symbol:          __libc_start_main
+        Type:            R_RISCV_JUMP_SLOT
+      - Offset:          0x2020
+        Symbol:          puts
+        Type:            R_RISCV_JUMP_SLOT
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+    Binding:         STB_GLOBAL
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+    Section:         .data
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+    Section:         .data
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+    Other:           [ STV_HIDDEN ]
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+    Binding:         STB_GLOBAL
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+    Size:            0x4
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+    Section:         .bss
+    Binding:         STB_GLOBAL
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+  - Name:            _start
+    Type:            STT_FUNC
+    Section:         .text
+    Binding:         STB_GLOBAL
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+    Index:           SHN_ABS
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+    Type:            STT_FUNC
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+    Section:         .bss
+    Binding:         STB_GLOBAL
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+    Type:            STT_FUNC
+    Section:         .text
+    Binding:         STB_GLOBAL
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+    Size:            0x24
+  - Name:            '__cxa_finalize@GLIBC_2.27'
+    Type:            STT_FUNC
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+    Section:         .tm_clone_table
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+    Binding:         STB_WEAK
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+    Binding:         STB_WEAK
+  - Name:            puts
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+  - Name:            __cxa_finalize
+    Type:            STT_FUNC
+    Binding:         STB_WEAK
+  - Name:            _ITM_registerTMCloneTable
+    Binding:         STB_WEAK
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+...

bolt/test/RISCV/lit.local.cfg

+if 'RISCV' not in config.root.targets:
+    config.unsupported = True
+
+flags = '--target=riscv64 -nostdlib -ffreestanding -Wl,--no-relax,--emit-relocs'
+
+config.substitutions.insert(0, ('%cflags', f'%cflags {flags}'))
+config.substitutions.insert(0, ('%cxxflags', f'%cxxflags {flags}'))

bolt/test/RISCV/plt-gnu-ld.test

+// This test checks that the PLT symbols are properly recognized
+// by the BOLT tool.
+
+// RUN: yaml2obj %p/Inputs/plt-gnu-ld.yaml &> %t.exe
+// RUN: llvm-bolt %t.exe -o %t.bolt.exe --print-cfg --print-only=main \
+// RUN:   | FileCheck %s
+
+// CHECK: Binary Function "main" after building cfg {
+// CHECK: auipc ra, puts@PLT

bolt/test/RISCV/reloc-branch.s

+// RUN: %clang %cflags -o %t %s
+// RUN: llvm-bolt --print-cfg --print-only=_start -o /dev/null %t \
+// RUN:    | FileCheck %s
+
+  .text
+  .globl _start
+  .p2align 1
+// CHECK: Binary Function "_start" after building cfg {
+_start:
+// CHECK: beq zero, zero, .Ltmp0
+  beq zero, zero, 1f
+  nop
+// CHECK: .Ltmp0
+1:
+  ret
+  .size _start, .-_start

bolt/test/RISCV/reloc-call.s

+// RUN: %clang %cflags -o %t %s
+// RUN: llvm-bolt --print-fix-riscv-calls --print-only=_start -o /dev/null %t \
+// RUN:    | FileCheck %s
+
+  .text
+
+  .global f
+  .p2align 1
+f:
+  ret
+  .size f, .-f
+
+// CHECK: Binary Function "_start" after fix-riscv-calls {
+  .globl _start
+  .p2align 1
+_start:
+// CHECK: auipc ra, f
+// CHECK-NEXT: jalr ra, 0(ra)
+  call f
+  ret
+  .size _start, .-_start

bolt/test/RISCV/reloc-got.s

+// RUN: %clang %cflags -o %t %s
+// RUN: llvm-bolt --print-cfg --print-only=_start -o /dev/null %t \
+// RUN:    | FileCheck %s
+
+  .data
+  .globl d
+  .p2align 3
+d:
+  .dword 0
+
+  .text
+  .globl _start
+  .p2align 1
+// CHECK: Binary Function "_start" after building cfg {
+_start:
+  nop // Here to not make the _start and .Ltmp0 symbols coincide
+// CHECK: .Ltmp0
+// CHECK: auipc t0, %pcrel_hi(__BOLT_got_zero+{{[0-9]+}})
+// CHECK-NEXT: ld t0, %pcrel_lo(.Ltmp0)(t0)
+1:
+  auipc t0, %got_pcrel_hi(d)
+  ld t0, %pcrel_lo(1b)(t0)
+  ret
+  .size _start, .-_start

bolt/test/RISCV/reloc-jal.s

+// RUN: %clang %cflags -o %t %s
+// RUN: llvm-bolt --print-cfg --print-only=_start -o /dev/null %t \
+// RUN:    | FileCheck %s
+
+  .text
+
+  .global f
+  .p2align 1
+f:
+  ret
+  .size f, .-f
+
+// CHECK: Binary Function "_start" after building cfg {
+  .globl _start
+  .p2align 1
+_start:
+// CHECK: jal ra, f
+  jal ra, f
+  ret
+  .size _start, .-_start

bolt/test/RISCV/reloc-pcrel.s

+// RUN: %clang %cflags -o %t %s
+// RUN: llvm-bolt --print-cfg --print-only=_start -o /dev/null %t \
+// RUN:    | FileCheck %s
+
+  .data
+  .globl d
+  .p2align 3
+d:
+  .dword 0
+
+  .text
+  .globl _start
+  .p2align 1
+// CHECK: Binary Function "_start" after building cfg {
+_start:
+  nop // Here to not make the _start and .Ltmp0 symbols coincide
+// CHECK: .Ltmp0
+// CHECK: auipc t0, %pcrel_hi(d)
+// CHECK-NEXT: ld t0, %pcrel_lo(.Ltmp0)(t0)
+  ld t0, d
+  ret
+  .size _start, .-_start

bolt/test/RISCV/reloc-rvc-branch.s

+// RUN: %clang %cflags -o %t %s
+// RUN: llvm-bolt --print-cfg --print-only=_start -o /dev/null %t \
+// RUN:    | FileCheck %s
+
+  .text
+  .globl _start
+  .p2align 1
+// CHECK: Binary Function "_start" after building cfg {
+_start:
+// CHECK: beqz a0, .Ltmp0
+  c.beqz a0, 1f
+  nop
+// CHECK: .Ltmp0
+1:
+  ret
+  .size _start, .-_start

bolt/test/RISCV/reloc-rvc-jump.s

+// RUN: %clang %cflags -o %t %s
+// RUN: llvm-bolt --print-cfg --print-only=_start -o /dev/null %t \
+// RUN:    | FileCheck %s
+
+  .text
+  .globl _start
+  .p2align 1
+// CHECK: Binary Function "_start" after building cfg {
+_start:
+// CHECK: j .Ltmp0
+  c.j 1f
+  nop
+// CHECK: .Ltmp0
+1:
+  ret
+  .size _start, .-_start