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Differential D143895

[AArch64] Fix incorrect `isLegalAddressingMode`
ClosedPublic

Authored by chill on Feb 13 2023, 2:48 AM.

Details

Reviewers
t.p.northover
fhahn
dmgreen
labrinea
Commits
rG6c9066fe2ecc: Recommit "[AArch64] Fix incorrect `isLegalAddressingMode`"
rG0827e2fa3fd1: [AArch64] Fix incorrect `isLegalAddressingMode`
Summary

AArch64TargetLowering::isLegalAddressingMode has a number of defects, including
accepting an addressing mode, which consists of only an immediate operand, or not checking
the offset range for an addressing mode in the form 1*ScaledReg + Offs.

This patch fixes the above issues.

Diff Detail

Event Timeline

chill created this revision.Feb 13 2023, 2:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 13 2023, 2:48 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
chill requested review of this revision.Feb 13 2023, 2:48 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 13 2023, 2:48 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
chill added a parent revision: D143894: [CodeGenPrepare] Increase the limit on the number of instructions to scan.Feb 13 2023, 2:56 AM
chill added a child revision: D143896: [NFC][CodeGenPrepare] Match against the correct instruction when checking profitability of folding an address.
Harbormaster completed remote builds in B213377: Diff 496894.Feb 13 2023, 4:19 AM
chill edited the summary of this revision. (Show Details)Feb 13 2023, 6:37 AM
chill added reviewers: t.p.northover, fhahn.Feb 13 2023, 8:36 AM
Herald added a subscriber: StephenFan. · View Herald TranscriptFeb 13 2023, 8:36 AM
chill updated this revision to Diff 503839.Mar 9 2023, 10:30 AM
Harbormaster completed remote builds in B218440: Diff 503839.Mar 9 2023, 12:20 PM
chill updated this revision to Diff 508535.Mar 27 2023, 2:16 AM

Fixed a few places in LSR where we called isLegalAddressingMode without a base register, even
though we meant an addressing mode with a base register.

Harbormaster completed remote builds in B221926: Diff 508535.Mar 27 2023, 3:21 AM
chill updated this revision to Diff 509368.Mar 29 2023, 7:44 AM

+ canonicalise 2*Reg into Reg + Reg

Harbormaster completed remote builds in B222524: Diff 509368.Mar 29 2023, 12:14 PM
chill edited parent revisions, added: D145707: [LiveInterval] Fix live range overlap check; removed: D143894: [CodeGenPrepare] Increase the limit on the number of instructions to scan.Mar 30 2023, 6:39 AM
chill added a comment.Apr 6 2023, 7:11 AM

Ping?

chill added reviewers: dmgreen, labrinea.Apr 17 2023, 1:59 AM
dmgreen added a comment.Apr 19 2023, 3:44 AM

I can certainly imagine that we haven't got Addressing modes without a BaseReg entirely correct in the past and just assumed it was present. The change in IsSimplerBaseSCEVForTarget I added recently and look more correct now.

llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
3186 ↗(On Diff #509368)

Can you give more details why this is changed to HasBaseReg? It seems that isAlwaysFoldable already sets ScaledReg to 1 or -1, so this now tests for BaseReg + 1/-1*ScaledReg + IncOffset?

chill added inline comments.Apr 19 2023, 7:12 AM
llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
3186 ↗(On Diff #509368)

Right, it's incorrect.
However, I'd rather see if I can fix it by changing isAlwaysFoldable, that invents a scale existence without any external input.

To be continued ...

chill updated this revision to Diff 515006.Apr 19 2023, 10:04 AM
chill marked an inline comment as done.
Harbormaster completed remote builds in B226639: Diff 515006.Apr 19 2023, 10:49 AM
dmgreen accepted this revision.Apr 20 2023, 5:53 AM

Thanks. LGTM

This revision is now accepted and ready to land.Apr 20 2023, 5:53 AM
This revision was landed with ongoing or failed builds.Apr 20 2023, 7:45 AM
Closed by commit rG0827e2fa3fd1: [AArch64] Fix incorrect `isLegalAddressingMode` (authored by chill). · Explain Why
This revision was automatically updated to reflect the committed changes.
chill added a commit: rG0827e2fa3fd1: [AArch64] Fix incorrect `isLegalAddressingMode`.
chill added a reverting change: rGed7ada259f66: Revert "[AArch64] Fix incorrect `isLegalAddressingMode`".Apr 20 2023, 8:11 AM
chill reopened this revision.Apr 20 2023, 8:11 AM
This revision is now accepted and ready to land.Apr 20 2023, 8:11 AM
chill planned changes to this revision.Apr 20 2023, 8:11 AM
chill updated this revision to Diff 515716.Apr 21 2023, 6:39 AM

Work around TargetLowering::AddrMode no longer an aggregate in C++20.

This revision is now accepted and ready to land.Apr 21 2023, 6:39 AM
chill requested review of this revision.Apr 21 2023, 7:18 AM
dmgreen accepted this revision.Apr 21 2023, 7:25 AM

LGTM still.

This revision is now accepted and ready to land.Apr 21 2023, 7:25 AM
This revision was landed with ongoing or failed builds.Apr 21 2023, 8:21 AM
Closed by commit rG6c9066fe2ecc: Recommit "[AArch64] Fix incorrect `isLegalAddressingMode`" (authored by chill). · Explain Why
This revision was automatically updated to reflect the committed changes.
chill added a commit: rG6c9066fe2ecc: Recommit "[AArch64] Fix incorrect `isLegalAddressingMode`".

Revision Contents

PathSize
llvm/
lib/
CodeGen/
70 lines
Target/
AArch64/
19 lines
test/
Transforms/
LoopStrengthReduce/
AArch64/
6 lines
unittests/
Target/
AArch64/
174 lines
1 line

Diff 503839

llvm/lib/CodeGen/CodeGenPrepare.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,604 Lines • ▼ Show 20 Lines case Instruction::AddrSpaceCast: {
unsigned SrcAS = unsigned SrcAS =
AddrInst->getOperand(0)->getType()->getPointerAddressSpace(); AddrInst->getOperand(0)->getType()->getPointerAddressSpace();
unsigned DestAS = AddrInst->getType()->getPointerAddressSpace(); unsigned DestAS = AddrInst->getType()->getPointerAddressSpace();
if (TLI.getTargetMachine().isNoopAddrSpaceCast(SrcAS, DestAS)) if (TLI.getTargetMachine().isNoopAddrSpaceCast(SrcAS, DestAS))
return matchAddr(AddrInst->getOperand(0), Depth); return matchAddr(AddrInst->getOperand(0), Depth);
return false; return false;
} }
case Instruction::Add: { case Instruction::Add: {
// Check to see if we can merge in the RHS then the LHS. If so, we win. // Check to see if we can merge in one operand, then the other. If so, we
// win.
ExtAddrMode BackupAddrMode = AddrMode; ExtAddrMode BackupAddrMode = AddrMode;
unsigned OldSize = AddrModeInsts.size(); unsigned OldSize = AddrModeInsts.size();
// Start a transaction at this point. // Start a transaction at this point.
// The LHS may match but not the RHS. // The LHS may match but not the RHS.
// Therefore, we need a higher level restoration point to undo partially // Therefore, we need a higher level restoration point to undo partially
// matched operation. // matched operation.
TypePromotionTransaction::ConstRestorationPt LastKnownGood = TypePromotionTransaction::ConstRestorationPt LastKnownGood =
TPT.getRestorationPoint(); TPT.getRestorationPoint();
// Try to match an integer constant second to increase its chance of ending
// up in `BaseOffs`, resp. decrease its chance of ending up in `BaseReg`.
int First = 0, Second = 1;
if (isa<ConstantInt>(AddrInst->getOperand(First))
&& !isa<ConstantInt>(AddrInst->getOperand(Second)))
std::swap(First, Second);
AddrMode.InBounds = false; AddrMode.InBounds = false;
if (matchAddr(AddrInst->getOperand(1), Depth + 1) && if (matchAddr(AddrInst->getOperand(First), Depth + 1) &&
matchAddr(AddrInst->getOperand(0), Depth + 1)) matchAddr(AddrInst->getOperand(Second), Depth + 1))
return true; return true;
// Restore the old addr mode info. // Restore the old addr mode info.
AddrMode = BackupAddrMode; AddrMode = BackupAddrMode;
AddrModeInsts.resize(OldSize); AddrModeInsts.resize(OldSize);
TPT.rollback(LastKnownGood); TPT.rollback(LastKnownGood);
// Otherwise this was over-aggressive. Try merging in the LHS then the RHS. // Otherwise this was over-aggressive. Try merging operands in the opposite
if (matchAddr(AddrInst->getOperand(0), Depth + 1) && // order.
matchAddr(AddrInst->getOperand(1), Depth + 1)) if (matchAddr(AddrInst->getOperand(Second), Depth + 1) &&
matchAddr(AddrInst->getOperand(First), Depth + 1))
return true; return true;
// Otherwise we definitely can't merge the ADD in. // Otherwise we definitely can't merge the ADD in.
AddrMode = BackupAddrMode; AddrMode = BackupAddrMode;
AddrModeInsts.resize(OldSize); AddrModeInsts.resize(OldSize);
TPT.rollback(LastKnownGood); TPT.rollback(LastKnownGood);
break; break;
} }
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines for (unsigned i = 1, e = AddrInst->getNumOperands(); i != e; ++i, ++GTI) {
} }
} }
} }
// A common case is for the GEP to only do a constant offset. In this case, // A common case is for the GEP to only do a constant offset. In this case,
// just add it to the disp field and check validity. // just add it to the disp field and check validity.
if (VariableOperand == -1) { if (VariableOperand == -1) {
AddrMode.BaseOffs += ConstantOffset; AddrMode.BaseOffs += ConstantOffset;
if (ConstantOffset == 0 ||
TLI.isLegalAddressingMode(DL, AddrMode, AccessTy, AddrSpace)) {
// Check to see if we can fold the base pointer in too.
if (matchAddr(AddrInst->getOperand(0), Depth + 1)) { if (matchAddr(AddrInst->getOperand(0), Depth + 1)) {
if (!cast<GEPOperator>(AddrInst)->isInBounds()) if (!cast<GEPOperator>(AddrInst)->isInBounds())
AddrMode.InBounds = false; AddrMode.InBounds = false;
return true; return true;
} }
} else if (EnableGEPOffsetSplit && isa<GetElementPtrInst>(AddrInst) && AddrMode.BaseOffs -= ConstantOffset;
if (EnableGEPOffsetSplit && isa<GetElementPtrInst>(AddrInst) &&
TLI.shouldConsiderGEPOffsetSplit() && Depth == 0 && TLI.shouldConsiderGEPOffsetSplit() && Depth == 0 &&
ConstantOffset > 0) { ConstantOffset > 0) {
// Record GEPs with non-zero offsets as candidates for splitting in the // Record GEPs with non-zero offsets as candidates for splitting in
// event that the offset cannot fit into the r+i addressing mode. // the event that the offset cannot fit into the r+i addressing mode.
// Simple and common case that only one GEP is used in calculating the // Simple and common case that only one GEP is used in calculating the
// address for the memory access. // address for the memory access.
Value *Base = AddrInst->getOperand(0); Value *Base = AddrInst->getOperand(0);
auto *BaseI = dyn_cast<Instruction>(Base); auto *BaseI = dyn_cast<Instruction>(Base);
auto *GEP = cast<GetElementPtrInst>(AddrInst); auto *GEP = cast<GetElementPtrInst>(AddrInst);
if (isa<Argument>(Base) || isa<GlobalValue>(Base) || if (isa<Argument>(Base) || isa<GlobalValue>(Base) ||
(BaseI && !isa<CastInst>(BaseI) && (BaseI && !isa<CastInst>(BaseI) &&
!isa<GetElementPtrInst>(BaseI))) { !isa<GetElementPtrInst>(BaseI))) {
// Make sure the parent block allows inserting non-PHI instructions // Make sure the parent block allows inserting non-PHI instructions
// before the terminator. // before the terminator.
BasicBlock *Parent = BasicBlock *Parent = BaseI ? BaseI->getParent()
BaseI ? BaseI->getParent() : &GEP->getFunction()->getEntryBlock(); : &GEP->getFunction()->getEntryBlock();
if (!Parent->getTerminator()->isEHPad()) if (!Parent->getTerminator()->isEHPad())
LargeOffsetGEP = std::make_pair(GEP, ConstantOffset); LargeOffsetGEP = std::make_pair(GEP, ConstantOffset);
} }
} }
AddrMode.BaseOffs -= ConstantOffset;
return false; return false;
} }
// Save the valid addressing mode in case we can't match. // Save the valid addressing mode in case we can't match.
ExtAddrMode BackupAddrMode = AddrMode; ExtAddrMode BackupAddrMode = AddrMode;
unsigned OldSize = AddrModeInsts.size(); unsigned OldSize = AddrModeInsts.size();
// See if the scale and offset amount is valid for this target. // See if the scale and offset amount is valid for this target.
▲ Show 20 Lines • Show All 1,272 Lines • ▼ Show 20 Lines for (auto &Entry : LargeOffsetGEPMap) {
Value *NewBaseGEP = nullptr; Value *NewBaseGEP = nullptr;
auto *LargeOffsetGEP = LargeOffsetGEPs.begin(); auto *LargeOffsetGEP = LargeOffsetGEPs.begin();
while (LargeOffsetGEP != LargeOffsetGEPs.end()) { while (LargeOffsetGEP != LargeOffsetGEPs.end()) {
GetElementPtrInst *GEP = LargeOffsetGEP->first; GetElementPtrInst *GEP = LargeOffsetGEP->first;
int64_t Offset = LargeOffsetGEP->second; int64_t Offset = LargeOffsetGEP->second;
if (Offset != BaseOffset) { if (Offset != BaseOffset) {
TargetLowering::AddrMode AddrMode; TargetLowering::AddrMode AddrMode;
AddrMode.HasBaseReg = true;
AddrMode.BaseOffs = Offset - BaseOffset; AddrMode.BaseOffs = Offset - BaseOffset;
// The result type of the GEP might not be the type of the memory // The result type of the GEP might not be the type of the memory
// access. // access.
if (!TLI->isLegalAddressingMode(*DL, AddrMode, if (!TLI->isLegalAddressingMode(*DL, AddrMode,
GEP->getResultElementType(), GEP->getResultElementType(),
GEP->getAddressSpace())) { GEP->getAddressSpace())) {
// We need to create a new base if the offset to the current base is // We need to create a new base if the offset to the current base is
// too large to fit into the addressing mode. So, a very large struct // too large to fit into the addressing mode. So, a very large struct
▲ Show 20 Lines • Show All 2,539 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 14,863 Lines • ▼ Show 20 Lines
// immediates is the same as for an add or a sub. // immediates is the same as for an add or a sub.
bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const { bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
return isLegalAddImmediate(Immed); return isLegalAddImmediate(Immed);
} }
/// isLegalAddressingMode - Return true if the addressing mode represented /// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type. /// by AM is legal for this target, for a load/store of the specified type.
bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL, bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
const AddrMode &AM, Type *Ty, const AddrMode &AMode, Type *Ty,
unsigned AS, Instruction *I) const { unsigned AS, Instruction *I) const {
// AArch64 has five basic addressing modes: // AArch64 has five basic addressing modes:
// reg // reg
// reg + 9-bit signed offset // reg + 9-bit signed offset
// reg + SIZE_IN_BYTES * 12-bit unsigned offset // reg + SIZE_IN_BYTES * 12-bit unsigned offset
// reg1 + reg2 // reg1 + reg2
// reg + SIZE_IN_BYTES * reg // reg + SIZE_IN_BYTES * reg
// No global is ever allowed as a base. // No global is ever allowed as a base.
if (AM.BaseGV) if (AMode.BaseGV)
return false; return false;
// No reg+reg+imm addressing. // No reg+reg+imm addressing.
if (AM.HasBaseReg && AM.BaseOffs && AM.Scale) if (AMode.HasBaseReg && AMode.BaseOffs && AMode.Scale)
return false;
// Canonicalise `1*ScaledReg + imm` into `BaseReg + imm`.
AddrMode AM = AMode;
if (AM.Scale && !AM.HasBaseReg) {
if (AM.Scale != 1)
return false;
AM.HasBaseReg = true;
AM.Scale = 0;
}
// A base register is required in all addressing modes.
if (!AM.HasBaseReg)
return false; return false;
// FIXME: Update this method to support scalable addressing modes. // FIXME: Update this method to support scalable addressing modes.
if (Ty->isScalableTargetExtTy()) if (Ty->isScalableTargetExtTy())
return AM.HasBaseReg && !AM.BaseOffs && !AM.Scale; return AM.HasBaseReg && !AM.BaseOffs && !AM.Scale;
if (isa<ScalableVectorType>(Ty)) { if (isa<ScalableVectorType>(Ty)) {
uint64_t VecElemNumBytes = uint64_t VecElemNumBytes =
▲ Show 20 Lines • Show All 9,612 Lines • Show Last 20 Lines

llvm/test/Transforms/LoopStrengthReduce/AArch64/lsr-pre-inc-offset-check.ll

Show All 14 Lines
; preferred addresing mode is preindexed. ; preferred addresing mode is preindexed.
%"Type" = type <{[166 x [338 x i8]]}> %"Type" = type <{[166 x [338 x i8]]}>
define void @test_lsr_pre_inc_offset_check(ptr %p) { define void @test_lsr_pre_inc_offset_check(ptr %p) {
; CHECK-LABEL: test_lsr_pre_inc_offset_check: ; CHECK-LABEL: test_lsr_pre_inc_offset_check:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, #165 ; CHECK-NEXT: mov w8, #165
; CHECK-NEXT: add x9, x0, #340 ; CHECK-NEXT: add x9, x0, #339
; CHECK-NEXT: mov w10, #2 ; CHECK-NEXT: mov w10, #2
; CHECK-NEXT: .LBB0_1: // %main ; CHECK-NEXT: .LBB0_1: // %main
; CHECK-NEXT: // =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
; CHECK-NEXT: stur wzr, [x9, #-1] ; CHECK-NEXT: str wzr, [x9]
; CHECK-NEXT: subs x8, x8, #1 ; CHECK-NEXT: subs x8, x8, #1
; CHECK-NEXT: strb w10, [x9] ; CHECK-NEXT: strb w10, [x9, #1]
; CHECK-NEXT: add x9, x9, #338 ; CHECK-NEXT: add x9, x9, #338
; CHECK-NEXT: b.ne .LBB0_1 ; CHECK-NEXT: b.ne .LBB0_1
; CHECK-NEXT: // %bb.2: // %exit ; CHECK-NEXT: // %bb.2: // %exit
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
br label %main br label %main
exit: exit:
ret void ret void
Show All 16 Lines

llvm/unittests/Target/AArch64/AddressingModes.cpp

  • This file was added.
#include "AArch64Subtarget.h"
#include "AArch64TargetMachine.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gtest/gtest.h"
#include <initializer_list>
#include <memory>
using namespace llvm;
namespace {
struct TestCase {
TargetLowering::AddrMode AM;
unsigned TypeBits;
bool Result;
};
const std::initializer_list<TestCase> Tests = {
// {BaseGV, BaseOffs, HasBaseReg, Scale}, Bits, Result
{{reinterpret_cast<GlobalValue *>(-1), 0, false}, 64, false},
{{nullptr, 8, true, 1}, 64, false},
{{nullptr, 0, false, 2}, 64, false},
{{nullptr, 0, false, 1}, 64, true},
{{nullptr, 4, false, 0}, 64, false},
{{nullptr, 0, true, 1}, 64, true},
{{nullptr, 0, true, 1}, 32, true},
{{nullptr, 0, true, 1}, 16, true},
{{nullptr, 0, true, 1}, 8, true},
{{nullptr, 0, true, 2}, 64, false},
{{nullptr, 0, true, 2}, 32, false},
{{nullptr, 0, true, 2}, 16, true},
{{nullptr, 0, true, 2}, 8, false},
{{nullptr, 0, true, 4}, 64, false},
{{nullptr, 0, true, 4}, 32, true},
{{nullptr, 0, true, 4}, 16, false},
{{nullptr, 0, true, 4}, 8, false},
{{nullptr, 0, true, 8}, 64, true},
{{nullptr, 0, true, 8}, 32, false},
{{nullptr, 0, true, 8}, 16, false},
{{nullptr, 0, true, 8}, 8, false},
{{nullptr, 0, true, 16}, 64, false},
{{nullptr, 0, true, 16}, 32, false},
{{nullptr, 0, true, 16}, 16, false},
{{nullptr, 0, true, 16}, 8, false},
{{nullptr, -257, true, 0}, 64, false},
{{nullptr, -256, true, 0}, 64, true},
{{nullptr, -255, true, 0}, 64, true},
{{nullptr, -1, true, 0}, 64, true},
{{nullptr, 0, true, 0}, 64, true},
{{nullptr, 1, true, 0}, 64, true},
{{nullptr, 254, true, 0}, 64, true},
{{nullptr, 255, true, 0}, 64, true},
{{nullptr, 256, true, 0}, 64, true},
{{nullptr, 257, true, 0}, 64, false},
{{nullptr, 258, true, 0}, 64, false},
{{nullptr, 259, true, 0}, 64, false},
{{nullptr, 260, true, 0}, 64, false},
{{nullptr, 261, true, 0}, 64, false},
{{nullptr, 262, true, 0}, 64, false},
{{nullptr, 263, true, 0}, 64, false},
{{nullptr, 264, true, 0}, 64, true},
{{nullptr, 4096 * 8 - 8, true, 0}, 64, true},
{{nullptr, 4096 * 8 - 7, true, 0}, 64, false},
{{nullptr, 4096 * 8 - 6, true, 0}, 64, false},
{{nullptr, 4096 * 8 - 5, true, 0}, 64, false},
{{nullptr, 4096 * 8 - 4, true, 0}, 64, false},
{{nullptr, 4096 * 8 - 3, true, 0}, 64, false},
{{nullptr, 4096 * 8 - 2, true, 0}, 64, false},
{{nullptr, 4096 * 8 - 1, true, 0}, 64, false},
{{nullptr, 4096 * 8, true, 0}, 64, false},
{{nullptr, 4096 * 8 + 1, true, 0}, 64, false},
{{nullptr, 4096 * 8 + 2, true, 0}, 64, false},
{{nullptr, 4096 * 8 + 3, true, 0}, 64, false},
{{nullptr, 4096 * 8 + 4, true, 0}, 64, false},
{{nullptr, 4096 * 8 + 5, true, 0}, 64, false},
{{nullptr, 4096 * 8 + 6, true, 0}, 64, false},
{{nullptr, 4096 * 8 + 7, true, 0}, 64, false},
{{nullptr, 4096 * 8 + 8, true, 0}, 64, false},
{{nullptr, -257, true, 0}, 32, false},
{{nullptr, -256, true, 0}, 32, true},
{{nullptr, -255, true, 0}, 32, true},
{{nullptr, -1, true, 0}, 32, true},
{{nullptr, 0, true, 0}, 32, true},
{{nullptr, 1, true, 0}, 32, true},
{{nullptr, 254, true, 0}, 32, true},
{{nullptr, 255, true, 0}, 32, true},
{{nullptr, 256, true, 0}, 32, true},
{{nullptr, 257, true, 0}, 32, false},
{{nullptr, 258, true, 0}, 32, false},
{{nullptr, 259, true, 0}, 32, false},
{{nullptr, 260, true, 0}, 32, true},
{{nullptr, 4096 * 4 - 4, true, 0}, 32, true},
{{nullptr, 4096 * 4 - 3, true, 0}, 32, false},
{{nullptr, 4096 * 4 - 2, true, 0}, 32, false},
{{nullptr, 4096 * 4 - 1, true, 0}, 32, false},
{{nullptr, 4096 * 4, true, 0}, 32, false},
{{nullptr, 4096 * 4 + 1, true, 0}, 32, false},
{{nullptr, 4096 * 4 + 2, true, 0}, 32, false},
{{nullptr, 4096 * 4 + 3, true, 0}, 32, false},
{{nullptr, 4096 * 4 + 4, true, 0}, 32, false},
{{nullptr, -257, true, 0}, 16, false},
{{nullptr, -256, true, 0}, 16, true},
{{nullptr, -255, true, 0}, 16, true},
{{nullptr, -1, true, 0}, 16, true},
{{nullptr, 0, true, 0}, 16, true},
{{nullptr, 1, true, 0}, 16, true},
{{nullptr, 254, true, 0}, 16, true},
{{nullptr, 255, true, 0}, 16, true},
{{nullptr, 256, true, 0}, 16, true},
{{nullptr, 257, true, 0}, 16, false},
{{nullptr, 258, true, 0}, 16, true},
{{nullptr, 4096 * 2 - 2, true, 0}, 16, true},
{{nullptr, 4096 * 2 - 1, true, 0}, 16, false},
{{nullptr, 4096 * 2, true, 0}, 16, false},
{{nullptr, 4096 * 2 + 1, true, 0}, 16, false},
{{nullptr, 4096 * 2 + 2, true, 0}, 16, false},
{{nullptr, -257, true, 0}, 8, false},
{{nullptr, -256, true, 0}, 8, true},
{{nullptr, -255, true, 0}, 8, true},
{{nullptr, -1, true, 0}, 8, true},
{{nullptr, 0, true, 0}, 8, true},
{{nullptr, 1, true, 0}, 8, true},
{{nullptr, 254, true, 0}, 8, true},
{{nullptr, 255, true, 0}, 8, true},
{{nullptr, 256, true, 0}, 8, true},
{{nullptr, 257, true, 0}, 8, true},
{{nullptr, 4096 - 2, true, 0}, 8, true},
{{nullptr, 4096 - 1, true, 0}, 8, true},
{{nullptr, 4096, true, 0}, 8, false},
{{nullptr, 4096 + 1, true, 0}, 8, false},
};
} // namespace
TEST(AddressingModes, AddressingModes) {
LLVMInitializeAArch64TargetInfo();
LLVMInitializeAArch64Target();
LLVMInitializeAArch64TargetMC();
std::string Error;
auto TT = Triple::normalize("aarch64");
const Target *T = TargetRegistry::lookupTarget(TT, Error);
std::unique_ptr<TargetMachine> TM(
T->createTargetMachine(TT, "generic", "", TargetOptions(), std::nullopt,
std::nullopt, CodeGenOpt::Default));
AArch64Subtarget ST(TM->getTargetTriple(), TM->getTargetCPU(),
TM->getTargetCPU(), TM->getTargetFeatureString(), *TM,
true);
auto *TLI = ST.getTargetLowering();
DataLayout DL("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
LLVMContext Ctx;
for (const auto &Test : Tests) {
Type *Typ = Type::getIntNTy(Ctx, Test.TypeBits);
ASSERT_EQ(TLI->isLegalAddressingMode(DL, Test.AM, Typ, 0), Test.Result);
}
}

llvm/unittests/Target/AArch64/CMakeLists.txt

Show All 16 Linesset(LLVM_LINK_COMPONENTS
SelectionDAG SelectionDAG
Support Support
Target Target
TargetParser TargetParser
) )
add_llvm_target_unittest(AArch64Tests add_llvm_target_unittest(AArch64Tests
AArch64InstPrinterTest.cpp AArch64InstPrinterTest.cpp
AddressingModes.cpp
DecomposeStackOffsetTest.cpp DecomposeStackOffsetTest.cpp
InstSizes.cpp InstSizes.cpp
MatrixRegisterAliasing.cpp MatrixRegisterAliasing.cpp
SMEAttributesTest.cpp SMEAttributesTest.cpp
) )
set_property(TARGET AArch64Tests PROPERTY FOLDER "Tests/UnitTests/TargetTests") set_property(TARGET AArch64Tests PROPERTY FOLDER "Tests/UnitTests/TargetTests")